kernel/drivers/video/fbdev/omap/lcdc.c

   1 /*
   2  * OMAP1 internal LCD controller
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Imre Deak <imre.deak@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, write to the Free Software Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  20  */
  21 #include <linux/module.h>
  22 #include <linux/device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/err.h>
  26 #include <linux/mm.h>
  27 #include <linux/fb.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/vmalloc.h>
  30 #include <linux/clk.h>
  31 #include <linux/gfp.h>
  32
  33 #include <mach/lcdc.h>
  34 #include <linux/omap-dma.h>
  35
  36 #include <asm/mach-types.h>
  37
  38 #include "omapfb.h"
  39
  40 #include "lcdc.h"
  41
  42 #define MODULE_NAME                     "lcdc"
  43
  44 #define MAX_PALETTE_SIZE                PAGE_SIZE
  45
  46 enum lcdc_load_mode {
  47         OMAP_LCDC_LOAD_PALETTE,
  48         OMAP_LCDC_LOAD_FRAME,
  49         OMAP_LCDC_LOAD_PALETTE_AND_FRAME
  50 };
  51
  52 static struct omap_lcd_controller {
  53         enum omapfb_update_mode update_mode;
  54         int                     ext_mode;
  55
  56         unsigned long           frame_offset;
  57         int                     screen_width;
  58         int                     xres;
  59         int                     yres;
  60
  61         enum omapfb_color_format        color_mode;
  62         int                     bpp;
  63         void                    *palette_virt;
  64         dma_addr_t              palette_phys;
  65         int                     palette_code;
  66         int                     palette_size;
  67
  68         unsigned int            irq_mask;
  69         struct completion       last_frame_complete;
  70         struct completion       palette_load_complete;
  71         struct clk              *lcd_ck;
  72         struct omapfb_device    *fbdev;
  73
  74         void                    (*dma_callback)(void *data);
  75         void                    *dma_callback_data;
  76
  77         dma_addr_t              vram_phys;
  78         void                    *vram_virt;
  79         unsigned long           vram_size;
  80 } lcdc;
  81
  82 static void inline enable_irqs(int mask)
  83 {
  84         lcdc.irq_mask |= mask;
  85 }
  86
  87 static void inline disable_irqs(int mask)
  88 {
  89         lcdc.irq_mask &= ~mask;
  90 }
  91
  92 static void set_load_mode(enum lcdc_load_mode mode)
  93 {
  94         u32 l;
  95
  96         l = omap_readl(OMAP_LCDC_CONTROL);
  97         l &= ~(3 << 20);
  98         switch (mode) {
  99         case OMAP_LCDC_LOAD_PALETTE:
 100                 l |= 1 << 20;
 101                 break;
 102         case OMAP_LCDC_LOAD_FRAME:
 103                 l |= 2 << 20;
 104                 break;
 105         case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
 106                 break;
 107         default:
 108                 BUG();
 109         }
 110         omap_writel(l, OMAP_LCDC_CONTROL);
 111 }
 112
 113 static void enable_controller(void)
 114 {
 115         u32 l;
 116
 117         l = omap_readl(OMAP_LCDC_CONTROL);
 118         l |= OMAP_LCDC_CTRL_LCD_EN;
 119         l &= ~OMAP_LCDC_IRQ_MASK;
 120         l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE;        /* enabled IRQs */
 121         omap_writel(l, OMAP_LCDC_CONTROL);
 122 }
 123
 124 static void disable_controller_async(void)
 125 {
 126         u32 l;
 127         u32 mask;
 128
 129         l = omap_readl(OMAP_LCDC_CONTROL);
 130         mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
 131         /*
 132          * Preserve the DONE mask, since we still want to get the
 133          * final DONE irq. It will be disabled in the IRQ handler.
 134          */
 135         mask &= ~OMAP_LCDC_IRQ_DONE;
 136         l &= ~mask;
 137         omap_writel(l, OMAP_LCDC_CONTROL);
 138 }
 139
 140 static void disable_controller(void)
 141 {
 142         init_completion(&lcdc.last_frame_complete);
 143         disable_controller_async();
 144         if (!wait_for_completion_timeout(&lcdc.last_frame_complete,
 145                                 msecs_to_jiffies(500)))
 146                 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
 147 }
 148
 149 static void reset_controller(u32 status)
 150 {
 151         static unsigned long reset_count;
 152         static unsigned long last_jiffies;
 153
 154         disable_controller_async();
 155         reset_count++;
 156         if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
 157                 dev_err(lcdc.fbdev->dev,
 158                           "resetting (status %#010x,reset count %lu)\n",
 159                           status, reset_count);
 160                 last_jiffies = jiffies;
 161         }
 162         if (reset_count < 100) {
 163                 enable_controller();
 164         } else {
 165                 reset_count = 0;
 166                 dev_err(lcdc.fbdev->dev,
 167                         "too many reset attempts, giving up.\n");
 168         }
 169 }
 170
 171 /*
 172  * Configure the LCD DMA according to the current mode specified by parameters
 173  * in lcdc.fbdev and fbdev->var.
 174  */
 175 static void setup_lcd_dma(void)
 176 {
 177         static const int dma_elem_type[] = {
 178                 0,
 179                 OMAP_DMA_DATA_TYPE_S8,
 180                 OMAP_DMA_DATA_TYPE_S16,
 181                 0,
 182                 OMAP_DMA_DATA_TYPE_S32,
 183         };
 184         struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par;
 185         struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
 186         unsigned long   src;
 187         int             esize, xelem, yelem;
 188
 189         src = lcdc.vram_phys + lcdc.frame_offset;
 190
 191         switch (var->rotate) {
 192         case 0:
 193                 if (plane->info.mirror || (src & 3) ||
 194                     lcdc.color_mode == OMAPFB_COLOR_YUV420 ||
 195                     (lcdc.xres & 1))
 196                         esize = 2;
 197                 else
 198                         esize = 4;
 199                 xelem = lcdc.xres * lcdc.bpp / 8 / esize;
 200                 yelem = lcdc.yres;
 201                 break;
 202         case 90:
 203         case 180:
 204         case 270:
 205                 if (cpu_is_omap15xx()) {
 206                         BUG();
 207                 }
 208                 esize = 2;
 209                 xelem = lcdc.yres * lcdc.bpp / 16;
 210                 yelem = lcdc.xres;
 211                 break;
 212         default:
 213                 BUG();
 214                 return;
 215         }
 216 #ifdef VERBOSE
 217         dev_dbg(lcdc.fbdev->dev,
 218                  "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
 219                  src, esize, xelem, yelem);
 220 #endif
 221         omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
 222         if (!cpu_is_omap15xx()) {
 223                 int bpp = lcdc.bpp;
 224
 225                 /*
 226                  * YUV support is only for external mode when we have the
 227                  * YUV window embedded in a 16bpp frame buffer.
 228                  */
 229                 if (lcdc.color_mode == OMAPFB_COLOR_YUV420)
 230                         bpp = 16;
 231                 /* Set virtual xres elem size */
 232                 omap_set_lcd_dma_b1_vxres(
 233                         lcdc.screen_width * bpp / 8 / esize);
 234                 /* Setup transformations */
 235                 omap_set_lcd_dma_b1_rotation(var->rotate);
 236                 omap_set_lcd_dma_b1_mirror(plane->info.mirror);
 237         }
 238         omap_setup_lcd_dma();
 239 }
 240
 241 static irqreturn_t lcdc_irq_handler(int irq, void *dev_id)
 242 {
 243         u32 status;
 244
 245         status = omap_readl(OMAP_LCDC_STATUS);
 246
 247         if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
 248                 reset_controller(status);
 249         else {
 250                 if (status & OMAP_LCDC_STAT_DONE) {
 251                         u32 l;
 252
 253                         /*
 254                          * Disable IRQ_DONE. The status bit will be cleared
 255                          * only when the controller is reenabled and we don't
 256                          * want to get more interrupts.
 257                          */
 258                         l = omap_readl(OMAP_LCDC_CONTROL);
 259                         l &= ~OMAP_LCDC_IRQ_DONE;
 260                         omap_writel(l, OMAP_LCDC_CONTROL);
 261                         complete(&lcdc.last_frame_complete);
 262                 }
 263                 if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
 264                         disable_controller_async();
 265                         complete(&lcdc.palette_load_complete);
 266                 }
 267         }
 268
 269         /*
 270          * Clear these interrupt status bits.
 271          * Sync_lost, FUF bits were cleared by disabling the LCD controller
 272          * LOADED_PALETTE can be cleared this way only in palette only
 273          * load mode. In other load modes it's cleared by disabling the
 274          * controller.
 275          */
 276         status &= ~(OMAP_LCDC_STAT_VSYNC |
 277                     OMAP_LCDC_STAT_LOADED_PALETTE |
 278                     OMAP_LCDC_STAT_ABC |
 279                     OMAP_LCDC_STAT_LINE_INT);
 280         omap_writel(status, OMAP_LCDC_STATUS);
 281         return IRQ_HANDLED;
 282 }
 283
 284 /*
 285  * Change to a new video mode. We defer this to a later time to avoid any
 286  * flicker and not to mess up the current LCD DMA context. For this we disable
 287  * the LCD controller, which will generate a DONE irq after the last frame has
 288  * been transferred. Then it'll be safe to reconfigure both the LCD controller
 289  * as well as the LCD DMA.
 290  */
 291 static int omap_lcdc_setup_plane(int plane, int channel_out,
 292                                  unsigned long offset, int screen_width,
 293                                  int pos_x, int pos_y, int width, int height,
 294                                  int color_mode)
 295 {
 296         struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
 297         struct lcd_panel *panel = lcdc.fbdev->panel;
 298         int rot_x, rot_y;
 299
 300         if (var->rotate == 0) {
 301                 rot_x = panel->x_res;
 302                 rot_y = panel->y_res;
 303         } else {
 304                 rot_x = panel->y_res;
 305                 rot_y = panel->x_res;
 306         }
 307         if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
 308             width > rot_x || height > rot_y) {
 309 #ifdef VERBOSE
 310                 dev_dbg(lcdc.fbdev->dev,
 311                         "invalid plane params plane %d pos_x %d pos_y %d "
 312                         "w %d h %d\n", plane, pos_x, pos_y, width, height);
 313 #endif
 314                 return -EINVAL;
 315         }
 316
 317         lcdc.frame_offset = offset;
 318         lcdc.xres = width;
 319         lcdc.yres = height;
 320         lcdc.screen_width = screen_width;
 321         lcdc.color_mode = color_mode;
 322
 323         switch (color_mode) {
 324         case OMAPFB_COLOR_CLUT_8BPP:
 325                 lcdc.bpp = 8;
 326                 lcdc.palette_code = 0x3000;
 327                 lcdc.palette_size = 512;
 328                 break;
 329         case OMAPFB_COLOR_RGB565:
 330                 lcdc.bpp = 16;
 331                 lcdc.palette_code = 0x4000;
 332                 lcdc.palette_size = 32;
 333                 break;
 334         case OMAPFB_COLOR_RGB444:
 335                 lcdc.bpp = 16;
 336                 lcdc.palette_code = 0x4000;
 337                 lcdc.palette_size = 32;
 338                 break;
 339         case OMAPFB_COLOR_YUV420:
 340                 if (lcdc.ext_mode) {
 341                         lcdc.bpp = 12;
 342                         break;
 343                 }
 344                 /* fallthrough */
 345         case OMAPFB_COLOR_YUV422:
 346                 if (lcdc.ext_mode) {
 347                         lcdc.bpp = 16;
 348                         break;
 349                 }
 350                 /* fallthrough */
 351         default:
 352                 /* FIXME: other BPPs.
 353                  * bpp1: code  0,     size 256
 354                  * bpp2: code  0x1000 size 256
 355                  * bpp4: code  0x2000 size 256
 356                  * bpp12: code 0x4000 size 32
 357                  */
 358                 dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode);
 359                 BUG();
 360                 return -1;
 361         }
 362
 363         if (lcdc.ext_mode) {
 364                 setup_lcd_dma();
 365                 return 0;
 366         }
 367
 368         if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
 369                 disable_controller();
 370                 omap_stop_lcd_dma();
 371                 setup_lcd_dma();
 372                 enable_controller();
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int omap_lcdc_enable_plane(int plane, int enable)
 379 {
 380         dev_dbg(lcdc.fbdev->dev,
 381                 "plane %d enable %d update_mode %d ext_mode %d\n",
 382                 plane, enable, lcdc.update_mode, lcdc.ext_mode);
 383         if (plane != OMAPFB_PLANE_GFX)
 384                 return -EINVAL;
 385
 386         return 0;
 387 }
 388
 389 /*
 390  * Configure the LCD DMA for a palette load operation and do the palette
 391  * downloading synchronously. We don't use the frame+palette load mode of
 392  * the controller, since the palette can always be downloaded separately.
 393  */
 394 static void load_palette(void)
 395 {
 396         u16     *palette;
 397
 398         palette = (u16 *)lcdc.palette_virt;
 399
 400         *(u16 *)palette &= 0x0fff;
 401         *(u16 *)palette |= lcdc.palette_code;
 402
 403         omap_set_lcd_dma_b1(lcdc.palette_phys,
 404                 lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
 405
 406         omap_set_lcd_dma_single_transfer(1);
 407         omap_setup_lcd_dma();
 408
 409         init_completion(&lcdc.palette_load_complete);
 410         enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
 411         set_load_mode(OMAP_LCDC_LOAD_PALETTE);
 412         enable_controller();
 413         if (!wait_for_completion_timeout(&lcdc.palette_load_complete,
 414                                 msecs_to_jiffies(500)))
 415                 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
 416         /* The controller gets disabled in the irq handler */
 417         disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
 418         omap_stop_lcd_dma();
 419
 420         omap_set_lcd_dma_single_transfer(lcdc.ext_mode);
 421 }
 422
 423 /* Used only in internal controller mode */
 424 static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
 425                                u16 transp, int update_hw_pal)
 426 {
 427         u16 *palette;
 428
 429         if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
 430                 return -EINVAL;
 431
 432         palette = (u16 *)lcdc.palette_virt;
 433
 434         palette[regno] &= ~0x0fff;
 435         palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
 436                            (blue >> 12);
 437
 438         if (update_hw_pal) {
 439                 disable_controller();
 440                 omap_stop_lcd_dma();
 441                 load_palette();
 442                 setup_lcd_dma();
 443                 set_load_mode(OMAP_LCDC_LOAD_FRAME);
 444                 enable_controller();
 445         }
 446
 447         return 0;
 448 }
 449
 450 static void calc_ck_div(int is_tft, int pck, int *pck_div)
 451 {
 452         unsigned long lck;
 453
 454         pck = max(1, pck);
 455         lck = clk_get_rate(lcdc.lcd_ck);
 456         *pck_div = (lck + pck - 1) / pck;
 457         if (is_tft)
 458                 *pck_div = max(2, *pck_div);
 459         else
 460                 *pck_div = max(3, *pck_div);
 461         if (*pck_div > 255) {
 462                 /* FIXME: try to adjust logic clock divider as well */
 463                 *pck_div = 255;
 464                 dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n",
 465                          pck / 1000);
 466         }
 467 }
 468
 469 static void inline setup_regs(void)
 470 {
 471         u32 l;
 472         struct lcd_panel *panel = lcdc.fbdev->panel;
 473         int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
 474         unsigned long lck;
 475         int pcd;
 476
 477         l = omap_readl(OMAP_LCDC_CONTROL);
 478         l &= ~OMAP_LCDC_CTRL_LCD_TFT;
 479         l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
 480 #ifdef CONFIG_MACH_OMAP_PALMTE
 481 /* FIXME:if (machine_is_omap_palmte()) { */
 482                 /* PalmTE uses alternate TFT setting in 8BPP mode */
 483                 l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
 484 /*      } */
 485 #endif
 486         omap_writel(l, OMAP_LCDC_CONTROL);
 487
 488         l = omap_readl(OMAP_LCDC_TIMING2);
 489         l &= ~(((1 << 6) - 1) << 20);
 490         l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
 491         omap_writel(l, OMAP_LCDC_TIMING2);
 492
 493         l = panel->x_res - 1;
 494         l |= (panel->hsw - 1) << 10;
 495         l |= (panel->hfp - 1) << 16;
 496         l |= (panel->hbp - 1) << 24;
 497         omap_writel(l, OMAP_LCDC_TIMING0);
 498
 499         l = panel->y_res - 1;
 500         l |= (panel->vsw - 1) << 10;
 501         l |= panel->vfp << 16;
 502         l |= panel->vbp << 24;
 503         omap_writel(l, OMAP_LCDC_TIMING1);
 504
 505         l = omap_readl(OMAP_LCDC_TIMING2);
 506         l &= ~0xff;
 507
 508         lck = clk_get_rate(lcdc.lcd_ck);
 509
 510         if (!panel->pcd)
 511                 calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
 512         else {
 513                 dev_warn(lcdc.fbdev->dev,
 514                     "Pixel clock divider value is obsolete.\n"
 515                     "Try to set pixel_clock to %lu and pcd to 0 "
 516                     "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
 517                         lck / panel->pcd / 1000, panel->name);
 518
 519                 pcd = panel->pcd;
 520         }
 521         l |= pcd & 0xff;
 522         l |= panel->acb << 8;
 523         omap_writel(l, OMAP_LCDC_TIMING2);
 524
 525         /* update panel info with the exact clock */
 526         panel->pixel_clock = lck / pcd / 1000;
 527 }
 528
 529 /*
 530  * Configure the LCD controller, download the color palette and start a looped
 531  * DMA transfer of the frame image data. Called only in internal
 532  * controller mode.
 533  */
 534 static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
 535 {
 536         int r = 0;
 537
 538         if (mode != lcdc.update_mode) {
 539                 switch (mode) {
 540                 case OMAPFB_AUTO_UPDATE:
 541                         setup_regs();
 542                         load_palette();
 543
 544                         /* Setup and start LCD DMA */
 545                         setup_lcd_dma();
 546
 547                         set_load_mode(OMAP_LCDC_LOAD_FRAME);
 548                         enable_irqs(OMAP_LCDC_IRQ_DONE);
 549                         /* This will start the actual DMA transfer */
 550                         enable_controller();
 551                         lcdc.update_mode = mode;
 552                         break;
 553                 case OMAPFB_UPDATE_DISABLED:
 554                         disable_controller();
 555                         omap_stop_lcd_dma();
 556                         lcdc.update_mode = mode;
 557                         break;
 558                 default:
 559                         r = -EINVAL;
 560                 }
 561         }
 562
 563         return r;
 564 }
 565
 566 static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
 567 {
 568         return lcdc.update_mode;
 569 }
 570
 571 /* PM code called only in internal controller mode */
 572 static void omap_lcdc_suspend(void)
 573 {
 574         omap_lcdc_set_update_mode(OMAPFB_UPDATE_DISABLED);
 575 }
 576
 577 static void omap_lcdc_resume(void)
 578 {
 579         omap_lcdc_set_update_mode(OMAPFB_AUTO_UPDATE);
 580 }
 581
 582 static void omap_lcdc_get_caps(int plane, struct omapfb_caps *caps)
 583 {
 584         return;
 585 }
 586
 587 int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data)
 588 {
 589         BUG_ON(callback == NULL);
 590
 591         if (lcdc.dma_callback)
 592                 return -EBUSY;
 593         else {
 594                 lcdc.dma_callback = callback;
 595                 lcdc.dma_callback_data = data;
 596         }
 597         return 0;
 598 }
 599 EXPORT_SYMBOL(omap_lcdc_set_dma_callback);
 600
 601 void omap_lcdc_free_dma_callback(void)
 602 {
 603         lcdc.dma_callback = NULL;
 604 }
 605 EXPORT_SYMBOL(omap_lcdc_free_dma_callback);
 606
 607 static void lcdc_dma_handler(u16 status, void *data)
 608 {
 609         if (lcdc.dma_callback)
 610                 lcdc.dma_callback(lcdc.dma_callback_data);
 611 }
 612
 613 static int alloc_palette_ram(void)
 614 {
 615         lcdc.palette_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
 616                 MAX_PALETTE_SIZE, &lcdc.palette_phys, GFP_KERNEL);
 617         if (lcdc.palette_virt == NULL) {
 618                 dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n");
 619                 return -ENOMEM;
 620         }
 621         memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE);
 622
 623         return 0;
 624 }
 625
 626 static void free_palette_ram(void)
 627 {
 628         dma_free_writecombine(lcdc.fbdev->dev, MAX_PALETTE_SIZE,
 629                         lcdc.palette_virt, lcdc.palette_phys);
 630 }
 631
 632 static int alloc_fbmem(struct omapfb_mem_region *region)
 633 {
 634         int bpp;
 635         int frame_size;
 636         struct lcd_panel *panel = lcdc.fbdev->panel;
 637
 638         bpp = panel->bpp;
 639         if (bpp == 12)
 640                 bpp = 16;
 641         frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res);
 642         if (region->size > frame_size)
 643                 frame_size = region->size;
 644         lcdc.vram_size = frame_size;
 645         lcdc.vram_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
 646                         lcdc.vram_size, &lcdc.vram_phys, GFP_KERNEL);
 647         if (lcdc.vram_virt == NULL) {
 648                 dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n");
 649                 return -ENOMEM;
 650         }
 651         region->size = frame_size;
 652         region->paddr = lcdc.vram_phys;
 653         region->vaddr = lcdc.vram_virt;
 654         region->alloc = 1;
 655
 656         memset(lcdc.vram_virt, 0, lcdc.vram_size);
 657
 658         return 0;
 659 }
 660
 661 static void free_fbmem(void)
 662 {
 663         dma_free_writecombine(lcdc.fbdev->dev, lcdc.vram_size,
 664                               lcdc.vram_virt, lcdc.vram_phys);
 665 }
 666
 667 static int setup_fbmem(struct omapfb_mem_desc *req_md)
 668 {
 669         if (!req_md->region_cnt) {
 670                 dev_err(lcdc.fbdev->dev, "no memory regions defined\n");
 671                 return -EINVAL;
 672         }
 673
 674         if (req_md->region_cnt > 1) {
 675                 dev_err(lcdc.fbdev->dev, "only one plane is supported\n");
 676                 req_md->region_cnt = 1;
 677         }
 678
 679         return alloc_fbmem(&req_md->region[0]);
 680 }
 681
 682 static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
 683                           struct omapfb_mem_desc *req_vram)
 684 {
 685         int r;
 686         u32 l;
 687         int rate;
 688         struct clk *tc_ck;
 689
 690         lcdc.irq_mask = 0;
 691
 692         lcdc.fbdev = fbdev;
 693         lcdc.ext_mode = ext_mode;
 694
 695         l = 0;
 696         omap_writel(l, OMAP_LCDC_CONTROL);
 697
 698         /* FIXME:
 699          * According to errata some platforms have a clock rate limitiation
 700          */
 701         lcdc.lcd_ck = clk_get(fbdev->dev, "lcd_ck");
 702         if (IS_ERR(lcdc.lcd_ck)) {
 703                 dev_err(fbdev->dev, "unable to access LCD clock\n");
 704                 r = PTR_ERR(lcdc.lcd_ck);
 705                 goto fail0;
 706         }
 707
 708         tc_ck = clk_get(fbdev->dev, "tc_ck");
 709         if (IS_ERR(tc_ck)) {
 710                 dev_err(fbdev->dev, "unable to access TC clock\n");
 711                 r = PTR_ERR(tc_ck);
 712                 goto fail1;
 713         }
 714
 715         rate = clk_get_rate(tc_ck);
 716         clk_put(tc_ck);
 717
 718         if (machine_is_ams_delta())
 719                 rate /= 4;
 720         if (machine_is_omap_h3())
 721                 rate /= 3;
 722         r = clk_set_rate(lcdc.lcd_ck, rate);
 723         if (r) {
 724                 dev_err(fbdev->dev, "failed to adjust LCD rate\n");
 725                 goto fail1;
 726         }
 727         clk_enable(lcdc.lcd_ck);
 728
 729         r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
 730         if (r) {
 731                 dev_err(fbdev->dev, "unable to get IRQ\n");
 732                 goto fail2;
 733         }
 734
 735         r = omap_request_lcd_dma(lcdc_dma_handler, NULL);
 736         if (r) {
 737                 dev_err(fbdev->dev, "unable to get LCD DMA\n");
 738                 goto fail3;
 739         }
 740
 741         omap_set_lcd_dma_single_transfer(ext_mode);
 742         omap_set_lcd_dma_ext_controller(ext_mode);
 743
 744         if (!ext_mode)
 745                 if ((r = alloc_palette_ram()) < 0)
 746                         goto fail4;
 747
 748         if ((r = setup_fbmem(req_vram)) < 0)
 749                 goto fail5;
 750
 751         pr_info("omapfb: LCDC initialized\n");
 752
 753         return 0;
 754 fail5:
 755         if (!ext_mode)
 756                 free_palette_ram();
 757 fail4:
 758         omap_free_lcd_dma();
 759 fail3:
 760         free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
 761 fail2:
 762         clk_disable(lcdc.lcd_ck);
 763 fail1:
 764         clk_put(lcdc.lcd_ck);
 765 fail0:
 766         return r;
 767 }
 768
 769 static void omap_lcdc_cleanup(void)
 770 {
 771         if (!lcdc.ext_mode)
 772                 free_palette_ram();
 773         free_fbmem();
 774         omap_free_lcd_dma();
 775         free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
 776         clk_disable(lcdc.lcd_ck);
 777         clk_put(lcdc.lcd_ck);
 778 }
 779
 780 const struct lcd_ctrl omap1_int_ctrl = {
 781         .name                   = "internal",
 782         .init                   = omap_lcdc_init,
 783         .cleanup                = omap_lcdc_cleanup,
 784         .get_caps               = omap_lcdc_get_caps,
 785         .set_update_mode        = omap_lcdc_set_update_mode,
 786         .get_update_mode        = omap_lcdc_get_update_mode,
 787         .update_window          = NULL,
 788         .suspend                = omap_lcdc_suspend,
 789         .resume                 = omap_lcdc_resume,
 790         .setup_plane            = omap_lcdc_setup_plane,
 791         .enable_plane           = omap_lcdc_enable_plane,
 792         .setcolreg              = omap_lcdc_setcolreg,
 793 };