1 #ifndef __REG_BITS_2700G_
2 #define __REG_BITS_2700G_
4 /* use defines from asm-arm/arch-pxa/bitfields.h for bit fields access */
5 #define UData(Data) ((unsigned long) (Data))
6 #define Fld(Size, Shft) (((Size) << 16) + (Shft))
7 #define FSize(Field) ((Field) >> 16)
8 #define FShft(Field) ((Field) & 0x0000FFFF)
9 #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
10 #define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
11 #define F1stBit(Field) (UData (1) << FShft (Field))
13 #define SYSRST_RST (1 << 0)
15 /* SYSCLKSRC - SYSCLK Source Control Register */
16 #define SYSCLKSRC_SEL Fld(2,0)
17 #define SYSCLKSRC_REF ((0x0) << FShft(SYSCLKSRC_SEL))
18 #define SYSCLKSRC_PLL_1 ((0x1) << FShft(SYSCLKSRC_SEL))
19 #define SYSCLKSRC_PLL_2 ((0x2) << FShft(SYSCLKSRC_SEL))
21 /* PIXCLKSRC - PIXCLK Source Control Register */
22 #define PIXCLKSRC_SEL Fld(2,0)
23 #define PIXCLKSRC_REF ((0x0) << FShft(PIXCLKSRC_SEL))
24 #define PIXCLKSRC_PLL_1 ((0x1) << FShft(PIXCLKSRC_SEL))
25 #define PIXCLKSRC_PLL_2 ((0x2) << FShft(PIXCLKSRC_SEL))
27 /* Clock Disable Register */
28 #define CLKSLEEP_SLP (1 << 0)
30 /* Core PLL Control Register */
31 #define CORE_PLL_M Fld(6,7)
32 #define Core_Pll_M(x) ((x) << FShft(CORE_PLL_M))
33 #define CORE_PLL_N Fld(3,4)
34 #define Core_Pll_N(x) ((x) << FShft(CORE_PLL_N))
35 #define CORE_PLL_P Fld(3,1)
36 #define Core_Pll_P(x) ((x) << FShft(CORE_PLL_P))
37 #define CORE_PLL_EN (1 << 0)
39 /* Display PLL Control Register */
40 #define DISP_PLL_M Fld(6,7)
41 #define Disp_Pll_M(x) ((x) << FShft(DISP_PLL_M))
42 #define DISP_PLL_N Fld(3,4)
43 #define Disp_Pll_N(x) ((x) << FShft(DISP_PLL_N))
44 #define DISP_PLL_P Fld(3,1)
45 #define Disp_Pll_P(x) ((x) << FShft(DISP_PLL_P))
46 #define DISP_PLL_EN (1 << 0)
48 /* PLL status register */
49 #define PLLSTAT_CORE_PLL_LOST_L (1 << 3)
50 #define PLLSTAT_CORE_PLL_LSTS (1 << 2)
51 #define PLLSTAT_DISP_PLL_LOST_L (1 << 1)
52 #define PLLSTAT_DISP_PLL_LSTS (1 << 0)
54 /* Video and scale clock control register */
55 #define VOVRCLK_EN (1 << 0)
57 /* Pixel clock control register */
58 #define PIXCLK_EN (1 << 0)
60 /* Memory clock control register */
61 #define MEMCLK_EN (1 << 0)
63 /* MBX clock control register */
64 #define MBXCLK_DIV Fld(2,2)
65 #define MBXCLK_DIV_1 ((0x0) << FShft(MBXCLK_DIV))
66 #define MBXCLK_DIV_2 ((0x1) << FShft(MBXCLK_DIV))
67 #define MBXCLK_DIV_3 ((0x2) << FShft(MBXCLK_DIV))
68 #define MBXCLK_DIV_4 ((0x3) << FShft(MBXCLK_DIV))
69 #define MBXCLK_EN Fld(2,0)
70 #define MBXCLK_EN_NONE ((0x0) << FShft(MBXCLK_EN))
71 #define MBXCLK_EN_2D ((0x1) << FShft(MBXCLK_EN))
72 #define MBXCLK_EN_BOTH ((0x2) << FShft(MBXCLK_EN))
74 /* M24 clock control register */
75 #define M24CLK_DIV Fld(2,1)
76 #define M24CLK_DIV_1 ((0x0) << FShft(M24CLK_DIV))
77 #define M24CLK_DIV_2 ((0x1) << FShft(M24CLK_DIV))
78 #define M24CLK_DIV_3 ((0x2) << FShft(M24CLK_DIV))
79 #define M24CLK_DIV_4 ((0x3) << FShft(M24CLK_DIV))
80 #define M24CLK_EN (1 << 0)
82 /* SDRAM clock control register */
83 #define SDCLK_EN (1 << 0)
85 /* PixClk Divisor Register */
86 #define PIXCLKDIV_PD Fld(9,0)
87 #define Pixclkdiv_Pd(x) ((x) << FShft(PIXCLKDIV_PD))
89 /* LCD Config control register */
90 #define LCDCFG_IN_FMT Fld(3,28)
91 #define Lcdcfg_In_Fmt(x) ((x) << FShft(LCDCFG_IN_FMT))
92 #define LCDCFG_LCD1DEN_POL (1 << 27)
93 #define LCDCFG_LCD1FCLK_POL (1 << 26)
94 #define LCDCFG_LCD1LCLK_POL (1 << 25)
95 #define LCDCFG_LCD1D_POL (1 << 24)
96 #define LCDCFG_LCD2DEN_POL (1 << 23)
97 #define LCDCFG_LCD2FCLK_POL (1 << 22)
98 #define LCDCFG_LCD2LCLK_POL (1 << 21)
99 #define LCDCFG_LCD2D_POL (1 << 20)
100 #define LCDCFG_LCD1_TS (1 << 19)
101 #define LCDCFG_LCD1D_DS (1 << 18)
102 #define LCDCFG_LCD1C_DS (1 << 17)
103 #define LCDCFG_LCD1_IS_IN (1 << 16)
104 #define LCDCFG_LCD2_TS (1 << 3)
105 #define LCDCFG_LCD2D_DS (1 << 2)
106 #define LCDCFG_LCD2C_DS (1 << 1)
107 #define LCDCFG_LCD2_IS_IN (1 << 0)
109 /* On-Die Frame Buffer Power Control Register */
110 #define ODFBPWR_SLOW (1 << 2)
111 #define ODFBPWR_MODE Fld(2,0)
112 #define ODFBPWR_MODE_ACT ((0x0) << FShft(ODFBPWR_MODE))
113 #define ODFBPWR_MODE_ACT_LP ((0x1) << FShft(ODFBPWR_MODE))
114 #define ODFBPWR_MODE_SLEEP ((0x2) << FShft(ODFBPWR_MODE))
115 #define ODFBPWR_MODE_SHUTD ((0x3) << FShft(ODFBPWR_MODE))
117 /* On-Die Frame Buffer Power State Status Register */
118 #define ODFBSTAT_ACT (1 << 2)
119 #define ODFBSTAT_SLP (1 << 1)
120 #define ODFBSTAT_SDN (1 << 0)
122 /* LMRST - Local Memory (SDRAM) Reset */
123 #define LMRST_MC_RST (1 << 0)
125 /* LMCFG - Local Memory (SDRAM) Configuration Register */
126 #define LMCFG_LMC_DS (1 << 5)
127 #define LMCFG_LMD_DS (1 << 4)
128 #define LMCFG_LMA_DS (1 << 3)
129 #define LMCFG_LMC_TS (1 << 2)
130 #define LMCFG_LMD_TS (1 << 1)
131 #define LMCFG_LMA_TS (1 << 0)
133 /* LMPWR - Local Memory (SDRAM) Power Control Register */
134 #define LMPWR_MC_PWR_CNT Fld(2,0)
135 #define LMPWR_MC_PWR_ACT ((0x0) << FShft(LMPWR_MC_PWR_CNT)) /* Active */
136 #define LMPWR_MC_PWR_SRM ((0x1) << FShft(LMPWR_MC_PWR_CNT)) /* Self-refresh */
137 #define LMPWR_MC_PWR_DPD ((0x3) << FShft(LMPWR_MC_PWR_CNT)) /* deep power down */
139 /* LMPWRSTAT - Local Memory (SDRAM) Power Status Register */
140 #define LMPWRSTAT_MC_PWR_CNT Fld(2,0)
141 #define LMPWRSTAT_MC_PWR_ACT ((0x0) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Active */
142 #define LMPWRSTAT_MC_PWR_SRM ((0x1) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Self-refresh */
143 #define LMPWRSTAT_MC_PWR_DPD ((0x3) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* deep power down */
145 /* LMTYPE - Local Memory (SDRAM) Type Register */
146 #define LMTYPE_CASLAT Fld(3,10)
147 #define LMTYPE_CASLAT_1 ((0x1) << FShft(LMTYPE_CASLAT))
148 #define LMTYPE_CASLAT_2 ((0x2) << FShft(LMTYPE_CASLAT))
149 #define LMTYPE_CASLAT_3 ((0x3) << FShft(LMTYPE_CASLAT))
150 #define LMTYPE_BKSZ Fld(2,8)
151 #define LMTYPE_BKSZ_1 ((0x1) << FShft(LMTYPE_BKSZ))
152 #define LMTYPE_BKSZ_2 ((0x2) << FShft(LMTYPE_BKSZ))
153 #define LMTYPE_ROWSZ Fld(4,4)
154 #define LMTYPE_ROWSZ_11 ((0xb) << FShft(LMTYPE_ROWSZ))
155 #define LMTYPE_ROWSZ_12 ((0xc) << FShft(LMTYPE_ROWSZ))
156 #define LMTYPE_ROWSZ_13 ((0xd) << FShft(LMTYPE_ROWSZ))
157 #define LMTYPE_COLSZ Fld(4,0)
158 #define LMTYPE_COLSZ_7 ((0x7) << FShft(LMTYPE_COLSZ))
159 #define LMTYPE_COLSZ_8 ((0x8) << FShft(LMTYPE_COLSZ))
160 #define LMTYPE_COLSZ_9 ((0x9) << FShft(LMTYPE_COLSZ))
161 #define LMTYPE_COLSZ_10 ((0xa) << FShft(LMTYPE_COLSZ))
162 #define LMTYPE_COLSZ_11 ((0xb) << FShft(LMTYPE_COLSZ))
163 #define LMTYPE_COLSZ_12 ((0xc) << FShft(LMTYPE_COLSZ))
165 /* LMTIM - Local Memory (SDRAM) Timing Register */
166 #define LMTIM_TRAS Fld(4,16)
167 #define Lmtim_Tras(x) ((x) << FShft(LMTIM_TRAS))
168 #define LMTIM_TRP Fld(4,12)
169 #define Lmtim_Trp(x) ((x) << FShft(LMTIM_TRP))
170 #define LMTIM_TRCD Fld(4,8)
171 #define Lmtim_Trcd(x) ((x) << FShft(LMTIM_TRCD))
172 #define LMTIM_TRC Fld(4,4)
173 #define Lmtim_Trc(x) ((x) << FShft(LMTIM_TRC))
174 #define LMTIM_TDPL Fld(4,0)
175 #define Lmtim_Tdpl(x) ((x) << FShft(LMTIM_TDPL))
177 /* LMREFRESH - Local Memory (SDRAM) tREF Control Register */
178 #define LMREFRESH_TREF Fld(2,0)
179 #define Lmrefresh_Tref(x) ((x) << FShft(LMREFRESH_TREF))
181 /* GSCTRL - Graphics surface control register */
182 #define GSCTRL_LUT_EN (1 << 31)
183 #define GSCTRL_GPIXFMT Fld(4,27)
184 #define GSCTRL_GPIXFMT_INDEXED ((0x0) << FShft(GSCTRL_GPIXFMT))
185 #define GSCTRL_GPIXFMT_ARGB4444 ((0x4) << FShft(GSCTRL_GPIXFMT))
186 #define GSCTRL_GPIXFMT_ARGB1555 ((0x5) << FShft(GSCTRL_GPIXFMT))
187 #define GSCTRL_GPIXFMT_RGB888 ((0x6) << FShft(GSCTRL_GPIXFMT))
188 #define GSCTRL_GPIXFMT_RGB565 ((0x7) << FShft(GSCTRL_GPIXFMT))
189 #define GSCTRL_GPIXFMT_ARGB8888 ((0x8) << FShft(GSCTRL_GPIXFMT))
190 #define GSCTRL_GAMMA_EN (1 << 26)
192 #define GSCTRL_GSWIDTH Fld(11,11)
193 #define Gsctrl_Width(Pixel) /* Display Width [1..2048 pix.] */ \
194 (((Pixel) - 1) << FShft(GSCTRL_GSWIDTH))
196 #define GSCTRL_GSHEIGHT Fld(11,0)
197 #define Gsctrl_Height(Pixel) /* Display Height [1..2048 pix.] */ \
198 (((Pixel) - 1) << FShft(GSCTRL_GSHEIGHT))
201 #define GBBASE_GLALPHA Fld(8,24)
202 #define Gbbase_Glalpha(x) ((x) << FShft(GBBASE_GLALPHA))
204 #define GBBASE_COLKEY Fld(24,0)
205 #define Gbbase_Colkey(x) ((x) << FShft(GBBASE_COLKEY))
208 #define GDRCTRL_PIXDBL (1 << 31)
209 #define GDRCTRL_PIXHLV (1 << 30)
210 #define GDRCTRL_LNDBL (1 << 29)
211 #define GDRCTRL_LNHLV (1 << 28)
212 #define GDRCTRL_COLKEYM Fld(24,0)
213 #define Gdrctrl_Colkeym(x) ((x) << FShft(GDRCTRL_COLKEYM))
215 /* GSCADR graphics stream control address register fields */
216 #define GSCADR_STR_EN (1 << 31)
217 #define GSCADR_COLKEY_EN (1 << 30)
218 #define GSCADR_COLKEYSRC (1 << 29)
219 #define GSCADR_BLEND_M Fld(2,27)
220 #define GSCADR_BLEND_NONE ((0x0) << FShft(GSCADR_BLEND_M))
221 #define GSCADR_BLEND_INV ((0x1) << FShft(GSCADR_BLEND_M))
222 #define GSCADR_BLEND_GLOB ((0x2) << FShft(GSCADR_BLEND_M))
223 #define GSCADR_BLEND_PIX ((0x3) << FShft(GSCADR_BLEND_M))
224 #define GSCADR_BLEND_POS Fld(2,24)
225 #define GSCADR_BLEND_GFX ((0x0) << FShft(GSCADR_BLEND_POS))
226 #define GSCADR_BLEND_VID ((0x1) << FShft(GSCADR_BLEND_POS))
227 #define GSCADR_BLEND_CUR ((0x2) << FShft(GSCADR_BLEND_POS))
228 #define GSCADR_GBASE_ADR Fld(23,0)
229 #define Gscadr_Gbase_Adr(x) ((x) << FShft(GSCADR_GBASE_ADR))
231 /* GSADR graphics stride address register fields */
232 #define GSADR_SRCSTRIDE Fld(10,22)
233 #define Gsadr_Srcstride(x) ((x) << FShft(GSADR_SRCSTRIDE))
234 #define GSADR_XSTART Fld(11,11)
235 #define Gsadr_Xstart(x) ((x) << FShft(GSADR_XSTART))
236 #define GSADR_YSTART Fld(11,0)
237 #define Gsadr_Ystart(y) ((y) << FShft(GSADR_YSTART))
239 /* GPLUT graphics palette register fields */
240 #define GPLUT_LUTADR Fld(8,24)
241 #define Gplut_Lutadr(x) ((x) << FShft(GPLUT_LUTADR))
242 #define GPLUT_LUTDATA Fld(24,0)
243 #define Gplut_Lutdata(x) ((x) << FShft(GPLUT_LUTDATA))
245 /* VSCTRL - Video Surface Control Register */
246 #define VSCTRL_VPIXFMT Fld(4,27)
247 #define VSCTRL_VPIXFMT_YUV12 ((0x9) << FShft(VSCTRL_VPIXFMT))
248 #define VSCTRL_VPIXFMT_UY0VY1 ((0xc) << FShft(VSCTRL_VPIXFMT))
249 #define VSCTRL_VPIXFMT_VY0UY1 ((0xd) << FShft(VSCTRL_VPIXFMT))
250 #define VSCTRL_VPIXFMT_Y0UY1V ((0xe) << FShft(VSCTRL_VPIXFMT))
251 #define VSCTRL_VPIXFMT_Y0VY1U ((0xf) << FShft(VSCTRL_VPIXFMT))
252 #define VSCTRL_GAMMA_EN (1 << 26)
253 #define VSCTRL_CSC_EN (1 << 25)
254 #define VSCTRL_COSITED (1 << 22)
255 #define VSCTRL_VSWIDTH Fld(11,11)
256 #define Vsctrl_Width(Pixels) /* Video Width [1-2048] */ \
257 (((Pixels) - 1) << FShft(VSCTRL_VSWIDTH))
258 #define VSCTRL_VSHEIGHT Fld(11,0)
259 #define Vsctrl_Height(Pixels) /* Video Height [1-2048] */ \
260 (((Pixels) - 1) << FShft(VSCTRL_VSHEIGHT))
262 /* VBBASE - Video Blending Base Register */
263 #define VBBASE_GLALPHA Fld(8,24)
264 #define Vbbase_Glalpha(x) ((x) << FShft(VBBASE_GLALPHA))
266 #define VBBASE_COLKEY Fld(24,0)
267 #define Vbbase_Colkey(x) ((x) << FShft(VBBASE_COLKEY))
269 /* VCMSK - Video Color Key Mask Register */
270 #define VCMSK_COLKEY_M Fld(24,0)
271 #define Vcmsk_colkey_m(x) ((x) << FShft(VCMSK_COLKEY_M))
273 /* VSCADR - Video Stream Control Rddress Register */
274 #define VSCADR_STR_EN (1 << 31)
275 #define VSCADR_COLKEY_EN (1 << 30)
276 #define VSCADR_COLKEYSRC (1 << 29)
277 #define VSCADR_BLEND_M Fld(2,27)
278 #define VSCADR_BLEND_NONE ((0x0) << FShft(VSCADR_BLEND_M))
279 #define VSCADR_BLEND_INV ((0x1) << FShft(VSCADR_BLEND_M))
280 #define VSCADR_BLEND_GLOB ((0x2) << FShft(VSCADR_BLEND_M))
281 #define VSCADR_BLEND_PIX ((0x3) << FShft(VSCADR_BLEND_M))
282 #define VSCADR_BLEND_POS Fld(2,24)
283 #define VSCADR_BLEND_GFX ((0x0) << FShft(VSCADR_BLEND_POS))
284 #define VSCADR_BLEND_VID ((0x1) << FShft(VSCADR_BLEND_POS))
285 #define VSCADR_BLEND_CUR ((0x2) << FShft(VSCADR_BLEND_POS))
286 #define VSCADR_VBASE_ADR Fld(23,0)
287 #define Vscadr_Vbase_Adr(x) ((x) << FShft(VSCADR_VBASE_ADR))
289 /* VUBASE - Video U Base Register */
290 #define VUBASE_UVHALFSTR (1 << 31)
291 #define VUBASE_UBASE_ADR Fld(24,0)
292 #define Vubase_Ubase_Adr(x) ((x) << FShft(VUBASE_UBASE_ADR))
294 /* VVBASE - Video V Base Register */
295 #define VVBASE_VBASE_ADR Fld(24,0)
296 #define Vvbase_Vbase_Adr(x) ((x) << FShft(VVBASE_VBASE_ADR))
298 /* VSADR - Video Stride Address Register */
299 #define VSADR_SRCSTRIDE Fld(10,22)
300 #define Vsadr_Srcstride(x) ((x) << FShft(VSADR_SRCSTRIDE))
301 #define VSADR_XSTART Fld(11,11)
302 #define Vsadr_Xstart(x) ((x) << FShft(VSADR_XSTART))
303 #define VSADR_YSTART Fld(11,0)
304 #define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART))
306 /* VSCTRL - Video Surface Control Register */
307 #define VSCTRL_VPIXFMT Fld(4,27)
308 #define VSCTRL_VPIXFMT_YUV12 ((0x9) << FShft(VSCTRL_VPIXFMT))
309 #define VSCTRL_VPIXFMT_UY0VY1 ((0xc) << FShft(VSCTRL_VPIXFMT))
310 #define VSCTRL_VPIXFMT_VY0UY1 ((0xd) << FShft(VSCTRL_VPIXFMT))
311 #define VSCTRL_VPIXFMT_Y0UY1V ((0xe) << FShft(VSCTRL_VPIXFMT))
312 #define VSCTRL_VPIXFMT_Y0VY1U ((0xf) << FShft(VSCTRL_VPIXFMT))
313 #define VSCTRL_GAMMA_EN (1 << 26)
314 #define VSCTRL_CSC_EN (1 << 25)
315 #define VSCTRL_COSITED (1 << 22)
316 #define VSCTRL_VSWIDTH Fld(11,11)
317 #define Vsctrl_Width(Pixels) /* Video Width [1-2048] */ \
318 (((Pixels) - 1) << FShft(VSCTRL_VSWIDTH))
319 #define VSCTRL_VSHEIGHT Fld(11,0)
320 #define Vsctrl_Height(Pixels) /* Video Height [1-2048] */ \
321 (((Pixels) - 1) << FShft(VSCTRL_VSHEIGHT))
323 /* VBBASE - Video Blending Base Register */
324 #define VBBASE_GLALPHA Fld(8,24)
325 #define Vbbase_Glalpha(x) ((x) << FShft(VBBASE_GLALPHA))
327 #define VBBASE_COLKEY Fld(24,0)
328 #define Vbbase_Colkey(x) ((x) << FShft(VBBASE_COLKEY))
330 /* VCMSK - Video Color Key Mask Register */
331 #define VCMSK_COLKEY_M Fld(24,0)
332 #define Vcmsk_colkey_m(x) ((x) << FShft(VCMSK_COLKEY_M))
334 /* VSCADR - Video Stream Control Rddress Register */
335 #define VSCADR_STR_EN (1 << 31)
336 #define VSCADR_COLKEY_EN (1 << 30)
337 #define VSCADR_COLKEYSRC (1 << 29)
338 #define VSCADR_BLEND_M Fld(2,27)
339 #define VSCADR_BLEND_NONE ((0x0) << FShft(VSCADR_BLEND_M))
340 #define VSCADR_BLEND_INV ((0x1) << FShft(VSCADR_BLEND_M))
341 #define VSCADR_BLEND_GLOB ((0x2) << FShft(VSCADR_BLEND_M))
342 #define VSCADR_BLEND_PIX ((0x3) << FShft(VSCADR_BLEND_M))
343 #define VSCADR_BLEND_POS Fld(2,24)
344 #define VSCADR_BLEND_GFX ((0x0) << FShft(VSCADR_BLEND_POS))
345 #define VSCADR_BLEND_VID ((0x1) << FShft(VSCADR_BLEND_POS))
346 #define VSCADR_BLEND_CUR ((0x2) << FShft(VSCADR_BLEND_POS))
347 #define VSCADR_VBASE_ADR Fld(23,0)
348 #define Vscadr_Vbase_Adr(x) ((x) << FShft(VSCADR_VBASE_ADR))
350 /* VUBASE - Video U Base Register */
351 #define VUBASE_UVHALFSTR (1 << 31)
352 #define VUBASE_UBASE_ADR Fld(24,0)
353 #define Vubase_Ubase_Adr(x) ((x) << FShft(VUBASE_UBASE_ADR))
355 /* VVBASE - Video V Base Register */
356 #define VVBASE_VBASE_ADR Fld(24,0)
357 #define Vvbase_Vbase_Adr(x) ((x) << FShft(VVBASE_VBASE_ADR))
359 /* VSADR - Video Stride Address Register */
360 #define VSADR_SRCSTRIDE Fld(10,22)
361 #define Vsadr_Srcstride(x) ((x) << FShft(VSADR_SRCSTRIDE))
362 #define VSADR_XSTART Fld(11,11)
363 #define Vsadr_Xstart(x) ((x) << FShft(VSADR_XSTART))
364 #define VSADR_YSTART Fld(11,0)
365 #define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART))
367 /* HCCTRL - Hardware Cursor Register fields */
368 #define HCCTRL_CUR_EN (1 << 31)
369 #define HCCTRL_COLKEY_EN (1 << 29)
370 #define HCCTRL_COLKEYSRC (1 << 28)
371 #define HCCTRL_BLEND_M Fld(2,26)
372 #define HCCTRL_BLEND_NONE ((0x0) << FShft(HCCTRL_BLEND_M))
373 #define HCCTRL_BLEND_INV ((0x1) << FShft(HCCTRL_BLEND_M))
374 #define HCCTRL_BLEND_GLOB ((0x2) << FShft(HCCTRL_BLEND_M))
375 #define HCCTRL_BLEND_PIX ((0x3) << FShft(HCCTRL_BLEND_M))
376 #define HCCTRL_CPIXFMT Fld(3,23)
377 #define HCCTRL_CPIXFMT_RGB332 ((0x3) << FShft(HCCTRL_CPIXFMT))
378 #define HCCTRL_CPIXFMT_ARGB4444 ((0x4) << FShft(HCCTRL_CPIXFMT))
379 #define HCCTRL_CPIXFMT_ARGB1555 ((0x5) << FShft(HCCTRL_CPIXFMT))
380 #define HCCTRL_CBASE_ADR Fld(23,0)
381 #define Hcctrl_Cbase_Adr(x) ((x) << FShft(HCCTRL_CBASE_ADR))
383 /* HCSIZE Hardware Cursor Size Register fields */
384 #define HCSIZE_BLEND_POS Fld(2,29)
385 #define HCSIZE_BLEND_GFX ((0x0) << FShft(HCSIZE_BLEND_POS))
386 #define HCSIZE_BLEND_VID ((0x1) << FShft(HCSIZE_BLEND_POS))
387 #define HCSIZE_BLEND_CUR ((0x2) << FShft(HCSIZE_BLEND_POS))
388 #define HCSIZE_CWIDTH Fld(3,16)
389 #define Hcsize_Cwidth(x) ((x) << FShft(HCSIZE_CWIDTH))
390 #define HCSIZE_CHEIGHT Fld(3,0)
391 #define Hcsize_Cheight(x) ((x) << FShft(HCSIZE_CHEIGHT))
393 /* HCPOS Hardware Cursor Position Register fields */
394 #define HCPOS_SWITCHSRC (1 << 30)
395 #define HCPOS_CURBLINK Fld(6,24)
396 #define Hcpos_Curblink(x) ((x) << FShft(HCPOS_CURBLINK))
397 #define HCPOS_XSTART Fld(12,12)
398 #define Hcpos_Xstart(x) ((x) << FShft(HCPOS_XSTART))
399 #define HCPOS_YSTART Fld(12,0)
400 #define Hcpos_Ystart(y) ((y) << FShft(HCPOS_YSTART))
402 /* HCBADR Hardware Cursor Blend Address Register */
403 #define HCBADR_GLALPHA Fld(8,24)
404 #define Hcbadr_Glalpha(x) ((x) << FShft(HCBADR_GLALPHA))
405 #define HCBADR_COLKEY Fld(24,0)
406 #define Hcbadr_Colkey(x) ((x) << FShft(HCBADR_COLKEY))
408 /* HCCKMSK - Hardware Cursor Color Key Mask Register */
409 #define HCCKMSK_COLKEY_M Fld(24,0)
410 #define Hcckmsk_Colkey_M(x) ((x) << FShft(HCCKMSK_COLKEY_M))
412 /* DSCTRL - Display sync control register */
413 #define DSCTRL_SYNCGEN_EN (1 << 31)
414 #define DSCTRL_DPL_RST (1 << 29)
415 #define DSCTRL_PWRDN_M (1 << 28)
416 #define DSCTRL_UPDSYNCCNT (1 << 26)
417 #define DSCTRL_UPDINTCNT (1 << 25)
418 #define DSCTRL_UPDCNT (1 << 24)
419 #define DSCTRL_UPDWAIT Fld(4,16)
420 #define Dsctrl_Updwait(x) ((x) << FShft(DSCTRL_UPDWAIT))
421 #define DSCTRL_CLKPOL (1 << 11)
422 #define DSCTRL_CSYNC_EN (1 << 10)
423 #define DSCTRL_VS_SLAVE (1 << 7)
424 #define DSCTRL_HS_SLAVE (1 << 6)
425 #define DSCTRL_BLNK_POL (1 << 5)
426 #define DSCTRL_BLNK_DIS (1 << 4)
427 #define DSCTRL_VS_POL (1 << 3)
428 #define DSCTRL_VS_DIS (1 << 2)
429 #define DSCTRL_HS_POL (1 << 1)
430 #define DSCTRL_HS_DIS (1 << 0)
432 /* DHT01 - Display horizontal timing register 01 */
433 #define DHT01_HBPS Fld(12,16)
434 #define Dht01_Hbps(x) ((x) << FShft(DHT01_HBPS))
435 #define DHT01_HT Fld(12,0)
436 #define Dht01_Ht(x) ((x) << FShft(DHT01_HT))
438 /* DHT02 - Display horizontal timing register 02 */
439 #define DHT02_HAS Fld(12,16)
440 #define Dht02_Has(x) ((x) << FShft(DHT02_HAS))
441 #define DHT02_HLBS Fld(12,0)
442 #define Dht02_Hlbs(x) ((x) << FShft(DHT02_HLBS))
444 /* DHT03 - Display horizontal timing register 03 */
445 #define DHT03_HFPS Fld(12,16)
446 #define Dht03_Hfps(x) ((x) << FShft(DHT03_HFPS))
447 #define DHT03_HRBS Fld(12,0)
448 #define Dht03_Hrbs(x) ((x) << FShft(DHT03_HRBS))
450 /* DVT01 - Display vertical timing register 01 */
451 #define DVT01_VBPS Fld(12,16)
452 #define Dvt01_Vbps(x) ((x) << FShft(DVT01_VBPS))
453 #define DVT01_VT Fld(12,0)
454 #define Dvt01_Vt(x) ((x) << FShft(DVT01_VT))
456 /* DVT02 - Display vertical timing register 02 */
457 #define DVT02_VAS Fld(12,16)
458 #define Dvt02_Vas(x) ((x) << FShft(DVT02_VAS))
459 #define DVT02_VTBS Fld(12,0)
460 #define Dvt02_Vtbs(x) ((x) << FShft(DVT02_VTBS))
462 /* DVT03 - Display vertical timing register 03 */
463 #define DVT03_VFPS Fld(12,16)
464 #define Dvt03_Vfps(x) ((x) << FShft(DVT03_VFPS))
465 #define DVT03_VBBS Fld(12,0)
466 #define Dvt03_Vbbs(x) ((x) << FShft(DVT03_VBBS))
468 /* DVECTRL - display vertical event control register */
469 #define DVECTRL_VEVENT Fld(12,16)
470 #define Dvectrl_Vevent(x) ((x) << FShft(DVECTRL_VEVENT))
471 #define DVECTRL_VFETCH Fld(12,0)
472 #define Dvectrl_Vfetch(x) ((x) << FShft(DVECTRL_VFETCH))
474 /* DHDET - display horizontal DE timing register */
475 #define DHDET_HDES Fld(12,16)
476 #define Dhdet_Hdes(x) ((x) << FShft(DHDET_HDES))
477 #define DHDET_HDEF Fld(12,0)
478 #define Dhdet_Hdef(x) ((x) << FShft(DHDET_HDEF))
480 /* DVDET - display vertical DE timing register */
481 #define DVDET_VDES Fld(12,16)
482 #define Dvdet_Vdes(x) ((x) << FShft(DVDET_VDES))
483 #define DVDET_VDEF Fld(12,0)
484 #define Dvdet_Vdef(x) ((x) << FShft(DVDET_VDEF))
486 /* DODMSK - display output data mask register */
487 #define DODMSK_MASK_LVL (1 << 31)
488 #define DODMSK_BLNK_LVL (1 << 30)
489 #define DODMSK_MASK_B Fld(8,16)
490 #define Dodmsk_Mask_B(x) ((x) << FShft(DODMSK_MASK_B))
491 #define DODMSK_MASK_G Fld(8,8)
492 #define Dodmsk_Mask_G(x) ((x) << FShft(DODMSK_MASK_G))
493 #define DODMSK_MASK_R Fld(8,0)
494 #define Dodmsk_Mask_R(x) ((x) << FShft(DODMSK_MASK_R))
496 /* DBCOL - display border color control register */
497 #define DBCOL_BORDCOL Fld(24,0)
498 #define Dbcol_Bordcol(x) ((x) << FShft(DBCOL_BORDCOL))
500 /* DVLNUM - display vertical line number register */
501 #define DVLNUM_VLINE Fld(12,0)
502 #define Dvlnum_Vline(x) ((x) << FShft(DVLNUM_VLINE))
504 /* DMCTRL - Display Memory Control Register */
505 #define DMCTRL_MEM_REF Fld(2,30)
506 #define DMCTRL_MEM_REF_ACT ((0x0) << FShft(DMCTRL_MEM_REF))
507 #define DMCTRL_MEM_REF_HB ((0x1) << FShft(DMCTRL_MEM_REF))
508 #define DMCTRL_MEM_REF_VB ((0x2) << FShft(DMCTRL_MEM_REF))
509 #define DMCTRL_MEM_REF_BOTH ((0x3) << FShft(DMCTRL_MEM_REF))
510 #define DMCTRL_UV_THRHLD Fld(6,24)
511 #define Dmctrl_Uv_Thrhld(x) ((x) << FShft(DMCTRL_UV_THRHLD))
512 #define DMCTRL_V_THRHLD Fld(7,16)
513 #define Dmctrl_V_Thrhld(x) ((x) << FShft(DMCTRL_V_THRHLD))
514 #define DMCTRL_D_THRHLD Fld(7,8)
515 #define Dmctrl_D_Thrhld(x) ((x) << FShft(DMCTRL_D_THRHLD))
516 #define DMCTRL_BURSTLEN Fld(6,0)
517 #define Dmctrl_Burstlen(x) ((x) << FShft(DMCTRL_BURSTLEN))
519 /* DINTRS - Display Interrupt Status Register */
520 #define DINTRS_CUR_OR_S (1 << 18)
521 #define DINTRS_STR2_OR_S (1 << 17)
522 #define DINTRS_STR1_OR_S (1 << 16)
523 #define DINTRS_CUR_UR_S (1 << 6)
524 #define DINTRS_STR2_UR_S (1 << 5)
525 #define DINTRS_STR1_UR_S (1 << 4)
526 #define DINTRS_VEVENT1_S (1 << 3)
527 #define DINTRS_VEVENT0_S (1 << 2)
528 #define DINTRS_HBLNK1_S (1 << 1)
529 #define DINTRS_HBLNK0_S (1 << 0)
531 /* DINTRE - Display Interrupt Enable Register */
532 #define DINTRE_CUR_OR_EN (1 << 18)
533 #define DINTRE_STR2_OR_EN (1 << 17)
534 #define DINTRE_STR1_OR_EN (1 << 16)
535 #define DINTRE_CUR_UR_EN (1 << 6)
536 #define DINTRE_STR2_UR_EN (1 << 5)
537 #define DINTRE_STR1_UR_EN (1 << 4)
538 #define DINTRE_VEVENT1_EN (1 << 3)
539 #define DINTRE_VEVENT0_EN (1 << 2)
540 #define DINTRE_HBLNK1_EN (1 << 1)
541 #define DINTRE_HBLNK0_EN (1 << 0)
543 /* DINTRS - Display Interrupt Status Register */
544 #define DINTRS_CUR_OR_S (1 << 18)
545 #define DINTRS_STR2_OR_S (1 << 17)
546 #define DINTRS_STR1_OR_S (1 << 16)
547 #define DINTRS_CUR_UR_S (1 << 6)
548 #define DINTRS_STR2_UR_S (1 << 5)
549 #define DINTRS_STR1_UR_S (1 << 4)
550 #define DINTRS_VEVENT1_S (1 << 3)
551 #define DINTRS_VEVENT0_S (1 << 2)
552 #define DINTRS_HBLNK1_S (1 << 1)
553 #define DINTRS_HBLNK0_S (1 << 0)
555 /* DINTRE - Display Interrupt Enable Register */
556 #define DINTRE_CUR_OR_EN (1 << 18)
557 #define DINTRE_STR2_OR_EN (1 << 17)
558 #define DINTRE_STR1_OR_EN (1 << 16)
559 #define DINTRE_CUR_UR_EN (1 << 6)
560 #define DINTRE_STR2_UR_EN (1 << 5)
561 #define DINTRE_STR1_UR_EN (1 << 4)
562 #define DINTRE_VEVENT1_EN (1 << 3)
563 #define DINTRE_VEVENT0_EN (1 << 2)
564 #define DINTRE_HBLNK1_EN (1 << 1)
565 #define DINTRE_HBLNK0_EN (1 << 0)
568 /* DLSTS - display load status register */
569 #define DLSTS_RLD_ADONE (1 << 23)
570 /* #define DLSTS_RLD_ADOUT Fld(23,0) */
572 /* DLLCTRL - display list load control register */
573 #define DLLCTRL_RLD_ADRLN Fld(8,24)
574 #define Dllctrl_Rld_Adrln(x) ((x) << FShft(DLLCTRL_RLD_ADRLN))
576 /* CLIPCTRL - Clipping Control Register */
577 #define CLIPCTRL_HSKIP Fld(11,16)
578 #define Clipctrl_Hskip ((x) << FShft(CLIPCTRL_HSKIP))
579 #define CLIPCTRL_VSKIP Fld(11,0)
580 #define Clipctrl_Vskip ((x) << FShft(CLIPCTRL_VSKIP))
582 /* SPOCTRL - Scale Pitch/Order Control Register */
583 #define SPOCTRL_H_SC_BP (1 << 31)
584 #define SPOCTRL_V_SC_BP (1 << 30)
585 #define SPOCTRL_HV_SC_OR (1 << 29)
586 #define SPOCTRL_VS_UR_C (1 << 27)
587 #define SPOCTRL_VORDER Fld(2,16)
588 #define SPOCTRL_VORDER_1TAP ((0x0) << FShft(SPOCTRL_VORDER))
589 #define SPOCTRL_VORDER_2TAP ((0x1) << FShft(SPOCTRL_VORDER))
590 #define SPOCTRL_VORDER_4TAP ((0x3) << FShft(SPOCTRL_VORDER))
591 #define SPOCTRL_VPITCH Fld(16,0)
592 #define Spoctrl_Vpitch(x) ((x) << FShft(SPOCTRL_VPITCH))
594 /* SVCTRL - Scale Vertical Control Register */
595 #define SVCTRL_INITIAL1 Fld(16,16)
596 #define Svctrl_Initial1(x) ((x) << FShft(SVCTRL_INITIAL1))
597 #define SVCTRL_INITIAL2 Fld(16,0)
598 #define Svctrl_Initial2(x) ((x) << FShft(SVCTRL_INITIAL2))
600 /* SHCTRL - Scale Horizontal Control Register */
601 #define SHCTRL_HINITIAL Fld(16,16)
602 #define Shctrl_Hinitial(x) ((x) << FShft(SHCTRL_HINITIAL))
603 #define SHCTRL_HDECIM (1 << 15)
604 #define SHCTRL_HPITCH Fld(15,0)
605 #define Shctrl_Hpitch(x) ((x) << FShft(SHCTRL_HPITCH))
607 /* SSSIZE - Scale Surface Size Register */
608 #define SSSIZE_SC_WIDTH Fld(11,16)
609 #define Sssize_Sc_Width(x) ((x) << FShft(SSSIZE_SC_WIDTH))
610 #define SSSIZE_SC_HEIGHT Fld(11,0)
611 #define Sssize_Sc_Height(x) ((x) << FShft(SSSIZE_SC_HEIGHT))
613 #endif /* __REG_BITS_2700G_ */
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