2 * xHCI host controller driver PCI Bus Glue.
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/acpi.h>
29 #include "xhci-trace.h"
31 #define SSIC_PORT_NUM 2
32 #define SSIC_PORT_CFG2 0x880c
33 #define SSIC_PORT_CFG2_OFFSET 0x30
34 #define PROG_DONE (1 << 30)
35 #define SSIC_PORT_UNUSED (1 << 31)
37 /* Device for a quirk */
38 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
42 #define PCI_VENDOR_ID_ETRON 0x1b6f
43 #define PCI_DEVICE_ID_EJ168 0x7023
45 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
47 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
48 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
49 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
50 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
52 static const char hcd_name[] = "xhci_hcd";
54 static struct hc_driver __read_mostly xhci_pci_hc_driver;
56 static int xhci_pci_setup(struct usb_hcd *hcd);
58 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
59 .extra_priv_size = sizeof(struct xhci_hcd),
60 .reset = xhci_pci_setup,
63 /* called after powerup, by probe or system-pm "wakeup" */
64 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
67 * TODO: Implement finding debug ports later.
68 * TODO: see if there are any quirks that need to be added to handle
69 * new extended capabilities.
72 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
73 if (!pci_set_mwi(pdev))
74 xhci_dbg(xhci, "MWI active\n");
76 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
80 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
82 struct pci_dev *pdev = to_pci_dev(dev);
84 /* Look for vendor-specific quirks */
85 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
86 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
87 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
88 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
89 pdev->revision == 0x0) {
90 xhci->quirks |= XHCI_RESET_EP_QUIRK;
91 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
92 "QUIRK: Fresco Logic xHC needs configure"
93 " endpoint cmd after reset endpoint");
95 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
96 pdev->revision == 0x4) {
97 xhci->quirks |= XHCI_SLOW_SUSPEND;
98 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
99 "QUIRK: Fresco Logic xHC revision %u"
100 "must be suspended extra slowly",
103 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
104 xhci->quirks |= XHCI_BROKEN_STREAMS;
105 /* Fresco Logic confirms: all revisions of this chip do not
106 * support MSI, even though some of them claim to in their PCI
109 xhci->quirks |= XHCI_BROKEN_MSI;
110 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
111 "QUIRK: Fresco Logic revision %u "
112 "has broken MSI implementation",
114 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
117 if (pdev->vendor == PCI_VENDOR_ID_NEC)
118 xhci->quirks |= XHCI_NEC_HOST;
120 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
121 xhci->quirks |= XHCI_AMD_0x96_HOST;
124 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
125 xhci->quirks |= XHCI_AMD_PLL_FIX;
127 if (pdev->vendor == PCI_VENDOR_ID_AMD)
128 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
130 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
131 xhci->quirks |= XHCI_LPM_SUPPORT;
132 xhci->quirks |= XHCI_INTEL_HOST;
133 xhci->quirks |= XHCI_AVOID_BEI;
135 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
136 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
137 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
138 xhci->limit_active_eps = 64;
139 xhci->quirks |= XHCI_SW_BW_CHECKING;
141 * PPT desktop boards DH77EB and DH77DF will power back on after
142 * a few seconds of being shutdown. The fix for this is to
143 * switch the ports from xHCI to EHCI on shutdown. We can't use
144 * DMI information to find those particular boards (since each
145 * vendor will change the board name), so we have to key off all
148 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
150 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
151 pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
152 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
153 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
155 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
156 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
157 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
158 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
159 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI)) {
160 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
162 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
163 pdev->device == PCI_DEVICE_ID_EJ168) {
164 xhci->quirks |= XHCI_RESET_ON_RESUME;
165 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
166 xhci->quirks |= XHCI_BROKEN_STREAMS;
168 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
169 pdev->device == 0x0015)
170 xhci->quirks |= XHCI_RESET_ON_RESUME;
171 if (pdev->vendor == PCI_VENDOR_ID_VIA)
172 xhci->quirks |= XHCI_RESET_ON_RESUME;
174 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
175 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
176 pdev->device == 0x3432)
177 xhci->quirks |= XHCI_BROKEN_STREAMS;
179 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
180 pdev->device == 0x1042)
181 xhci->quirks |= XHCI_BROKEN_STREAMS;
183 if (xhci->quirks & XHCI_RESET_ON_RESUME)
184 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
185 "QUIRK: Resetting on resume");
189 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
191 static const u8 intel_dsm_uuid[] = {
192 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
193 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
195 union acpi_object *obj;
197 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
202 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
203 #endif /* CONFIG_ACPI */
205 /* called during probe() after chip reset completes */
206 static int xhci_pci_setup(struct usb_hcd *hcd)
208 struct xhci_hcd *xhci;
209 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
212 xhci = hcd_to_xhci(hcd);
214 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
216 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
220 if (!usb_hcd_is_primary_hcd(hcd))
223 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
225 /* Find any debug ports */
226 retval = xhci_pci_reinit(xhci, pdev);
234 * We need to register our own PCI probe function (instead of the USB core's
235 * function) in order to create a second roothub under xHCI.
237 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
240 struct xhci_hcd *xhci;
241 struct hc_driver *driver;
244 driver = (struct hc_driver *)id->driver_data;
246 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
247 pm_runtime_get_noresume(&dev->dev);
249 /* Register the USB 2.0 roothub.
250 * FIXME: USB core must know to register the USB 2.0 roothub first.
251 * This is sort of silly, because we could just set the HCD driver flags
252 * to say USB 2.0, but I'm not sure what the implications would be in
253 * the other parts of the HCD code.
255 retval = usb_hcd_pci_probe(dev, id);
260 /* USB 2.0 roothub is stored in the PCI device now. */
261 hcd = dev_get_drvdata(&dev->dev);
262 xhci = hcd_to_xhci(hcd);
263 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
265 if (!xhci->shared_hcd) {
267 goto dealloc_usb2_hcd;
270 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
274 /* Roothub already marked as USB 3.0 speed */
276 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
277 HCC_MAX_PSA(xhci->hcc_params) >= 4)
278 xhci->shared_hcd->can_do_streams = 1;
280 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
281 xhci_pme_acpi_rtd3_enable(dev);
283 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
284 pm_runtime_put_noidle(&dev->dev);
289 usb_put_hcd(xhci->shared_hcd);
291 usb_hcd_pci_remove(dev);
293 pm_runtime_put_noidle(&dev->dev);
297 static void xhci_pci_remove(struct pci_dev *dev)
299 struct xhci_hcd *xhci;
301 xhci = hcd_to_xhci(pci_get_drvdata(dev));
302 if (xhci->shared_hcd) {
303 usb_remove_hcd(xhci->shared_hcd);
304 usb_put_hcd(xhci->shared_hcd);
306 usb_hcd_pci_remove(dev);
308 /* Workaround for spurious wakeups at shutdown with HSW */
309 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
310 pci_set_power_state(dev, PCI_D3hot);
315 * In some Intel xHCI controllers, in order to get D3 working,
316 * through a vendor specific SSIC CONFIG register at offset 0x883c,
317 * SSIC PORT need to be marked as "unused" before putting xHCI
318 * into D3. After D3 exit, the SSIC port need to be marked as "used".
319 * Without this change, xHCI might not enter D3 state.
320 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
321 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
323 static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend)
325 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
326 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
331 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
332 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
334 for (i = 0; i < SSIC_PORT_NUM; i++) {
335 reg = (void __iomem *) xhci->cap_regs +
337 i * SSIC_PORT_CFG2_OFFSET;
340 * Notify SSIC that SSIC profile programming
343 val = readl(reg) & ~PROG_DONE;
346 /* Mark SSIC port as unused(suspend) or used(resume) */
349 val |= SSIC_PORT_UNUSED;
351 val &= ~SSIC_PORT_UNUSED;
354 /* Notify SSIC that SSIC profile programming is done */
355 val = readl(reg) | PROG_DONE;
361 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
363 writel(val | BIT(28), reg);
367 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
369 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
370 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
373 * Systems with the TI redriver that loses port status change events
374 * need to have the registers polled during D3, so avoid D3cold.
376 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
377 pdev->no_d3cold = true;
379 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
380 xhci_pme_quirk(hcd, true);
382 return xhci_suspend(xhci, do_wakeup);
385 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
387 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
388 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
391 /* The BIOS on systems with the Intel Panther Point chipset may or may
392 * not support xHCI natively. That means that during system resume, it
393 * may switch the ports back to EHCI so that users can use their
394 * keyboard to select a kernel from GRUB after resume from hibernate.
396 * The BIOS is supposed to remember whether the OS had xHCI ports
397 * enabled before resume, and switch the ports back to xHCI when the
398 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
401 * Unconditionally switch the ports back to xHCI after a system resume.
402 * It should not matter whether the EHCI or xHCI controller is
403 * resumed first. It's enough to do the switchover in xHCI because
404 * USB core won't notice anything as the hub driver doesn't start
405 * running again until after all the devices (including both EHCI and
406 * xHCI host controllers) have been resumed.
409 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
410 usb_enable_intel_xhci_ports(pdev);
412 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
413 xhci_pme_quirk(hcd, false);
415 retval = xhci_resume(xhci, hibernated);
418 #endif /* CONFIG_PM */
420 /*-------------------------------------------------------------------------*/
422 /* PCI driver selection metadata; PCI hotplugging uses this */
423 static const struct pci_device_id pci_ids[] = { {
424 /* handle any USB 3.0 xHCI controller */
425 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
426 .driver_data = (unsigned long) &xhci_pci_hc_driver,
428 { /* end: all zeroes */ }
430 MODULE_DEVICE_TABLE(pci, pci_ids);
432 /* pci driver glue; this is a "new style" PCI driver module */
433 static struct pci_driver xhci_pci_driver = {
434 .name = (char *) hcd_name,
437 .probe = xhci_pci_probe,
438 .remove = xhci_pci_remove,
439 /* suspend and resume implemented later */
441 .shutdown = usb_hcd_pci_shutdown,
444 .pm = &usb_hcd_pci_pm_ops
449 static int __init xhci_pci_init(void)
451 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
453 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
454 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
456 return pci_register_driver(&xhci_pci_driver);
458 module_init(xhci_pci_init);
460 static void __exit xhci_pci_exit(void)
462 pci_unregister_driver(&xhci_pci_driver);
464 module_exit(xhci_pci_exit);
466 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
467 MODULE_LICENSE("GPL");