kernel/drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  43 {
  44         switch (state) {
  45         case EP0_UNCONNECTED:
  46                 return "Unconnected";
  47         case EP0_SETUP_PHASE:
  48                 return "Setup Phase";
  49         case EP0_DATA_PHASE:
  50                 return "Data Phase";
  51         case EP0_STATUS_PHASE:
  52                 return "Status Phase";
  53         default:
  54                 return "UNKNOWN";
  55         }
  56 }
  57
  58 static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum,
  59                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  60 {
  61         struct dwc3_trb                 *trb;
  62         struct dwc3_ep                  *dep;
  63
  64         dep = dwc->eps[epnum];
  65
  66         trb = &dwc->ep0_trb[dep->free_slot];
  67
  68         if (chain)
  69                 dep->free_slot++;
  70
  71         trb->bpl = lower_32_bits(buf_dma);
  72         trb->bph = upper_32_bits(buf_dma);
  73         trb->size = len;
  74         trb->ctrl = type;
  75
  76         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  77                         | DWC3_TRB_CTRL_ISP_IMI);
  78
  79         if (chain)
  80                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  81         else
  82                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  83                                 | DWC3_TRB_CTRL_LST);
  84
  85         trace_dwc3_prepare_trb(dep, trb);
  86 }
  87
  88 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum)
  89 {
  90         struct dwc3_gadget_ep_cmd_params params;
  91         struct dwc3_ep                  *dep;
  92         int                             ret;
  93
  94         dep = dwc->eps[epnum];
  95         if (dep->flags & DWC3_EP_BUSY) {
  96                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  97                 return 0;
  98         }
  99
 100         memset(&params, 0, sizeof(params));
 101         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 102         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 103
 104         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 105                         DWC3_DEPCMD_STARTTRANSFER, &params);
 106         if (ret < 0) {
 107                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
 108                                 dep->name);
 109                 return ret;
 110         }
 111
 112         dep->flags |= DWC3_EP_BUSY;
 113         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 114                         dep->number);
 115
 116         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 117
 118         return 0;
 119 }
 120
 121 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 122                 struct dwc3_request *req)
 123 {
 124         struct dwc3             *dwc = dep->dwc;
 125
 126         req->request.actual     = 0;
 127         req->request.status     = -EINPROGRESS;
 128         req->epnum              = dep->number;
 129
 130         list_add_tail(&req->list, &dep->request_list);
 131
 132         /*
 133          * Gadget driver might not be quick enough to queue a request
 134          * before we get a Transfer Not Ready event on this endpoint.
 135          *
 136          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 137          * flag is set, it's telling us that as soon as Gadget queues the
 138          * required request, we should kick the transfer here because the
 139          * IRQ we were waiting for is long gone.
 140          */
 141         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 142                 unsigned        direction;
 143
 144                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 145
 146                 if (dwc->ep0state != EP0_DATA_PHASE) {
 147                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 148                         return 0;
 149                 }
 150
 151                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 152
 153                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 154                                 DWC3_EP0_DIR_IN);
 155
 156                 return 0;
 157         }
 158
 159         /*
 160          * In case gadget driver asked us to delay the STATUS phase,
 161          * handle it here.
 162          */
 163         if (dwc->delayed_status) {
 164                 unsigned        direction;
 165
 166                 direction = !dwc->ep0_expect_in;
 167                 dwc->delayed_status = false;
 168                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 169
 170                 if (dwc->ep0state == EP0_STATUS_PHASE)
 171                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 172                 else
 173                         dwc3_trace(trace_dwc3_ep0,
 174                                         "too early for delayed status");
 175
 176                 return 0;
 177         }
 178
 179         /*
 180          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 181          *
 182          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 183          * come before issueing Start Transfer command, but if we do, we will
 184          * miss situations where the host starts another SETUP phase instead of
 185          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 186          * Layer Compliance Suite.
 187          *
 188          * The problem surfaces due to the fact that in case of back-to-back
 189          * SETUP packets there will be no XferNotReady(DATA) generated and we
 190          * will be stuck waiting for XferNotReady(DATA) forever.
 191          *
 192          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 193          * it tells us to start Data Phase right away. It also mentions that if
 194          * we receive a SETUP phase instead of the DATA phase, core will issue
 195          * XferComplete for the DATA phase, before actually initiating it in
 196          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 197          * can only be used to print some debugging logs, as the core expects
 198          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 199          * just so it completes right away, without transferring anything and,
 200          * only then, we can go back to the SETUP phase.
 201          *
 202          * Because of this scenario, SNPS decided to change the programming
 203          * model of control transfers and support on-demand transfers only for
 204          * the STATUS phase. To fix the issue we have now, we will always wait
 205          * for gadget driver to queue the DATA phase's struct usb_request, then
 206          * start it right away.
 207          *
 208          * If we're actually in a 2-stage transfer, we will wait for
 209          * XferNotReady(STATUS).
 210          */
 211         if (dwc->three_stage_setup) {
 212                 unsigned        direction;
 213
 214                 direction = dwc->ep0_expect_in;
 215                 dwc->ep0state = EP0_DATA_PHASE;
 216
 217                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 218
 219                 dep->flags &= ~DWC3_EP0_DIR_IN;
 220         }
 221
 222         return 0;
 223 }
 224
 225 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 226                 gfp_t gfp_flags)
 227 {
 228         struct dwc3_request             *req = to_dwc3_request(request);
 229         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 230         struct dwc3                     *dwc = dep->dwc;
 231
 232         unsigned long                   flags;
 233
 234         int                             ret;
 235
 236         spin_lock_irqsave(&dwc->lock, flags);
 237         if (!dep->endpoint.desc) {
 238                 dwc3_trace(trace_dwc3_ep0,
 239                                 "trying to queue request %p to disabled %s",
 240                                 request, dep->name);
 241                 ret = -ESHUTDOWN;
 242                 goto out;
 243         }
 244
 245         /* we share one TRB for ep0/1 */
 246         if (!list_empty(&dep->request_list)) {
 247                 ret = -EBUSY;
 248                 goto out;
 249         }
 250
 251         dwc3_trace(trace_dwc3_ep0,
 252                         "queueing request %p to %s length %d state '%s'",
 253                         request, dep->name, request->length,
 254                         dwc3_ep0_state_string(dwc->ep0state));
 255
 256         ret = __dwc3_gadget_ep0_queue(dep, req);
 257
 258 out:
 259         spin_unlock_irqrestore(&dwc->lock, flags);
 260
 261         return ret;
 262 }
 263
 264 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 265 {
 266         struct dwc3_ep          *dep;
 267
 268         /* reinitialize physical ep1 */
 269         dep = dwc->eps[1];
 270         dep->flags = DWC3_EP_ENABLED;
 271
 272         /* stall is always issued on EP0 */
 273         dep = dwc->eps[0];
 274         __dwc3_gadget_ep_set_halt(dep, 1, false);
 275         dep->flags = DWC3_EP_ENABLED;
 276         dwc->delayed_status = false;
 277
 278         if (!list_empty(&dep->request_list)) {
 279                 struct dwc3_request     *req;
 280
 281                 req = next_request(&dep->request_list);
 282                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 283         }
 284
 285         dwc->ep0state = EP0_SETUP_PHASE;
 286         dwc3_ep0_out_start(dwc);
 287 }
 288
 289 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 290 {
 291         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 292         struct dwc3                     *dwc = dep->dwc;
 293
 294         dwc3_ep0_stall_and_restart(dwc);
 295
 296         return 0;
 297 }
 298
 299 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 300 {
 301         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 302         struct dwc3                     *dwc = dep->dwc;
 303         unsigned long                   flags;
 304         int                             ret;
 305
 306         spin_lock_irqsave(&dwc->lock, flags);
 307         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 308         spin_unlock_irqrestore(&dwc->lock, flags);
 309
 310         return ret;
 311 }
 312
 313 void dwc3_ep0_out_start(struct dwc3 *dwc)
 314 {
 315         int                             ret;
 316
 317         dwc3_ep0_prepare_one_trb(dwc, 0, dwc->ctrl_req_addr, 8,
 318                         DWC3_TRBCTL_CONTROL_SETUP, false);
 319         ret = dwc3_ep0_start_trans(dwc, 0);
 320         WARN_ON(ret < 0);
 321 }
 322
 323 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 324 {
 325         struct dwc3_ep          *dep;
 326         u32                     windex = le16_to_cpu(wIndex_le);
 327         u32                     epnum;
 328
 329         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 330         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 331                 epnum |= 1;
 332
 333         dep = dwc->eps[epnum];
 334         if (dep->flags & DWC3_EP_ENABLED)
 335                 return dep;
 336
 337         return NULL;
 338 }
 339
 340 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 341 {
 342 }
 343 /*
 344  * ch 9.4.5
 345  */
 346 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 347                 struct usb_ctrlrequest *ctrl)
 348 {
 349         struct dwc3_ep          *dep;
 350         u32                     recip;
 351         u32                     reg;
 352         u16                     usb_status = 0;
 353         __le16                  *response_pkt;
 354
 355         recip = ctrl->bRequestType & USB_RECIP_MASK;
 356         switch (recip) {
 357         case USB_RECIP_DEVICE:
 358                 /*
 359                  * LTM will be set once we know how to set this in HW.
 360                  */
 361                 usb_status |= dwc->gadget.is_selfpowered;
 362
 363                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 364                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 365                         if (reg & DWC3_DCTL_INITU1ENA)
 366                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 367                         if (reg & DWC3_DCTL_INITU2ENA)
 368                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 369                 }
 370
 371                 break;
 372
 373         case USB_RECIP_INTERFACE:
 374                 /*
 375                  * Function Remote Wake Capable D0
 376                  * Function Remote Wakeup       D1
 377                  */
 378                 break;
 379
 380         case USB_RECIP_ENDPOINT:
 381                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 382                 if (!dep)
 383                         return -EINVAL;
 384
 385                 if (dep->flags & DWC3_EP_STALL)
 386                         usb_status = 1 << USB_ENDPOINT_HALT;
 387                 break;
 388         default:
 389                 return -EINVAL;
 390         }
 391
 392         response_pkt = (__le16 *) dwc->setup_buf;
 393         *response_pkt = cpu_to_le16(usb_status);
 394
 395         dep = dwc->eps[0];
 396         dwc->ep0_usb_req.dep = dep;
 397         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 398         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 399         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 400
 401         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 402 }
 403
 404 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 405                 struct usb_ctrlrequest *ctrl, int set)
 406 {
 407         struct dwc3_ep          *dep;
 408         u32                     recip;
 409         u32                     wValue;
 410         u32                     wIndex;
 411         u32                     reg;
 412         int                     ret;
 413         enum usb_device_state   state;
 414
 415         wValue = le16_to_cpu(ctrl->wValue);
 416         wIndex = le16_to_cpu(ctrl->wIndex);
 417         recip = ctrl->bRequestType & USB_RECIP_MASK;
 418         state = dwc->gadget.state;
 419
 420         switch (recip) {
 421         case USB_RECIP_DEVICE:
 422
 423                 switch (wValue) {
 424                 case USB_DEVICE_REMOTE_WAKEUP:
 425                         break;
 426                 /*
 427                  * 9.4.1 says only only for SS, in AddressState only for
 428                  * default control pipe
 429                  */
 430                 case USB_DEVICE_U1_ENABLE:
 431                         if (state != USB_STATE_CONFIGURED)
 432                                 return -EINVAL;
 433                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 434                                 return -EINVAL;
 435
 436                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 437                         if (set)
 438                                 reg |= DWC3_DCTL_INITU1ENA;
 439                         else
 440                                 reg &= ~DWC3_DCTL_INITU1ENA;
 441                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 442                         break;
 443
 444                 case USB_DEVICE_U2_ENABLE:
 445                         if (state != USB_STATE_CONFIGURED)
 446                                 return -EINVAL;
 447                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 448                                 return -EINVAL;
 449
 450                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 451                         if (set)
 452                                 reg |= DWC3_DCTL_INITU2ENA;
 453                         else
 454                                 reg &= ~DWC3_DCTL_INITU2ENA;
 455                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 456                         break;
 457
 458                 case USB_DEVICE_LTM_ENABLE:
 459                         return -EINVAL;
 460
 461                 case USB_DEVICE_TEST_MODE:
 462                         if ((wIndex & 0xff) != 0)
 463                                 return -EINVAL;
 464                         if (!set)
 465                                 return -EINVAL;
 466
 467                         dwc->test_mode_nr = wIndex >> 8;
 468                         dwc->test_mode = true;
 469                         break;
 470                 default:
 471                         return -EINVAL;
 472                 }
 473                 break;
 474
 475         case USB_RECIP_INTERFACE:
 476                 switch (wValue) {
 477                 case USB_INTRF_FUNC_SUSPEND:
 478                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 479                                 /* XXX enable Low power suspend */
 480                                 ;
 481                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 482                                 /* XXX enable remote wakeup */
 483                                 ;
 484                         break;
 485                 default:
 486                         return -EINVAL;
 487                 }
 488                 break;
 489
 490         case USB_RECIP_ENDPOINT:
 491                 switch (wValue) {
 492                 case USB_ENDPOINT_HALT:
 493                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 494                         if (!dep)
 495                                 return -EINVAL;
 496                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 497                                 break;
 498                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 499                         if (ret)
 500                                 return -EINVAL;
 501                         break;
 502                 default:
 503                         return -EINVAL;
 504                 }
 505                 break;
 506
 507         default:
 508                 return -EINVAL;
 509         }
 510
 511         return 0;
 512 }
 513
 514 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 515 {
 516         enum usb_device_state state = dwc->gadget.state;
 517         u32 addr;
 518         u32 reg;
 519
 520         addr = le16_to_cpu(ctrl->wValue);
 521         if (addr > 127) {
 522                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 523                 return -EINVAL;
 524         }
 525
 526         if (state == USB_STATE_CONFIGURED) {
 527                 dwc3_trace(trace_dwc3_ep0,
 528                                 "trying to set address when configured");
 529                 return -EINVAL;
 530         }
 531
 532         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 533         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 534         reg |= DWC3_DCFG_DEVADDR(addr);
 535         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 536
 537         if (addr)
 538                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 539         else
 540                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 541
 542         return 0;
 543 }
 544
 545 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 546 {
 547         int ret;
 548
 549         spin_unlock(&dwc->lock);
 550         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 551         spin_lock(&dwc->lock);
 552         return ret;
 553 }
 554
 555 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 556 {
 557         enum usb_device_state state = dwc->gadget.state;
 558         u32 cfg;
 559         int ret;
 560         u32 reg;
 561
 562         cfg = le16_to_cpu(ctrl->wValue);
 563
 564         switch (state) {
 565         case USB_STATE_DEFAULT:
 566                 return -EINVAL;
 567
 568         case USB_STATE_ADDRESS:
 569                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 570                 /* if the cfg matches and the cfg is non zero */
 571                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 572
 573                         /*
 574                          * only change state if set_config has already
 575                          * been processed. If gadget driver returns
 576                          * USB_GADGET_DELAYED_STATUS, we will wait
 577                          * to change the state on the next usb_ep_queue()
 578                          */
 579                         if (ret == 0)
 580                                 usb_gadget_set_state(&dwc->gadget,
 581                                                 USB_STATE_CONFIGURED);
 582
 583                         /*
 584                          * Enable transition to U1/U2 state when
 585                          * nothing is pending from application.
 586                          */
 587                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 588                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 589                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 590
 591                         dwc->resize_fifos = true;
 592                         dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
 593                 }
 594                 break;
 595
 596         case USB_STATE_CONFIGURED:
 597                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 598                 if (!cfg && !ret)
 599                         usb_gadget_set_state(&dwc->gadget,
 600                                         USB_STATE_ADDRESS);
 601                 break;
 602         default:
 603                 ret = -EINVAL;
 604         }
 605         return ret;
 606 }
 607
 608 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 609 {
 610         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 611         struct dwc3     *dwc = dep->dwc;
 612
 613         u32             param = 0;
 614         u32             reg;
 615
 616         struct timing {
 617                 u8      u1sel;
 618                 u8      u1pel;
 619                 u16     u2sel;
 620                 u16     u2pel;
 621         } __packed timing;
 622
 623         int             ret;
 624
 625         memcpy(&timing, req->buf, sizeof(timing));
 626
 627         dwc->u1sel = timing.u1sel;
 628         dwc->u1pel = timing.u1pel;
 629         dwc->u2sel = le16_to_cpu(timing.u2sel);
 630         dwc->u2pel = le16_to_cpu(timing.u2pel);
 631
 632         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 633         if (reg & DWC3_DCTL_INITU2ENA)
 634                 param = dwc->u2pel;
 635         if (reg & DWC3_DCTL_INITU1ENA)
 636                 param = dwc->u1pel;
 637
 638         /*
 639          * According to Synopsys Databook, if parameter is
 640          * greater than 125, a value of zero should be
 641          * programmed in the register.
 642          */
 643         if (param > 125)
 644                 param = 0;
 645
 646         /* now that we have the time, issue DGCMD Set Sel */
 647         ret = dwc3_send_gadget_generic_command(dwc,
 648                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 649         WARN_ON(ret < 0);
 650 }
 651
 652 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 653 {
 654         struct dwc3_ep  *dep;
 655         enum usb_device_state state = dwc->gadget.state;
 656         u16             wLength;
 657         u16             wValue;
 658
 659         if (state == USB_STATE_DEFAULT)
 660                 return -EINVAL;
 661
 662         wValue = le16_to_cpu(ctrl->wValue);
 663         wLength = le16_to_cpu(ctrl->wLength);
 664
 665         if (wLength != 6) {
 666                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 667                                 wLength);
 668                 return -EINVAL;
 669         }
 670
 671         /*
 672          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 673          * queue a usb_request for 6 bytes.
 674          *
 675          * Remember, though, this controller can't handle non-wMaxPacketSize
 676          * aligned transfers on the OUT direction, so we queue a request for
 677          * wMaxPacketSize instead.
 678          */
 679         dep = dwc->eps[0];
 680         dwc->ep0_usb_req.dep = dep;
 681         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 682         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 683         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 684
 685         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 686 }
 687
 688 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 689 {
 690         u16             wLength;
 691         u16             wValue;
 692         u16             wIndex;
 693
 694         wValue = le16_to_cpu(ctrl->wValue);
 695         wLength = le16_to_cpu(ctrl->wLength);
 696         wIndex = le16_to_cpu(ctrl->wIndex);
 697
 698         if (wIndex || wLength)
 699                 return -EINVAL;
 700
 701         /*
 702          * REVISIT It's unclear from Databook what to do with this
 703          * value. For now, just cache it.
 704          */
 705         dwc->isoch_delay = wValue;
 706
 707         return 0;
 708 }
 709
 710 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 711 {
 712         int ret;
 713
 714         switch (ctrl->bRequest) {
 715         case USB_REQ_GET_STATUS:
 716                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
 717                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 718                 break;
 719         case USB_REQ_CLEAR_FEATURE:
 720                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
 721                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 722                 break;
 723         case USB_REQ_SET_FEATURE:
 724                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
 725                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 726                 break;
 727         case USB_REQ_SET_ADDRESS:
 728                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
 729                 ret = dwc3_ep0_set_address(dwc, ctrl);
 730                 break;
 731         case USB_REQ_SET_CONFIGURATION:
 732                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
 733                 ret = dwc3_ep0_set_config(dwc, ctrl);
 734                 break;
 735         case USB_REQ_SET_SEL:
 736                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
 737                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 738                 break;
 739         case USB_REQ_SET_ISOCH_DELAY:
 740                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
 741                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 742                 break;
 743         default:
 744                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
 745                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 746                 break;
 747         }
 748
 749         return ret;
 750 }
 751
 752 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 753                 const struct dwc3_event_depevt *event)
 754 {
 755         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 756         int ret = -EINVAL;
 757         u32 len;
 758
 759         if (!dwc->gadget_driver)
 760                 goto out;
 761
 762         trace_dwc3_ctrl_req(ctrl);
 763
 764         len = le16_to_cpu(ctrl->wLength);
 765         if (!len) {
 766                 dwc->three_stage_setup = false;
 767                 dwc->ep0_expect_in = false;
 768                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 769         } else {
 770                 dwc->three_stage_setup = true;
 771                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 772                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 773         }
 774
 775         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 776                 ret = dwc3_ep0_std_request(dwc, ctrl);
 777         else
 778                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 779
 780         if (ret == USB_GADGET_DELAYED_STATUS)
 781                 dwc->delayed_status = true;
 782
 783 out:
 784         if (ret < 0)
 785                 dwc3_ep0_stall_and_restart(dwc);
 786 }
 787
 788 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 789                 const struct dwc3_event_depevt *event)
 790 {
 791         struct dwc3_request     *r = NULL;
 792         struct usb_request      *ur;
 793         struct dwc3_trb         *trb;
 794         struct dwc3_ep          *ep0;
 795         unsigned                transfer_size = 0;
 796         unsigned                maxp;
 797         unsigned                remaining_ur_length;
 798         void                    *buf;
 799         u32                     transferred = 0;
 800         u32                     status;
 801         u32                     length;
 802         u8                      epnum;
 803
 804         epnum = event->endpoint_number;
 805         ep0 = dwc->eps[0];
 806
 807         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 808
 809         trb = dwc->ep0_trb;
 810
 811         trace_dwc3_complete_trb(ep0, trb);
 812
 813         r = next_request(&ep0->request_list);
 814         if (!r)
 815                 return;
 816
 817         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 818         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 819                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 820
 821                 if (r)
 822                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 823
 824                 return;
 825         }
 826
 827         ur = &r->request;
 828         buf = ur->buf;
 829         remaining_ur_length = ur->length;
 830
 831         length = trb->size & DWC3_TRB_SIZE_MASK;
 832
 833         maxp = ep0->endpoint.maxpacket;
 834
 835         if (dwc->ep0_bounced) {
 836                 /*
 837                  * Handle the first TRB before handling the bounce buffer if
 838                  * the request length is greater than the bounce buffer size
 839                  */
 840                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
 841                         transfer_size = ALIGN(ur->length - maxp, maxp);
 842                         transferred = transfer_size - length;
 843                         buf = (u8 *)buf + transferred;
 844                         ur->actual += transferred;
 845                         remaining_ur_length -= transferred;
 846
 847                         trb++;
 848                         length = trb->size & DWC3_TRB_SIZE_MASK;
 849
 850                         ep0->free_slot = 0;
 851                 }
 852
 853                 transfer_size = roundup((ur->length - transfer_size),
 854                                         maxp);
 855
 856                 transferred = min_t(u32, remaining_ur_length,
 857                                     transfer_size - length);
 858                 memcpy(buf, dwc->ep0_bounce, transferred);
 859         } else {
 860                 transferred = ur->length - length;
 861         }
 862
 863         ur->actual += transferred;
 864
 865         if ((epnum & 1) && ur->actual < ur->length) {
 866                 /* for some reason we did not get everything out */
 867
 868                 dwc3_ep0_stall_and_restart(dwc);
 869         } else {
 870                 dwc3_gadget_giveback(ep0, r, 0);
 871
 872                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 873                                 ur->length && ur->zero) {
 874                         int ret;
 875
 876                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 877
 878                         dwc3_ep0_prepare_one_trb(dwc, epnum, dwc->ctrl_req_addr,
 879                                         0, DWC3_TRBCTL_CONTROL_DATA, false);
 880                         ret = dwc3_ep0_start_trans(dwc, epnum);
 881                         WARN_ON(ret < 0);
 882                 }
 883         }
 884 }
 885
 886 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 887                 const struct dwc3_event_depevt *event)
 888 {
 889         struct dwc3_request     *r;
 890         struct dwc3_ep          *dep;
 891         struct dwc3_trb         *trb;
 892         u32                     status;
 893
 894         dep = dwc->eps[0];
 895         trb = dwc->ep0_trb;
 896
 897         trace_dwc3_complete_trb(dep, trb);
 898
 899         if (!list_empty(&dep->request_list)) {
 900                 r = next_request(&dep->request_list);
 901
 902                 dwc3_gadget_giveback(dep, r, 0);
 903         }
 904
 905         if (dwc->test_mode) {
 906                 int ret;
 907
 908                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 909                 if (ret < 0) {
 910                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 911                                         dwc->test_mode_nr);
 912                         dwc3_ep0_stall_and_restart(dwc);
 913                         return;
 914                 }
 915         }
 916
 917         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 918         if (status == DWC3_TRBSTS_SETUP_PENDING)
 919                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 920
 921         dwc->ep0state = EP0_SETUP_PHASE;
 922         dwc3_ep0_out_start(dwc);
 923 }
 924
 925 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 926                         const struct dwc3_event_depevt *event)
 927 {
 928         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 929
 930         dep->flags &= ~DWC3_EP_BUSY;
 931         dep->resource_index = 0;
 932         dwc->setup_packet_pending = false;
 933
 934         switch (dwc->ep0state) {
 935         case EP0_SETUP_PHASE:
 936                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 937                 dwc3_ep0_inspect_setup(dwc, event);
 938                 break;
 939
 940         case EP0_DATA_PHASE:
 941                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 942                 dwc3_ep0_complete_data(dwc, event);
 943                 break;
 944
 945         case EP0_STATUS_PHASE:
 946                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 947                 dwc3_ep0_complete_status(dwc, event);
 948                 break;
 949         default:
 950                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 951         }
 952 }
 953
 954 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 955                 struct dwc3_ep *dep, struct dwc3_request *req)
 956 {
 957         int                     ret;
 958
 959         req->direction = !!dep->number;
 960
 961         if (req->request.length == 0) {
 962                 dwc3_ep0_prepare_one_trb(dwc, dep->number,
 963                                 dwc->ctrl_req_addr, 0,
 964                                 DWC3_TRBCTL_CONTROL_DATA, false);
 965                 ret = dwc3_ep0_start_trans(dwc, dep->number);
 966         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 967                         && (dep->number == 0)) {
 968                 u32     transfer_size = 0;
 969                 u32     maxpacket;
 970
 971                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 972                                 dep->number);
 973                 if (ret) {
 974                         dev_dbg(dwc->dev, "failed to map request\n");
 975                         return;
 976                 }
 977
 978                 maxpacket = dep->endpoint.maxpacket;
 979
 980                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
 981                         transfer_size = ALIGN(req->request.length - maxpacket,
 982                                               maxpacket);
 983                         dwc3_ep0_prepare_one_trb(dwc, dep->number,
 984                                                    req->request.dma,
 985                                                    transfer_size,
 986                                                    DWC3_TRBCTL_CONTROL_DATA,
 987                                                    true);
 988                 }
 989
 990                 transfer_size = roundup((req->request.length - transfer_size),
 991                                         maxpacket);
 992
 993                 dwc->ep0_bounced = true;
 994
 995                 dwc3_ep0_prepare_one_trb(dwc, dep->number,
 996                                 dwc->ep0_bounce_addr, transfer_size,
 997                                 DWC3_TRBCTL_CONTROL_DATA, false);
 998                 ret = dwc3_ep0_start_trans(dwc, dep->number);
 999         } else {
1000                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1001                                 dep->number);
1002                 if (ret) {
1003                         dev_dbg(dwc->dev, "failed to map request\n");
1004                         return;
1005                 }
1006
1007                 dwc3_ep0_prepare_one_trb(dwc, dep->number, req->request.dma,
1008                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1009                                 false);
1010                 ret = dwc3_ep0_start_trans(dwc, dep->number);
1011         }
1012
1013         WARN_ON(ret < 0);
1014 }
1015
1016 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1017 {
1018         struct dwc3             *dwc = dep->dwc;
1019         u32                     type;
1020
1021         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1022                 : DWC3_TRBCTL_CONTROL_STATUS2;
1023
1024         dwc3_ep0_prepare_one_trb(dwc, dep->number,
1025                         dwc->ctrl_req_addr, 0, type, false);
1026         return dwc3_ep0_start_trans(dwc, dep->number);
1027 }
1028
1029 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1030 {
1031         if (dwc->resize_fifos) {
1032                 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
1033                 dwc3_gadget_resize_tx_fifos(dwc);
1034                 dwc->resize_fifos = 0;
1035         }
1036
1037         WARN_ON(dwc3_ep0_start_control_status(dep));
1038 }
1039
1040 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1041                 const struct dwc3_event_depevt *event)
1042 {
1043         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1044
1045         __dwc3_ep0_do_control_status(dwc, dep);
1046 }
1047
1048 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1049 {
1050         struct dwc3_gadget_ep_cmd_params params;
1051         u32                     cmd;
1052         int                     ret;
1053
1054         if (!dep->resource_index)
1055                 return;
1056
1057         cmd = DWC3_DEPCMD_ENDTRANSFER;
1058         cmd |= DWC3_DEPCMD_CMDIOC;
1059         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1060         memset(&params, 0, sizeof(params));
1061         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1062         WARN_ON_ONCE(ret);
1063         dep->resource_index = 0;
1064 }
1065
1066 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1067                 const struct dwc3_event_depevt *event)
1068 {
1069         dwc->setup_packet_pending = true;
1070
1071         switch (event->status) {
1072         case DEPEVT_STATUS_CONTROL_DATA:
1073                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1074
1075                 /*
1076                  * We already have a DATA transfer in the controller's cache,
1077                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1078                  * it's for the wrong direction.
1079                  *
1080                  * In that case, we must issue END_TRANSFER command to the Data
1081                  * Phase we already have started and issue SetStall on the
1082                  * control endpoint.
1083                  */
1084                 if (dwc->ep0_expect_in != event->endpoint_number) {
1085                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1086
1087                         dwc3_trace(trace_dwc3_ep0,
1088                                         "Wrong direction for Data phase");
1089                         dwc3_ep0_end_control_data(dwc, dep);
1090                         dwc3_ep0_stall_and_restart(dwc);
1091                         return;
1092                 }
1093
1094                 break;
1095
1096         case DEPEVT_STATUS_CONTROL_STATUS:
1097                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1098                         return;
1099
1100                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1101
1102                 dwc->ep0state = EP0_STATUS_PHASE;
1103
1104                 if (dwc->delayed_status) {
1105                         WARN_ON_ONCE(event->endpoint_number != 1);
1106                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1107                         return;
1108                 }
1109
1110                 dwc3_ep0_do_control_status(dwc, event);
1111         }
1112 }
1113
1114 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1115                 const struct dwc3_event_depevt *event)
1116 {
1117         u8                      epnum = event->endpoint_number;
1118
1119         dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1120                         dwc3_ep_event_string(event->endpoint_event),
1121                         epnum >> 1, (epnum & 1) ? "in" : "out",
1122                         dwc3_ep0_state_string(dwc->ep0state));
1123
1124         switch (event->endpoint_event) {
1125         case DWC3_DEPEVT_XFERCOMPLETE:
1126                 dwc3_ep0_xfer_complete(dwc, event);
1127                 break;
1128
1129         case DWC3_DEPEVT_XFERNOTREADY:
1130                 dwc3_ep0_xfernotready(dwc, event);
1131                 break;
1132
1133         case DWC3_DEPEVT_XFERINPROGRESS:
1134         case DWC3_DEPEVT_RXTXFIFOEVT:
1135         case DWC3_DEPEVT_STREAMEVT:
1136         case DWC3_DEPEVT_EPCMDCMPLT:
1137                 break;
1138         }
1139 }