kernel/drivers/tty/serial/sunsab.c

   1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
   2  *
   3  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
   4  * Copyright (C) 2002, 2006  David S. Miller (davem@davemloft.net)
   5  *
   6  * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
   7  *   Maxim Krasnyanskiy <maxk@qualcomm.com>
   8  *
   9  * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
  10  * rates to be programmed into the UART.  Also eliminated a lot of
  11  * duplicated code in the console setup.
  12  *   Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
  13  *
  14  * Ported to new 2.5.x UART layer.
  15  *   David S. Miller <davem@davemloft.net>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/major.h>
  24 #include <linux/string.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/ioport.h>
  27 #include <linux/circ_buf.h>
  28 #include <linux/serial.h>
  29 #include <linux/sysrq.h>
  30 #include <linux/console.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/slab.h>
  33 #include <linux/delay.h>
  34 #include <linux/init.h>
  35 #include <linux/of_device.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/prom.h>
  40 #include <asm/setup.h>
  41
  42 #if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  43 #define SUPPORT_SYSRQ
  44 #endif
  45
  46 #include <linux/serial_core.h>
  47 #include <linux/sunserialcore.h>
  48
  49 #include "sunsab.h"
  50
  51 struct uart_sunsab_port {
  52         struct uart_port                port;           /* Generic UART port    */
  53         union sab82532_async_regs       __iomem *regs;  /* Chip registers       */
  54         unsigned long                   irqflags;       /* IRQ state flags      */
  55         int                             dsr;            /* Current DSR state    */
  56         unsigned int                    cec_timeout;    /* Chip poll timeout... */
  57         unsigned int                    tec_timeout;    /* likewise             */
  58         unsigned char                   interrupt_mask0;/* ISR0 masking         */
  59         unsigned char                   interrupt_mask1;/* ISR1 masking         */
  60         unsigned char                   pvr_dtr_bit;    /* Which PVR bit is DTR */
  61         unsigned char                   pvr_dsr_bit;    /* Which PVR bit is DSR */
  62         unsigned int                    gis_shift;
  63         int                             type;           /* SAB82532 version     */
  64
  65         /* Setting configuration bits while the transmitter is active
  66          * can cause garbage characters to get emitted by the chip.
  67          * Therefore, we cache such writes here and do the real register
  68          * write the next time the transmitter becomes idle.
  69          */
  70         unsigned int                    cached_ebrg;
  71         unsigned char                   cached_mode;
  72         unsigned char                   cached_pvr;
  73         unsigned char                   cached_dafo;
  74 };
  75
  76 /*
  77  * This assumes you have a 29.4912 MHz clock for your UART.
  78  */
  79 #define SAB_BASE_BAUD ( 29491200 / 16 )
  80
  81 static char *sab82532_version[16] = {
  82         "V1.0", "V2.0", "V3.2", "V(0x03)",
  83         "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
  84         "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
  85         "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
  86 };
  87
  88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
  89 #define SAB82532_MAX_CEC_TIMEOUT  50000 /* 2.5 TX CLKs (at 50 baud) */
  90
  91 #define SAB82532_RECV_FIFO_SIZE 32      /* Standard async fifo sizes */
  92 #define SAB82532_XMIT_FIFO_SIZE 32
  93
  94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
  95 {
  96         int timeout = up->tec_timeout;
  97
  98         while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
  99                 udelay(1);
 100 }
 101
 102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
 103 {
 104         int timeout = up->cec_timeout;
 105
 106         while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
 107                 udelay(1);
 108 }
 109
 110 static struct tty_port *
 111 receive_chars(struct uart_sunsab_port *up,
 112               union sab82532_irq_status *stat)
 113 {
 114         struct tty_port *port = NULL;
 115         unsigned char buf[32];
 116         int saw_console_brk = 0;
 117         int free_fifo = 0;
 118         int count = 0;
 119         int i;
 120
 121         if (up->port.state != NULL)             /* Unopened serial console */
 122                 port = &up->port.state->port;
 123
 124         /* Read number of BYTES (Character + Status) available. */
 125         if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
 126                 count = SAB82532_RECV_FIFO_SIZE;
 127                 free_fifo++;
 128         }
 129
 130         if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
 131                 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
 132                 free_fifo++;
 133         }
 134
 135         /* Issue a FIFO read command in case we where idle. */
 136         if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
 137                 sunsab_cec_wait(up);
 138                 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
 139                 return port;
 140         }
 141
 142         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 143                 free_fifo++;
 144
 145         /* Read the FIFO. */
 146         for (i = 0; i < count; i++)
 147                 buf[i] = readb(&up->regs->r.rfifo[i]);
 148
 149         /* Issue Receive Message Complete command. */
 150         if (free_fifo) {
 151                 sunsab_cec_wait(up);
 152                 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
 153         }
 154
 155         /* Count may be zero for BRK, so we check for it here */
 156         if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
 157             (up->port.line == up->port.cons->index))
 158                 saw_console_brk = 1;
 159
 160         if (count == 0) {
 161                 if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
 162                         stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
 163                                              SAB82532_ISR0_FERR);
 164                         up->port.icount.brk++;
 165                         uart_handle_break(&up->port);
 166                 }
 167         }
 168
 169         for (i = 0; i < count; i++) {
 170                 unsigned char ch = buf[i], flag;
 171
 172                 flag = TTY_NORMAL;
 173                 up->port.icount.rx++;
 174
 175                 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
 176                                                 SAB82532_ISR0_FERR |
 177                                                 SAB82532_ISR0_RFO)) ||
 178                     unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
 179                         /*
 180                          * For statistics only
 181                          */
 182                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 183                                 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
 184                                                      SAB82532_ISR0_FERR);
 185                                 up->port.icount.brk++;
 186                                 /*
 187                                  * We do the SysRQ and SAK checking
 188                                  * here because otherwise the break
 189                                  * may get masked by ignore_status_mask
 190                                  * or read_status_mask.
 191                                  */
 192                                 if (uart_handle_break(&up->port))
 193                                         continue;
 194                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 195                                 up->port.icount.parity++;
 196                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 197                                 up->port.icount.frame++;
 198                         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 199                                 up->port.icount.overrun++;
 200
 201                         /*
 202                          * Mask off conditions which should be ingored.
 203                          */
 204                         stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
 205                         stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
 206
 207                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 208                                 flag = TTY_BREAK;
 209                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 210                                 flag = TTY_PARITY;
 211                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 212                                 flag = TTY_FRAME;
 213                 }
 214
 215                 if (uart_handle_sysrq_char(&up->port, ch) || !port)
 216                         continue;
 217
 218                 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
 219                     (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
 220                         tty_insert_flip_char(port, ch, flag);
 221                 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 222                         tty_insert_flip_char(port, 0, TTY_OVERRUN);
 223         }
 224
 225         if (saw_console_brk)
 226                 sun_do_break();
 227
 228         return port;
 229 }
 230
 231 static void sunsab_stop_tx(struct uart_port *);
 232 static void sunsab_tx_idle(struct uart_sunsab_port *);
 233
 234 static void transmit_chars(struct uart_sunsab_port *up,
 235                            union sab82532_irq_status *stat)
 236 {
 237         struct circ_buf *xmit = &up->port.state->xmit;
 238         int i;
 239
 240         if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
 241                 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
 242                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 243                 set_bit(SAB82532_ALLS, &up->irqflags);
 244         }
 245
 246 #if 0 /* bde@nwlink.com says this check causes problems */
 247         if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
 248                 return;
 249 #endif
 250
 251         if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
 252                 return;
 253
 254         set_bit(SAB82532_XPR, &up->irqflags);
 255         sunsab_tx_idle(up);
 256
 257         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 258                 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 259                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 260                 return;
 261         }
 262
 263         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 264         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 265         clear_bit(SAB82532_ALLS, &up->irqflags);
 266
 267         /* Stuff 32 bytes into Transmit FIFO. */
 268         clear_bit(SAB82532_XPR, &up->irqflags);
 269         for (i = 0; i < up->port.fifosize; i++) {
 270                 writeb(xmit->buf[xmit->tail],
 271                        &up->regs->w.xfifo[i]);
 272                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 273                 up->port.icount.tx++;
 274                 if (uart_circ_empty(xmit))
 275                         break;
 276         }
 277
 278         /* Issue a Transmit Frame command. */
 279         sunsab_cec_wait(up);
 280         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 281
 282         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 283                 uart_write_wakeup(&up->port);
 284
 285         if (uart_circ_empty(xmit))
 286                 sunsab_stop_tx(&up->port);
 287 }
 288
 289 static void check_status(struct uart_sunsab_port *up,
 290                          union sab82532_irq_status *stat)
 291 {
 292         if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
 293                 uart_handle_dcd_change(&up->port,
 294                                        !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
 295
 296         if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
 297                 uart_handle_cts_change(&up->port,
 298                                        (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
 299
 300         if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
 301                 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
 302                 up->port.icount.dsr++;
 303         }
 304
 305         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 306 }
 307
 308 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
 309 {
 310         struct uart_sunsab_port *up = dev_id;
 311         struct tty_port *port = NULL;
 312         union sab82532_irq_status status;
 313         unsigned long flags;
 314         unsigned char gis;
 315
 316         spin_lock_irqsave(&up->port.lock, flags);
 317
 318         status.stat = 0;
 319         gis = readb(&up->regs->r.gis) >> up->gis_shift;
 320         if (gis & 1)
 321                 status.sreg.isr0 = readb(&up->regs->r.isr0);
 322         if (gis & 2)
 323                 status.sreg.isr1 = readb(&up->regs->r.isr1);
 324
 325         if (status.stat) {
 326                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 327                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
 328                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
 329                         port = receive_chars(up, &status);
 330                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
 331                     (status.sreg.isr1 & SAB82532_ISR1_CSC))
 332                         check_status(up, &status);
 333                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
 334                         transmit_chars(up, &status);
 335         }
 336
 337         spin_unlock_irqrestore(&up->port.lock, flags);
 338
 339         if (port)
 340                 tty_flip_buffer_push(port);
 341
 342         return IRQ_HANDLED;
 343 }
 344
 345 /* port->lock is not held.  */
 346 static unsigned int sunsab_tx_empty(struct uart_port *port)
 347 {
 348         struct uart_sunsab_port *up =
 349                 container_of(port, struct uart_sunsab_port, port);
 350         int ret;
 351
 352         /* Do not need a lock for a state test like this.  */
 353         if (test_bit(SAB82532_ALLS, &up->irqflags))
 354                 ret = TIOCSER_TEMT;
 355         else
 356                 ret = 0;
 357
 358         return ret;
 359 }
 360
 361 /* port->lock held by caller.  */
 362 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
 363 {
 364         struct uart_sunsab_port *up =
 365                 container_of(port, struct uart_sunsab_port, port);
 366
 367         if (mctrl & TIOCM_RTS) {
 368                 up->cached_mode &= ~SAB82532_MODE_FRTS;
 369                 up->cached_mode |= SAB82532_MODE_RTS;
 370         } else {
 371                 up->cached_mode |= (SAB82532_MODE_FRTS |
 372                                     SAB82532_MODE_RTS);
 373         }
 374         if (mctrl & TIOCM_DTR) {
 375                 up->cached_pvr &= ~(up->pvr_dtr_bit);
 376         } else {
 377                 up->cached_pvr |= up->pvr_dtr_bit;
 378         }
 379
 380         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 381         if (test_bit(SAB82532_XPR, &up->irqflags))
 382                 sunsab_tx_idle(up);
 383 }
 384
 385 /* port->lock is held by caller and interrupts are disabled.  */
 386 static unsigned int sunsab_get_mctrl(struct uart_port *port)
 387 {
 388         struct uart_sunsab_port *up =
 389                 container_of(port, struct uart_sunsab_port, port);
 390         unsigned char val;
 391         unsigned int result;
 392
 393         result = 0;
 394
 395         val = readb(&up->regs->r.pvr);
 396         result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
 397
 398         val = readb(&up->regs->r.vstr);
 399         result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
 400
 401         val = readb(&up->regs->r.star);
 402         result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
 403
 404         return result;
 405 }
 406
 407 /* port->lock held by caller.  */
 408 static void sunsab_stop_tx(struct uart_port *port)
 409 {
 410         struct uart_sunsab_port *up =
 411                 container_of(port, struct uart_sunsab_port, port);
 412
 413         up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 414         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 415 }
 416
 417 /* port->lock held by caller.  */
 418 static void sunsab_tx_idle(struct uart_sunsab_port *up)
 419 {
 420         if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
 421                 u8 tmp;
 422
 423                 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
 424                 writeb(up->cached_mode, &up->regs->rw.mode);
 425                 writeb(up->cached_pvr, &up->regs->rw.pvr);
 426                 writeb(up->cached_dafo, &up->regs->w.dafo);
 427
 428                 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
 429                 tmp = readb(&up->regs->rw.ccr2);
 430                 tmp &= ~0xc0;
 431                 tmp |= (up->cached_ebrg >> 2) & 0xc0;
 432                 writeb(tmp, &up->regs->rw.ccr2);
 433         }
 434 }
 435
 436 /* port->lock held by caller.  */
 437 static void sunsab_start_tx(struct uart_port *port)
 438 {
 439         struct uart_sunsab_port *up =
 440                 container_of(port, struct uart_sunsab_port, port);
 441         struct circ_buf *xmit = &up->port.state->xmit;
 442         int i;
 443
 444         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
 445                 return;
 446
 447         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 448         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 449
 450         if (!test_bit(SAB82532_XPR, &up->irqflags))
 451                 return;
 452
 453         clear_bit(SAB82532_ALLS, &up->irqflags);
 454         clear_bit(SAB82532_XPR, &up->irqflags);
 455
 456         for (i = 0; i < up->port.fifosize; i++) {
 457                 writeb(xmit->buf[xmit->tail],
 458                        &up->regs->w.xfifo[i]);
 459                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 460                 up->port.icount.tx++;
 461                 if (uart_circ_empty(xmit))
 462                         break;
 463         }
 464
 465         /* Issue a Transmit Frame command.  */
 466         sunsab_cec_wait(up);
 467         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 468 }
 469
 470 /* port->lock is not held.  */
 471 static void sunsab_send_xchar(struct uart_port *port, char ch)
 472 {
 473         struct uart_sunsab_port *up =
 474                 container_of(port, struct uart_sunsab_port, port);
 475         unsigned long flags;
 476
 477         if (ch == __DISABLED_CHAR)
 478                 return;
 479
 480         spin_lock_irqsave(&up->port.lock, flags);
 481
 482         sunsab_tec_wait(up);
 483         writeb(ch, &up->regs->w.tic);
 484
 485         spin_unlock_irqrestore(&up->port.lock, flags);
 486 }
 487
 488 /* port->lock held by caller.  */
 489 static void sunsab_stop_rx(struct uart_port *port)
 490 {
 491         struct uart_sunsab_port *up =
 492                 container_of(port, struct uart_sunsab_port, port);
 493
 494         up->interrupt_mask0 |= SAB82532_IMR0_TCD;
 495         writeb(up->interrupt_mask1, &up->regs->w.imr0);
 496 }
 497
 498 /* port->lock is not held.  */
 499 static void sunsab_break_ctl(struct uart_port *port, int break_state)
 500 {
 501         struct uart_sunsab_port *up =
 502                 container_of(port, struct uart_sunsab_port, port);
 503         unsigned long flags;
 504         unsigned char val;
 505
 506         spin_lock_irqsave(&up->port.lock, flags);
 507
 508         val = up->cached_dafo;
 509         if (break_state)
 510                 val |= SAB82532_DAFO_XBRK;
 511         else
 512                 val &= ~SAB82532_DAFO_XBRK;
 513         up->cached_dafo = val;
 514
 515         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 516         if (test_bit(SAB82532_XPR, &up->irqflags))
 517                 sunsab_tx_idle(up);
 518
 519         spin_unlock_irqrestore(&up->port.lock, flags);
 520 }
 521
 522 /* port->lock is not held.  */
 523 static int sunsab_startup(struct uart_port *port)
 524 {
 525         struct uart_sunsab_port *up =
 526                 container_of(port, struct uart_sunsab_port, port);
 527         unsigned long flags;
 528         unsigned char tmp;
 529         int err = request_irq(up->port.irq, sunsab_interrupt,
 530                               IRQF_SHARED, "sab", up);
 531         if (err)
 532                 return err;
 533
 534         spin_lock_irqsave(&up->port.lock, flags);
 535
 536         /*
 537          * Wait for any commands or immediate characters
 538          */
 539         sunsab_cec_wait(up);
 540         sunsab_tec_wait(up);
 541
 542         /*
 543          * Clear the FIFO buffers.
 544          */
 545         writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
 546         sunsab_cec_wait(up);
 547         writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
 548
 549         /*
 550          * Clear the interrupt registers.
 551          */
 552         (void) readb(&up->regs->r.isr0);
 553         (void) readb(&up->regs->r.isr1);
 554
 555         /*
 556          * Now, initialize the UART
 557          */
 558         writeb(0, &up->regs->w.ccr0);                           /* power-down */
 559         writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
 560                SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
 561         writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
 562         writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
 563                SAB82532_CCR2_TOE, &up->regs->w.ccr2);
 564         writeb(0, &up->regs->w.ccr3);
 565         writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
 566         up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
 567                            SAB82532_MODE_RAC);
 568         writeb(up->cached_mode, &up->regs->w.mode);
 569         writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
 570
 571         tmp = readb(&up->regs->rw.ccr0);
 572         tmp |= SAB82532_CCR0_PU;        /* power-up */
 573         writeb(tmp, &up->regs->rw.ccr0);
 574
 575         /*
 576          * Finally, enable interrupts
 577          */
 578         up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 579                                SAB82532_IMR0_PLLA);
 580         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 581         up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 582                                SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 583                                SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 584                                SAB82532_IMR1_XPR);
 585         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 586         set_bit(SAB82532_ALLS, &up->irqflags);
 587         set_bit(SAB82532_XPR, &up->irqflags);
 588
 589         spin_unlock_irqrestore(&up->port.lock, flags);
 590
 591         return 0;
 592 }
 593
 594 /* port->lock is not held.  */
 595 static void sunsab_shutdown(struct uart_port *port)
 596 {
 597         struct uart_sunsab_port *up =
 598                 container_of(port, struct uart_sunsab_port, port);
 599         unsigned long flags;
 600
 601         spin_lock_irqsave(&up->port.lock, flags);
 602
 603         /* Disable Interrupts */
 604         up->interrupt_mask0 = 0xff;
 605         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 606         up->interrupt_mask1 = 0xff;
 607         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 608
 609         /* Disable break condition */
 610         up->cached_dafo = readb(&up->regs->rw.dafo);
 611         up->cached_dafo &= ~SAB82532_DAFO_XBRK;
 612         writeb(up->cached_dafo, &up->regs->rw.dafo);
 613
 614         /* Disable Receiver */
 615         up->cached_mode &= ~SAB82532_MODE_RAC;
 616         writeb(up->cached_mode, &up->regs->rw.mode);
 617
 618         /*
 619          * XXX FIXME
 620          *
 621          * If the chip is powered down here the system hangs/crashes during
 622          * reboot or shutdown.  This needs to be investigated further,
 623          * similar behaviour occurs in 2.4 when the driver is configured
 624          * as a module only.  One hint may be that data is sometimes
 625          * transmitted at 9600 baud during shutdown (regardless of the
 626          * speed the chip was configured for when the port was open).
 627          */
 628 #if 0
 629         /* Power Down */
 630         tmp = readb(&up->regs->rw.ccr0);
 631         tmp &= ~SAB82532_CCR0_PU;
 632         writeb(tmp, &up->regs->rw.ccr0);
 633 #endif
 634
 635         spin_unlock_irqrestore(&up->port.lock, flags);
 636         free_irq(up->port.irq, up);
 637 }
 638
 639 /*
 640  * This is used to figure out the divisor speeds.
 641  *
 642  * The formula is:    Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
 643  *
 644  * with               0 <= N < 64 and 0 <= M < 16
 645  */
 646
 647 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
 648 {
 649         int     n, m;
 650
 651         if (baud == 0) {
 652                 *n_ret = 0;
 653                 *m_ret = 0;
 654                 return;
 655         }
 656
 657         /*
 658          * We scale numbers by 10 so that we get better accuracy
 659          * without having to use floating point.  Here we increment m
 660          * until n is within the valid range.
 661          */
 662         n = (SAB_BASE_BAUD * 10) / baud;
 663         m = 0;
 664         while (n >= 640) {
 665                 n = n / 2;
 666                 m++;
 667         }
 668         n = (n+5) / 10;
 669         /*
 670          * We try very hard to avoid speeds with M == 0 since they may
 671          * not work correctly for XTAL frequences above 10 MHz.
 672          */
 673         if ((m == 0) && ((n & 1) == 0)) {
 674                 n = n / 2;
 675                 m++;
 676         }
 677         *n_ret = n - 1;
 678         *m_ret = m;
 679 }
 680
 681 /* Internal routine, port->lock is held and local interrupts are disabled.  */
 682 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
 683                                   unsigned int iflag, unsigned int baud,
 684                                   unsigned int quot)
 685 {
 686         unsigned char dafo;
 687         int bits, n, m;
 688
 689         /* Byte size and parity */
 690         switch (cflag & CSIZE) {
 691               case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 692               case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
 693               case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
 694               case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
 695               /* Never happens, but GCC is too dumb to figure it out */
 696               default:  dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 697         }
 698
 699         if (cflag & CSTOPB) {
 700                 dafo |= SAB82532_DAFO_STOP;
 701                 bits++;
 702         }
 703
 704         if (cflag & PARENB) {
 705                 dafo |= SAB82532_DAFO_PARE;
 706                 bits++;
 707         }
 708
 709         if (cflag & PARODD) {
 710                 dafo |= SAB82532_DAFO_PAR_ODD;
 711         } else {
 712                 dafo |= SAB82532_DAFO_PAR_EVEN;
 713         }
 714         up->cached_dafo = dafo;
 715
 716         calc_ebrg(baud, &n, &m);
 717
 718         up->cached_ebrg = n | (m << 6);
 719
 720         up->tec_timeout = (10 * 1000000) / baud;
 721         up->cec_timeout = up->tec_timeout >> 2;
 722
 723         /* CTS flow control flags */
 724         /* We encode read_status_mask and ignore_status_mask like so:
 725          *
 726          * ---------------------
 727          * | ... | ISR1 | ISR0 |
 728          * ---------------------
 729          *  ..    15   8 7    0
 730          */
 731
 732         up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 733                                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
 734                                      SAB82532_ISR0_CDSC);
 735         up->port.read_status_mask |= (SAB82532_ISR1_CSC |
 736                                       SAB82532_ISR1_ALLS |
 737                                       SAB82532_ISR1_XPR) << 8;
 738         if (iflag & INPCK)
 739                 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
 740                                               SAB82532_ISR0_FERR);
 741         if (iflag & (IGNBRK | BRKINT | PARMRK))
 742                 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
 743
 744         /*
 745          * Characteres to ignore
 746          */
 747         up->port.ignore_status_mask = 0;
 748         if (iflag & IGNPAR)
 749                 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
 750                                                 SAB82532_ISR0_FERR);
 751         if (iflag & IGNBRK) {
 752                 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
 753                 /*
 754                  * If we're ignoring parity and break indicators,
 755                  * ignore overruns too (for real raw support).
 756                  */
 757                 if (iflag & IGNPAR)
 758                         up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
 759         }
 760
 761         /*
 762          * ignore all characters if CREAD is not set
 763          */
 764         if ((cflag & CREAD) == 0)
 765                 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
 766                                                 SAB82532_ISR0_TCD);
 767
 768         uart_update_timeout(&up->port, cflag,
 769                             (up->port.uartclk / (16 * quot)));
 770
 771         /* Now schedule a register update when the chip's
 772          * transmitter is idle.
 773          */
 774         up->cached_mode |= SAB82532_MODE_RAC;
 775         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 776         if (test_bit(SAB82532_XPR, &up->irqflags))
 777                 sunsab_tx_idle(up);
 778 }
 779
 780 /* port->lock is not held.  */
 781 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
 782                                struct ktermios *old)
 783 {
 784         struct uart_sunsab_port *up =
 785                 container_of(port, struct uart_sunsab_port, port);
 786         unsigned long flags;
 787         unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 788         unsigned int quot = uart_get_divisor(port, baud);
 789
 790         spin_lock_irqsave(&up->port.lock, flags);
 791         sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
 792         spin_unlock_irqrestore(&up->port.lock, flags);
 793 }
 794
 795 static const char *sunsab_type(struct uart_port *port)
 796 {
 797         struct uart_sunsab_port *up = (void *)port;
 798         static char buf[36];
 799
 800         sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
 801         return buf;
 802 }
 803
 804 static void sunsab_release_port(struct uart_port *port)
 805 {
 806 }
 807
 808 static int sunsab_request_port(struct uart_port *port)
 809 {
 810         return 0;
 811 }
 812
 813 static void sunsab_config_port(struct uart_port *port, int flags)
 814 {
 815 }
 816
 817 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
 818 {
 819         return -EINVAL;
 820 }
 821
 822 static struct uart_ops sunsab_pops = {
 823         .tx_empty       = sunsab_tx_empty,
 824         .set_mctrl      = sunsab_set_mctrl,
 825         .get_mctrl      = sunsab_get_mctrl,
 826         .stop_tx        = sunsab_stop_tx,
 827         .start_tx       = sunsab_start_tx,
 828         .send_xchar     = sunsab_send_xchar,
 829         .stop_rx        = sunsab_stop_rx,
 830         .break_ctl      = sunsab_break_ctl,
 831         .startup        = sunsab_startup,
 832         .shutdown       = sunsab_shutdown,
 833         .set_termios    = sunsab_set_termios,
 834         .type           = sunsab_type,
 835         .release_port   = sunsab_release_port,
 836         .request_port   = sunsab_request_port,
 837         .config_port    = sunsab_config_port,
 838         .verify_port    = sunsab_verify_port,
 839 };
 840
 841 static struct uart_driver sunsab_reg = {
 842         .owner                  = THIS_MODULE,
 843         .driver_name            = "sunsab",
 844         .dev_name               = "ttyS",
 845         .major                  = TTY_MAJOR,
 846 };
 847
 848 static struct uart_sunsab_port *sunsab_ports;
 849
 850 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
 851
 852 static void sunsab_console_putchar(struct uart_port *port, int c)
 853 {
 854         struct uart_sunsab_port *up =
 855                 container_of(port, struct uart_sunsab_port, port);
 856
 857         sunsab_tec_wait(up);
 858         writeb(c, &up->regs->w.tic);
 859 }
 860
 861 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
 862 {
 863         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 864         unsigned long flags;
 865         int locked = 1;
 866
 867         if (up->port.sysrq || oops_in_progress)
 868                 locked = spin_trylock_irqsave(&up->port.lock, flags);
 869         else
 870                 spin_lock_irqsave(&up->port.lock, flags);
 871
 872         uart_console_write(&up->port, s, n, sunsab_console_putchar);
 873         sunsab_tec_wait(up);
 874
 875         if (locked)
 876                 spin_unlock_irqrestore(&up->port.lock, flags);
 877 }
 878
 879 static int sunsab_console_setup(struct console *con, char *options)
 880 {
 881         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 882         unsigned long flags;
 883         unsigned int baud, quot;
 884
 885         /*
 886          * The console framework calls us for each and every port
 887          * registered. Defer the console setup until the requested
 888          * port has been properly discovered. A bit of a hack,
 889          * though...
 890          */
 891         if (up->port.type != PORT_SUNSAB)
 892                 return -1;
 893
 894         printk("Console: ttyS%d (SAB82532)\n",
 895                (sunsab_reg.minor - 64) + con->index);
 896
 897         sunserial_console_termios(con, up->port.dev->of_node);
 898
 899         switch (con->cflag & CBAUD) {
 900         case B150: baud = 150; break;
 901         case B300: baud = 300; break;
 902         case B600: baud = 600; break;
 903         case B1200: baud = 1200; break;
 904         case B2400: baud = 2400; break;
 905         case B4800: baud = 4800; break;
 906         default: case B9600: baud = 9600; break;
 907         case B19200: baud = 19200; break;
 908         case B38400: baud = 38400; break;
 909         case B57600: baud = 57600; break;
 910         case B115200: baud = 115200; break;
 911         case B230400: baud = 230400; break;
 912         case B460800: baud = 460800; break;
 913         }
 914
 915         /*
 916          * Temporary fix.
 917          */
 918         spin_lock_init(&up->port.lock);
 919
 920         /*
 921          * Initialize the hardware
 922          */
 923         sunsab_startup(&up->port);
 924
 925         spin_lock_irqsave(&up->port.lock, flags);
 926
 927         /*
 928          * Finally, enable interrupts
 929          */
 930         up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 931                                 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
 932         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 933         up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 934                                 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 935                                 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 936                                 SAB82532_IMR1_XPR;
 937         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 938
 939         quot = uart_get_divisor(&up->port, baud);
 940         sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
 941         sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
 942
 943         spin_unlock_irqrestore(&up->port.lock, flags);
 944
 945         return 0;
 946 }
 947
 948 static struct console sunsab_console = {
 949         .name   =       "ttyS",
 950         .write  =       sunsab_console_write,
 951         .device =       uart_console_device,
 952         .setup  =       sunsab_console_setup,
 953         .flags  =       CON_PRINTBUFFER,
 954         .index  =       -1,
 955         .data   =       &sunsab_reg,
 956 };
 957
 958 static inline struct console *SUNSAB_CONSOLE(void)
 959 {
 960         return &sunsab_console;
 961 }
 962 #else
 963 #define SUNSAB_CONSOLE()        (NULL)
 964 #define sunsab_console_init()   do { } while (0)
 965 #endif
 966
 967 static int sunsab_init_one(struct uart_sunsab_port *up,
 968                                      struct platform_device *op,
 969                                      unsigned long offset,
 970                                      int line)
 971 {
 972         up->port.line = line;
 973         up->port.dev = &op->dev;
 974
 975         up->port.mapbase = op->resource[0].start + offset;
 976         up->port.membase = of_ioremap(&op->resource[0], offset,
 977                                       sizeof(union sab82532_async_regs),
 978                                       "sab");
 979         if (!up->port.membase)
 980                 return -ENOMEM;
 981         up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
 982
 983         up->port.irq = op->archdata.irqs[0];
 984
 985         up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
 986         up->port.iotype = UPIO_MEM;
 987
 988         writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
 989
 990         up->port.ops = &sunsab_pops;
 991         up->port.type = PORT_SUNSAB;
 992         up->port.uartclk = SAB_BASE_BAUD;
 993
 994         up->type = readb(&up->regs->r.vstr) & 0x0f;
 995         writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
 996         writeb(0xff, &up->regs->w.pim);
 997         if ((up->port.line & 0x1) == 0) {
 998                 up->pvr_dsr_bit = (1 << 0);
 999                 up->pvr_dtr_bit = (1 << 1);
1000                 up->gis_shift = 2;
1001         } else {
1002                 up->pvr_dsr_bit = (1 << 3);
1003                 up->pvr_dtr_bit = (1 << 2);
1004                 up->gis_shift = 0;
1005         }
1006         up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1007         writeb(up->cached_pvr, &up->regs->w.pvr);
1008         up->cached_mode = readb(&up->regs->rw.mode);
1009         up->cached_mode |= SAB82532_MODE_FRTS;
1010         writeb(up->cached_mode, &up->regs->rw.mode);
1011         up->cached_mode |= SAB82532_MODE_RTS;
1012         writeb(up->cached_mode, &up->regs->rw.mode);
1013
1014         up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1015         up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1016
1017         return 0;
1018 }
1019
1020 static int sab_probe(struct platform_device *op)
1021 {
1022         static int inst;
1023         struct uart_sunsab_port *up;
1024         int err;
1025
1026         up = &sunsab_ports[inst * 2];
1027
1028         err = sunsab_init_one(&up[0], op,
1029                               0,
1030                               (inst * 2) + 0);
1031         if (err)
1032                 goto out;
1033
1034         err = sunsab_init_one(&up[1], op,
1035                               sizeof(union sab82532_async_regs),
1036                               (inst * 2) + 1);
1037         if (err)
1038                 goto out1;
1039
1040         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1041                                 &sunsab_reg, up[0].port.line,
1042                                 false);
1043
1044         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1045                                 &sunsab_reg, up[1].port.line,
1046                                 false);
1047
1048         err = uart_add_one_port(&sunsab_reg, &up[0].port);
1049         if (err)
1050                 goto out2;
1051
1052         err = uart_add_one_port(&sunsab_reg, &up[1].port);
1053         if (err)
1054                 goto out3;
1055
1056         platform_set_drvdata(op, &up[0]);
1057
1058         inst++;
1059
1060         return 0;
1061
1062 out3:
1063         uart_remove_one_port(&sunsab_reg, &up[0].port);
1064 out2:
1065         of_iounmap(&op->resource[0],
1066                    up[1].port.membase,
1067                    sizeof(union sab82532_async_regs));
1068 out1:
1069         of_iounmap(&op->resource[0],
1070                    up[0].port.membase,
1071                    sizeof(union sab82532_async_regs));
1072 out:
1073         return err;
1074 }
1075
1076 static int sab_remove(struct platform_device *op)
1077 {
1078         struct uart_sunsab_port *up = platform_get_drvdata(op);
1079
1080         uart_remove_one_port(&sunsab_reg, &up[1].port);
1081         uart_remove_one_port(&sunsab_reg, &up[0].port);
1082         of_iounmap(&op->resource[0],
1083                    up[1].port.membase,
1084                    sizeof(union sab82532_async_regs));
1085         of_iounmap(&op->resource[0],
1086                    up[0].port.membase,
1087                    sizeof(union sab82532_async_regs));
1088
1089         return 0;
1090 }
1091
1092 static const struct of_device_id sab_match[] = {
1093         {
1094                 .name = "se",
1095         },
1096         {
1097                 .name = "serial",
1098                 .compatible = "sab82532",
1099         },
1100         {},
1101 };
1102 MODULE_DEVICE_TABLE(of, sab_match);
1103
1104 static struct platform_driver sab_driver = {
1105         .driver = {
1106                 .name = "sab",
1107                 .of_match_table = sab_match,
1108         },
1109         .probe          = sab_probe,
1110         .remove         = sab_remove,
1111 };
1112
1113 static int __init sunsab_init(void)
1114 {
1115         struct device_node *dp;
1116         int err;
1117         int num_channels = 0;
1118
1119         for_each_node_by_name(dp, "se")
1120                 num_channels += 2;
1121         for_each_node_by_name(dp, "serial") {
1122                 if (of_device_is_compatible(dp, "sab82532"))
1123                         num_channels += 2;
1124         }
1125
1126         if (num_channels) {
1127                 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1128                                        num_channels, GFP_KERNEL);
1129                 if (!sunsab_ports)
1130                         return -ENOMEM;
1131
1132                 err = sunserial_register_minors(&sunsab_reg, num_channels);
1133                 if (err) {
1134                         kfree(sunsab_ports);
1135                         sunsab_ports = NULL;
1136
1137                         return err;
1138                 }
1139         }
1140
1141         return platform_driver_register(&sab_driver);
1142 }
1143
1144 static void __exit sunsab_exit(void)
1145 {
1146         platform_driver_unregister(&sab_driver);
1147         if (sunsab_reg.nr) {
1148                 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1149         }
1150
1151         kfree(sunsab_ports);
1152         sunsab_ports = NULL;
1153 }
1154
1155 module_init(sunsab_init);
1156 module_exit(sunsab_exit);
1157
1158 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1159 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1160 MODULE_LICENSE("GPL");