kernel/drivers/tty/serial/stm32-usart.c

   1 /*
   2  * Copyright (C) Maxime Coquelin 2015
   3  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   4  * License terms:  GNU General Public License (GPL), version 2
   5  *
   6  * Inspired by st-asc.c from STMicroelectronics (c)
   7  */
   8
   9 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  10 #define SUPPORT_SYSRQ
  11 #endif
  12
  13 #include <linux/module.h>
  14 #include <linux/serial.h>
  15 #include <linux/console.h>
  16 #include <linux/sysrq.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/tty.h>
  21 #include <linux/tty_flip.h>
  22 #include <linux/delay.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/serial_core.h>
  28 #include <linux/clk.h>
  29
  30 #define DRIVER_NAME "stm32-usart"
  31
  32 /* Register offsets */
  33 #define USART_SR                0x00
  34 #define USART_DR                0x04
  35 #define USART_BRR               0x08
  36 #define USART_CR1               0x0c
  37 #define USART_CR2               0x10
  38 #define USART_CR3               0x14
  39 #define USART_GTPR              0x18
  40
  41 /* USART_SR */
  42 #define USART_SR_PE             BIT(0)
  43 #define USART_SR_FE             BIT(1)
  44 #define USART_SR_NF             BIT(2)
  45 #define USART_SR_ORE            BIT(3)
  46 #define USART_SR_IDLE           BIT(4)
  47 #define USART_SR_RXNE           BIT(5)
  48 #define USART_SR_TC             BIT(6)
  49 #define USART_SR_TXE            BIT(7)
  50 #define USART_SR_LBD            BIT(8)
  51 #define USART_SR_CTS            BIT(9)
  52 #define USART_SR_ERR_MASK       (USART_SR_LBD | USART_SR_ORE | \
  53                                  USART_SR_FE | USART_SR_PE)
  54 /* Dummy bits */
  55 #define USART_SR_DUMMY_RX       BIT(16)
  56
  57 /* USART_DR */
  58 #define USART_DR_MASK           GENMASK(8, 0)
  59
  60 /* USART_BRR */
  61 #define USART_BRR_DIV_F_MASK    GENMASK(3, 0)
  62 #define USART_BRR_DIV_M_MASK    GENMASK(15, 4)
  63 #define USART_BRR_DIV_M_SHIFT   4
  64
  65 /* USART_CR1 */
  66 #define USART_CR1_SBK           BIT(0)
  67 #define USART_CR1_RWU           BIT(1)
  68 #define USART_CR1_RE            BIT(2)
  69 #define USART_CR1_TE            BIT(3)
  70 #define USART_CR1_IDLEIE        BIT(4)
  71 #define USART_CR1_RXNEIE        BIT(5)
  72 #define USART_CR1_TCIE          BIT(6)
  73 #define USART_CR1_TXEIE         BIT(7)
  74 #define USART_CR1_PEIE          BIT(8)
  75 #define USART_CR1_PS            BIT(9)
  76 #define USART_CR1_PCE           BIT(10)
  77 #define USART_CR1_WAKE          BIT(11)
  78 #define USART_CR1_M             BIT(12)
  79 #define USART_CR1_UE            BIT(13)
  80 #define USART_CR1_OVER8         BIT(15)
  81 #define USART_CR1_IE_MASK       GENMASK(8, 4)
  82
  83 /* USART_CR2 */
  84 #define USART_CR2_ADD_MASK      GENMASK(3, 0)
  85 #define USART_CR2_LBDL          BIT(5)
  86 #define USART_CR2_LBDIE         BIT(6)
  87 #define USART_CR2_LBCL          BIT(8)
  88 #define USART_CR2_CPHA          BIT(9)
  89 #define USART_CR2_CPOL          BIT(10)
  90 #define USART_CR2_CLKEN         BIT(11)
  91 #define USART_CR2_STOP_2B       BIT(13)
  92 #define USART_CR2_STOP_MASK     GENMASK(13, 12)
  93 #define USART_CR2_LINEN         BIT(14)
  94
  95 /* USART_CR3 */
  96 #define USART_CR3_EIE           BIT(0)
  97 #define USART_CR3_IREN          BIT(1)
  98 #define USART_CR3_IRLP          BIT(2)
  99 #define USART_CR3_HDSEL         BIT(3)
 100 #define USART_CR3_NACK          BIT(4)
 101 #define USART_CR3_SCEN          BIT(5)
 102 #define USART_CR3_DMAR          BIT(6)
 103 #define USART_CR3_DMAT          BIT(7)
 104 #define USART_CR3_RTSE          BIT(8)
 105 #define USART_CR3_CTSE          BIT(9)
 106 #define USART_CR3_CTSIE         BIT(10)
 107 #define USART_CR3_ONEBIT        BIT(11)
 108
 109 /* USART_GTPR */
 110 #define USART_GTPR_PSC_MASK     GENMASK(7, 0)
 111 #define USART_GTPR_GT_MASK      GENMASK(15, 8)
 112
 113 #define DRIVER_NAME "stm32-usart"
 114 #define STM32_SERIAL_NAME "ttyS"
 115 #define STM32_MAX_PORTS 6
 116
 117 struct stm32_port {
 118         struct uart_port port;
 119         struct clk *clk;
 120         bool hw_flow_control;
 121 };
 122
 123 static struct stm32_port stm32_ports[STM32_MAX_PORTS];
 124 static struct uart_driver stm32_usart_driver;
 125
 126 static void stm32_stop_tx(struct uart_port *port);
 127
 128 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
 129 {
 130         return container_of(port, struct stm32_port, port);
 131 }
 132
 133 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
 134 {
 135         u32 val;
 136
 137         val = readl_relaxed(port->membase + reg);
 138         val |= bits;
 139         writel_relaxed(val, port->membase + reg);
 140 }
 141
 142 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
 143 {
 144         u32 val;
 145
 146         val = readl_relaxed(port->membase + reg);
 147         val &= ~bits;
 148         writel_relaxed(val, port->membase + reg);
 149 }
 150
 151 static void stm32_receive_chars(struct uart_port *port)
 152 {
 153         struct tty_port *tport = &port->state->port;
 154         unsigned long c;
 155         u32 sr;
 156         char flag;
 157
 158         if (port->irq_wake)
 159                 pm_wakeup_event(tport->tty->dev, 0);
 160
 161         while ((sr = readl_relaxed(port->membase + USART_SR)) & USART_SR_RXNE) {
 162                 sr |= USART_SR_DUMMY_RX;
 163                 c = readl_relaxed(port->membase + USART_DR);
 164                 flag = TTY_NORMAL;
 165                 port->icount.rx++;
 166
 167                 if (sr & USART_SR_ERR_MASK) {
 168                         if (sr & USART_SR_LBD) {
 169                                 port->icount.brk++;
 170                                 if (uart_handle_break(port))
 171                                         continue;
 172                         } else if (sr & USART_SR_ORE) {
 173                                 port->icount.overrun++;
 174                         } else if (sr & USART_SR_PE) {
 175                                 port->icount.parity++;
 176                         } else if (sr & USART_SR_FE) {
 177                                 port->icount.frame++;
 178                         }
 179
 180                         sr &= port->read_status_mask;
 181
 182                         if (sr & USART_SR_LBD)
 183                                 flag = TTY_BREAK;
 184                         else if (sr & USART_SR_PE)
 185                                 flag = TTY_PARITY;
 186                         else if (sr & USART_SR_FE)
 187                                 flag = TTY_FRAME;
 188                 }
 189
 190                 if (uart_handle_sysrq_char(port, c))
 191                         continue;
 192                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 193         }
 194
 195         spin_unlock(&port->lock);
 196         tty_flip_buffer_push(tport);
 197         spin_lock(&port->lock);
 198 }
 199
 200 static void stm32_transmit_chars(struct uart_port *port)
 201 {
 202         struct circ_buf *xmit = &port->state->xmit;
 203
 204         if (port->x_char) {
 205                 writel_relaxed(port->x_char, port->membase + USART_DR);
 206                 port->x_char = 0;
 207                 port->icount.tx++;
 208                 return;
 209         }
 210
 211         if (uart_tx_stopped(port)) {
 212                 stm32_stop_tx(port);
 213                 return;
 214         }
 215
 216         if (uart_circ_empty(xmit)) {
 217                 stm32_stop_tx(port);
 218                 return;
 219         }
 220
 221         writel_relaxed(xmit->buf[xmit->tail], port->membase + USART_DR);
 222         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 223         port->icount.tx++;
 224
 225         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 226                 uart_write_wakeup(port);
 227
 228         if (uart_circ_empty(xmit))
 229                 stm32_stop_tx(port);
 230 }
 231
 232 static irqreturn_t stm32_interrupt(int irq, void *ptr)
 233 {
 234         struct uart_port *port = ptr;
 235         u32 sr;
 236
 237         spin_lock(&port->lock);
 238
 239         sr = readl_relaxed(port->membase + USART_SR);
 240
 241         if (sr & USART_SR_RXNE)
 242                 stm32_receive_chars(port);
 243
 244         if (sr & USART_SR_TXE)
 245                 stm32_transmit_chars(port);
 246
 247         spin_unlock(&port->lock);
 248
 249         return IRQ_HANDLED;
 250 }
 251
 252 static unsigned int stm32_tx_empty(struct uart_port *port)
 253 {
 254         return readl_relaxed(port->membase + USART_SR) & USART_SR_TXE;
 255 }
 256
 257 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 258 {
 259         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 260                 stm32_set_bits(port, USART_CR3, USART_CR3_RTSE);
 261         else
 262                 stm32_clr_bits(port, USART_CR3, USART_CR3_RTSE);
 263 }
 264
 265 static unsigned int stm32_get_mctrl(struct uart_port *port)
 266 {
 267         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 268         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 269 }
 270
 271 /* Transmit stop */
 272 static void stm32_stop_tx(struct uart_port *port)
 273 {
 274         stm32_clr_bits(port, USART_CR1, USART_CR1_TXEIE);
 275 }
 276
 277 /* There are probably characters waiting to be transmitted. */
 278 static void stm32_start_tx(struct uart_port *port)
 279 {
 280         struct circ_buf *xmit = &port->state->xmit;
 281
 282         if (uart_circ_empty(xmit))
 283                 return;
 284
 285         stm32_set_bits(port, USART_CR1, USART_CR1_TXEIE | USART_CR1_TE);
 286 }
 287
 288 /* Throttle the remote when input buffer is about to overflow. */
 289 static void stm32_throttle(struct uart_port *port)
 290 {
 291         unsigned long flags;
 292
 293         spin_lock_irqsave(&port->lock, flags);
 294         stm32_clr_bits(port, USART_CR1, USART_CR1_RXNEIE);
 295         spin_unlock_irqrestore(&port->lock, flags);
 296 }
 297
 298 /* Unthrottle the remote, the input buffer can now accept data. */
 299 static void stm32_unthrottle(struct uart_port *port)
 300 {
 301         unsigned long flags;
 302
 303         spin_lock_irqsave(&port->lock, flags);
 304         stm32_set_bits(port, USART_CR1, USART_CR1_RXNEIE);
 305         spin_unlock_irqrestore(&port->lock, flags);
 306 }
 307
 308 /* Receive stop */
 309 static void stm32_stop_rx(struct uart_port *port)
 310 {
 311         stm32_clr_bits(port, USART_CR1, USART_CR1_RXNEIE);
 312 }
 313
 314 /* Handle breaks - ignored by us */
 315 static void stm32_break_ctl(struct uart_port *port, int break_state)
 316 {
 317 }
 318
 319 static int stm32_startup(struct uart_port *port)
 320 {
 321         const char *name = to_platform_device(port->dev)->name;
 322         u32 val;
 323         int ret;
 324
 325         ret = request_irq(port->irq, stm32_interrupt, 0, name, port);
 326         if (ret)
 327                 return ret;
 328
 329         val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 330         stm32_set_bits(port, USART_CR1, val);
 331
 332         return 0;
 333 }
 334
 335 static void stm32_shutdown(struct uart_port *port)
 336 {
 337         u32 val;
 338
 339         val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 340         stm32_set_bits(port, USART_CR1, val);
 341
 342         free_irq(port->irq, port);
 343 }
 344
 345 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
 346                             struct ktermios *old)
 347 {
 348         struct stm32_port *stm32_port = to_stm32_port(port);
 349         unsigned int baud;
 350         u32 usartdiv, mantissa, fraction, oversampling;
 351         tcflag_t cflag = termios->c_cflag;
 352         u32 cr1, cr2, cr3;
 353         unsigned long flags;
 354
 355         if (!stm32_port->hw_flow_control)
 356                 cflag &= ~CRTSCTS;
 357
 358         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
 359
 360         spin_lock_irqsave(&port->lock, flags);
 361
 362         /* Stop serial port and reset value */
 363         writel_relaxed(0, port->membase + USART_CR1);
 364
 365         cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE | USART_CR1_RXNEIE;
 366         cr2 = 0;
 367         cr3 = 0;
 368
 369         if (cflag & CSTOPB)
 370                 cr2 |= USART_CR2_STOP_2B;
 371
 372         if (cflag & PARENB) {
 373                 cr1 |= USART_CR1_PCE;
 374                 if ((cflag & CSIZE) == CS8)
 375                         cr1 |= USART_CR1_M;
 376         }
 377
 378         if (cflag & PARODD)
 379                 cr1 |= USART_CR1_PS;
 380
 381         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
 382         if (cflag & CRTSCTS) {
 383                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 384                 cr3 |= USART_CR3_CTSE;
 385         }
 386
 387         usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
 388
 389         /*
 390          * The USART supports 16 or 8 times oversampling.
 391          * By default we prefer 16 times oversampling, so that the receiver
 392          * has a better tolerance to clock deviations.
 393          * 8 times oversampling is only used to achieve higher speeds.
 394          */
 395         if (usartdiv < 16) {
 396                 oversampling = 8;
 397                 stm32_set_bits(port, USART_CR1, USART_CR1_OVER8);
 398         } else {
 399                 oversampling = 16;
 400                 stm32_clr_bits(port, USART_CR1, USART_CR1_OVER8);
 401         }
 402
 403         mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
 404         fraction = usartdiv % oversampling;
 405         writel_relaxed(mantissa | fraction, port->membase + USART_BRR);
 406
 407         uart_update_timeout(port, cflag, baud);
 408
 409         port->read_status_mask = USART_SR_ORE;
 410         if (termios->c_iflag & INPCK)
 411                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
 412         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 413                 port->read_status_mask |= USART_SR_LBD;
 414
 415         /* Characters to ignore */
 416         port->ignore_status_mask = 0;
 417         if (termios->c_iflag & IGNPAR)
 418                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
 419         if (termios->c_iflag & IGNBRK) {
 420                 port->ignore_status_mask |= USART_SR_LBD;
 421                 /*
 422                  * If we're ignoring parity and break indicators,
 423                  * ignore overruns too (for real raw support).
 424                  */
 425                 if (termios->c_iflag & IGNPAR)
 426                         port->ignore_status_mask |= USART_SR_ORE;
 427         }
 428
 429         /* Ignore all characters if CREAD is not set */
 430         if ((termios->c_cflag & CREAD) == 0)
 431                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
 432
 433         writel_relaxed(cr3, port->membase + USART_CR3);
 434         writel_relaxed(cr2, port->membase + USART_CR2);
 435         writel_relaxed(cr1, port->membase + USART_CR1);
 436
 437         spin_unlock_irqrestore(&port->lock, flags);
 438 }
 439
 440 static const char *stm32_type(struct uart_port *port)
 441 {
 442         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
 443 }
 444
 445 static void stm32_release_port(struct uart_port *port)
 446 {
 447 }
 448
 449 static int stm32_request_port(struct uart_port *port)
 450 {
 451         return 0;
 452 }
 453
 454 static void stm32_config_port(struct uart_port *port, int flags)
 455 {
 456         if (flags & UART_CONFIG_TYPE)
 457                 port->type = PORT_STM32;
 458 }
 459
 460 static int
 461 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
 462 {
 463         /* No user changeable parameters */
 464         return -EINVAL;
 465 }
 466
 467 static void stm32_pm(struct uart_port *port, unsigned int state,
 468                 unsigned int oldstate)
 469 {
 470         struct stm32_port *stm32port = container_of(port,
 471                         struct stm32_port, port);
 472         unsigned long flags = 0;
 473
 474         switch (state) {
 475         case UART_PM_STATE_ON:
 476                 clk_prepare_enable(stm32port->clk);
 477                 break;
 478         case UART_PM_STATE_OFF:
 479                 spin_lock_irqsave(&port->lock, flags);
 480                 stm32_clr_bits(port, USART_CR1, USART_CR1_UE);
 481                 spin_unlock_irqrestore(&port->lock, flags);
 482                 clk_disable_unprepare(stm32port->clk);
 483                 break;
 484         }
 485 }
 486
 487 static const struct uart_ops stm32_uart_ops = {
 488         .tx_empty       = stm32_tx_empty,
 489         .set_mctrl      = stm32_set_mctrl,
 490         .get_mctrl      = stm32_get_mctrl,
 491         .stop_tx        = stm32_stop_tx,
 492         .start_tx       = stm32_start_tx,
 493         .throttle       = stm32_throttle,
 494         .unthrottle     = stm32_unthrottle,
 495         .stop_rx        = stm32_stop_rx,
 496         .break_ctl      = stm32_break_ctl,
 497         .startup        = stm32_startup,
 498         .shutdown       = stm32_shutdown,
 499         .set_termios    = stm32_set_termios,
 500         .pm             = stm32_pm,
 501         .type           = stm32_type,
 502         .release_port   = stm32_release_port,
 503         .request_port   = stm32_request_port,
 504         .config_port    = stm32_config_port,
 505         .verify_port    = stm32_verify_port,
 506 };
 507
 508 static int stm32_init_port(struct stm32_port *stm32port,
 509                           struct platform_device *pdev)
 510 {
 511         struct uart_port *port = &stm32port->port;
 512         struct resource *res;
 513         int ret;
 514
 515         port->iotype    = UPIO_MEM;
 516         port->flags     = UPF_BOOT_AUTOCONF;
 517         port->ops       = &stm32_uart_ops;
 518         port->dev       = &pdev->dev;
 519         port->irq       = platform_get_irq(pdev, 0);
 520
 521         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 522         port->membase = devm_ioremap_resource(&pdev->dev, res);
 523         if (IS_ERR(port->membase))
 524                 return PTR_ERR(port->membase);
 525         port->mapbase = res->start;
 526
 527         spin_lock_init(&port->lock);
 528
 529         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
 530         if (IS_ERR(stm32port->clk))
 531                 return PTR_ERR(stm32port->clk);
 532
 533         /* Ensure that clk rate is correct by enabling the clk */
 534         ret = clk_prepare_enable(stm32port->clk);
 535         if (ret)
 536                 return ret;
 537
 538         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
 539         if (!stm32port->port.uartclk)
 540                 ret = -EINVAL;
 541
 542         clk_disable_unprepare(stm32port->clk);
 543
 544         return ret;
 545 }
 546
 547 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
 548 {
 549         struct device_node *np = pdev->dev.of_node;
 550         int id;
 551
 552         if (!np)
 553                 return NULL;
 554
 555         id = of_alias_get_id(np, "serial");
 556         if (id < 0)
 557                 id = 0;
 558
 559         if (WARN_ON(id >= STM32_MAX_PORTS))
 560                 return NULL;
 561
 562         stm32_ports[id].hw_flow_control = of_property_read_bool(np,
 563                                                         "auto-flow-control");
 564         stm32_ports[id].port.line = id;
 565         return &stm32_ports[id];
 566 }
 567
 568 #ifdef CONFIG_OF
 569 static const struct of_device_id stm32_match[] = {
 570         { .compatible = "st,stm32-usart", },
 571         { .compatible = "st,stm32-uart", },
 572         {},
 573 };
 574
 575 MODULE_DEVICE_TABLE(of, stm32_match);
 576 #endif
 577
 578 static int stm32_serial_probe(struct platform_device *pdev)
 579 {
 580         int ret;
 581         struct stm32_port *stm32port;
 582
 583         stm32port = stm32_of_get_stm32_port(pdev);
 584         if (!stm32port)
 585                 return -ENODEV;
 586
 587         ret = stm32_init_port(stm32port, pdev);
 588         if (ret)
 589                 return ret;
 590
 591         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
 592         if (ret)
 593                 return ret;
 594
 595         platform_set_drvdata(pdev, &stm32port->port);
 596
 597         return 0;
 598 }
 599
 600 static int stm32_serial_remove(struct platform_device *pdev)
 601 {
 602         struct uart_port *port = platform_get_drvdata(pdev);
 603
 604         return uart_remove_one_port(&stm32_usart_driver, port);
 605 }
 606
 607
 608 #ifdef CONFIG_SERIAL_STM32_CONSOLE
 609 static void stm32_console_putchar(struct uart_port *port, int ch)
 610 {
 611         while (!(readl_relaxed(port->membase + USART_SR) & USART_SR_TXE))
 612                 cpu_relax();
 613
 614         writel_relaxed(ch, port->membase + USART_DR);
 615 }
 616
 617 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
 618 {
 619         struct uart_port *port = &stm32_ports[co->index].port;
 620         unsigned long flags;
 621         u32 old_cr1, new_cr1;
 622         int locked = 1;
 623
 624         local_irq_save(flags);
 625         if (port->sysrq)
 626                 locked = 0;
 627         else if (oops_in_progress)
 628                 locked = spin_trylock(&port->lock);
 629         else
 630                 spin_lock(&port->lock);
 631
 632         /* Save and disable interrupts */
 633         old_cr1 = readl_relaxed(port->membase + USART_CR1);
 634         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
 635         writel_relaxed(new_cr1, port->membase + USART_CR1);
 636
 637         uart_console_write(port, s, cnt, stm32_console_putchar);
 638
 639         /* Restore interrupt state */
 640         writel_relaxed(old_cr1, port->membase + USART_CR1);
 641
 642         if (locked)
 643                 spin_unlock(&port->lock);
 644         local_irq_restore(flags);
 645 }
 646
 647 static int stm32_console_setup(struct console *co, char *options)
 648 {
 649         struct stm32_port *stm32port;
 650         int baud = 9600;
 651         int bits = 8;
 652         int parity = 'n';
 653         int flow = 'n';
 654
 655         if (co->index >= STM32_MAX_PORTS)
 656                 return -ENODEV;
 657
 658         stm32port = &stm32_ports[co->index];
 659
 660         /*
 661          * This driver does not support early console initialization
 662          * (use ARM early printk support instead), so we only expect
 663          * this to be called during the uart port registration when the
 664          * driver gets probed and the port should be mapped at that point.
 665          */
 666         if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
 667                 return -ENXIO;
 668
 669         if (options)
 670                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 671
 672         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
 673 }
 674
 675 static struct console stm32_console = {
 676         .name           = STM32_SERIAL_NAME,
 677         .device         = uart_console_device,
 678         .write          = stm32_console_write,
 679         .setup          = stm32_console_setup,
 680         .flags          = CON_PRINTBUFFER,
 681         .index          = -1,
 682         .data           = &stm32_usart_driver,
 683 };
 684
 685 #define STM32_SERIAL_CONSOLE (&stm32_console)
 686
 687 #else
 688 #define STM32_SERIAL_CONSOLE NULL
 689 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
 690
 691 static struct uart_driver stm32_usart_driver = {
 692         .driver_name    = DRIVER_NAME,
 693         .dev_name       = STM32_SERIAL_NAME,
 694         .major          = 0,
 695         .minor          = 0,
 696         .nr             = STM32_MAX_PORTS,
 697         .cons           = STM32_SERIAL_CONSOLE,
 698 };
 699
 700 static struct platform_driver stm32_serial_driver = {
 701         .probe          = stm32_serial_probe,
 702         .remove         = stm32_serial_remove,
 703         .driver = {
 704                 .name   = DRIVER_NAME,
 705                 .of_match_table = of_match_ptr(stm32_match),
 706         },
 707 };
 708
 709 static int __init usart_init(void)
 710 {
 711         static char banner[] __initdata = "STM32 USART driver initialized";
 712         int ret;
 713
 714         pr_info("%s\n", banner);
 715
 716         ret = uart_register_driver(&stm32_usart_driver);
 717         if (ret)
 718                 return ret;
 719
 720         ret = platform_driver_register(&stm32_serial_driver);
 721         if (ret)
 722                 uart_unregister_driver(&stm32_usart_driver);
 723
 724         return ret;
 725 }
 726
 727 static void __exit usart_exit(void)
 728 {
 729         platform_driver_unregister(&stm32_serial_driver);
 730         uart_unregister_driver(&stm32_usart_driver);
 731 }
 732
 733 module_init(usart_init);
 734 module_exit(usart_exit);
 735
 736 MODULE_ALIAS("platform:" DRIVER_NAME);
 737 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
 738 MODULE_LICENSE("GPL v2");