kernel/drivers/tty/serial/fsl_lpuart.c

   1 /*
   2  *  Freescale lpuart serial port driver
   3  *
   4  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13 #define SUPPORT_SYSRQ
  14 #endif
  15
  16 #include <linux/clk.h>
  17 #include <linux/console.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dmapool.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_dma.h>
  27 #include <linux/serial_core.h>
  28 #include <linux/slab.h>
  29 #include <linux/tty_flip.h>
  30
  31 /* All registers are 8-bit width */
  32 #define UARTBDH                 0x00
  33 #define UARTBDL                 0x01
  34 #define UARTCR1                 0x02
  35 #define UARTCR2                 0x03
  36 #define UARTSR1                 0x04
  37 #define UARTCR3                 0x06
  38 #define UARTDR                  0x07
  39 #define UARTCR4                 0x0a
  40 #define UARTCR5                 0x0b
  41 #define UARTMODEM               0x0d
  42 #define UARTPFIFO               0x10
  43 #define UARTCFIFO               0x11
  44 #define UARTSFIFO               0x12
  45 #define UARTTWFIFO              0x13
  46 #define UARTTCFIFO              0x14
  47 #define UARTRWFIFO              0x15
  48
  49 #define UARTBDH_LBKDIE          0x80
  50 #define UARTBDH_RXEDGIE         0x40
  51 #define UARTBDH_SBR_MASK        0x1f
  52
  53 #define UARTCR1_LOOPS           0x80
  54 #define UARTCR1_RSRC            0x20
  55 #define UARTCR1_M               0x10
  56 #define UARTCR1_WAKE            0x08
  57 #define UARTCR1_ILT             0x04
  58 #define UARTCR1_PE              0x02
  59 #define UARTCR1_PT              0x01
  60
  61 #define UARTCR2_TIE             0x80
  62 #define UARTCR2_TCIE            0x40
  63 #define UARTCR2_RIE             0x20
  64 #define UARTCR2_ILIE            0x10
  65 #define UARTCR2_TE              0x08
  66 #define UARTCR2_RE              0x04
  67 #define UARTCR2_RWU             0x02
  68 #define UARTCR2_SBK             0x01
  69
  70 #define UARTSR1_TDRE            0x80
  71 #define UARTSR1_TC              0x40
  72 #define UARTSR1_RDRF            0x20
  73 #define UARTSR1_IDLE            0x10
  74 #define UARTSR1_OR              0x08
  75 #define UARTSR1_NF              0x04
  76 #define UARTSR1_FE              0x02
  77 #define UARTSR1_PE              0x01
  78
  79 #define UARTCR3_R8              0x80
  80 #define UARTCR3_T8              0x40
  81 #define UARTCR3_TXDIR           0x20
  82 #define UARTCR3_TXINV           0x10
  83 #define UARTCR3_ORIE            0x08
  84 #define UARTCR3_NEIE            0x04
  85 #define UARTCR3_FEIE            0x02
  86 #define UARTCR3_PEIE            0x01
  87
  88 #define UARTCR4_MAEN1           0x80
  89 #define UARTCR4_MAEN2           0x40
  90 #define UARTCR4_M10             0x20
  91 #define UARTCR4_BRFA_MASK       0x1f
  92 #define UARTCR4_BRFA_OFF        0
  93
  94 #define UARTCR5_TDMAS           0x80
  95 #define UARTCR5_RDMAS           0x20
  96
  97 #define UARTMODEM_RXRTSE        0x08
  98 #define UARTMODEM_TXRTSPOL      0x04
  99 #define UARTMODEM_TXRTSE        0x02
 100 #define UARTMODEM_TXCTSE        0x01
 101
 102 #define UARTPFIFO_TXFE          0x80
 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 104 #define UARTPFIFO_TXSIZE_OFF    4
 105 #define UARTPFIFO_RXFE          0x08
 106 #define UARTPFIFO_RXSIZE_OFF    0
 107
 108 #define UARTCFIFO_TXFLUSH       0x80
 109 #define UARTCFIFO_RXFLUSH       0x40
 110 #define UARTCFIFO_RXOFE         0x04
 111 #define UARTCFIFO_TXOFE         0x02
 112 #define UARTCFIFO_RXUFE         0x01
 113
 114 #define UARTSFIFO_TXEMPT        0x80
 115 #define UARTSFIFO_RXEMPT        0x40
 116 #define UARTSFIFO_RXOF          0x04
 117 #define UARTSFIFO_TXOF          0x02
 118 #define UARTSFIFO_RXUF          0x01
 119
 120 /* 32-bit register defination */
 121 #define UARTBAUD                0x00
 122 #define UARTSTAT                0x04
 123 #define UARTCTRL                0x08
 124 #define UARTDATA                0x0C
 125 #define UARTMATCH               0x10
 126 #define UARTMODIR               0x14
 127 #define UARTFIFO                0x18
 128 #define UARTWATER               0x1c
 129
 130 #define UARTBAUD_MAEN1          0x80000000
 131 #define UARTBAUD_MAEN2          0x40000000
 132 #define UARTBAUD_M10            0x20000000
 133 #define UARTBAUD_TDMAE          0x00800000
 134 #define UARTBAUD_RDMAE          0x00200000
 135 #define UARTBAUD_MATCFG         0x00400000
 136 #define UARTBAUD_BOTHEDGE       0x00020000
 137 #define UARTBAUD_RESYNCDIS      0x00010000
 138 #define UARTBAUD_LBKDIE         0x00008000
 139 #define UARTBAUD_RXEDGIE        0x00004000
 140 #define UARTBAUD_SBNS           0x00002000
 141 #define UARTBAUD_SBR            0x00000000
 142 #define UARTBAUD_SBR_MASK       0x1fff
 143
 144 #define UARTSTAT_LBKDIF         0x80000000
 145 #define UARTSTAT_RXEDGIF        0x40000000
 146 #define UARTSTAT_MSBF           0x20000000
 147 #define UARTSTAT_RXINV          0x10000000
 148 #define UARTSTAT_RWUID          0x08000000
 149 #define UARTSTAT_BRK13          0x04000000
 150 #define UARTSTAT_LBKDE          0x02000000
 151 #define UARTSTAT_RAF            0x01000000
 152 #define UARTSTAT_TDRE           0x00800000
 153 #define UARTSTAT_TC             0x00400000
 154 #define UARTSTAT_RDRF           0x00200000
 155 #define UARTSTAT_IDLE           0x00100000
 156 #define UARTSTAT_OR             0x00080000
 157 #define UARTSTAT_NF             0x00040000
 158 #define UARTSTAT_FE             0x00020000
 159 #define UARTSTAT_PE             0x00010000
 160 #define UARTSTAT_MA1F           0x00008000
 161 #define UARTSTAT_M21F           0x00004000
 162
 163 #define UARTCTRL_R8T9           0x80000000
 164 #define UARTCTRL_R9T8           0x40000000
 165 #define UARTCTRL_TXDIR          0x20000000
 166 #define UARTCTRL_TXINV          0x10000000
 167 #define UARTCTRL_ORIE           0x08000000
 168 #define UARTCTRL_NEIE           0x04000000
 169 #define UARTCTRL_FEIE           0x02000000
 170 #define UARTCTRL_PEIE           0x01000000
 171 #define UARTCTRL_TIE            0x00800000
 172 #define UARTCTRL_TCIE           0x00400000
 173 #define UARTCTRL_RIE            0x00200000
 174 #define UARTCTRL_ILIE           0x00100000
 175 #define UARTCTRL_TE             0x00080000
 176 #define UARTCTRL_RE             0x00040000
 177 #define UARTCTRL_RWU            0x00020000
 178 #define UARTCTRL_SBK            0x00010000
 179 #define UARTCTRL_MA1IE          0x00008000
 180 #define UARTCTRL_MA2IE          0x00004000
 181 #define UARTCTRL_IDLECFG        0x00000100
 182 #define UARTCTRL_LOOPS          0x00000080
 183 #define UARTCTRL_DOZEEN         0x00000040
 184 #define UARTCTRL_RSRC           0x00000020
 185 #define UARTCTRL_M              0x00000010
 186 #define UARTCTRL_WAKE           0x00000008
 187 #define UARTCTRL_ILT            0x00000004
 188 #define UARTCTRL_PE             0x00000002
 189 #define UARTCTRL_PT             0x00000001
 190
 191 #define UARTDATA_NOISY          0x00008000
 192 #define UARTDATA_PARITYE        0x00004000
 193 #define UARTDATA_FRETSC         0x00002000
 194 #define UARTDATA_RXEMPT         0x00001000
 195 #define UARTDATA_IDLINE         0x00000800
 196 #define UARTDATA_MASK           0x3ff
 197
 198 #define UARTMODIR_IREN          0x00020000
 199 #define UARTMODIR_TXCTSSRC      0x00000020
 200 #define UARTMODIR_TXCTSC        0x00000010
 201 #define UARTMODIR_RXRTSE        0x00000008
 202 #define UARTMODIR_TXRTSPOL      0x00000004
 203 #define UARTMODIR_TXRTSE        0x00000002
 204 #define UARTMODIR_TXCTSE        0x00000001
 205
 206 #define UARTFIFO_TXEMPT         0x00800000
 207 #define UARTFIFO_RXEMPT         0x00400000
 208 #define UARTFIFO_TXOF           0x00020000
 209 #define UARTFIFO_RXUF           0x00010000
 210 #define UARTFIFO_TXFLUSH        0x00008000
 211 #define UARTFIFO_RXFLUSH        0x00004000
 212 #define UARTFIFO_TXOFE          0x00000200
 213 #define UARTFIFO_RXUFE          0x00000100
 214 #define UARTFIFO_TXFE           0x00000080
 215 #define UARTFIFO_FIFOSIZE_MASK  0x7
 216 #define UARTFIFO_TXSIZE_OFF     4
 217 #define UARTFIFO_RXFE           0x00000008
 218 #define UARTFIFO_RXSIZE_OFF     0
 219
 220 #define UARTWATER_COUNT_MASK    0xff
 221 #define UARTWATER_TXCNT_OFF     8
 222 #define UARTWATER_RXCNT_OFF     24
 223 #define UARTWATER_WATER_MASK    0xff
 224 #define UARTWATER_TXWATER_OFF   0
 225 #define UARTWATER_RXWATER_OFF   16
 226
 227 #define FSL_UART_RX_DMA_BUFFER_SIZE     64
 228
 229 #define DRIVER_NAME     "fsl-lpuart"
 230 #define DEV_NAME        "ttyLP"
 231 #define UART_NR         6
 232
 233 struct lpuart_port {
 234         struct uart_port        port;
 235         struct clk              *clk;
 236         unsigned int            txfifo_size;
 237         unsigned int            rxfifo_size;
 238         bool                    lpuart32;
 239
 240         bool                    lpuart_dma_tx_use;
 241         bool                    lpuart_dma_rx_use;
 242         struct dma_chan         *dma_tx_chan;
 243         struct dma_chan         *dma_rx_chan;
 244         struct dma_async_tx_descriptor  *dma_tx_desc;
 245         struct dma_async_tx_descriptor  *dma_rx_desc;
 246         dma_addr_t              dma_tx_buf_bus;
 247         dma_addr_t              dma_rx_buf_bus;
 248         dma_cookie_t            dma_tx_cookie;
 249         dma_cookie_t            dma_rx_cookie;
 250         unsigned char           *dma_tx_buf_virt;
 251         unsigned char           *dma_rx_buf_virt;
 252         unsigned int            dma_tx_bytes;
 253         unsigned int            dma_rx_bytes;
 254         int                     dma_tx_in_progress;
 255         int                     dma_rx_in_progress;
 256         unsigned int            dma_rx_timeout;
 257         struct timer_list       lpuart_timer;
 258 };
 259
 260 static const struct of_device_id lpuart_dt_ids[] = {
 261         {
 262                 .compatible = "fsl,vf610-lpuart",
 263         },
 264         {
 265                 .compatible = "fsl,ls1021a-lpuart",
 266         },
 267         { /* sentinel */ }
 268 };
 269 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 270
 271 /* Forward declare this for the dma callbacks*/
 272 static void lpuart_dma_tx_complete(void *arg);
 273 static void lpuart_dma_rx_complete(void *arg);
 274
 275 static u32 lpuart32_read(void __iomem *addr)
 276 {
 277         return ioread32be(addr);
 278 }
 279
 280 static void lpuart32_write(u32 val, void __iomem *addr)
 281 {
 282         iowrite32be(val, addr);
 283 }
 284
 285 static void lpuart_stop_tx(struct uart_port *port)
 286 {
 287         unsigned char temp;
 288
 289         temp = readb(port->membase + UARTCR2);
 290         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 291         writeb(temp, port->membase + UARTCR2);
 292 }
 293
 294 static void lpuart32_stop_tx(struct uart_port *port)
 295 {
 296         unsigned long temp;
 297
 298         temp = lpuart32_read(port->membase + UARTCTRL);
 299         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 300         lpuart32_write(temp, port->membase + UARTCTRL);
 301 }
 302
 303 static void lpuart_stop_rx(struct uart_port *port)
 304 {
 305         unsigned char temp;
 306
 307         temp = readb(port->membase + UARTCR2);
 308         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 309 }
 310
 311 static void lpuart32_stop_rx(struct uart_port *port)
 312 {
 313         unsigned long temp;
 314
 315         temp = lpuart32_read(port->membase + UARTCTRL);
 316         lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
 317 }
 318
 319 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport,
 320                 struct tty_port *tty, int count)
 321 {
 322         int copied;
 323
 324         sport->port.icount.rx += count;
 325
 326         if (!tty) {
 327                 dev_err(sport->port.dev, "No tty port\n");
 328                 return;
 329         }
 330
 331         dma_sync_single_for_cpu(sport->port.dev, sport->dma_rx_buf_bus,
 332                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
 333         copied = tty_insert_flip_string(tty,
 334                         ((unsigned char *)(sport->dma_rx_buf_virt)), count);
 335
 336         if (copied != count) {
 337                 WARN_ON(1);
 338                 dev_err(sport->port.dev, "RxData copy to tty layer failed\n");
 339         }
 340
 341         dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
 342                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
 343 }
 344
 345 static void lpuart_pio_tx(struct lpuart_port *sport)
 346 {
 347         struct circ_buf *xmit = &sport->port.state->xmit;
 348         unsigned long flags;
 349
 350         spin_lock_irqsave(&sport->port.lock, flags);
 351
 352         while (!uart_circ_empty(xmit) &&
 353                 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
 354                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 355                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 356                 sport->port.icount.tx++;
 357         }
 358
 359         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 360                 uart_write_wakeup(&sport->port);
 361
 362         if (uart_circ_empty(xmit))
 363                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
 364                         sport->port.membase + UARTCR5);
 365
 366         spin_unlock_irqrestore(&sport->port.lock, flags);
 367 }
 368
 369 static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
 370 {
 371         struct circ_buf *xmit = &sport->port.state->xmit;
 372         dma_addr_t tx_bus_addr;
 373
 374         dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
 375                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 376         sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);
 377         tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
 378         sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
 379                                         tx_bus_addr, sport->dma_tx_bytes,
 380                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 381
 382         if (!sport->dma_tx_desc) {
 383                 dev_err(sport->port.dev, "Not able to get desc for tx\n");
 384                 return -EIO;
 385         }
 386
 387         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 388         sport->dma_tx_desc->callback_param = sport;
 389         sport->dma_tx_in_progress = 1;
 390         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 391         dma_async_issue_pending(sport->dma_tx_chan);
 392
 393         return 0;
 394 }
 395
 396 static void lpuart_prepare_tx(struct lpuart_port *sport)
 397 {
 398         struct circ_buf *xmit = &sport->port.state->xmit;
 399         unsigned long count =  CIRC_CNT_TO_END(xmit->head,
 400                                         xmit->tail, UART_XMIT_SIZE);
 401
 402         if (!count)
 403                 return;
 404
 405         if (count < sport->txfifo_size)
 406                 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
 407                                 sport->port.membase + UARTCR5);
 408         else {
 409                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
 410                                 sport->port.membase + UARTCR5);
 411                 lpuart_dma_tx(sport, count);
 412         }
 413 }
 414
 415 static void lpuart_dma_tx_complete(void *arg)
 416 {
 417         struct lpuart_port *sport = arg;
 418         struct circ_buf *xmit = &sport->port.state->xmit;
 419         unsigned long flags;
 420
 421         async_tx_ack(sport->dma_tx_desc);
 422
 423         spin_lock_irqsave(&sport->port.lock, flags);
 424
 425         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 426         sport->dma_tx_in_progress = 0;
 427
 428         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 429                 uart_write_wakeup(&sport->port);
 430
 431         lpuart_prepare_tx(sport);
 432
 433         spin_unlock_irqrestore(&sport->port.lock, flags);
 434 }
 435
 436 static int lpuart_dma_rx(struct lpuart_port *sport)
 437 {
 438         dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
 439                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
 440         sport->dma_rx_desc = dmaengine_prep_slave_single(sport->dma_rx_chan,
 441                         sport->dma_rx_buf_bus, FSL_UART_RX_DMA_BUFFER_SIZE,
 442                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 443
 444         if (!sport->dma_rx_desc) {
 445                 dev_err(sport->port.dev, "Not able to get desc for rx\n");
 446                 return -EIO;
 447         }
 448
 449         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
 450         sport->dma_rx_desc->callback_param = sport;
 451         sport->dma_rx_in_progress = 1;
 452         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
 453         dma_async_issue_pending(sport->dma_rx_chan);
 454
 455         return 0;
 456 }
 457
 458 static void lpuart_flush_buffer(struct uart_port *port)
 459 {
 460         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 461         if (sport->lpuart_dma_tx_use) {
 462                 dmaengine_terminate_all(sport->dma_tx_chan);
 463                 sport->dma_tx_in_progress = 0;
 464         }
 465 }
 466
 467 static void lpuart_dma_rx_complete(void *arg)
 468 {
 469         struct lpuart_port *sport = arg;
 470         struct tty_port *port = &sport->port.state->port;
 471         unsigned long flags;
 472
 473         async_tx_ack(sport->dma_rx_desc);
 474         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
 475
 476         spin_lock_irqsave(&sport->port.lock, flags);
 477
 478         sport->dma_rx_in_progress = 0;
 479         lpuart_copy_rx_to_tty(sport, port, FSL_UART_RX_DMA_BUFFER_SIZE);
 480         tty_flip_buffer_push(port);
 481         lpuart_dma_rx(sport);
 482
 483         spin_unlock_irqrestore(&sport->port.lock, flags);
 484 }
 485
 486 static void lpuart_timer_func(unsigned long data)
 487 {
 488         struct lpuart_port *sport = (struct lpuart_port *)data;
 489         struct tty_port *port = &sport->port.state->port;
 490         struct dma_tx_state state;
 491         unsigned long flags;
 492         unsigned char temp;
 493         int count;
 494
 495         del_timer(&sport->lpuart_timer);
 496         dmaengine_pause(sport->dma_rx_chan);
 497         dmaengine_tx_status(sport->dma_rx_chan, sport->dma_rx_cookie, &state);
 498         dmaengine_terminate_all(sport->dma_rx_chan);
 499         count = FSL_UART_RX_DMA_BUFFER_SIZE - state.residue;
 500         async_tx_ack(sport->dma_rx_desc);
 501
 502         spin_lock_irqsave(&sport->port.lock, flags);
 503
 504         sport->dma_rx_in_progress = 0;
 505         lpuart_copy_rx_to_tty(sport, port, count);
 506         tty_flip_buffer_push(port);
 507         temp = readb(sport->port.membase + UARTCR5);
 508         writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
 509
 510         spin_unlock_irqrestore(&sport->port.lock, flags);
 511 }
 512
 513 static inline void lpuart_prepare_rx(struct lpuart_port *sport)
 514 {
 515         unsigned long flags;
 516         unsigned char temp;
 517
 518         spin_lock_irqsave(&sport->port.lock, flags);
 519
 520         sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
 521         add_timer(&sport->lpuart_timer);
 522
 523         lpuart_dma_rx(sport);
 524         temp = readb(sport->port.membase + UARTCR5);
 525         writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5);
 526
 527         spin_unlock_irqrestore(&sport->port.lock, flags);
 528 }
 529
 530 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 531 {
 532         struct circ_buf *xmit = &sport->port.state->xmit;
 533
 534         while (!uart_circ_empty(xmit) &&
 535                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 536                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 537                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 538                 sport->port.icount.tx++;
 539         }
 540
 541         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 542                 uart_write_wakeup(&sport->port);
 543
 544         if (uart_circ_empty(xmit))
 545                 lpuart_stop_tx(&sport->port);
 546 }
 547
 548 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 549 {
 550         struct circ_buf *xmit = &sport->port.state->xmit;
 551         unsigned long txcnt;
 552
 553         txcnt = lpuart32_read(sport->port.membase + UARTWATER);
 554         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 555         txcnt &= UARTWATER_COUNT_MASK;
 556         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 557                 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
 558                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 559                 sport->port.icount.tx++;
 560                 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
 561                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 562                 txcnt &= UARTWATER_COUNT_MASK;
 563         }
 564
 565         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 566                 uart_write_wakeup(&sport->port);
 567
 568         if (uart_circ_empty(xmit))
 569                 lpuart32_stop_tx(&sport->port);
 570 }
 571
 572 static void lpuart_start_tx(struct uart_port *port)
 573 {
 574         struct lpuart_port *sport = container_of(port,
 575                         struct lpuart_port, port);
 576         struct circ_buf *xmit = &sport->port.state->xmit;
 577         unsigned char temp;
 578
 579         temp = readb(port->membase + UARTCR2);
 580         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 581
 582         if (sport->lpuart_dma_tx_use) {
 583                 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
 584                         lpuart_prepare_tx(sport);
 585         } else {
 586                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 587                         lpuart_transmit_buffer(sport);
 588         }
 589 }
 590
 591 static void lpuart32_start_tx(struct uart_port *port)
 592 {
 593         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 594         unsigned long temp;
 595
 596         temp = lpuart32_read(port->membase + UARTCTRL);
 597         lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
 598
 599         if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
 600                 lpuart32_transmit_buffer(sport);
 601 }
 602
 603 static irqreturn_t lpuart_txint(int irq, void *dev_id)
 604 {
 605         struct lpuart_port *sport = dev_id;
 606         struct circ_buf *xmit = &sport->port.state->xmit;
 607         unsigned long flags;
 608
 609         spin_lock_irqsave(&sport->port.lock, flags);
 610         if (sport->port.x_char) {
 611                 if (sport->lpuart32)
 612                         lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
 613                 else
 614                         writeb(sport->port.x_char, sport->port.membase + UARTDR);
 615                 goto out;
 616         }
 617
 618         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 619                 if (sport->lpuart32)
 620                         lpuart32_stop_tx(&sport->port);
 621                 else
 622                         lpuart_stop_tx(&sport->port);
 623                 goto out;
 624         }
 625
 626         if (sport->lpuart32)
 627                 lpuart32_transmit_buffer(sport);
 628         else
 629                 lpuart_transmit_buffer(sport);
 630
 631         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 632                 uart_write_wakeup(&sport->port);
 633
 634 out:
 635         spin_unlock_irqrestore(&sport->port.lock, flags);
 636         return IRQ_HANDLED;
 637 }
 638
 639 static irqreturn_t lpuart_rxint(int irq, void *dev_id)
 640 {
 641         struct lpuart_port *sport = dev_id;
 642         unsigned int flg, ignored = 0;
 643         struct tty_port *port = &sport->port.state->port;
 644         unsigned long flags;
 645         unsigned char rx, sr;
 646
 647         spin_lock_irqsave(&sport->port.lock, flags);
 648
 649         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 650                 flg = TTY_NORMAL;
 651                 sport->port.icount.rx++;
 652                 /*
 653                  * to clear the FE, OR, NF, FE, PE flags,
 654                  * read SR1 then read DR
 655                  */
 656                 sr = readb(sport->port.membase + UARTSR1);
 657                 rx = readb(sport->port.membase + UARTDR);
 658
 659                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 660                         continue;
 661
 662                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 663                         if (sr & UARTSR1_PE)
 664                                 sport->port.icount.parity++;
 665                         else if (sr & UARTSR1_FE)
 666                                 sport->port.icount.frame++;
 667
 668                         if (sr & UARTSR1_OR)
 669                                 sport->port.icount.overrun++;
 670
 671                         if (sr & sport->port.ignore_status_mask) {
 672                                 if (++ignored > 100)
 673                                         goto out;
 674                                 continue;
 675                         }
 676
 677                         sr &= sport->port.read_status_mask;
 678
 679                         if (sr & UARTSR1_PE)
 680                                 flg = TTY_PARITY;
 681                         else if (sr & UARTSR1_FE)
 682                                 flg = TTY_FRAME;
 683
 684                         if (sr & UARTSR1_OR)
 685                                 flg = TTY_OVERRUN;
 686
 687 #ifdef SUPPORT_SYSRQ
 688                         sport->port.sysrq = 0;
 689 #endif
 690                 }
 691
 692                 tty_insert_flip_char(port, rx, flg);
 693         }
 694
 695 out:
 696         spin_unlock_irqrestore(&sport->port.lock, flags);
 697
 698         tty_flip_buffer_push(port);
 699         return IRQ_HANDLED;
 700 }
 701
 702 static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
 703 {
 704         struct lpuart_port *sport = dev_id;
 705         unsigned int flg, ignored = 0;
 706         struct tty_port *port = &sport->port.state->port;
 707         unsigned long flags;
 708         unsigned long rx, sr;
 709
 710         spin_lock_irqsave(&sport->port.lock, flags);
 711
 712         while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
 713                 flg = TTY_NORMAL;
 714                 sport->port.icount.rx++;
 715                 /*
 716                  * to clear the FE, OR, NF, FE, PE flags,
 717                  * read STAT then read DATA reg
 718                  */
 719                 sr = lpuart32_read(sport->port.membase + UARTSTAT);
 720                 rx = lpuart32_read(sport->port.membase + UARTDATA);
 721                 rx &= 0x3ff;
 722
 723                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 724                         continue;
 725
 726                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 727                         if (sr & UARTSTAT_PE)
 728                                 sport->port.icount.parity++;
 729                         else if (sr & UARTSTAT_FE)
 730                                 sport->port.icount.frame++;
 731
 732                         if (sr & UARTSTAT_OR)
 733                                 sport->port.icount.overrun++;
 734
 735                         if (sr & sport->port.ignore_status_mask) {
 736                                 if (++ignored > 100)
 737                                         goto out;
 738                                 continue;
 739                         }
 740
 741                         sr &= sport->port.read_status_mask;
 742
 743                         if (sr & UARTSTAT_PE)
 744                                 flg = TTY_PARITY;
 745                         else if (sr & UARTSTAT_FE)
 746                                 flg = TTY_FRAME;
 747
 748                         if (sr & UARTSTAT_OR)
 749                                 flg = TTY_OVERRUN;
 750
 751 #ifdef SUPPORT_SYSRQ
 752                         sport->port.sysrq = 0;
 753 #endif
 754                 }
 755
 756                 tty_insert_flip_char(port, rx, flg);
 757         }
 758
 759 out:
 760         spin_unlock_irqrestore(&sport->port.lock, flags);
 761
 762         tty_flip_buffer_push(port);
 763         return IRQ_HANDLED;
 764 }
 765
 766 static irqreturn_t lpuart_int(int irq, void *dev_id)
 767 {
 768         struct lpuart_port *sport = dev_id;
 769         unsigned char sts, crdma;
 770
 771         sts = readb(sport->port.membase + UARTSR1);
 772         crdma = readb(sport->port.membase + UARTCR5);
 773
 774         if (sts & UARTSR1_RDRF && !(crdma & UARTCR5_RDMAS)) {
 775                 if (sport->lpuart_dma_rx_use)
 776                         lpuart_prepare_rx(sport);
 777                 else
 778                         lpuart_rxint(irq, dev_id);
 779         }
 780         if (sts & UARTSR1_TDRE && !(crdma & UARTCR5_TDMAS)) {
 781                 if (sport->lpuart_dma_tx_use)
 782                         lpuart_pio_tx(sport);
 783                 else
 784                         lpuart_txint(irq, dev_id);
 785         }
 786
 787         return IRQ_HANDLED;
 788 }
 789
 790 static irqreturn_t lpuart32_int(int irq, void *dev_id)
 791 {
 792         struct lpuart_port *sport = dev_id;
 793         unsigned long sts, rxcount;
 794
 795         sts = lpuart32_read(sport->port.membase + UARTSTAT);
 796         rxcount = lpuart32_read(sport->port.membase + UARTWATER);
 797         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
 798
 799         if (sts & UARTSTAT_RDRF || rxcount > 0)
 800                 lpuart32_rxint(irq, dev_id);
 801
 802         if ((sts & UARTSTAT_TDRE) &&
 803                 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
 804                 lpuart_txint(irq, dev_id);
 805
 806         lpuart32_write(sts, sport->port.membase + UARTSTAT);
 807         return IRQ_HANDLED;
 808 }
 809
 810 /* return TIOCSER_TEMT when transmitter is not busy */
 811 static unsigned int lpuart_tx_empty(struct uart_port *port)
 812 {
 813         return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
 814                 TIOCSER_TEMT : 0;
 815 }
 816
 817 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 818 {
 819         return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
 820                 TIOCSER_TEMT : 0;
 821 }
 822
 823 static unsigned int lpuart_get_mctrl(struct uart_port *port)
 824 {
 825         unsigned int temp = 0;
 826         unsigned char reg;
 827
 828         reg = readb(port->membase + UARTMODEM);
 829         if (reg & UARTMODEM_TXCTSE)
 830                 temp |= TIOCM_CTS;
 831
 832         if (reg & UARTMODEM_RXRTSE)
 833                 temp |= TIOCM_RTS;
 834
 835         return temp;
 836 }
 837
 838 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
 839 {
 840         unsigned int temp = 0;
 841         unsigned long reg;
 842
 843         reg = lpuart32_read(port->membase + UARTMODIR);
 844         if (reg & UARTMODIR_TXCTSE)
 845                 temp |= TIOCM_CTS;
 846
 847         if (reg & UARTMODIR_RXRTSE)
 848                 temp |= TIOCM_RTS;
 849
 850         return temp;
 851 }
 852
 853 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 854 {
 855         unsigned char temp;
 856
 857         temp = readb(port->membase + UARTMODEM) &
 858                         ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
 859
 860         if (mctrl & TIOCM_RTS)
 861                 temp |= UARTMODEM_RXRTSE;
 862
 863         if (mctrl & TIOCM_CTS)
 864                 temp |= UARTMODEM_TXCTSE;
 865
 866         writeb(temp, port->membase + UARTMODEM);
 867 }
 868
 869 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 870 {
 871         unsigned long temp;
 872
 873         temp = lpuart32_read(port->membase + UARTMODIR) &
 874                         ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
 875
 876         if (mctrl & TIOCM_RTS)
 877                 temp |= UARTMODIR_RXRTSE;
 878
 879         if (mctrl & TIOCM_CTS)
 880                 temp |= UARTMODIR_TXCTSE;
 881
 882         lpuart32_write(temp, port->membase + UARTMODIR);
 883 }
 884
 885 static void lpuart_break_ctl(struct uart_port *port, int break_state)
 886 {
 887         unsigned char temp;
 888
 889         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
 890
 891         if (break_state != 0)
 892                 temp |= UARTCR2_SBK;
 893
 894         writeb(temp, port->membase + UARTCR2);
 895 }
 896
 897 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
 898 {
 899         unsigned long temp;
 900
 901         temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
 902
 903         if (break_state != 0)
 904                 temp |= UARTCTRL_SBK;
 905
 906         lpuart32_write(temp, port->membase + UARTCTRL);
 907 }
 908
 909 static void lpuart_setup_watermark(struct lpuart_port *sport)
 910 {
 911         unsigned char val, cr2;
 912         unsigned char cr2_saved;
 913
 914         cr2 = readb(sport->port.membase + UARTCR2);
 915         cr2_saved = cr2;
 916         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
 917                         UARTCR2_RIE | UARTCR2_RE);
 918         writeb(cr2, sport->port.membase + UARTCR2);
 919
 920         val = readb(sport->port.membase + UARTPFIFO);
 921         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
 922                         sport->port.membase + UARTPFIFO);
 923
 924         /* explicitly clear RDRF */
 925         readb(sport->port.membase + UARTSR1);
 926
 927         /* flush Tx and Rx FIFO */
 928         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 929                         sport->port.membase + UARTCFIFO);
 930
 931         writeb(0, sport->port.membase + UARTTWFIFO);
 932         writeb(1, sport->port.membase + UARTRWFIFO);
 933
 934         /* Restore cr2 */
 935         writeb(cr2_saved, sport->port.membase + UARTCR2);
 936 }
 937
 938 static void lpuart32_setup_watermark(struct lpuart_port *sport)
 939 {
 940         unsigned long val, ctrl;
 941         unsigned long ctrl_saved;
 942
 943         ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
 944         ctrl_saved = ctrl;
 945         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
 946                         UARTCTRL_RIE | UARTCTRL_RE);
 947         lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
 948
 949         /* enable FIFO mode */
 950         val = lpuart32_read(sport->port.membase + UARTFIFO);
 951         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
 952         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
 953         lpuart32_write(val, sport->port.membase + UARTFIFO);
 954
 955         /* set the watermark */
 956         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
 957         lpuart32_write(val, sport->port.membase + UARTWATER);
 958
 959         /* Restore cr2 */
 960         lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
 961 }
 962
 963 static int lpuart_dma_tx_request(struct uart_port *port)
 964 {
 965         struct lpuart_port *sport = container_of(port,
 966                                         struct lpuart_port, port);
 967         struct dma_slave_config dma_tx_sconfig;
 968         dma_addr_t dma_bus;
 969         unsigned char *dma_buf;
 970         int ret;
 971
 972         dma_bus = dma_map_single(sport->dma_tx_chan->device->dev,
 973                                 sport->port.state->xmit.buf,
 974                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 975
 976         if (dma_mapping_error(sport->dma_tx_chan->device->dev, dma_bus)) {
 977                 dev_err(sport->port.dev, "dma_map_single tx failed\n");
 978                 return -ENOMEM;
 979         }
 980
 981         dma_buf = sport->port.state->xmit.buf;
 982         dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
 983         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 984         dma_tx_sconfig.dst_maxburst = sport->txfifo_size;
 985         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 986         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 987
 988         if (ret < 0) {
 989                 dev_err(sport->port.dev,
 990                                 "Dma slave config failed, err = %d\n", ret);
 991                 return ret;
 992         }
 993
 994         sport->dma_tx_buf_virt = dma_buf;
 995         sport->dma_tx_buf_bus = dma_bus;
 996         sport->dma_tx_in_progress = 0;
 997
 998         return 0;
 999 }
1000
1001 static int lpuart_dma_rx_request(struct uart_port *port)
1002 {
1003         struct lpuart_port *sport = container_of(port,
1004                                         struct lpuart_port, port);
1005         struct dma_slave_config dma_rx_sconfig;
1006         dma_addr_t dma_bus;
1007         unsigned char *dma_buf;
1008         int ret;
1009
1010         dma_buf = devm_kzalloc(sport->port.dev,
1011                                 FSL_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL);
1012
1013         if (!dma_buf) {
1014                 dev_err(sport->port.dev, "Dma rx alloc failed\n");
1015                 return -ENOMEM;
1016         }
1017
1018         dma_bus = dma_map_single(sport->dma_rx_chan->device->dev, dma_buf,
1019                                 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1020
1021         if (dma_mapping_error(sport->dma_rx_chan->device->dev, dma_bus)) {
1022                 dev_err(sport->port.dev, "dma_map_single rx failed\n");
1023                 return -ENOMEM;
1024         }
1025
1026         dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
1027         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1028         dma_rx_sconfig.src_maxburst = 1;
1029         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1030         ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
1031
1032         if (ret < 0) {
1033                 dev_err(sport->port.dev,
1034                                 "Dma slave config failed, err = %d\n", ret);
1035                 return ret;
1036         }
1037
1038         sport->dma_rx_buf_virt = dma_buf;
1039         sport->dma_rx_buf_bus = dma_bus;
1040         sport->dma_rx_in_progress = 0;
1041
1042         return 0;
1043 }
1044
1045 static void lpuart_dma_tx_free(struct uart_port *port)
1046 {
1047         struct lpuart_port *sport = container_of(port,
1048                                         struct lpuart_port, port);
1049
1050         dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
1051                         UART_XMIT_SIZE, DMA_TO_DEVICE);
1052
1053         sport->dma_tx_buf_bus = 0;
1054         sport->dma_tx_buf_virt = NULL;
1055 }
1056
1057 static void lpuart_dma_rx_free(struct uart_port *port)
1058 {
1059         struct lpuart_port *sport = container_of(port,
1060                                         struct lpuart_port, port);
1061
1062         dma_unmap_single(sport->port.dev, sport->dma_rx_buf_bus,
1063                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1064
1065         sport->dma_rx_buf_bus = 0;
1066         sport->dma_rx_buf_virt = NULL;
1067 }
1068
1069 static int lpuart_startup(struct uart_port *port)
1070 {
1071         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1072         int ret;
1073         unsigned long flags;
1074         unsigned char temp;
1075
1076         /* determine FIFO size and enable FIFO mode */
1077         temp = readb(sport->port.membase + UARTPFIFO);
1078
1079         sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1080                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1081
1082         sport->port.fifosize = sport->txfifo_size;
1083
1084         sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1085                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1086
1087         if (sport->dma_rx_chan && !lpuart_dma_rx_request(port)) {
1088                 sport->lpuart_dma_rx_use = true;
1089                 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1090                             (unsigned long)sport);
1091         } else
1092                 sport->lpuart_dma_rx_use = false;
1093
1094
1095         if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1096                 sport->lpuart_dma_tx_use = true;
1097                 temp = readb(port->membase + UARTCR5);
1098                 temp &= ~UARTCR5_RDMAS;
1099                 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1100         } else
1101                 sport->lpuart_dma_tx_use = false;
1102
1103         ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1104                                 DRIVER_NAME, sport);
1105         if (ret)
1106                 return ret;
1107
1108         spin_lock_irqsave(&sport->port.lock, flags);
1109
1110         lpuart_setup_watermark(sport);
1111
1112         temp = readb(sport->port.membase + UARTCR2);
1113         temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1114         writeb(temp, sport->port.membase + UARTCR2);
1115
1116         spin_unlock_irqrestore(&sport->port.lock, flags);
1117         return 0;
1118 }
1119
1120 static int lpuart32_startup(struct uart_port *port)
1121 {
1122         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1123         int ret;
1124         unsigned long flags;
1125         unsigned long temp;
1126
1127         /* determine FIFO size */
1128         temp = lpuart32_read(sport->port.membase + UARTFIFO);
1129
1130         sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1131                 UARTFIFO_FIFOSIZE_MASK) - 1);
1132
1133         sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1134                 UARTFIFO_FIFOSIZE_MASK) - 1);
1135
1136         ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1137                                 DRIVER_NAME, sport);
1138         if (ret)
1139                 return ret;
1140
1141         spin_lock_irqsave(&sport->port.lock, flags);
1142
1143         lpuart32_setup_watermark(sport);
1144
1145         temp = lpuart32_read(sport->port.membase + UARTCTRL);
1146         temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1147         temp |= UARTCTRL_ILIE;
1148         lpuart32_write(temp, sport->port.membase + UARTCTRL);
1149
1150         spin_unlock_irqrestore(&sport->port.lock, flags);
1151         return 0;
1152 }
1153
1154 static void lpuart_shutdown(struct uart_port *port)
1155 {
1156         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1157         unsigned char temp;
1158         unsigned long flags;
1159
1160         spin_lock_irqsave(&port->lock, flags);
1161
1162         /* disable Rx/Tx and interrupts */
1163         temp = readb(port->membase + UARTCR2);
1164         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1165                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1166         writeb(temp, port->membase + UARTCR2);
1167
1168         spin_unlock_irqrestore(&port->lock, flags);
1169
1170         devm_free_irq(port->dev, port->irq, sport);
1171
1172         if (sport->lpuart_dma_rx_use) {
1173                 lpuart_dma_rx_free(&sport->port);
1174                 del_timer_sync(&sport->lpuart_timer);
1175         }
1176
1177         if (sport->lpuart_dma_tx_use)
1178                 lpuart_dma_tx_free(&sport->port);
1179 }
1180
1181 static void lpuart32_shutdown(struct uart_port *port)
1182 {
1183         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1184         unsigned long temp;
1185         unsigned long flags;
1186
1187         spin_lock_irqsave(&port->lock, flags);
1188
1189         /* disable Rx/Tx and interrupts */
1190         temp = lpuart32_read(port->membase + UARTCTRL);
1191         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1192                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1193         lpuart32_write(temp, port->membase + UARTCTRL);
1194
1195         spin_unlock_irqrestore(&port->lock, flags);
1196
1197         devm_free_irq(port->dev, port->irq, sport);
1198 }
1199
1200 static void
1201 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1202                    struct ktermios *old)
1203 {
1204         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1205         unsigned long flags;
1206         unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
1207         unsigned int  baud;
1208         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1209         unsigned int sbr, brfa;
1210
1211         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1212         old_cr2 = readb(sport->port.membase + UARTCR2);
1213         cr4 = readb(sport->port.membase + UARTCR4);
1214         bdh = readb(sport->port.membase + UARTBDH);
1215         modem = readb(sport->port.membase + UARTMODEM);
1216         /*
1217          * only support CS8 and CS7, and for CS7 must enable PE.
1218          * supported mode:
1219          *  - (7,e/o,1)
1220          *  - (8,n,1)
1221          *  - (8,m/s,1)
1222          *  - (8,e/o,1)
1223          */
1224         while ((termios->c_cflag & CSIZE) != CS8 &&
1225                 (termios->c_cflag & CSIZE) != CS7) {
1226                 termios->c_cflag &= ~CSIZE;
1227                 termios->c_cflag |= old_csize;
1228                 old_csize = CS8;
1229         }
1230
1231         if ((termios->c_cflag & CSIZE) == CS8 ||
1232                 (termios->c_cflag & CSIZE) == CS7)
1233                 cr1 = old_cr1 & ~UARTCR1_M;
1234
1235         if (termios->c_cflag & CMSPAR) {
1236                 if ((termios->c_cflag & CSIZE) != CS8) {
1237                         termios->c_cflag &= ~CSIZE;
1238                         termios->c_cflag |= CS8;
1239                 }
1240                 cr1 |= UARTCR1_M;
1241         }
1242
1243         if (termios->c_cflag & CRTSCTS) {
1244                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1245         } else {
1246                 termios->c_cflag &= ~CRTSCTS;
1247                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1248         }
1249
1250         if (termios->c_cflag & CSTOPB)
1251                 termios->c_cflag &= ~CSTOPB;
1252
1253         /* parity must be enabled when CS7 to match 8-bits format */
1254         if ((termios->c_cflag & CSIZE) == CS7)
1255                 termios->c_cflag |= PARENB;
1256
1257         if ((termios->c_cflag & PARENB)) {
1258                 if (termios->c_cflag & CMSPAR) {
1259                         cr1 &= ~UARTCR1_PE;
1260                         cr1 |= UARTCR1_M;
1261                 } else {
1262                         cr1 |= UARTCR1_PE;
1263                         if ((termios->c_cflag & CSIZE) == CS8)
1264                                 cr1 |= UARTCR1_M;
1265                         if (termios->c_cflag & PARODD)
1266                                 cr1 |= UARTCR1_PT;
1267                         else
1268                                 cr1 &= ~UARTCR1_PT;
1269                 }
1270         }
1271
1272         /* ask the core to calculate the divisor */
1273         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1274
1275         spin_lock_irqsave(&sport->port.lock, flags);
1276
1277         sport->port.read_status_mask = 0;
1278         if (termios->c_iflag & INPCK)
1279                 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
1280         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1281                 sport->port.read_status_mask |= UARTSR1_FE;
1282
1283         /* characters to ignore */
1284         sport->port.ignore_status_mask = 0;
1285         if (termios->c_iflag & IGNPAR)
1286                 sport->port.ignore_status_mask |= UARTSR1_PE;
1287         if (termios->c_iflag & IGNBRK) {
1288                 sport->port.ignore_status_mask |= UARTSR1_FE;
1289                 /*
1290                  * if we're ignoring parity and break indicators,
1291                  * ignore overruns too (for real raw support).
1292                  */
1293                 if (termios->c_iflag & IGNPAR)
1294                         sport->port.ignore_status_mask |= UARTSR1_OR;
1295         }
1296
1297         /* update the per-port timeout */
1298         uart_update_timeout(port, termios->c_cflag, baud);
1299
1300         if (sport->lpuart_dma_rx_use) {
1301                 /* Calculate delay for 1.5 DMA buffers */
1302                 sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
1303                                         FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
1304                                         sport->rxfifo_size / 2;
1305                 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1306                         sport->dma_rx_timeout * 1000 / HZ, sport->port.timeout);
1307                 if (sport->dma_rx_timeout < msecs_to_jiffies(20))
1308                         sport->dma_rx_timeout = msecs_to_jiffies(20);
1309         }
1310
1311         /* wait transmit engin complete */
1312         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1313                 barrier();
1314
1315         /* disable transmit and receive */
1316         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1317                         sport->port.membase + UARTCR2);
1318
1319         sbr = sport->port.uartclk / (16 * baud);
1320         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1321         bdh &= ~UARTBDH_SBR_MASK;
1322         bdh |= (sbr >> 8) & 0x1F;
1323         cr4 &= ~UARTCR4_BRFA_MASK;
1324         brfa &= UARTCR4_BRFA_MASK;
1325         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1326         writeb(bdh, sport->port.membase + UARTBDH);
1327         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1328         writeb(cr1, sport->port.membase + UARTCR1);
1329         writeb(modem, sport->port.membase + UARTMODEM);
1330
1331         /* restore control register */
1332         writeb(old_cr2, sport->port.membase + UARTCR2);
1333
1334         spin_unlock_irqrestore(&sport->port.lock, flags);
1335 }
1336
1337 static void
1338 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1339                    struct ktermios *old)
1340 {
1341         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1342         unsigned long flags;
1343         unsigned long ctrl, old_ctrl, bd, modem;
1344         unsigned int  baud;
1345         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1346         unsigned int sbr;
1347
1348         ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1349         bd = lpuart32_read(sport->port.membase + UARTBAUD);
1350         modem = lpuart32_read(sport->port.membase + UARTMODIR);
1351         /*
1352          * only support CS8 and CS7, and for CS7 must enable PE.
1353          * supported mode:
1354          *  - (7,e/o,1)
1355          *  - (8,n,1)
1356          *  - (8,m/s,1)
1357          *  - (8,e/o,1)
1358          */
1359         while ((termios->c_cflag & CSIZE) != CS8 &&
1360                 (termios->c_cflag & CSIZE) != CS7) {
1361                 termios->c_cflag &= ~CSIZE;
1362                 termios->c_cflag |= old_csize;
1363                 old_csize = CS8;
1364         }
1365
1366         if ((termios->c_cflag & CSIZE) == CS8 ||
1367                 (termios->c_cflag & CSIZE) == CS7)
1368                 ctrl = old_ctrl & ~UARTCTRL_M;
1369
1370         if (termios->c_cflag & CMSPAR) {
1371                 if ((termios->c_cflag & CSIZE) != CS8) {
1372                         termios->c_cflag &= ~CSIZE;
1373                         termios->c_cflag |= CS8;
1374                 }
1375                 ctrl |= UARTCTRL_M;
1376         }
1377
1378         if (termios->c_cflag & CRTSCTS) {
1379                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1380         } else {
1381                 termios->c_cflag &= ~CRTSCTS;
1382                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1383         }
1384
1385         if (termios->c_cflag & CSTOPB)
1386                 termios->c_cflag &= ~CSTOPB;
1387
1388         /* parity must be enabled when CS7 to match 8-bits format */
1389         if ((termios->c_cflag & CSIZE) == CS7)
1390                 termios->c_cflag |= PARENB;
1391
1392         if ((termios->c_cflag & PARENB)) {
1393                 if (termios->c_cflag & CMSPAR) {
1394                         ctrl &= ~UARTCTRL_PE;
1395                         ctrl |= UARTCTRL_M;
1396                 } else {
1397                         ctrl |= UARTCR1_PE;
1398                         if ((termios->c_cflag & CSIZE) == CS8)
1399                                 ctrl |= UARTCTRL_M;
1400                         if (termios->c_cflag & PARODD)
1401                                 ctrl |= UARTCTRL_PT;
1402                         else
1403                                 ctrl &= ~UARTCTRL_PT;
1404                 }
1405         }
1406
1407         /* ask the core to calculate the divisor */
1408         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1409
1410         spin_lock_irqsave(&sport->port.lock, flags);
1411
1412         sport->port.read_status_mask = 0;
1413         if (termios->c_iflag & INPCK)
1414                 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1415         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1416                 sport->port.read_status_mask |= UARTSTAT_FE;
1417
1418         /* characters to ignore */
1419         sport->port.ignore_status_mask = 0;
1420         if (termios->c_iflag & IGNPAR)
1421                 sport->port.ignore_status_mask |= UARTSTAT_PE;
1422         if (termios->c_iflag & IGNBRK) {
1423                 sport->port.ignore_status_mask |= UARTSTAT_FE;
1424                 /*
1425                  * if we're ignoring parity and break indicators,
1426                  * ignore overruns too (for real raw support).
1427                  */
1428                 if (termios->c_iflag & IGNPAR)
1429                         sport->port.ignore_status_mask |= UARTSTAT_OR;
1430         }
1431
1432         /* update the per-port timeout */
1433         uart_update_timeout(port, termios->c_cflag, baud);
1434
1435         /* wait transmit engin complete */
1436         while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1437                 barrier();
1438
1439         /* disable transmit and receive */
1440         lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1441                         sport->port.membase + UARTCTRL);
1442
1443         sbr = sport->port.uartclk / (16 * baud);
1444         bd &= ~UARTBAUD_SBR_MASK;
1445         bd |= sbr & UARTBAUD_SBR_MASK;
1446         bd |= UARTBAUD_BOTHEDGE;
1447         bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1448         lpuart32_write(bd, sport->port.membase + UARTBAUD);
1449         lpuart32_write(modem, sport->port.membase + UARTMODIR);
1450         lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1451         /* restore control register */
1452
1453         spin_unlock_irqrestore(&sport->port.lock, flags);
1454 }
1455
1456 static const char *lpuart_type(struct uart_port *port)
1457 {
1458         return "FSL_LPUART";
1459 }
1460
1461 static void lpuart_release_port(struct uart_port *port)
1462 {
1463         /* nothing to do */
1464 }
1465
1466 static int lpuart_request_port(struct uart_port *port)
1467 {
1468         return  0;
1469 }
1470
1471 /* configure/autoconfigure the port */
1472 static void lpuart_config_port(struct uart_port *port, int flags)
1473 {
1474         if (flags & UART_CONFIG_TYPE)
1475                 port->type = PORT_LPUART;
1476 }
1477
1478 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1479 {
1480         int ret = 0;
1481
1482         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1483                 ret = -EINVAL;
1484         if (port->irq != ser->irq)
1485                 ret = -EINVAL;
1486         if (ser->io_type != UPIO_MEM)
1487                 ret = -EINVAL;
1488         if (port->uartclk / 16 != ser->baud_base)
1489                 ret = -EINVAL;
1490         if (port->iobase != ser->port)
1491                 ret = -EINVAL;
1492         if (ser->hub6 != 0)
1493                 ret = -EINVAL;
1494         return ret;
1495 }
1496
1497 static struct uart_ops lpuart_pops = {
1498         .tx_empty       = lpuart_tx_empty,
1499         .set_mctrl      = lpuart_set_mctrl,
1500         .get_mctrl      = lpuart_get_mctrl,
1501         .stop_tx        = lpuart_stop_tx,
1502         .start_tx       = lpuart_start_tx,
1503         .stop_rx        = lpuart_stop_rx,
1504         .break_ctl      = lpuart_break_ctl,
1505         .startup        = lpuart_startup,
1506         .shutdown       = lpuart_shutdown,
1507         .set_termios    = lpuart_set_termios,
1508         .type           = lpuart_type,
1509         .request_port   = lpuart_request_port,
1510         .release_port   = lpuart_release_port,
1511         .config_port    = lpuart_config_port,
1512         .verify_port    = lpuart_verify_port,
1513         .flush_buffer   = lpuart_flush_buffer,
1514 };
1515
1516 static struct uart_ops lpuart32_pops = {
1517         .tx_empty       = lpuart32_tx_empty,
1518         .set_mctrl      = lpuart32_set_mctrl,
1519         .get_mctrl      = lpuart32_get_mctrl,
1520         .stop_tx        = lpuart32_stop_tx,
1521         .start_tx       = lpuart32_start_tx,
1522         .stop_rx        = lpuart32_stop_rx,
1523         .break_ctl      = lpuart32_break_ctl,
1524         .startup        = lpuart32_startup,
1525         .shutdown       = lpuart32_shutdown,
1526         .set_termios    = lpuart32_set_termios,
1527         .type           = lpuart_type,
1528         .request_port   = lpuart_request_port,
1529         .release_port   = lpuart_release_port,
1530         .config_port    = lpuart_config_port,
1531         .verify_port    = lpuart_verify_port,
1532         .flush_buffer   = lpuart_flush_buffer,
1533 };
1534
1535 static struct lpuart_port *lpuart_ports[UART_NR];
1536
1537 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1538 static void lpuart_console_putchar(struct uart_port *port, int ch)
1539 {
1540         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1541                 barrier();
1542
1543         writeb(ch, port->membase + UARTDR);
1544 }
1545
1546 static void lpuart32_console_putchar(struct uart_port *port, int ch)
1547 {
1548         while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1549                 barrier();
1550
1551         lpuart32_write(ch, port->membase + UARTDATA);
1552 }
1553
1554 static void
1555 lpuart_console_write(struct console *co, const char *s, unsigned int count)
1556 {
1557         struct lpuart_port *sport = lpuart_ports[co->index];
1558         unsigned char  old_cr2, cr2;
1559
1560         /* first save CR2 and then disable interrupts */
1561         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1562         cr2 |= (UARTCR2_TE |  UARTCR2_RE);
1563         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1564         writeb(cr2, sport->port.membase + UARTCR2);
1565
1566         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1567
1568         /* wait for transmitter finish complete and restore CR2 */
1569         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1570                 barrier();
1571
1572         writeb(old_cr2, sport->port.membase + UARTCR2);
1573 }
1574
1575 static void
1576 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1577 {
1578         struct lpuart_port *sport = lpuart_ports[co->index];
1579         unsigned long  old_cr, cr;
1580
1581         /* first save CR2 and then disable interrupts */
1582         cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1583         cr |= (UARTCTRL_TE |  UARTCTRL_RE);
1584         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1585         lpuart32_write(cr, sport->port.membase + UARTCTRL);
1586
1587         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1588
1589         /* wait for transmitter finish complete and restore CR2 */
1590         while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1591                 barrier();
1592
1593         lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1594 }
1595
1596 /*
1597  * if the port was already initialised (eg, by a boot loader),
1598  * try to determine the current setup.
1599  */
1600 static void __init
1601 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1602                            int *parity, int *bits)
1603 {
1604         unsigned char cr, bdh, bdl, brfa;
1605         unsigned int sbr, uartclk, baud_raw;
1606
1607         cr = readb(sport->port.membase + UARTCR2);
1608         cr &= UARTCR2_TE | UARTCR2_RE;
1609         if (!cr)
1610                 return;
1611
1612         /* ok, the port was enabled */
1613
1614         cr = readb(sport->port.membase + UARTCR1);
1615
1616         *parity = 'n';
1617         if (cr & UARTCR1_PE) {
1618                 if (cr & UARTCR1_PT)
1619                         *parity = 'o';
1620                 else
1621                         *parity = 'e';
1622         }
1623
1624         if (cr & UARTCR1_M)
1625                 *bits = 9;
1626         else
1627                 *bits = 8;
1628
1629         bdh = readb(sport->port.membase + UARTBDH);
1630         bdh &= UARTBDH_SBR_MASK;
1631         bdl = readb(sport->port.membase + UARTBDL);
1632         sbr = bdh;
1633         sbr <<= 8;
1634         sbr |= bdl;
1635         brfa = readb(sport->port.membase + UARTCR4);
1636         brfa &= UARTCR4_BRFA_MASK;
1637
1638         uartclk = clk_get_rate(sport->clk);
1639         /*
1640          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1641          */
1642         baud_raw = uartclk / (16 * (sbr + brfa / 32));
1643
1644         if (*baud != baud_raw)
1645                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1646                                 "from %d to %d\n", baud_raw, *baud);
1647 }
1648
1649 static void __init
1650 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1651                            int *parity, int *bits)
1652 {
1653         unsigned long cr, bd;
1654         unsigned int sbr, uartclk, baud_raw;
1655
1656         cr = lpuart32_read(sport->port.membase + UARTCTRL);
1657         cr &= UARTCTRL_TE | UARTCTRL_RE;
1658         if (!cr)
1659                 return;
1660
1661         /* ok, the port was enabled */
1662
1663         cr = lpuart32_read(sport->port.membase + UARTCTRL);
1664
1665         *parity = 'n';
1666         if (cr & UARTCTRL_PE) {
1667                 if (cr & UARTCTRL_PT)
1668                         *parity = 'o';
1669                 else
1670                         *parity = 'e';
1671         }
1672
1673         if (cr & UARTCTRL_M)
1674                 *bits = 9;
1675         else
1676                 *bits = 8;
1677
1678         bd = lpuart32_read(sport->port.membase + UARTBAUD);
1679         bd &= UARTBAUD_SBR_MASK;
1680         sbr = bd;
1681         uartclk = clk_get_rate(sport->clk);
1682         /*
1683          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1684          */
1685         baud_raw = uartclk / (16 * sbr);
1686
1687         if (*baud != baud_raw)
1688                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1689                                 "from %d to %d\n", baud_raw, *baud);
1690 }
1691
1692 static int __init lpuart_console_setup(struct console *co, char *options)
1693 {
1694         struct lpuart_port *sport;
1695         int baud = 115200;
1696         int bits = 8;
1697         int parity = 'n';
1698         int flow = 'n';
1699
1700         /*
1701          * check whether an invalid uart number has been specified, and
1702          * if so, search for the first available port that does have
1703          * console support.
1704          */
1705         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1706                 co->index = 0;
1707
1708         sport = lpuart_ports[co->index];
1709         if (sport == NULL)
1710                 return -ENODEV;
1711
1712         if (options)
1713                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1714         else
1715                 if (sport->lpuart32)
1716                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
1717                 else
1718                         lpuart_console_get_options(sport, &baud, &parity, &bits);
1719
1720         if (sport->lpuart32)
1721                 lpuart32_setup_watermark(sport);
1722         else
1723                 lpuart_setup_watermark(sport);
1724
1725         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1726 }
1727
1728 static struct uart_driver lpuart_reg;
1729 static struct console lpuart_console = {
1730         .name           = DEV_NAME,
1731         .write          = lpuart_console_write,
1732         .device         = uart_console_device,
1733         .setup          = lpuart_console_setup,
1734         .flags          = CON_PRINTBUFFER,
1735         .index          = -1,
1736         .data           = &lpuart_reg,
1737 };
1738
1739 static struct console lpuart32_console = {
1740         .name           = DEV_NAME,
1741         .write          = lpuart32_console_write,
1742         .device         = uart_console_device,
1743         .setup          = lpuart_console_setup,
1744         .flags          = CON_PRINTBUFFER,
1745         .index          = -1,
1746         .data           = &lpuart_reg,
1747 };
1748
1749 #define LPUART_CONSOLE  (&lpuart_console)
1750 #define LPUART32_CONSOLE        (&lpuart32_console)
1751 #else
1752 #define LPUART_CONSOLE  NULL
1753 #define LPUART32_CONSOLE        NULL
1754 #endif
1755
1756 static struct uart_driver lpuart_reg = {
1757         .owner          = THIS_MODULE,
1758         .driver_name    = DRIVER_NAME,
1759         .dev_name       = DEV_NAME,
1760         .nr             = ARRAY_SIZE(lpuart_ports),
1761         .cons           = LPUART_CONSOLE,
1762 };
1763
1764 static int lpuart_probe(struct platform_device *pdev)
1765 {
1766         struct device_node *np = pdev->dev.of_node;
1767         struct lpuart_port *sport;
1768         struct resource *res;
1769         int ret;
1770
1771         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1772         if (!sport)
1773                 return -ENOMEM;
1774
1775         pdev->dev.coherent_dma_mask = 0;
1776
1777         ret = of_alias_get_id(np, "serial");
1778         if (ret < 0) {
1779                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1780                 return ret;
1781         }
1782         sport->port.line = ret;
1783         sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
1784
1785         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1786         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1787         if (IS_ERR(sport->port.membase))
1788                 return PTR_ERR(sport->port.membase);
1789
1790         sport->port.mapbase = res->start;
1791         sport->port.dev = &pdev->dev;
1792         sport->port.type = PORT_LPUART;
1793         sport->port.iotype = UPIO_MEM;
1794         sport->port.irq = platform_get_irq(pdev, 0);
1795         if (sport->lpuart32)
1796                 sport->port.ops = &lpuart32_pops;
1797         else
1798                 sport->port.ops = &lpuart_pops;
1799         sport->port.flags = UPF_BOOT_AUTOCONF;
1800
1801         sport->clk = devm_clk_get(&pdev->dev, "ipg");
1802         if (IS_ERR(sport->clk)) {
1803                 ret = PTR_ERR(sport->clk);
1804                 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1805                 return ret;
1806         }
1807
1808         ret = clk_prepare_enable(sport->clk);
1809         if (ret) {
1810                 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1811                 return ret;
1812         }
1813
1814         sport->port.uartclk = clk_get_rate(sport->clk);
1815
1816         lpuart_ports[sport->port.line] = sport;
1817
1818         platform_set_drvdata(pdev, &sport->port);
1819
1820         if (sport->lpuart32)
1821                 lpuart_reg.cons = LPUART32_CONSOLE;
1822         else
1823                 lpuart_reg.cons = LPUART_CONSOLE;
1824
1825         ret = uart_add_one_port(&lpuart_reg, &sport->port);
1826         if (ret) {
1827                 clk_disable_unprepare(sport->clk);
1828                 return ret;
1829         }
1830
1831         sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
1832         if (!sport->dma_tx_chan)
1833                 dev_info(sport->port.dev, "DMA tx channel request failed, "
1834                                 "operating without tx DMA\n");
1835
1836         sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
1837         if (!sport->dma_rx_chan)
1838                 dev_info(sport->port.dev, "DMA rx channel request failed, "
1839                                 "operating without rx DMA\n");
1840
1841         return 0;
1842 }
1843
1844 static int lpuart_remove(struct platform_device *pdev)
1845 {
1846         struct lpuart_port *sport = platform_get_drvdata(pdev);
1847
1848         uart_remove_one_port(&lpuart_reg, &sport->port);
1849
1850         clk_disable_unprepare(sport->clk);
1851
1852         if (sport->dma_tx_chan)
1853                 dma_release_channel(sport->dma_tx_chan);
1854
1855         if (sport->dma_rx_chan)
1856                 dma_release_channel(sport->dma_rx_chan);
1857
1858         return 0;
1859 }
1860
1861 #ifdef CONFIG_PM_SLEEP
1862 static int lpuart_suspend(struct device *dev)
1863 {
1864         struct lpuart_port *sport = dev_get_drvdata(dev);
1865         unsigned long temp;
1866
1867         if (sport->lpuart32) {
1868                 /* disable Rx/Tx and interrupts */
1869                 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1870                 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
1871                 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1872         } else {
1873                 /* disable Rx/Tx and interrupts */
1874                 temp = readb(sport->port.membase + UARTCR2);
1875                 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
1876                 writeb(temp, sport->port.membase + UARTCR2);
1877         }
1878
1879         uart_suspend_port(&lpuart_reg, &sport->port);
1880
1881         return 0;
1882 }
1883
1884 static int lpuart_resume(struct device *dev)
1885 {
1886         struct lpuart_port *sport = dev_get_drvdata(dev);
1887         unsigned long temp;
1888
1889         if (sport->lpuart32) {
1890                 lpuart32_setup_watermark(sport);
1891                 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1892                 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
1893                          UARTCTRL_TE | UARTCTRL_ILIE);
1894                 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1895         } else {
1896                 lpuart_setup_watermark(sport);
1897                 temp = readb(sport->port.membase + UARTCR2);
1898                 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1899                 writeb(temp, sport->port.membase + UARTCR2);
1900         }
1901
1902         uart_resume_port(&lpuart_reg, &sport->port);
1903
1904         return 0;
1905 }
1906 #endif
1907
1908 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
1909
1910 static struct platform_driver lpuart_driver = {
1911         .probe          = lpuart_probe,
1912         .remove         = lpuart_remove,
1913         .driver         = {
1914                 .name   = "fsl-lpuart",
1915                 .of_match_table = lpuart_dt_ids,
1916                 .pm     = &lpuart_pm_ops,
1917         },
1918 };
1919
1920 static int __init lpuart_serial_init(void)
1921 {
1922         int ret = uart_register_driver(&lpuart_reg);
1923
1924         if (ret)
1925                 return ret;
1926
1927         ret = platform_driver_register(&lpuart_driver);
1928         if (ret)
1929                 uart_unregister_driver(&lpuart_reg);
1930
1931         return ret;
1932 }
1933
1934 static void __exit lpuart_serial_exit(void)
1935 {
1936         platform_driver_unregister(&lpuart_driver);
1937         uart_unregister_driver(&lpuart_reg);
1938 }
1939
1940 module_init(lpuart_serial_init);
1941 module_exit(lpuart_serial_exit);
1942
1943 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
1944 MODULE_LICENSE("GPL v2");