2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/module.h>
26 #include <linux/tty.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/serial.h>
31 #include <linux/clk.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
37 #include <linux/of_device.h>
38 #include <linux/of_gpio.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmaengine.h>
41 #include <linux/atmel_pdc.h>
42 #include <linux/atmel_serial.h>
43 #include <linux/uaccess.h>
44 #include <linux/platform_data/atmel.h>
45 #include <linux/timer.h>
46 #include <linux/gpio.h>
47 #include <linux/gpio/consumer.h>
48 #include <linux/err.h>
49 #include <linux/irq.h>
50 #include <linux/suspend.h>
53 #include <asm/ioctls.h>
55 #define PDC_BUFFER_SIZE 512
56 /* Revisit: We should calculate this based on the actual port settings */
57 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
59 /* The minium number of data FIFOs should be able to contain */
60 #define ATMEL_MIN_FIFO_SIZE 8
62 * These two offsets are substracted from the RX FIFO size to define the RTS
63 * high and low thresholds
65 #define ATMEL_RTS_HIGH_OFFSET 16
66 #define ATMEL_RTS_LOW_OFFSET 20
68 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
72 #include <linux/serial_core.h>
74 #include "serial_mctrl_gpio.h"
76 static void atmel_start_rx(struct uart_port *port);
77 static void atmel_stop_rx(struct uart_port *port);
79 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
81 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
82 * should coexist with the 8250 driver, such as if we have an external 16C550
84 #define SERIAL_ATMEL_MAJOR 204
85 #define MINOR_START 154
86 #define ATMEL_DEVICENAME "ttyAT"
90 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
91 * name, but it is legally reserved for the 8250 driver. */
92 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
93 #define MINOR_START 64
94 #define ATMEL_DEVICENAME "ttyS"
98 #define ATMEL_ISR_PASS_LIMIT 256
100 struct atmel_dma_buffer {
103 unsigned int dma_size;
107 struct atmel_uart_char {
112 #define ATMEL_SERIAL_RINGSIZE 1024
115 * at91: 6 USARTs and one DBGU port (SAM9260)
118 #define ATMEL_MAX_UART 7
121 * We wrap our port structure around the generic uart_port.
123 struct atmel_uart_port {
124 struct uart_port uart; /* uart */
125 struct clk *clk; /* uart clock */
126 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
127 u32 backup_imr; /* IMR saved during suspend */
128 int break_active; /* break being received */
130 bool use_dma_rx; /* enable DMA receiver */
131 bool use_pdc_rx; /* enable PDC receiver */
132 short pdc_rx_idx; /* current PDC RX buffer */
133 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
135 bool use_dma_tx; /* enable DMA transmitter */
136 bool use_pdc_tx; /* enable PDC transmitter */
137 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
139 spinlock_t lock_tx; /* port lock */
140 spinlock_t lock_rx; /* port lock */
141 struct dma_chan *chan_tx;
142 struct dma_chan *chan_rx;
143 struct dma_async_tx_descriptor *desc_tx;
144 struct dma_async_tx_descriptor *desc_rx;
145 dma_cookie_t cookie_tx;
146 dma_cookie_t cookie_rx;
147 struct scatterlist sg_tx;
148 struct scatterlist sg_rx;
149 struct tasklet_struct tasklet;
150 unsigned int irq_status;
151 unsigned int irq_status_prev;
152 unsigned int status_change;
155 struct circ_buf rx_ring;
157 struct mctrl_gpios *gpios;
158 int gpio_irq[UART_GPIO_MAX];
159 unsigned int tx_done_mask;
164 bool is_usart; /* usart or uart */
165 struct timer_list uart_timer; /* uart timer */
168 unsigned int pending;
169 unsigned int pending_status;
170 spinlock_t lock_suspended;
172 int (*prepare_rx)(struct uart_port *port);
173 int (*prepare_tx)(struct uart_port *port);
174 void (*schedule_rx)(struct uart_port *port);
175 void (*schedule_tx)(struct uart_port *port);
176 void (*release_rx)(struct uart_port *port);
177 void (*release_tx)(struct uart_port *port);
180 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
181 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
184 static struct console atmel_console;
187 #if defined(CONFIG_OF)
188 static const struct of_device_id atmel_serial_dt_ids[] = {
189 { .compatible = "atmel,at91rm9200-usart" },
190 { .compatible = "atmel,at91sam9260-usart" },
194 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
197 static inline struct atmel_uart_port *
198 to_atmel_uart_port(struct uart_port *uart)
200 return container_of(uart, struct atmel_uart_port, uart);
203 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
205 return __raw_readl(port->membase + reg);
208 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
210 __raw_writel(value, port->membase + reg);
215 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
216 static inline u8 atmel_uart_read_char(struct uart_port *port)
218 return __raw_readl(port->membase + ATMEL_US_RHR);
221 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
223 __raw_writel(value, port->membase + ATMEL_US_THR);
228 static inline u8 atmel_uart_read_char(struct uart_port *port)
230 return __raw_readb(port->membase + ATMEL_US_RHR);
233 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
235 __raw_writeb(value, port->membase + ATMEL_US_THR);
240 #ifdef CONFIG_SERIAL_ATMEL_PDC
241 static bool atmel_use_pdc_rx(struct uart_port *port)
243 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
245 return atmel_port->use_pdc_rx;
248 static bool atmel_use_pdc_tx(struct uart_port *port)
250 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
252 return atmel_port->use_pdc_tx;
255 static bool atmel_use_pdc_rx(struct uart_port *port)
260 static bool atmel_use_pdc_tx(struct uart_port *port)
266 static bool atmel_use_dma_tx(struct uart_port *port)
268 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
270 return atmel_port->use_dma_tx;
273 static bool atmel_use_dma_rx(struct uart_port *port)
275 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
277 return atmel_port->use_dma_rx;
280 static bool atmel_use_fifo(struct uart_port *port)
282 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
284 return atmel_port->fifo_size;
287 static unsigned int atmel_get_lines_status(struct uart_port *port)
289 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
290 unsigned int status, ret = 0;
292 status = atmel_uart_readl(port, ATMEL_US_CSR);
294 mctrl_gpio_get(atmel_port->gpios, &ret);
296 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
299 status &= ~ATMEL_US_CTS;
301 status |= ATMEL_US_CTS;
304 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
307 status &= ~ATMEL_US_DSR;
309 status |= ATMEL_US_DSR;
312 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
315 status &= ~ATMEL_US_RI;
317 status |= ATMEL_US_RI;
320 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
323 status &= ~ATMEL_US_DCD;
325 status |= ATMEL_US_DCD;
331 /* Enable or disable the rs485 support */
332 static int atmel_config_rs485(struct uart_port *port,
333 struct serial_rs485 *rs485conf)
335 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
338 /* Disable interrupts */
339 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
341 mode = atmel_uart_readl(port, ATMEL_US_MR);
343 /* Resetting serial mode to RS232 (0x0) */
344 mode &= ~ATMEL_US_USMODE;
346 port->rs485 = *rs485conf;
348 if (rs485conf->flags & SER_RS485_ENABLED) {
349 dev_dbg(port->dev, "Setting UART to RS485\n");
350 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
351 atmel_uart_writel(port, ATMEL_US_TTGR,
352 rs485conf->delay_rts_after_send);
353 mode |= ATMEL_US_USMODE_RS485;
355 dev_dbg(port->dev, "Setting UART to RS232\n");
356 if (atmel_use_pdc_tx(port))
357 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
360 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
362 atmel_uart_writel(port, ATMEL_US_MR, mode);
364 /* Enable interrupts */
365 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
371 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
373 static u_int atmel_tx_empty(struct uart_port *port)
375 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
381 * Set state of the modem control output lines
383 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
385 unsigned int control = 0;
386 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
387 unsigned int rts_paused, rts_ready;
388 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
390 /* override mode to RS485 if needed, otherwise keep the current mode */
391 if (port->rs485.flags & SER_RS485_ENABLED) {
392 atmel_uart_writel(port, ATMEL_US_TTGR,
393 port->rs485.delay_rts_after_send);
394 mode &= ~ATMEL_US_USMODE;
395 mode |= ATMEL_US_USMODE_RS485;
398 /* set the RTS line state according to the mode */
399 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
400 /* force RTS line to high level */
401 rts_paused = ATMEL_US_RTSEN;
403 /* give the control of the RTS line back to the hardware */
404 rts_ready = ATMEL_US_RTSDIS;
406 /* force RTS line to high level */
407 rts_paused = ATMEL_US_RTSDIS;
409 /* force RTS line to low level */
410 rts_ready = ATMEL_US_RTSEN;
413 if (mctrl & TIOCM_RTS)
414 control |= rts_ready;
416 control |= rts_paused;
418 if (mctrl & TIOCM_DTR)
419 control |= ATMEL_US_DTREN;
421 control |= ATMEL_US_DTRDIS;
423 atmel_uart_writel(port, ATMEL_US_CR, control);
425 mctrl_gpio_set(atmel_port->gpios, mctrl);
427 /* Local loopback mode? */
428 mode &= ~ATMEL_US_CHMODE;
429 if (mctrl & TIOCM_LOOP)
430 mode |= ATMEL_US_CHMODE_LOC_LOOP;
432 mode |= ATMEL_US_CHMODE_NORMAL;
434 atmel_uart_writel(port, ATMEL_US_MR, mode);
438 * Get state of the modem control input lines
440 static u_int atmel_get_mctrl(struct uart_port *port)
442 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
443 unsigned int ret = 0, status;
445 status = atmel_uart_readl(port, ATMEL_US_CSR);
448 * The control signals are active low.
450 if (!(status & ATMEL_US_DCD))
452 if (!(status & ATMEL_US_CTS))
454 if (!(status & ATMEL_US_DSR))
456 if (!(status & ATMEL_US_RI))
459 return mctrl_gpio_get(atmel_port->gpios, &ret);
465 static void atmel_stop_tx(struct uart_port *port)
467 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
469 if (atmel_use_pdc_tx(port)) {
470 /* disable PDC transmit */
471 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
475 * Disable the transmitter.
476 * This is mandatory when DMA is used, otherwise the DMA buffer
477 * is fully transmitted.
479 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
481 /* Disable interrupts */
482 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
484 if ((port->rs485.flags & SER_RS485_ENABLED) &&
485 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
486 atmel_start_rx(port);
490 * Start transmitting.
492 static void atmel_start_tx(struct uart_port *port)
494 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
496 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
498 /* The transmitter is already running. Yes, we
502 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
503 if ((port->rs485.flags & SER_RS485_ENABLED) &&
504 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
507 if (atmel_use_pdc_tx(port))
508 /* re-enable PDC transmit */
509 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
511 /* Enable interrupts */
512 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
514 /* re-enable the transmitter */
515 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
519 * start receiving - port is in process of being opened.
521 static void atmel_start_rx(struct uart_port *port)
523 /* reset status and receiver */
524 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
526 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
528 if (atmel_use_pdc_rx(port)) {
529 /* enable PDC controller */
530 atmel_uart_writel(port, ATMEL_US_IER,
531 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
532 port->read_status_mask);
533 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
535 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
540 * Stop receiving - port is in process of being closed.
542 static void atmel_stop_rx(struct uart_port *port)
544 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
546 if (atmel_use_pdc_rx(port)) {
547 /* disable PDC receive */
548 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
549 atmel_uart_writel(port, ATMEL_US_IDR,
550 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
551 port->read_status_mask);
553 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
558 * Enable modem status interrupts
560 static void atmel_enable_ms(struct uart_port *port)
562 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
566 * Interrupt should not be enabled twice
568 if (atmel_port->ms_irq_enabled)
571 atmel_port->ms_irq_enabled = true;
573 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
574 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
576 ier |= ATMEL_US_CTSIC;
578 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
579 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
581 ier |= ATMEL_US_DSRIC;
583 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
584 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
586 ier |= ATMEL_US_RIIC;
588 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
589 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
591 ier |= ATMEL_US_DCDIC;
593 atmel_uart_writel(port, ATMEL_US_IER, ier);
597 * Disable modem status interrupts
599 static void atmel_disable_ms(struct uart_port *port)
601 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
605 * Interrupt should not be disabled twice
607 if (!atmel_port->ms_irq_enabled)
610 atmel_port->ms_irq_enabled = false;
612 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
613 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
615 idr |= ATMEL_US_CTSIC;
617 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
618 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
620 idr |= ATMEL_US_DSRIC;
622 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
623 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
625 idr |= ATMEL_US_RIIC;
627 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
628 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
630 idr |= ATMEL_US_DCDIC;
632 atmel_uart_writel(port, ATMEL_US_IDR, idr);
636 * Control the transmission of a break signal
638 static void atmel_break_ctl(struct uart_port *port, int break_state)
640 if (break_state != 0)
642 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
645 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
649 * Stores the incoming character in the ring buffer
652 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
655 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
656 struct circ_buf *ring = &atmel_port->rx_ring;
657 struct atmel_uart_char *c;
659 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
660 /* Buffer overflow, ignore char */
663 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
667 /* Make sure the character is stored before we update head. */
670 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
674 * Deal with parity, framing and overrun errors.
676 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
679 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
681 if (status & ATMEL_US_RXBRK) {
682 /* ignore side-effect */
683 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
686 if (status & ATMEL_US_PARE)
687 port->icount.parity++;
688 if (status & ATMEL_US_FRAME)
689 port->icount.frame++;
690 if (status & ATMEL_US_OVRE)
691 port->icount.overrun++;
695 * Characters received (called from interrupt handler)
697 static void atmel_rx_chars(struct uart_port *port)
699 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
700 unsigned int status, ch;
702 status = atmel_uart_readl(port, ATMEL_US_CSR);
703 while (status & ATMEL_US_RXRDY) {
704 ch = atmel_uart_read_char(port);
707 * note that the error handling code is
708 * out of the main execution path
710 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
711 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
712 || atmel_port->break_active)) {
715 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
717 if (status & ATMEL_US_RXBRK
718 && !atmel_port->break_active) {
719 atmel_port->break_active = 1;
720 atmel_uart_writel(port, ATMEL_US_IER,
724 * This is either the end-of-break
725 * condition or we've received at
726 * least one character without RXBRK
727 * being set. In both cases, the next
728 * RXBRK will indicate start-of-break.
730 atmel_uart_writel(port, ATMEL_US_IDR,
732 status &= ~ATMEL_US_RXBRK;
733 atmel_port->break_active = 0;
737 atmel_buffer_rx_char(port, status, ch);
738 status = atmel_uart_readl(port, ATMEL_US_CSR);
741 tasklet_schedule(&atmel_port->tasklet);
745 * Transmit characters (called from tasklet with TXRDY interrupt
748 static void atmel_tx_chars(struct uart_port *port)
750 struct circ_buf *xmit = &port->state->xmit;
751 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
754 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
755 atmel_uart_write_char(port, port->x_char);
759 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
762 while (atmel_uart_readl(port, ATMEL_US_CSR) &
763 atmel_port->tx_done_mask) {
764 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
765 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
767 if (uart_circ_empty(xmit))
771 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
772 uart_write_wakeup(port);
774 if (!uart_circ_empty(xmit))
775 /* Enable interrupts */
776 atmel_uart_writel(port, ATMEL_US_IER,
777 atmel_port->tx_done_mask);
780 static void atmel_complete_tx_dma(void *arg)
782 struct atmel_uart_port *atmel_port = arg;
783 struct uart_port *port = &atmel_port->uart;
784 struct circ_buf *xmit = &port->state->xmit;
785 struct dma_chan *chan = atmel_port->chan_tx;
788 spin_lock_irqsave(&port->lock, flags);
791 dmaengine_terminate_all(chan);
792 xmit->tail += atmel_port->tx_len;
793 xmit->tail &= UART_XMIT_SIZE - 1;
795 port->icount.tx += atmel_port->tx_len;
797 spin_lock_irq(&atmel_port->lock_tx);
798 async_tx_ack(atmel_port->desc_tx);
799 atmel_port->cookie_tx = -EINVAL;
800 atmel_port->desc_tx = NULL;
801 spin_unlock_irq(&atmel_port->lock_tx);
803 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
804 uart_write_wakeup(port);
807 * xmit is a circular buffer so, if we have just send data from
808 * xmit->tail to the end of xmit->buf, now we have to transmit the
809 * remaining data from the beginning of xmit->buf to xmit->head.
811 if (!uart_circ_empty(xmit))
812 tasklet_schedule(&atmel_port->tasklet);
814 spin_unlock_irqrestore(&port->lock, flags);
817 static void atmel_release_tx_dma(struct uart_port *port)
819 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
820 struct dma_chan *chan = atmel_port->chan_tx;
823 dmaengine_terminate_all(chan);
824 dma_release_channel(chan);
825 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
829 atmel_port->desc_tx = NULL;
830 atmel_port->chan_tx = NULL;
831 atmel_port->cookie_tx = -EINVAL;
835 * Called from tasklet with TXRDY interrupt is disabled.
837 static void atmel_tx_dma(struct uart_port *port)
839 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
840 struct circ_buf *xmit = &port->state->xmit;
841 struct dma_chan *chan = atmel_port->chan_tx;
842 struct dma_async_tx_descriptor *desc;
843 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
844 unsigned int tx_len, part1_len, part2_len, sg_len;
845 dma_addr_t phys_addr;
847 /* Make sure we have an idle channel */
848 if (atmel_port->desc_tx != NULL)
851 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
854 * Port xmit buffer is already mapped,
855 * and it is one page... Just adjust
856 * offsets and lengths. Since it is a circular buffer,
857 * we have to transmit till the end, and then the rest.
858 * Take the port lock to get a
859 * consistent xmit buffer state.
861 tx_len = CIRC_CNT_TO_END(xmit->head,
865 if (atmel_port->fifo_size) {
866 /* multi data mode */
867 part1_len = (tx_len & ~0x3); /* DWORD access */
868 part2_len = (tx_len & 0x3); /* BYTE access */
870 /* single data (legacy) mode */
872 part2_len = tx_len; /* BYTE access only */
875 sg_init_table(sgl, 2);
877 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
880 sg_dma_address(sg) = phys_addr;
881 sg_dma_len(sg) = part1_len;
883 phys_addr += part1_len;
888 sg_dma_address(sg) = phys_addr;
889 sg_dma_len(sg) = part2_len;
893 * save tx_len so atmel_complete_tx_dma() will increase
894 * xmit->tail correctly
896 atmel_port->tx_len = tx_len;
898 desc = dmaengine_prep_slave_sg(chan,
905 dev_err(port->dev, "Failed to send via dma!\n");
909 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
911 atmel_port->desc_tx = desc;
912 desc->callback = atmel_complete_tx_dma;
913 desc->callback_param = atmel_port;
914 atmel_port->cookie_tx = dmaengine_submit(desc);
917 if (port->rs485.flags & SER_RS485_ENABLED) {
918 /* DMA done, stop TX, start RX for RS485 */
919 atmel_start_rx(port);
923 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
924 uart_write_wakeup(port);
927 static int atmel_prepare_tx_dma(struct uart_port *port)
929 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
931 struct dma_slave_config config;
935 dma_cap_set(DMA_SLAVE, mask);
937 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
938 if (atmel_port->chan_tx == NULL)
940 dev_info(port->dev, "using %s for tx DMA transfers\n",
941 dma_chan_name(atmel_port->chan_tx));
943 spin_lock_init(&atmel_port->lock_tx);
944 sg_init_table(&atmel_port->sg_tx, 1);
945 /* UART circular tx buffer is an aligned page. */
946 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
947 sg_set_page(&atmel_port->sg_tx,
948 virt_to_page(port->state->xmit.buf),
950 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
951 nent = dma_map_sg(port->dev,
957 dev_dbg(port->dev, "need to release resource of dma\n");
960 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
961 sg_dma_len(&atmel_port->sg_tx),
962 port->state->xmit.buf,
963 &sg_dma_address(&atmel_port->sg_tx));
966 /* Configure the slave DMA */
967 memset(&config, 0, sizeof(config));
968 config.direction = DMA_MEM_TO_DEV;
969 config.dst_addr_width = (atmel_port->fifo_size) ?
970 DMA_SLAVE_BUSWIDTH_4_BYTES :
971 DMA_SLAVE_BUSWIDTH_1_BYTE;
972 config.dst_addr = port->mapbase + ATMEL_US_THR;
973 config.dst_maxburst = 1;
975 ret = dmaengine_slave_config(atmel_port->chan_tx,
978 dev_err(port->dev, "DMA tx slave configuration failed\n");
985 dev_err(port->dev, "TX channel not available, switch to pio\n");
986 atmel_port->use_dma_tx = 0;
987 if (atmel_port->chan_tx)
988 atmel_release_tx_dma(port);
992 static void atmel_complete_rx_dma(void *arg)
994 struct uart_port *port = arg;
995 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
997 tasklet_schedule(&atmel_port->tasklet);
1000 static void atmel_release_rx_dma(struct uart_port *port)
1002 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1003 struct dma_chan *chan = atmel_port->chan_rx;
1006 dmaengine_terminate_all(chan);
1007 dma_release_channel(chan);
1008 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1012 atmel_port->desc_rx = NULL;
1013 atmel_port->chan_rx = NULL;
1014 atmel_port->cookie_rx = -EINVAL;
1017 static void atmel_rx_from_dma(struct uart_port *port)
1019 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1020 struct tty_port *tport = &port->state->port;
1021 struct circ_buf *ring = &atmel_port->rx_ring;
1022 struct dma_chan *chan = atmel_port->chan_rx;
1023 struct dma_tx_state state;
1024 enum dma_status dmastat;
1028 /* Reset the UART timeout early so that we don't miss one */
1029 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1030 dmastat = dmaengine_tx_status(chan,
1031 atmel_port->cookie_rx,
1033 /* Restart a new tasklet if DMA status is error */
1034 if (dmastat == DMA_ERROR) {
1035 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1036 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1037 tasklet_schedule(&atmel_port->tasklet);
1041 /* CPU claims ownership of RX DMA buffer */
1042 dma_sync_sg_for_cpu(port->dev,
1048 * ring->head points to the end of data already written by the DMA.
1049 * ring->tail points to the beginning of data to be read by the
1051 * The current transfer size should not be larger than the dma buffer
1054 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1055 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1057 * At this point ring->head may point to the first byte right after the
1058 * last byte of the dma buffer:
1059 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1061 * However ring->tail must always points inside the dma buffer:
1062 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1064 * Since we use a ring buffer, we have to handle the case
1065 * where head is lower than tail. In such a case, we first read from
1066 * tail to the end of the buffer then reset tail.
1068 if (ring->head < ring->tail) {
1069 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1071 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1073 port->icount.rx += count;
1076 /* Finally we read data from tail to head */
1077 if (ring->tail < ring->head) {
1078 count = ring->head - ring->tail;
1080 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1081 /* Wrap ring->head if needed */
1082 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1084 ring->tail = ring->head;
1085 port->icount.rx += count;
1088 /* USART retreives ownership of RX DMA buffer */
1089 dma_sync_sg_for_device(port->dev,
1095 * Drop the lock here since it might end up calling
1096 * uart_start(), which takes the lock.
1098 spin_unlock(&port->lock);
1099 tty_flip_buffer_push(tport);
1100 spin_lock(&port->lock);
1102 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1105 static int atmel_prepare_rx_dma(struct uart_port *port)
1107 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1108 struct dma_async_tx_descriptor *desc;
1109 dma_cap_mask_t mask;
1110 struct dma_slave_config config;
1111 struct circ_buf *ring;
1114 ring = &atmel_port->rx_ring;
1117 dma_cap_set(DMA_CYCLIC, mask);
1119 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1120 if (atmel_port->chan_rx == NULL)
1122 dev_info(port->dev, "using %s for rx DMA transfers\n",
1123 dma_chan_name(atmel_port->chan_rx));
1125 spin_lock_init(&atmel_port->lock_rx);
1126 sg_init_table(&atmel_port->sg_rx, 1);
1127 /* UART circular rx buffer is an aligned page. */
1128 BUG_ON(!PAGE_ALIGNED(ring->buf));
1129 sg_set_page(&atmel_port->sg_rx,
1130 virt_to_page(ring->buf),
1131 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1132 (unsigned long)ring->buf & ~PAGE_MASK);
1133 nent = dma_map_sg(port->dev,
1139 dev_dbg(port->dev, "need to release resource of dma\n");
1142 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1143 sg_dma_len(&atmel_port->sg_rx),
1145 &sg_dma_address(&atmel_port->sg_rx));
1148 /* Configure the slave DMA */
1149 memset(&config, 0, sizeof(config));
1150 config.direction = DMA_DEV_TO_MEM;
1151 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1152 config.src_addr = port->mapbase + ATMEL_US_RHR;
1153 config.src_maxburst = 1;
1155 ret = dmaengine_slave_config(atmel_port->chan_rx,
1158 dev_err(port->dev, "DMA rx slave configuration failed\n");
1162 * Prepare a cyclic dma transfer, assign 2 descriptors,
1163 * each one is half ring buffer size
1165 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1166 sg_dma_address(&atmel_port->sg_rx),
1167 sg_dma_len(&atmel_port->sg_rx),
1168 sg_dma_len(&atmel_port->sg_rx)/2,
1170 DMA_PREP_INTERRUPT);
1171 desc->callback = atmel_complete_rx_dma;
1172 desc->callback_param = port;
1173 atmel_port->desc_rx = desc;
1174 atmel_port->cookie_rx = dmaengine_submit(desc);
1179 dev_err(port->dev, "RX channel not available, switch to pio\n");
1180 atmel_port->use_dma_rx = 0;
1181 if (atmel_port->chan_rx)
1182 atmel_release_rx_dma(port);
1186 static void atmel_uart_timer_callback(unsigned long data)
1188 struct uart_port *port = (void *)data;
1189 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1191 tasklet_schedule(&atmel_port->tasklet);
1192 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1196 * receive interrupt handler.
1199 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1201 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1203 if (atmel_use_pdc_rx(port)) {
1205 * PDC receive. Just schedule the tasklet and let it
1206 * figure out the details.
1208 * TODO: We're not handling error flags correctly at
1211 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1212 atmel_uart_writel(port, ATMEL_US_IDR,
1213 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1214 tasklet_schedule(&atmel_port->tasklet);
1217 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1218 ATMEL_US_FRAME | ATMEL_US_PARE))
1219 atmel_pdc_rxerr(port, pending);
1222 if (atmel_use_dma_rx(port)) {
1223 if (pending & ATMEL_US_TIMEOUT) {
1224 atmel_uart_writel(port, ATMEL_US_IDR,
1226 tasklet_schedule(&atmel_port->tasklet);
1230 /* Interrupt receive */
1231 if (pending & ATMEL_US_RXRDY)
1232 atmel_rx_chars(port);
1233 else if (pending & ATMEL_US_RXBRK) {
1235 * End of break detected. If it came along with a
1236 * character, atmel_rx_chars will handle it.
1238 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1239 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1240 atmel_port->break_active = 0;
1245 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1248 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1250 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1252 if (pending & atmel_port->tx_done_mask) {
1253 /* Either PDC or interrupt transmission */
1254 atmel_uart_writel(port, ATMEL_US_IDR,
1255 atmel_port->tx_done_mask);
1256 tasklet_schedule(&atmel_port->tasklet);
1261 * status flags interrupt handler.
1264 atmel_handle_status(struct uart_port *port, unsigned int pending,
1265 unsigned int status)
1267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1269 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1270 | ATMEL_US_CTSIC)) {
1271 atmel_port->irq_status = status;
1272 atmel_port->status_change = atmel_port->irq_status ^
1273 atmel_port->irq_status_prev;
1274 atmel_port->irq_status_prev = status;
1275 tasklet_schedule(&atmel_port->tasklet);
1282 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1284 struct uart_port *port = dev_id;
1285 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1286 unsigned int status, pending, mask, pass_counter = 0;
1287 bool gpio_handled = false;
1289 spin_lock(&atmel_port->lock_suspended);
1292 status = atmel_get_lines_status(port);
1293 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1294 pending = status & mask;
1295 if (!gpio_handled) {
1297 * Dealing with GPIO interrupt
1299 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS])
1300 pending |= ATMEL_US_CTSIC;
1302 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR])
1303 pending |= ATMEL_US_DSRIC;
1305 if (irq == atmel_port->gpio_irq[UART_GPIO_RI])
1306 pending |= ATMEL_US_RIIC;
1308 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD])
1309 pending |= ATMEL_US_DCDIC;
1311 gpio_handled = true;
1316 if (atmel_port->suspended) {
1317 atmel_port->pending |= pending;
1318 atmel_port->pending_status = status;
1319 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1324 atmel_handle_receive(port, pending);
1325 atmel_handle_status(port, pending, status);
1326 atmel_handle_transmit(port, pending);
1327 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1329 spin_unlock(&atmel_port->lock_suspended);
1331 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1334 static void atmel_release_tx_pdc(struct uart_port *port)
1336 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1337 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1339 dma_unmap_single(port->dev,
1346 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1348 static void atmel_tx_pdc(struct uart_port *port)
1350 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1351 struct circ_buf *xmit = &port->state->xmit;
1352 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1355 /* nothing left to transmit? */
1356 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1359 xmit->tail += pdc->ofs;
1360 xmit->tail &= UART_XMIT_SIZE - 1;
1362 port->icount.tx += pdc->ofs;
1365 /* more to transmit - setup next transfer */
1367 /* disable PDC transmit */
1368 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1370 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1371 dma_sync_single_for_device(port->dev,
1376 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1379 atmel_uart_writel(port, ATMEL_PDC_TPR,
1380 pdc->dma_addr + xmit->tail);
1381 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1382 /* re-enable PDC transmit */
1383 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1384 /* Enable interrupts */
1385 atmel_uart_writel(port, ATMEL_US_IER,
1386 atmel_port->tx_done_mask);
1388 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1389 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1390 /* DMA done, stop TX, start RX for RS485 */
1391 atmel_start_rx(port);
1395 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1396 uart_write_wakeup(port);
1399 static int atmel_prepare_tx_pdc(struct uart_port *port)
1401 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1402 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1403 struct circ_buf *xmit = &port->state->xmit;
1405 pdc->buf = xmit->buf;
1406 pdc->dma_addr = dma_map_single(port->dev,
1410 pdc->dma_size = UART_XMIT_SIZE;
1416 static void atmel_rx_from_ring(struct uart_port *port)
1418 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1419 struct circ_buf *ring = &atmel_port->rx_ring;
1421 unsigned int status;
1423 while (ring->head != ring->tail) {
1424 struct atmel_uart_char c;
1426 /* Make sure c is loaded after head. */
1429 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1431 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1438 * note that the error handling code is
1439 * out of the main execution path
1441 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1442 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1443 if (status & ATMEL_US_RXBRK) {
1444 /* ignore side-effect */
1445 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1448 if (uart_handle_break(port))
1451 if (status & ATMEL_US_PARE)
1452 port->icount.parity++;
1453 if (status & ATMEL_US_FRAME)
1454 port->icount.frame++;
1455 if (status & ATMEL_US_OVRE)
1456 port->icount.overrun++;
1458 status &= port->read_status_mask;
1460 if (status & ATMEL_US_RXBRK)
1462 else if (status & ATMEL_US_PARE)
1464 else if (status & ATMEL_US_FRAME)
1469 if (uart_handle_sysrq_char(port, c.ch))
1472 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1476 * Drop the lock here since it might end up calling
1477 * uart_start(), which takes the lock.
1479 spin_unlock(&port->lock);
1480 tty_flip_buffer_push(&port->state->port);
1481 spin_lock(&port->lock);
1484 static void atmel_release_rx_pdc(struct uart_port *port)
1486 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1489 for (i = 0; i < 2; i++) {
1490 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1492 dma_unmap_single(port->dev,
1500 static void atmel_rx_from_pdc(struct uart_port *port)
1502 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1503 struct tty_port *tport = &port->state->port;
1504 struct atmel_dma_buffer *pdc;
1505 int rx_idx = atmel_port->pdc_rx_idx;
1511 /* Reset the UART timeout early so that we don't miss one */
1512 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1514 pdc = &atmel_port->pdc_rx[rx_idx];
1515 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1518 /* If the PDC has switched buffers, RPR won't contain
1519 * any address within the current buffer. Since head
1520 * is unsigned, we just need a one-way comparison to
1523 * In this case, we just need to consume the entire
1524 * buffer and resubmit it for DMA. This will clear the
1525 * ENDRX bit as well, so that we can safely re-enable
1526 * all interrupts below.
1528 head = min(head, pdc->dma_size);
1530 if (likely(head != tail)) {
1531 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1532 pdc->dma_size, DMA_FROM_DEVICE);
1535 * head will only wrap around when we recycle
1536 * the DMA buffer, and when that happens, we
1537 * explicitly set tail to 0. So head will
1538 * always be greater than tail.
1540 count = head - tail;
1542 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1545 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1546 pdc->dma_size, DMA_FROM_DEVICE);
1548 port->icount.rx += count;
1553 * If the current buffer is full, we need to check if
1554 * the next one contains any additional data.
1556 if (head >= pdc->dma_size) {
1558 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1559 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1562 atmel_port->pdc_rx_idx = rx_idx;
1564 } while (head >= pdc->dma_size);
1567 * Drop the lock here since it might end up calling
1568 * uart_start(), which takes the lock.
1570 spin_unlock(&port->lock);
1571 tty_flip_buffer_push(tport);
1572 spin_lock(&port->lock);
1574 atmel_uart_writel(port, ATMEL_US_IER,
1575 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1578 static int atmel_prepare_rx_pdc(struct uart_port *port)
1580 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1583 for (i = 0; i < 2; i++) {
1584 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1586 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1587 if (pdc->buf == NULL) {
1589 dma_unmap_single(port->dev,
1590 atmel_port->pdc_rx[0].dma_addr,
1593 kfree(atmel_port->pdc_rx[0].buf);
1595 atmel_port->use_pdc_rx = 0;
1598 pdc->dma_addr = dma_map_single(port->dev,
1602 pdc->dma_size = PDC_BUFFER_SIZE;
1606 atmel_port->pdc_rx_idx = 0;
1608 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1609 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1611 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1612 atmel_port->pdc_rx[1].dma_addr);
1613 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1619 * tasklet handling tty stuff outside the interrupt handler.
1621 static void atmel_tasklet_func(unsigned long data)
1623 struct uart_port *port = (struct uart_port *)data;
1624 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1625 unsigned int status = atmel_port->irq_status;
1626 unsigned int status_change = atmel_port->status_change;
1628 /* The interrupt handler does not take the lock */
1629 spin_lock(&port->lock);
1631 atmel_port->schedule_tx(port);
1633 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1634 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1635 /* TODO: All reads to CSR will clear these interrupts! */
1636 if (status_change & ATMEL_US_RI)
1638 if (status_change & ATMEL_US_DSR)
1640 if (status_change & ATMEL_US_DCD)
1641 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1642 if (status_change & ATMEL_US_CTS)
1643 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1645 wake_up_interruptible(&port->state->port.delta_msr_wait);
1647 atmel_port->status_change = 0;
1650 atmel_port->schedule_rx(port);
1652 spin_unlock(&port->lock);
1655 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1656 struct platform_device *pdev)
1658 struct device_node *np = pdev->dev.of_node;
1659 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1662 /* DMA/PDC usage specification */
1663 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1664 if (of_get_property(np, "dmas", NULL)) {
1665 atmel_port->use_dma_rx = true;
1666 atmel_port->use_pdc_rx = false;
1668 atmel_port->use_dma_rx = false;
1669 atmel_port->use_pdc_rx = true;
1672 atmel_port->use_dma_rx = false;
1673 atmel_port->use_pdc_rx = false;
1676 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1677 if (of_get_property(np, "dmas", NULL)) {
1678 atmel_port->use_dma_tx = true;
1679 atmel_port->use_pdc_tx = false;
1681 atmel_port->use_dma_tx = false;
1682 atmel_port->use_pdc_tx = true;
1685 atmel_port->use_dma_tx = false;
1686 atmel_port->use_pdc_tx = false;
1690 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1691 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1692 atmel_port->use_dma_rx = false;
1693 atmel_port->use_dma_tx = false;
1698 static void atmel_init_rs485(struct uart_port *port,
1699 struct platform_device *pdev)
1701 struct device_node *np = pdev->dev.of_node;
1702 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1705 struct serial_rs485 *rs485conf = &port->rs485;
1707 /* rs485 properties */
1708 if (of_property_read_u32_array(np, "rs485-rts-delay",
1709 rs485_delay, 2) == 0) {
1710 rs485conf->delay_rts_before_send = rs485_delay[0];
1711 rs485conf->delay_rts_after_send = rs485_delay[1];
1712 rs485conf->flags = 0;
1715 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1716 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1718 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1720 rs485conf->flags |= SER_RS485_ENABLED;
1722 port->rs485 = pdata->rs485;
1727 static void atmel_set_ops(struct uart_port *port)
1729 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1731 if (atmel_use_dma_rx(port)) {
1732 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1733 atmel_port->schedule_rx = &atmel_rx_from_dma;
1734 atmel_port->release_rx = &atmel_release_rx_dma;
1735 } else if (atmel_use_pdc_rx(port)) {
1736 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1737 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1738 atmel_port->release_rx = &atmel_release_rx_pdc;
1740 atmel_port->prepare_rx = NULL;
1741 atmel_port->schedule_rx = &atmel_rx_from_ring;
1742 atmel_port->release_rx = NULL;
1745 if (atmel_use_dma_tx(port)) {
1746 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1747 atmel_port->schedule_tx = &atmel_tx_dma;
1748 atmel_port->release_tx = &atmel_release_tx_dma;
1749 } else if (atmel_use_pdc_tx(port)) {
1750 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1751 atmel_port->schedule_tx = &atmel_tx_pdc;
1752 atmel_port->release_tx = &atmel_release_tx_pdc;
1754 atmel_port->prepare_tx = NULL;
1755 atmel_port->schedule_tx = &atmel_tx_chars;
1756 atmel_port->release_tx = NULL;
1761 * Get ip name usart or uart
1763 static void atmel_get_ip_name(struct uart_port *port)
1765 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1766 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1769 /* usart and uart ascii */
1773 atmel_port->is_usart = false;
1775 if (name == usart) {
1776 dev_dbg(port->dev, "This is usart\n");
1777 atmel_port->is_usart = true;
1778 } else if (name == uart) {
1779 dev_dbg(port->dev, "This is uart\n");
1780 atmel_port->is_usart = false;
1782 /* fallback for older SoCs: use version field */
1783 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1787 dev_dbg(port->dev, "This version is usart\n");
1788 atmel_port->is_usart = true;
1792 dev_dbg(port->dev, "This version is uart\n");
1793 atmel_port->is_usart = false;
1796 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1801 static void atmel_free_gpio_irq(struct uart_port *port)
1803 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1804 enum mctrl_gpio_idx i;
1806 for (i = 0; i < UART_GPIO_MAX; i++)
1807 if (atmel_port->gpio_irq[i] >= 0)
1808 free_irq(atmel_port->gpio_irq[i], port);
1811 static int atmel_request_gpio_irq(struct uart_port *port)
1813 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1814 int *irq = atmel_port->gpio_irq;
1815 enum mctrl_gpio_idx i;
1818 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1822 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1823 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH,
1824 "atmel_serial", port);
1826 dev_err(port->dev, "atmel_startup - Can't get %d irq\n",
1831 * If something went wrong, rollback.
1833 while (err && (--i >= 0))
1835 free_irq(irq[i], port);
1841 * Perform initialization and enable port for reception
1843 static int atmel_startup(struct uart_port *port)
1845 struct platform_device *pdev = to_platform_device(port->dev);
1846 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1847 struct tty_struct *tty = port->state->port.tty;
1851 * Ensure that no interrupts are enabled otherwise when
1852 * request_irq() is called we could get stuck trying to
1853 * handle an unexpected interrupt
1855 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1856 atmel_port->ms_irq_enabled = false;
1861 retval = request_irq(port->irq, atmel_interrupt,
1862 IRQF_SHARED | IRQF_COND_SUSPEND,
1863 tty ? tty->name : "atmel_serial", port);
1865 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1870 * Get the GPIO lines IRQ
1872 retval = atmel_request_gpio_irq(port);
1876 tasklet_enable(&atmel_port->tasklet);
1879 * Initialize DMA (if necessary)
1881 atmel_init_property(atmel_port, pdev);
1882 atmel_set_ops(port);
1884 if (atmel_port->prepare_rx) {
1885 retval = atmel_port->prepare_rx(port);
1887 atmel_set_ops(port);
1890 if (atmel_port->prepare_tx) {
1891 retval = atmel_port->prepare_tx(port);
1893 atmel_set_ops(port);
1897 * Enable FIFO when available
1899 if (atmel_port->fifo_size) {
1900 unsigned int txrdym = ATMEL_US_ONE_DATA;
1901 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1904 atmel_uart_writel(port, ATMEL_US_CR,
1909 if (atmel_use_dma_tx(port))
1910 txrdym = ATMEL_US_FOUR_DATA;
1912 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1913 if (atmel_port->rts_high &&
1914 atmel_port->rts_low)
1915 fmr |= ATMEL_US_FRTSC |
1916 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1917 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1919 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1922 /* Save current CSR for comparison in atmel_tasklet_func() */
1923 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1924 atmel_port->irq_status = atmel_port->irq_status_prev;
1927 * Finally, enable the serial port
1929 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1930 /* enable xmit & rcvr */
1931 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1933 setup_timer(&atmel_port->uart_timer,
1934 atmel_uart_timer_callback,
1935 (unsigned long)port);
1937 if (atmel_use_pdc_rx(port)) {
1938 /* set UART timeout */
1939 if (!atmel_port->is_usart) {
1940 mod_timer(&atmel_port->uart_timer,
1941 jiffies + uart_poll_timeout(port));
1942 /* set USART timeout */
1944 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1945 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1947 atmel_uart_writel(port, ATMEL_US_IER,
1948 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1950 /* enable PDC controller */
1951 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1952 } else if (atmel_use_dma_rx(port)) {
1953 /* set UART timeout */
1954 if (!atmel_port->is_usart) {
1955 mod_timer(&atmel_port->uart_timer,
1956 jiffies + uart_poll_timeout(port));
1957 /* set USART timeout */
1959 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1960 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1962 atmel_uart_writel(port, ATMEL_US_IER,
1966 /* enable receive only */
1967 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1973 free_irq(port->irq, port);
1979 * Flush any TX data submitted for DMA. Called when the TX circular
1982 static void atmel_flush_buffer(struct uart_port *port)
1984 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1986 if (atmel_use_pdc_tx(port)) {
1987 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1988 atmel_port->pdc_tx.ofs = 0;
1995 static void atmel_shutdown(struct uart_port *port)
1997 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2000 * Prevent any tasklets being scheduled during
2003 del_timer_sync(&atmel_port->uart_timer);
2006 * Clear out any scheduled tasklets before
2007 * we destroy the buffers
2009 tasklet_disable(&atmel_port->tasklet);
2010 tasklet_kill(&atmel_port->tasklet);
2013 * Ensure everything is stopped and
2014 * disable all interrupts, port and break condition.
2016 atmel_stop_rx(port);
2017 atmel_stop_tx(port);
2019 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2020 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2024 * Shut-down the DMA.
2026 if (atmel_port->release_rx)
2027 atmel_port->release_rx(port);
2028 if (atmel_port->release_tx)
2029 atmel_port->release_tx(port);
2032 * Reset ring buffer pointers
2034 atmel_port->rx_ring.head = 0;
2035 atmel_port->rx_ring.tail = 0;
2038 * Free the interrupts
2040 free_irq(port->irq, port);
2041 atmel_free_gpio_irq(port);
2043 atmel_port->ms_irq_enabled = false;
2045 atmel_flush_buffer(port);
2049 * Power / Clock management.
2051 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2052 unsigned int oldstate)
2054 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2059 * Enable the peripheral clock for this serial port.
2060 * This is called on uart_open() or a resume event.
2062 clk_prepare_enable(atmel_port->clk);
2064 /* re-enable interrupts if we disabled some on suspend */
2065 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2068 /* Back up the interrupt mask and disable all interrupts */
2069 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2070 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2073 * Disable the peripheral clock for this serial port.
2074 * This is called on uart_close() or a suspend event.
2076 clk_disable_unprepare(atmel_port->clk);
2079 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2084 * Change the port parameters
2086 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2087 struct ktermios *old)
2089 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2090 unsigned long flags;
2091 unsigned int old_mode, mode, imr, quot, baud;
2093 /* save the current mode register */
2094 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2096 /* reset the mode, clock divisor, parity, stop bits and data size */
2097 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2098 ATMEL_US_PAR | ATMEL_US_USMODE);
2100 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2101 quot = uart_get_divisor(port, baud);
2103 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2105 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2109 switch (termios->c_cflag & CSIZE) {
2111 mode |= ATMEL_US_CHRL_5;
2114 mode |= ATMEL_US_CHRL_6;
2117 mode |= ATMEL_US_CHRL_7;
2120 mode |= ATMEL_US_CHRL_8;
2125 if (termios->c_cflag & CSTOPB)
2126 mode |= ATMEL_US_NBSTOP_2;
2129 if (termios->c_cflag & PARENB) {
2130 /* Mark or Space parity */
2131 if (termios->c_cflag & CMSPAR) {
2132 if (termios->c_cflag & PARODD)
2133 mode |= ATMEL_US_PAR_MARK;
2135 mode |= ATMEL_US_PAR_SPACE;
2136 } else if (termios->c_cflag & PARODD)
2137 mode |= ATMEL_US_PAR_ODD;
2139 mode |= ATMEL_US_PAR_EVEN;
2141 mode |= ATMEL_US_PAR_NONE;
2143 spin_lock_irqsave(&port->lock, flags);
2145 port->read_status_mask = ATMEL_US_OVRE;
2146 if (termios->c_iflag & INPCK)
2147 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2148 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2149 port->read_status_mask |= ATMEL_US_RXBRK;
2151 if (atmel_use_pdc_rx(port))
2152 /* need to enable error interrupts */
2153 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2156 * Characters to ignore
2158 port->ignore_status_mask = 0;
2159 if (termios->c_iflag & IGNPAR)
2160 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2161 if (termios->c_iflag & IGNBRK) {
2162 port->ignore_status_mask |= ATMEL_US_RXBRK;
2164 * If we're ignoring parity and break indicators,
2165 * ignore overruns too (for real raw support).
2167 if (termios->c_iflag & IGNPAR)
2168 port->ignore_status_mask |= ATMEL_US_OVRE;
2170 /* TODO: Ignore all characters if CREAD is set.*/
2172 /* update the per-port timeout */
2173 uart_update_timeout(port, termios->c_cflag, baud);
2176 * save/disable interrupts. The tty layer will ensure that the
2177 * transmitter is empty if requested by the caller, so there's
2178 * no need to wait for it here.
2180 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2181 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2183 /* disable receiver and transmitter */
2184 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2187 if (port->rs485.flags & SER_RS485_ENABLED) {
2188 atmel_uart_writel(port, ATMEL_US_TTGR,
2189 port->rs485.delay_rts_after_send);
2190 mode |= ATMEL_US_USMODE_RS485;
2191 } else if (termios->c_cflag & CRTSCTS) {
2192 /* RS232 with hardware handshake (RTS/CTS) */
2193 if (atmel_use_fifo(port) &&
2194 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2196 * with ATMEL_US_USMODE_HWHS set, the controller will
2197 * be able to drive the RTS pin high/low when the RX
2198 * FIFO is above RXFTHRES/below RXFTHRES2.
2199 * It will also disable the transmitter when the CTS
2201 * This mode is not activated if CTS pin is a GPIO
2202 * because in this case, the transmitter is always
2203 * disabled (there must be an internal pull-up
2204 * responsible for this behaviour).
2205 * If the RTS pin is a GPIO, the controller won't be
2206 * able to drive it according to the FIFO thresholds,
2207 * but it will be handled by the driver.
2209 mode |= ATMEL_US_USMODE_HWHS;
2212 * For platforms without FIFO, the flow control is
2213 * handled by the driver.
2215 mode |= ATMEL_US_USMODE_NORMAL;
2218 /* RS232 without hadware handshake */
2219 mode |= ATMEL_US_USMODE_NORMAL;
2222 /* set the mode, clock divisor, parity, stop bits and data size */
2223 atmel_uart_writel(port, ATMEL_US_MR, mode);
2226 * when switching the mode, set the RTS line state according to the
2227 * new mode, otherwise keep the former state
2229 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2230 unsigned int rts_state;
2232 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2233 /* let the hardware control the RTS line */
2234 rts_state = ATMEL_US_RTSDIS;
2236 /* force RTS line to low level */
2237 rts_state = ATMEL_US_RTSEN;
2240 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2243 /* set the baud rate */
2244 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2245 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2246 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2248 /* restore interrupts */
2249 atmel_uart_writel(port, ATMEL_US_IER, imr);
2251 /* CTS flow-control and modem-status interrupts */
2252 if (UART_ENABLE_MS(port, termios->c_cflag))
2253 atmel_enable_ms(port);
2255 atmel_disable_ms(port);
2257 spin_unlock_irqrestore(&port->lock, flags);
2260 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2262 if (termios->c_line == N_PPS) {
2263 port->flags |= UPF_HARDPPS_CD;
2264 spin_lock_irq(&port->lock);
2265 atmel_enable_ms(port);
2266 spin_unlock_irq(&port->lock);
2268 port->flags &= ~UPF_HARDPPS_CD;
2269 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2270 spin_lock_irq(&port->lock);
2271 atmel_disable_ms(port);
2272 spin_unlock_irq(&port->lock);
2278 * Return string describing the specified port
2280 static const char *atmel_type(struct uart_port *port)
2282 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2286 * Release the memory region(s) being used by 'port'.
2288 static void atmel_release_port(struct uart_port *port)
2290 struct platform_device *pdev = to_platform_device(port->dev);
2291 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2293 release_mem_region(port->mapbase, size);
2295 if (port->flags & UPF_IOREMAP) {
2296 iounmap(port->membase);
2297 port->membase = NULL;
2302 * Request the memory region(s) being used by 'port'.
2304 static int atmel_request_port(struct uart_port *port)
2306 struct platform_device *pdev = to_platform_device(port->dev);
2307 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2309 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2312 if (port->flags & UPF_IOREMAP) {
2313 port->membase = ioremap(port->mapbase, size);
2314 if (port->membase == NULL) {
2315 release_mem_region(port->mapbase, size);
2324 * Configure/autoconfigure the port.
2326 static void atmel_config_port(struct uart_port *port, int flags)
2328 if (flags & UART_CONFIG_TYPE) {
2329 port->type = PORT_ATMEL;
2330 atmel_request_port(port);
2335 * Verify the new serial_struct (for TIOCSSERIAL).
2337 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2340 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2342 if (port->irq != ser->irq)
2344 if (ser->io_type != SERIAL_IO_MEM)
2346 if (port->uartclk / 16 != ser->baud_base)
2348 if (port->mapbase != (unsigned long)ser->iomem_base)
2350 if (port->iobase != ser->port)
2357 #ifdef CONFIG_CONSOLE_POLL
2358 static int atmel_poll_get_char(struct uart_port *port)
2360 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2363 return atmel_uart_read_char(port);
2366 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2368 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2371 atmel_uart_write_char(port, ch);
2375 static struct uart_ops atmel_pops = {
2376 .tx_empty = atmel_tx_empty,
2377 .set_mctrl = atmel_set_mctrl,
2378 .get_mctrl = atmel_get_mctrl,
2379 .stop_tx = atmel_stop_tx,
2380 .start_tx = atmel_start_tx,
2381 .stop_rx = atmel_stop_rx,
2382 .enable_ms = atmel_enable_ms,
2383 .break_ctl = atmel_break_ctl,
2384 .startup = atmel_startup,
2385 .shutdown = atmel_shutdown,
2386 .flush_buffer = atmel_flush_buffer,
2387 .set_termios = atmel_set_termios,
2388 .set_ldisc = atmel_set_ldisc,
2390 .release_port = atmel_release_port,
2391 .request_port = atmel_request_port,
2392 .config_port = atmel_config_port,
2393 .verify_port = atmel_verify_port,
2394 .pm = atmel_serial_pm,
2395 #ifdef CONFIG_CONSOLE_POLL
2396 .poll_get_char = atmel_poll_get_char,
2397 .poll_put_char = atmel_poll_put_char,
2402 * Configure the port from the platform device resource info.
2404 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2405 struct platform_device *pdev)
2408 struct uart_port *port = &atmel_port->uart;
2409 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2411 atmel_init_property(atmel_port, pdev);
2412 atmel_set_ops(port);
2414 atmel_init_rs485(port, pdev);
2416 port->iotype = UPIO_MEM;
2417 port->flags = UPF_BOOT_AUTOCONF;
2418 port->ops = &atmel_pops;
2420 port->dev = &pdev->dev;
2421 port->mapbase = pdev->resource[0].start;
2422 port->irq = pdev->resource[1].start;
2423 port->rs485_config = atmel_config_rs485;
2425 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2426 (unsigned long)port);
2427 tasklet_disable(&atmel_port->tasklet);
2429 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2431 if (pdata && pdata->regs) {
2432 /* Already mapped by setup code */
2433 port->membase = pdata->regs;
2435 port->flags |= UPF_IOREMAP;
2436 port->membase = NULL;
2439 /* for console, the clock could already be configured */
2440 if (!atmel_port->clk) {
2441 atmel_port->clk = clk_get(&pdev->dev, "usart");
2442 if (IS_ERR(atmel_port->clk)) {
2443 ret = PTR_ERR(atmel_port->clk);
2444 atmel_port->clk = NULL;
2447 ret = clk_prepare_enable(atmel_port->clk);
2449 clk_put(atmel_port->clk);
2450 atmel_port->clk = NULL;
2453 port->uartclk = clk_get_rate(atmel_port->clk);
2454 clk_disable_unprepare(atmel_port->clk);
2455 /* only enable clock when USART is in use */
2458 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2459 if (port->rs485.flags & SER_RS485_ENABLED)
2460 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2461 else if (atmel_use_pdc_tx(port)) {
2462 port->fifosize = PDC_BUFFER_SIZE;
2463 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2465 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2471 struct platform_device *atmel_default_console_device; /* the serial console device */
2473 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2474 static void atmel_console_putchar(struct uart_port *port, int ch)
2476 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2478 atmel_uart_write_char(port, ch);
2482 * Interrupts are disabled on entering
2484 static void atmel_console_write(struct console *co, const char *s, u_int count)
2486 struct uart_port *port = &atmel_ports[co->index].uart;
2487 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2488 unsigned int status, imr;
2489 unsigned int pdc_tx;
2492 * First, save IMR and then disable interrupts
2494 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2495 atmel_uart_writel(port, ATMEL_US_IDR,
2496 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2498 /* Store PDC transmit status and disable it */
2499 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2500 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2502 uart_console_write(port, s, count, atmel_console_putchar);
2505 * Finally, wait for transmitter to become empty
2509 status = atmel_uart_readl(port, ATMEL_US_CSR);
2510 } while (!(status & ATMEL_US_TXRDY));
2512 /* Restore PDC transmit status */
2514 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2516 /* set interrupts back the way they were */
2517 atmel_uart_writel(port, ATMEL_US_IER, imr);
2521 * If the port was already initialised (eg, by a boot loader),
2522 * try to determine the current setup.
2524 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2525 int *parity, int *bits)
2527 unsigned int mr, quot;
2530 * If the baud rate generator isn't running, the port wasn't
2531 * initialized by the boot loader.
2533 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2537 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2538 if (mr == ATMEL_US_CHRL_8)
2543 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2544 if (mr == ATMEL_US_PAR_EVEN)
2546 else if (mr == ATMEL_US_PAR_ODD)
2550 * The serial core only rounds down when matching this to a
2551 * supported baud rate. Make sure we don't end up slightly
2552 * lower than one of those, as it would make us fall through
2553 * to a much lower baud rate than we really want.
2555 *baud = port->uartclk / (16 * (quot - 1));
2558 static int __init atmel_console_setup(struct console *co, char *options)
2561 struct uart_port *port = &atmel_ports[co->index].uart;
2567 if (port->membase == NULL) {
2568 /* Port not initialized yet - delay setup */
2572 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2576 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2577 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2578 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2581 uart_parse_options(options, &baud, &parity, &bits, &flow);
2583 atmel_console_get_options(port, &baud, &parity, &bits);
2585 return uart_set_options(port, co, baud, parity, bits, flow);
2588 static struct uart_driver atmel_uart;
2590 static struct console atmel_console = {
2591 .name = ATMEL_DEVICENAME,
2592 .write = atmel_console_write,
2593 .device = uart_console_device,
2594 .setup = atmel_console_setup,
2595 .flags = CON_PRINTBUFFER,
2597 .data = &atmel_uart,
2600 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2603 * Early console initialization (before VM subsystem initialized).
2605 static int __init atmel_console_init(void)
2608 if (atmel_default_console_device) {
2609 struct atmel_uart_data *pdata =
2610 dev_get_platdata(&atmel_default_console_device->dev);
2611 int id = pdata->num;
2612 struct atmel_uart_port *port = &atmel_ports[id];
2614 port->backup_imr = 0;
2615 port->uart.line = id;
2617 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2618 ret = atmel_init_port(port, atmel_default_console_device);
2621 register_console(&atmel_console);
2627 console_initcall(atmel_console_init);
2630 * Late console initialization.
2632 static int __init atmel_late_console_init(void)
2634 if (atmel_default_console_device
2635 && !(atmel_console.flags & CON_ENABLED))
2636 register_console(&atmel_console);
2641 core_initcall(atmel_late_console_init);
2643 static inline bool atmel_is_console_port(struct uart_port *port)
2645 return port->cons && port->cons->index == port->line;
2649 #define ATMEL_CONSOLE_DEVICE NULL
2651 static inline bool atmel_is_console_port(struct uart_port *port)
2657 static struct uart_driver atmel_uart = {
2658 .owner = THIS_MODULE,
2659 .driver_name = "atmel_serial",
2660 .dev_name = ATMEL_DEVICENAME,
2661 .major = SERIAL_ATMEL_MAJOR,
2662 .minor = MINOR_START,
2663 .nr = ATMEL_MAX_UART,
2664 .cons = ATMEL_CONSOLE_DEVICE,
2668 static bool atmel_serial_clk_will_stop(void)
2670 #ifdef CONFIG_ARCH_AT91
2671 return at91_suspend_entering_slow_clock();
2677 static int atmel_serial_suspend(struct platform_device *pdev,
2680 struct uart_port *port = platform_get_drvdata(pdev);
2681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2683 if (atmel_is_console_port(port) && console_suspend_enabled) {
2684 /* Drain the TX shifter */
2685 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2690 /* we can not wake up if we're running on slow clock */
2691 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2692 if (atmel_serial_clk_will_stop()) {
2693 unsigned long flags;
2695 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2696 atmel_port->suspended = true;
2697 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2698 device_set_wakeup_enable(&pdev->dev, 0);
2701 uart_suspend_port(&atmel_uart, port);
2706 static int atmel_serial_resume(struct platform_device *pdev)
2708 struct uart_port *port = platform_get_drvdata(pdev);
2709 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2710 unsigned long flags;
2712 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2713 if (atmel_port->pending) {
2714 atmel_handle_receive(port, atmel_port->pending);
2715 atmel_handle_status(port, atmel_port->pending,
2716 atmel_port->pending_status);
2717 atmel_handle_transmit(port, atmel_port->pending);
2718 atmel_port->pending = 0;
2720 atmel_port->suspended = false;
2721 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2723 uart_resume_port(&atmel_uart, port);
2724 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2729 #define atmel_serial_suspend NULL
2730 #define atmel_serial_resume NULL
2733 static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev)
2735 enum mctrl_gpio_idx i;
2736 struct gpio_desc *gpiod;
2738 p->gpios = mctrl_gpio_init_noauto(dev, 0);
2739 if (IS_ERR(p->gpios))
2740 return PTR_ERR(p->gpios);
2742 for (i = 0; i < UART_GPIO_MAX; i++) {
2743 gpiod = mctrl_gpio_to_gpiod(p->gpios, i);
2744 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
2745 p->gpio_irq[i] = gpiod_to_irq(gpiod);
2747 p->gpio_irq[i] = -EINVAL;
2753 static void atmel_serial_probe_fifos(struct atmel_uart_port *port,
2754 struct platform_device *pdev)
2756 port->fifo_size = 0;
2760 if (of_property_read_u32(pdev->dev.of_node,
2765 if (!port->fifo_size)
2768 if (port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2769 port->fifo_size = 0;
2770 dev_err(&pdev->dev, "Invalid FIFO size\n");
2775 * 0 <= rts_low <= rts_high <= fifo_size
2776 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2777 * to flush their internal TX FIFO, commonly up to 16 data, before
2778 * actually stopping to send new data. So we try to set the RTS High
2779 * Threshold to a reasonably high value respecting this 16 data
2780 * empirical rule when possible.
2782 port->rts_high = max_t(int, port->fifo_size >> 1,
2783 port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2784 port->rts_low = max_t(int, port->fifo_size >> 2,
2785 port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2787 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2789 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2791 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2795 static int atmel_serial_probe(struct platform_device *pdev)
2797 struct atmel_uart_port *port;
2798 struct device_node *np = pdev->dev.of_node;
2799 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2804 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2807 ret = of_alias_get_id(np, "serial");
2813 /* port id not found in platform data nor device-tree aliases:
2814 * auto-enumerate it */
2815 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2817 if (ret >= ATMEL_MAX_UART) {
2822 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2823 /* port already in use */
2828 port = &atmel_ports[ret];
2829 port->backup_imr = 0;
2830 port->uart.line = ret;
2831 atmel_serial_probe_fifos(port, pdev);
2833 spin_lock_init(&port->lock_suspended);
2835 ret = atmel_init_gpios(port, &pdev->dev);
2837 dev_err(&pdev->dev, "Failed to initialize GPIOs.");
2841 ret = atmel_init_port(port, pdev);
2845 if (!atmel_use_pdc_rx(&port->uart)) {
2847 data = kmalloc(sizeof(struct atmel_uart_char)
2848 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2850 goto err_alloc_ring;
2851 port->rx_ring.buf = data;
2854 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED;
2856 ret = uart_add_one_port(&atmel_uart, &port->uart);
2860 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2861 if (atmel_is_console_port(&port->uart)
2862 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2864 * The serial core enabled the clock for us, so undo
2865 * the clk_prepare_enable() in atmel_console_setup()
2867 clk_disable_unprepare(port->clk);
2871 device_init_wakeup(&pdev->dev, 1);
2872 platform_set_drvdata(pdev, port);
2875 * The peripheral clock has been disabled by atmel_init_port():
2876 * enable it before accessing I/O registers
2878 clk_prepare_enable(port->clk);
2880 if (rs485_enabled) {
2881 atmel_uart_writel(&port->uart, ATMEL_US_MR,
2882 ATMEL_US_USMODE_NORMAL);
2883 atmel_uart_writel(&port->uart, ATMEL_US_CR, ATMEL_US_RTSEN);
2887 * Get port name of usart or uart
2889 atmel_get_ip_name(&port->uart);
2892 * The peripheral clock can now safely be disabled till the port
2895 clk_disable_unprepare(port->clk);
2900 kfree(port->rx_ring.buf);
2901 port->rx_ring.buf = NULL;
2903 if (!atmel_is_console_port(&port->uart)) {
2908 clear_bit(port->uart.line, atmel_ports_in_use);
2913 static int atmel_serial_remove(struct platform_device *pdev)
2915 struct uart_port *port = platform_get_drvdata(pdev);
2916 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2919 tasklet_kill(&atmel_port->tasklet);
2921 device_init_wakeup(&pdev->dev, 0);
2923 ret = uart_remove_one_port(&atmel_uart, port);
2925 kfree(atmel_port->rx_ring.buf);
2927 /* "port" is allocated statically, so we shouldn't free it */
2929 clear_bit(port->line, atmel_ports_in_use);
2931 clk_put(atmel_port->clk);
2936 static struct platform_driver atmel_serial_driver = {
2937 .probe = atmel_serial_probe,
2938 .remove = atmel_serial_remove,
2939 .suspend = atmel_serial_suspend,
2940 .resume = atmel_serial_resume,
2942 .name = "atmel_usart",
2943 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2947 static int __init atmel_serial_init(void)
2951 ret = uart_register_driver(&atmel_uart);
2955 ret = platform_driver_register(&atmel_serial_driver);
2957 uart_unregister_driver(&atmel_uart);
2962 static void __exit atmel_serial_exit(void)
2964 platform_driver_unregister(&atmel_serial_driver);
2965 uart_unregister_driver(&atmel_uart);
2968 module_init(atmel_serial_init);
2969 module_exit(atmel_serial_exit);
2971 MODULE_AUTHOR("Rick Bronson");
2972 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
2973 MODULE_LICENSE("GPL");
2974 MODULE_ALIAS("platform:atmel_usart");