kernel/drivers/tty/serial/8250/8250_ingenic.c

   1 /*
   2  * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
   3  * Copyright (C) 2015 Imagination Technologies
   4  *
   5  * Ingenic SoC UART support
   6  *
   7  * This program is free software; you can redistribute   it and/or modify it
   8  * under  the terms of   the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the   License, or (at your
  10  * option) any later version.
  11  *
  12  * You should have received a copy of the  GNU General Public License along
  13  * with this program; if not, write  to the Free Software Foundation, Inc.,
  14  * 675 Mass Ave, Cambridge, MA 02139, USA.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/console.h>
  19 #include <linux/io.h>
  20 #include <linux/libfdt.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_fdt.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/serial_8250.h>
  27 #include <linux/serial_core.h>
  28 #include <linux/serial_reg.h>
  29
  30 #include "8250.h"
  31
  32 /** ingenic_uart_config: SOC specific config data. */
  33 struct ingenic_uart_config {
  34         int tx_loadsz;
  35         int fifosize;
  36 };
  37
  38 struct ingenic_uart_data {
  39         struct clk      *clk_module;
  40         struct clk      *clk_baud;
  41         int             line;
  42 };
  43
  44 static const struct of_device_id of_match[];
  45
  46 #define UART_FCR_UME    BIT(4)
  47
  48 #define UART_MCR_MDCE   BIT(7)
  49 #define UART_MCR_FCM    BIT(6)
  50
  51 static struct earlycon_device *early_device;
  52
  53 static uint8_t __init early_in(struct uart_port *port, int offset)
  54 {
  55         return readl(port->membase + (offset << 2));
  56 }
  57
  58 static void __init early_out(struct uart_port *port, int offset, uint8_t value)
  59 {
  60         writel(value, port->membase + (offset << 2));
  61 }
  62
  63 static void __init ingenic_early_console_putc(struct uart_port *port, int c)
  64 {
  65         uint8_t lsr;
  66
  67         do {
  68                 lsr = early_in(port, UART_LSR);
  69         } while ((lsr & UART_LSR_TEMT) == 0);
  70
  71         early_out(port, UART_TX, c);
  72 }
  73
  74 static void __init ingenic_early_console_write(struct console *console,
  75                                               const char *s, unsigned int count)
  76 {
  77         uart_console_write(&early_device->port, s, count,
  78                            ingenic_early_console_putc);
  79 }
  80
  81 static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
  82 {
  83         void *fdt = initial_boot_params;
  84         const __be32 *prop;
  85         int offset;
  86
  87         offset = fdt_path_offset(fdt, "/ext");
  88         if (offset < 0)
  89                 return;
  90
  91         prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
  92         if (!prop)
  93                 return;
  94
  95         dev->port.uartclk = be32_to_cpup(prop);
  96 }
  97
  98 static int __init ingenic_early_console_setup(struct earlycon_device *dev,
  99                                               const char *opt)
 100 {
 101         struct uart_port *port = &dev->port;
 102         unsigned int baud, divisor;
 103
 104         if (!dev->port.membase)
 105                 return -ENODEV;
 106
 107         ingenic_early_console_setup_clock(dev);
 108
 109         baud = dev->baud ?: 115200;
 110         divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
 111
 112         early_out(port, UART_IER, 0);
 113         early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
 114         early_out(port, UART_DLL, 0);
 115         early_out(port, UART_DLM, 0);
 116         early_out(port, UART_LCR, UART_LCR_WLEN8);
 117         early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
 118                         UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
 119         early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
 120
 121         early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
 122         early_out(port, UART_DLL, divisor & 0xff);
 123         early_out(port, UART_DLM, (divisor >> 8) & 0xff);
 124         early_out(port, UART_LCR, UART_LCR_WLEN8);
 125
 126         early_device = dev;
 127         dev->con->write = ingenic_early_console_write;
 128
 129         return 0;
 130 }
 131
 132 EARLYCON_DECLARE(jz4740_uart, ingenic_early_console_setup);
 133 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
 134                     ingenic_early_console_setup);
 135
 136 EARLYCON_DECLARE(jz4775_uart, ingenic_early_console_setup);
 137 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
 138                     ingenic_early_console_setup);
 139
 140 EARLYCON_DECLARE(jz4780_uart, ingenic_early_console_setup);
 141 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
 142                     ingenic_early_console_setup);
 143
 144 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
 145 {
 146         int ier;
 147
 148         switch (offset) {
 149         case UART_FCR:
 150                 /* UART module enable */
 151                 value |= UART_FCR_UME;
 152                 break;
 153
 154         case UART_IER:
 155                 /* Enable receive timeout interrupt with the
 156                  * receive line status interrupt */
 157                 value |= (value & 0x4) << 2;
 158                 break;
 159
 160         case UART_MCR:
 161                 /* If we have enabled modem status IRQs we should enable modem
 162                  * mode. */
 163                 ier = p->serial_in(p, UART_IER);
 164
 165                 if (ier & UART_IER_MSI)
 166                         value |= UART_MCR_MDCE | UART_MCR_FCM;
 167                 else
 168                         value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
 169                 break;
 170
 171         default:
 172                 break;
 173         }
 174
 175         writeb(value, p->membase + (offset << p->regshift));
 176 }
 177
 178 static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
 179 {
 180         unsigned int value;
 181
 182         value = readb(p->membase + (offset << p->regshift));
 183
 184         /* Hide non-16550 compliant bits from higher levels */
 185         switch (offset) {
 186         case UART_FCR:
 187                 value &= ~UART_FCR_UME;
 188                 break;
 189
 190         case UART_MCR:
 191                 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
 192                 break;
 193
 194         default:
 195                 break;
 196         }
 197         return value;
 198 }
 199
 200 static int ingenic_uart_probe(struct platform_device *pdev)
 201 {
 202         struct uart_8250_port uart = {};
 203         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 204         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 205         struct ingenic_uart_data *data;
 206         const struct ingenic_uart_config *cdata;
 207         const struct of_device_id *match;
 208         int err, line;
 209
 210         match = of_match_device(of_match, &pdev->dev);
 211         if (!match) {
 212                 dev_err(&pdev->dev, "Error: No device match found\n");
 213                 return -ENODEV;
 214         }
 215         cdata = match->data;
 216
 217         if (!regs || !irq) {
 218                 dev_err(&pdev->dev, "no registers/irq defined\n");
 219                 return -EINVAL;
 220         }
 221
 222         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 223         if (!data)
 224                 return -ENOMEM;
 225
 226         spin_lock_init(&uart.port.lock);
 227         uart.port.type = PORT_16550A;
 228         uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
 229         uart.port.iotype = UPIO_MEM;
 230         uart.port.mapbase = regs->start;
 231         uart.port.regshift = 2;
 232         uart.port.serial_out = ingenic_uart_serial_out;
 233         uart.port.serial_in = ingenic_uart_serial_in;
 234         uart.port.irq = irq->start;
 235         uart.port.dev = &pdev->dev;
 236         uart.port.fifosize = cdata->fifosize;
 237         uart.tx_loadsz = cdata->tx_loadsz;
 238         uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
 239
 240         /* Check for a fixed line number */
 241         line = of_alias_get_id(pdev->dev.of_node, "serial");
 242         if (line >= 0)
 243                 uart.port.line = line;
 244
 245         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
 246                                          resource_size(regs));
 247         if (!uart.port.membase)
 248                 return -ENOMEM;
 249
 250         data->clk_module = devm_clk_get(&pdev->dev, "module");
 251         if (IS_ERR(data->clk_module)) {
 252                 err = PTR_ERR(data->clk_module);
 253                 if (err != -EPROBE_DEFER)
 254                         dev_err(&pdev->dev,
 255                                 "unable to get module clock: %d\n", err);
 256                 return err;
 257         }
 258
 259         data->clk_baud = devm_clk_get(&pdev->dev, "baud");
 260         if (IS_ERR(data->clk_baud)) {
 261                 err = PTR_ERR(data->clk_baud);
 262                 if (err != -EPROBE_DEFER)
 263                         dev_err(&pdev->dev,
 264                                 "unable to get baud clock: %d\n", err);
 265                 return err;
 266         }
 267
 268         err = clk_prepare_enable(data->clk_module);
 269         if (err) {
 270                 dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
 271                 goto out;
 272         }
 273
 274         err = clk_prepare_enable(data->clk_baud);
 275         if (err) {
 276                 dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
 277                 goto out_disable_moduleclk;
 278         }
 279         uart.port.uartclk = clk_get_rate(data->clk_baud);
 280
 281         data->line = serial8250_register_8250_port(&uart);
 282         if (data->line < 0) {
 283                 err = data->line;
 284                 goto out_disable_baudclk;
 285         }
 286
 287         platform_set_drvdata(pdev, data);
 288         return 0;
 289
 290 out_disable_baudclk:
 291         clk_disable_unprepare(data->clk_baud);
 292 out_disable_moduleclk:
 293         clk_disable_unprepare(data->clk_module);
 294 out:
 295         return err;
 296 }
 297
 298 static int ingenic_uart_remove(struct platform_device *pdev)
 299 {
 300         struct ingenic_uart_data *data = platform_get_drvdata(pdev);
 301
 302         serial8250_unregister_port(data->line);
 303         clk_disable_unprepare(data->clk_module);
 304         clk_disable_unprepare(data->clk_baud);
 305         return 0;
 306 }
 307
 308 static const struct ingenic_uart_config jz4740_uart_config = {
 309         .tx_loadsz = 8,
 310         .fifosize = 16,
 311 };
 312
 313 static const struct ingenic_uart_config jz4760_uart_config = {
 314         .tx_loadsz = 16,
 315         .fifosize = 32,
 316 };
 317
 318 static const struct ingenic_uart_config jz4780_uart_config = {
 319         .tx_loadsz = 32,
 320         .fifosize = 64,
 321 };
 322
 323 static const struct of_device_id of_match[] = {
 324         { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
 325         { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
 326         { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
 327         { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
 328         { /* sentinel */ }
 329 };
 330 MODULE_DEVICE_TABLE(of, of_match);
 331
 332 static struct platform_driver ingenic_uart_platform_driver = {
 333         .driver = {
 334                 .name           = "ingenic-uart",
 335                 .of_match_table = of_match,
 336         },
 337         .probe                  = ingenic_uart_probe,
 338         .remove                 = ingenic_uart_remove,
 339 };
 340
 341 module_platform_driver(ingenic_uart_platform_driver);
 342
 343 MODULE_AUTHOR("Paul Burton");
 344 MODULE_LICENSE("GPL");
 345 MODULE_DESCRIPTION("Ingenic SoC UART driver");