2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: Implement functions to access baseband
29 * BBuGetFrameTime - Calculate data frame transmitting time
30 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal
31 * parameter for baseband Tx
32 * BBbReadEmbedded - Embedded read baseband register via MAC
33 * BBbWriteEmbedded - Embedded write baseband register via MAC
34 * BBbVT3253Init - VIA VT3253 baseband chip init code
37 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
38 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
39 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCalculateParameter().
40 * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init().
42 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
43 * Modified BBvLoopbackOn & BBvLoopbackOff().
54 /*--------------------- Static Classes ----------------------------*/
56 /*--------------------- Static Variables --------------------------*/
58 /*--------------------- Static Functions --------------------------*/
60 /*--------------------- Export Variables --------------------------*/
62 /*--------------------- Static Definitions -------------------------*/
64 /*--------------------- Static Classes ----------------------------*/
66 /*--------------------- Static Variables --------------------------*/
68 #define CB_VT3253_INIT_FOR_RFMD 446
69 static unsigned char byVT3253InitTab_RFMD[CB_VT3253_INIT_FOR_RFMD][2] = {
518 #define CB_VT3253B0_INIT_FOR_RFMD 256
519 static unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
778 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
780 static unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
978 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
980 static unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1089 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1239 #define CB_VT3253B0_INIT_FOR_UW2451 256
1241 static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1350 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1500 #define CB_VT3253B0_AGC 193
1502 static unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1698 static const unsigned short awcFrameTime[MAX_RATE] = {
1699 10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216
1702 /*--------------------- Export Variables --------------------------*/
1704 * Description: Calculate data frame transmitting time
1708 * byPreambleType - Preamble Type
1709 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1710 * cbFrameLength - Baseband Type
1714 * Return Value: FrameTime
1719 unsigned char byPreambleType,
1720 unsigned char byPktType,
1721 unsigned int cbFrameLength,
1722 unsigned short wRate
1725 unsigned int uFrameTime;
1726 unsigned int uPreamble;
1728 unsigned int uRateIdx = (unsigned int) wRate;
1729 unsigned int uRate = 0;
1731 if (uRateIdx > RATE_54M) {
1736 uRate = (unsigned int)awcFrameTime[uRateIdx];
1738 if (uRateIdx <= 3) { /* CCK mode */
1739 if (byPreambleType == 1) /* Short */
1744 uFrameTime = (cbFrameLength * 80) / uRate; /* ????? */
1745 uTmp = (uFrameTime * uRate) / 80;
1746 if (cbFrameLength != uTmp)
1749 return uPreamble + uFrameTime;
1751 uFrameTime = (cbFrameLength * 8 + 22) / uRate; /* ???????? */
1752 uTmp = ((uFrameTime * uRate) - 22) / 8;
1753 if (cbFrameLength != uTmp)
1756 uFrameTime = uFrameTime * 4; /* ??????? */
1757 if (byPktType != PK_TYPE_11A)
1758 uFrameTime += 6; /* ?????? */
1760 return 20 + uFrameTime; /* ?????? */
1764 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1768 * priv - Device Structure
1769 * frame_length - Tx Frame Length
1772 * struct vnt_phy_field *phy
1773 * - pointer to Phy Length field
1774 * - pointer to Phy Service field
1775 * - pointer to Phy Signal field
1777 * Return Value: none
1780 void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length,
1781 u16 tx_rate, u8 pkt_type, struct vnt_phy_field *phy)
1787 u8 preamble_type = priv->byPreambleType;
1789 bit_count = frame_length * 8;
1800 count = bit_count / 2;
1802 if (preamble_type == 1)
1809 count = (bit_count * 10) / 55;
1810 tmp = (count * 55) / 10;
1812 if (tmp != bit_count)
1815 if (preamble_type == 1)
1822 count = bit_count / 11;
1825 if (tmp != bit_count) {
1828 if ((bit_count - tmp) <= 3)
1832 if (preamble_type == 1)
1839 if (pkt_type == PK_TYPE_11A)
1846 if (pkt_type == PK_TYPE_11A)
1853 if (pkt_type == PK_TYPE_11A)
1860 if (pkt_type == PK_TYPE_11A)
1867 if (pkt_type == PK_TYPE_11A)
1874 if (pkt_type == PK_TYPE_11A)
1881 if (pkt_type == PK_TYPE_11A)
1888 if (pkt_type == PK_TYPE_11A)
1894 if (pkt_type == PK_TYPE_11A)
1901 if (pkt_type == PK_TYPE_11B) {
1902 phy->service = 0x00;
1904 phy->service |= 0x80;
1905 phy->len = cpu_to_le16((u16)count);
1907 phy->service = 0x00;
1908 phy->len = cpu_to_le16((u16)frame_length);
1913 * Description: Read a byte from BASEBAND, by embedded programming
1917 * dwIoBase - I/O base address
1918 * byBBAddr - address of register in Baseband
1920 * pbyData - data read
1922 * Return Value: true if succeeded; false if failed.
1925 bool BBbReadEmbedded(struct vnt_private *priv,
1926 unsigned char byBBAddr, unsigned char *pbyData)
1928 void __iomem *dwIoBase = priv->PortOffset;
1930 unsigned char byValue;
1933 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
1936 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
1937 /* W_MAX_TIMEOUT is the timeout period */
1938 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1939 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
1940 if (byValue & BBREGCTL_DONE)
1945 VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData);
1947 if (ww == W_MAX_TIMEOUT) {
1949 pr_debug(" DBG_PORT80(0x30)\n");
1956 * Description: Write a Byte to BASEBAND, by embedded programming
1960 * dwIoBase - I/O base address
1961 * byBBAddr - address of register in Baseband
1962 * byData - data to write
1966 * Return Value: true if succeeded; false if failed.
1969 bool BBbWriteEmbedded(struct vnt_private *priv,
1970 unsigned char byBBAddr, unsigned char byData)
1972 void __iomem *dwIoBase = priv->PortOffset;
1974 unsigned char byValue;
1977 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
1979 VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData);
1981 /* turn on BBREGCTL_REGW */
1982 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
1983 /* W_MAX_TIMEOUT is the timeout period */
1984 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1985 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
1986 if (byValue & BBREGCTL_DONE)
1990 if (ww == W_MAX_TIMEOUT) {
1992 pr_debug(" DBG_PORT80(0x31)\n");
1999 * Description: VIA VT3253 Baseband chip init function
2003 * dwIoBase - I/O base address
2004 * byRevId - Revision ID
2005 * byRFType - RF type
2009 * Return Value: true if succeeded; false if failed.
2013 bool BBbVT3253Init(struct vnt_private *priv)
2015 bool bResult = true;
2017 void __iomem *dwIoBase = priv->PortOffset;
2018 unsigned char byRFType = priv->byRFType;
2019 unsigned char byLocalID = priv->byLocalID;
2021 if (byRFType == RF_RFMD2959) {
2022 if (byLocalID <= REV_ID_VT3253_A1) {
2023 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++)
2024 bResult &= BBbWriteEmbedded(priv,
2025 byVT3253InitTab_RFMD[ii][0],
2026 byVT3253InitTab_RFMD[ii][1]);
2029 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++)
2030 bResult &= BBbWriteEmbedded(priv,
2031 byVT3253B0_RFMD[ii][0],
2032 byVT3253B0_RFMD[ii][1]);
2034 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++)
2035 bResult &= BBbWriteEmbedded(priv,
2036 byVT3253B0_AGC4_RFMD2959[ii][0],
2037 byVT3253B0_AGC4_RFMD2959[ii][1]);
2039 VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2040 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT(0));
2042 priv->abyBBVGA[0] = 0x18;
2043 priv->abyBBVGA[1] = 0x0A;
2044 priv->abyBBVGA[2] = 0x0;
2045 priv->abyBBVGA[3] = 0x0;
2046 priv->ldBmThreshold[0] = -70;
2047 priv->ldBmThreshold[1] = -50;
2048 priv->ldBmThreshold[2] = 0;
2049 priv->ldBmThreshold[3] = 0;
2050 } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S)) {
2051 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2052 bResult &= BBbWriteEmbedded(priv,
2053 byVT3253B0_AIROHA2230[ii][0],
2054 byVT3253B0_AIROHA2230[ii][1]);
2056 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2057 bResult &= BBbWriteEmbedded(priv,
2058 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2060 priv->abyBBVGA[0] = 0x1C;
2061 priv->abyBBVGA[1] = 0x10;
2062 priv->abyBBVGA[2] = 0x0;
2063 priv->abyBBVGA[3] = 0x0;
2064 priv->ldBmThreshold[0] = -70;
2065 priv->ldBmThreshold[1] = -48;
2066 priv->ldBmThreshold[2] = 0;
2067 priv->ldBmThreshold[3] = 0;
2068 } else if (byRFType == RF_UW2451) {
2069 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2070 bResult &= BBbWriteEmbedded(priv,
2071 byVT3253B0_UW2451[ii][0],
2072 byVT3253B0_UW2451[ii][1]);
2074 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2075 bResult &= BBbWriteEmbedded(priv,
2076 byVT3253B0_AGC[ii][0],
2077 byVT3253B0_AGC[ii][1]);
2079 VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2080 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT(0));
2082 priv->abyBBVGA[0] = 0x14;
2083 priv->abyBBVGA[1] = 0x0A;
2084 priv->abyBBVGA[2] = 0x0;
2085 priv->abyBBVGA[3] = 0x0;
2086 priv->ldBmThreshold[0] = -60;
2087 priv->ldBmThreshold[1] = -50;
2088 priv->ldBmThreshold[2] = 0;
2089 priv->ldBmThreshold[3] = 0;
2090 } else if (byRFType == RF_UW2452) {
2091 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2092 bResult &= BBbWriteEmbedded(priv,
2093 byVT3253B0_UW2451[ii][0],
2094 byVT3253B0_UW2451[ii][1]);
2096 /* Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2097 /*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/
2098 /* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2099 /*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/
2100 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2101 bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06);
2103 /* {{RobertYu:20050125, request by Jack */
2104 bResult &= BBbWriteEmbedded(priv, 0x90, 0x20);
2105 bResult &= BBbWriteEmbedded(priv, 0x97, 0xeb);
2108 /* {{RobertYu:20050221, request by Jack */
2109 bResult &= BBbWriteEmbedded(priv, 0xa6, 0x00);
2110 bResult &= BBbWriteEmbedded(priv, 0xa8, 0x30);
2112 bResult &= BBbWriteEmbedded(priv, 0xb0, 0x58);
2114 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2115 bResult &= BBbWriteEmbedded(priv,
2116 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2118 priv->abyBBVGA[0] = 0x14;
2119 priv->abyBBVGA[1] = 0x0A;
2120 priv->abyBBVGA[2] = 0x0;
2121 priv->abyBBVGA[3] = 0x0;
2122 priv->ldBmThreshold[0] = -60;
2123 priv->ldBmThreshold[1] = -50;
2124 priv->ldBmThreshold[2] = 0;
2125 priv->ldBmThreshold[3] = 0;
2128 } else if (byRFType == RF_VT3226) {
2129 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2130 bResult &= BBbWriteEmbedded(priv,
2131 byVT3253B0_AIROHA2230[ii][0],
2132 byVT3253B0_AIROHA2230[ii][1]);
2134 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2135 bResult &= BBbWriteEmbedded(priv,
2136 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2138 priv->abyBBVGA[0] = 0x1C;
2139 priv->abyBBVGA[1] = 0x10;
2140 priv->abyBBVGA[2] = 0x0;
2141 priv->abyBBVGA[3] = 0x0;
2142 priv->ldBmThreshold[0] = -70;
2143 priv->ldBmThreshold[1] = -48;
2144 priv->ldBmThreshold[2] = 0;
2145 priv->ldBmThreshold[3] = 0;
2146 /* Fix VT3226 DFC system timing issue */
2147 MACvSetRFLE_LatchBase(dwIoBase);
2148 /* {{ RobertYu: 20050104 */
2149 } else if (byRFType == RF_AIROHA7230) {
2150 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2151 bResult &= BBbWriteEmbedded(priv,
2152 byVT3253B0_AIROHA2230[ii][0],
2153 byVT3253B0_AIROHA2230[ii][1]);
2156 /* {{ RobertYu:20050223, request by JerryChung */
2157 /* Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2158 /*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/
2159 /* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2160 /*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/
2161 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2162 bResult &= BBbWriteEmbedded(priv, 0xd7, 0x06);
2165 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2166 bResult &= BBbWriteEmbedded(priv,
2167 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2169 priv->abyBBVGA[0] = 0x1C;
2170 priv->abyBBVGA[1] = 0x10;
2171 priv->abyBBVGA[2] = 0x0;
2172 priv->abyBBVGA[3] = 0x0;
2173 priv->ldBmThreshold[0] = -70;
2174 priv->ldBmThreshold[1] = -48;
2175 priv->ldBmThreshold[2] = 0;
2176 priv->ldBmThreshold[3] = 0;
2179 /* No VGA Table now */
2180 priv->bUpdateBBVGA = false;
2181 priv->abyBBVGA[0] = 0x1C;
2184 if (byLocalID > REV_ID_VT3253_A1) {
2185 BBbWriteEmbedded(priv, 0x04, 0x7F);
2186 BBbWriteEmbedded(priv, 0x0D, 0x01);
2193 * Description: Set ShortSlotTime mode
2197 * priv - Device Structure
2201 * Return Value: none
2205 BBvSetShortSlotTime(struct vnt_private *priv)
2207 unsigned char byBBRxConf = 0;
2208 unsigned char byBBVGA = 0;
2210 BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */
2212 if (priv->bShortSlotTime)
2213 byBBRxConf &= 0xDF; /* 1101 1111 */
2215 byBBRxConf |= 0x20; /* 0010 0000 */
2217 /* patch for 3253B0 Baseband with Cardbus module */
2218 BBbReadEmbedded(priv, 0xE7, &byBBVGA);
2219 if (byBBVGA == priv->abyBBVGA[0])
2220 byBBRxConf |= 0x20; /* 0010 0000 */
2222 BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */
2225 void BBvSetVGAGainOffset(struct vnt_private *priv, unsigned char byData)
2227 unsigned char byBBRxConf = 0;
2229 BBbWriteEmbedded(priv, 0xE7, byData);
2231 BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */
2232 /* patch for 3253B0 Baseband with Cardbus module */
2233 if (byData == priv->abyBBVGA[0])
2234 byBBRxConf |= 0x20; /* 0010 0000 */
2235 else if (priv->bShortSlotTime)
2236 byBBRxConf &= 0xDF; /* 1101 1111 */
2238 byBBRxConf |= 0x20; /* 0010 0000 */
2239 priv->byBBVGACurrent = byData;
2240 BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */
2244 * Description: Baseband SoftwareReset
2248 * dwIoBase - I/O base address
2252 * Return Value: none
2256 BBvSoftwareReset(struct vnt_private *priv)
2258 BBbWriteEmbedded(priv, 0x50, 0x40);
2259 BBbWriteEmbedded(priv, 0x50, 0);
2260 BBbWriteEmbedded(priv, 0x9C, 0x01);
2261 BBbWriteEmbedded(priv, 0x9C, 0);
2265 * Description: Baseband Power Save Mode ON
2269 * dwIoBase - I/O base address
2273 * Return Value: none
2277 BBvPowerSaveModeON(struct vnt_private *priv)
2279 unsigned char byOrgData;
2281 BBbReadEmbedded(priv, 0x0D, &byOrgData);
2282 byOrgData |= BIT(0);
2283 BBbWriteEmbedded(priv, 0x0D, byOrgData);
2287 * Description: Baseband Power Save Mode OFF
2291 * dwIoBase - I/O base address
2295 * Return Value: none
2299 BBvPowerSaveModeOFF(struct vnt_private *priv)
2301 unsigned char byOrgData;
2303 BBbReadEmbedded(priv, 0x0D, &byOrgData);
2304 byOrgData &= ~(BIT(0));
2305 BBbWriteEmbedded(priv, 0x0D, byOrgData);
2309 * Description: Set Tx Antenna mode
2313 * priv - Device Structure
2314 * byAntennaMode - Antenna Mode
2318 * Return Value: none
2323 BBvSetTxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode)
2325 unsigned char byBBTxConf;
2327 BBbReadEmbedded(priv, 0x09, &byBBTxConf); /* CR09 */
2328 if (byAntennaMode == ANT_DIVERSITY) {
2329 /* bit 1 is diversity */
2331 } else if (byAntennaMode == ANT_A) {
2332 /* bit 2 is ANTSEL */
2333 byBBTxConf &= 0xF9; /* 1111 1001 */
2334 } else if (byAntennaMode == ANT_B) {
2335 byBBTxConf &= 0xFD; /* 1111 1101 */
2338 BBbWriteEmbedded(priv, 0x09, byBBTxConf); /* CR09 */
2342 * Description: Set Rx Antenna mode
2346 * priv - Device Structure
2347 * byAntennaMode - Antenna Mode
2351 * Return Value: none
2356 BBvSetRxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode)
2358 unsigned char byBBRxConf;
2360 BBbReadEmbedded(priv, 0x0A, &byBBRxConf); /* CR10 */
2361 if (byAntennaMode == ANT_DIVERSITY) {
2364 } else if (byAntennaMode == ANT_A) {
2365 byBBRxConf &= 0xFC; /* 1111 1100 */
2366 } else if (byAntennaMode == ANT_B) {
2367 byBBRxConf &= 0xFE; /* 1111 1110 */
2370 BBbWriteEmbedded(priv, 0x0A, byBBRxConf); /* CR10 */
2374 * Description: BBvSetDeepSleep
2378 * priv - Device Structure
2382 * Return Value: none
2386 BBvSetDeepSleep(struct vnt_private *priv, unsigned char byLocalID)
2388 BBbWriteEmbedded(priv, 0x0C, 0x17); /* CR12 */
2389 BBbWriteEmbedded(priv, 0x0D, 0xB9); /* CR13 */
2393 BBvExitDeepSleep(struct vnt_private *priv, unsigned char byLocalID)
2395 BBbWriteEmbedded(priv, 0x0C, 0x00); /* CR12 */
2396 BBbWriteEmbedded(priv, 0x0D, 0x01); /* CR13 */