kernel/drivers/staging/rts5208/rtsx_chip.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG (wei_wang@realsil.com.cn)
  20  *   Micky Ching (micky_ching@realsil.com.cn)
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/vmalloc.h>
  28
  29 #include "rtsx.h"
  30 #include "sd.h"
  31 #include "xd.h"
  32 #include "ms.h"
  33
  34 static void rtsx_calibration(struct rtsx_chip *chip)
  35 {
  36         rtsx_write_phy_register(chip, 0x1B, 0x135E);
  37         wait_timeout(10);
  38         rtsx_write_phy_register(chip, 0x00, 0x0280);
  39         rtsx_write_phy_register(chip, 0x01, 0x7112);
  40         rtsx_write_phy_register(chip, 0x01, 0x7110);
  41         rtsx_write_phy_register(chip, 0x01, 0x7112);
  42         rtsx_write_phy_register(chip, 0x01, 0x7113);
  43         rtsx_write_phy_register(chip, 0x00, 0x0288);
  44 }
  45
  46 void rtsx_disable_card_int(struct rtsx_chip *chip)
  47 {
  48         u32 reg = rtsx_readl(chip, RTSX_BIER);
  49
  50         reg &= ~(XD_INT_EN | SD_INT_EN | MS_INT_EN);
  51         rtsx_writel(chip, RTSX_BIER, reg);
  52 }
  53
  54 void rtsx_enable_card_int(struct rtsx_chip *chip)
  55 {
  56         u32 reg = rtsx_readl(chip, RTSX_BIER);
  57         int i;
  58
  59         for (i = 0; i <= chip->max_lun; i++) {
  60                 if (chip->lun2card[i] & XD_CARD)
  61                         reg |= XD_INT_EN;
  62                 if (chip->lun2card[i] & SD_CARD)
  63                         reg |= SD_INT_EN;
  64                 if (chip->lun2card[i] & MS_CARD)
  65                         reg |= MS_INT_EN;
  66         }
  67         if (chip->hw_bypass_sd)
  68                 reg &= ~((u32)SD_INT_EN);
  69
  70         rtsx_writel(chip, RTSX_BIER, reg);
  71 }
  72
  73 void rtsx_enable_bus_int(struct rtsx_chip *chip)
  74 {
  75         u32 reg = 0;
  76 #ifndef DISABLE_CARD_INT
  77         int i;
  78 #endif
  79
  80         reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
  81
  82 #ifndef DISABLE_CARD_INT
  83         for (i = 0; i <= chip->max_lun; i++) {
  84                 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
  85                         i, chip->lun2card[i]);
  86
  87                 if (chip->lun2card[i] & XD_CARD)
  88                         reg |= XD_INT_EN;
  89                 if (chip->lun2card[i] & SD_CARD)
  90                         reg |= SD_INT_EN;
  91                 if (chip->lun2card[i] & MS_CARD)
  92                         reg |= MS_INT_EN;
  93         }
  94         if (chip->hw_bypass_sd)
  95                 reg &= ~((u32)SD_INT_EN);
  96 #endif
  97
  98         if (chip->ic_version >= IC_VER_C)
  99                 reg |= DELINK_INT_EN;
 100 #ifdef SUPPORT_OCP
 101         reg |= OC_INT_EN;
 102 #endif
 103         if (!chip->adma_mode)
 104                 reg |= DATA_DONE_INT_EN;
 105
 106         /* Enable Bus Interrupt */
 107         rtsx_writel(chip, RTSX_BIER, reg);
 108
 109         dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
 110 }
 111
 112 void rtsx_disable_bus_int(struct rtsx_chip *chip)
 113 {
 114         rtsx_writel(chip, RTSX_BIER, 0);
 115 }
 116
 117 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
 118 {
 119         int retval;
 120
 121         if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
 122                 if (chip->asic_code) {
 123                         retval = rtsx_write_register(chip, CARD_PULL_CTL5,
 124                                                      0xFF,
 125                                                      MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
 126                         if (retval) {
 127                                 rtsx_trace(chip);
 128                                 return retval;
 129                         }
 130                 } else {
 131                         retval = rtsx_write_register(chip, FPGA_PULL_CTL,
 132                                                      0xFF,
 133                                                      FPGA_SD_PULL_CTL_EN);
 134                         if (retval) {
 135                                 rtsx_trace(chip);
 136                                 return retval;
 137                         }
 138                 }
 139                 retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF,
 140                                              CARD_SHARE_48_SD);
 141                 if (retval) {
 142                         rtsx_trace(chip);
 143                         return retval;
 144                 }
 145
 146                 /* Enable SDIO internal clock */
 147                 retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01);
 148                 if (retval) {
 149                         rtsx_trace(chip);
 150                         return retval;
 151                 }
 152
 153                 retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF,
 154                                              SDIO_BUS_CTRL | SDIO_CD_CTRL);
 155                 if (retval) {
 156                         rtsx_trace(chip);
 157                         return retval;
 158                 }
 159
 160                 chip->sd_int = 1;
 161                 chip->sd_io = 1;
 162         } else {
 163                 chip->need_reset |= SD_CARD;
 164         }
 165
 166         return STATUS_SUCCESS;
 167 }
 168
 169 #ifdef HW_AUTO_SWITCH_SD_BUS
 170 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
 171 {
 172         u8 tmp;
 173         bool sw_bypass_sd = false;
 174         int retval;
 175
 176         if (chip->driver_first_load) {
 177                 if (CHECK_PID(chip, 0x5288)) {
 178                         retval = rtsx_read_register(chip, 0xFE5A, &tmp);
 179                         if (retval) {
 180                                 rtsx_trace(chip);
 181                                 return retval;
 182                         }
 183                         if (tmp & 0x08)
 184                                 sw_bypass_sd = true;
 185                 } else if (CHECK_PID(chip, 0x5208)) {
 186                         retval = rtsx_read_register(chip, 0xFE70, &tmp);
 187                         if (retval) {
 188                                 rtsx_trace(chip);
 189                                 return retval;
 190                         }
 191                         if (tmp & 0x80)
 192                                 sw_bypass_sd = true;
 193                 }
 194         } else {
 195                 if (chip->sdio_in_charge)
 196                         sw_bypass_sd = true;
 197         }
 198         dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
 199                 chip->sdio_in_charge);
 200         dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
 201                 chip->driver_first_load);
 202         dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
 203                 sw_bypass_sd);
 204
 205         if (sw_bypass_sd) {
 206                 u8 cd_toggle_mask = 0;
 207
 208                 retval = rtsx_read_register(chip, TLPTISTAT, &tmp);
 209                 if (retval) {
 210                         rtsx_trace(chip);
 211                         return retval;
 212                 }
 213                 cd_toggle_mask = 0x08;
 214
 215                 if (tmp & cd_toggle_mask) {
 216                         /* Disable sdio_bus_auto_switch */
 217                         if (CHECK_PID(chip, 0x5288)) {
 218                                 retval = rtsx_write_register(chip, 0xFE5A,
 219                                                              0x08, 0x00);
 220                                 if (retval) {
 221                                         rtsx_trace(chip);
 222                                         return retval;
 223                                 }
 224                         } else if (CHECK_PID(chip, 0x5208)) {
 225                                 retval = rtsx_write_register(chip, 0xFE70,
 226                                                              0x80, 0x00);
 227                                 if (retval) {
 228                                         rtsx_trace(chip);
 229                                         return retval;
 230                                 }
 231                         }
 232
 233                         retval = rtsx_write_register(chip, TLPTISTAT, 0xFF,
 234                                                      tmp);
 235                         if (retval) {
 236                                 rtsx_trace(chip);
 237                                 return retval;
 238                         }
 239
 240                         chip->need_reset |= SD_CARD;
 241                 } else {
 242                         dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
 243
 244                         if (chip->asic_code) {
 245                                 retval = sd_pull_ctl_enable(chip);
 246                                 if (retval != STATUS_SUCCESS) {
 247                                         rtsx_trace(chip);
 248                                         return STATUS_FAIL;
 249                                 }
 250                         } else {
 251                                 retval = rtsx_write_register(chip,
 252                                                              FPGA_PULL_CTL,
 253                                                              FPGA_SD_PULL_CTL_BIT | 0x20,
 254                                                              0);
 255                                 if (retval) {
 256                                         rtsx_trace(chip);
 257                                         return retval;
 258                                 }
 259                         }
 260                         retval = card_share_mode(chip, SD_CARD);
 261                         if (retval != STATUS_SUCCESS) {
 262                                 rtsx_trace(chip);
 263                                 return STATUS_FAIL;
 264                         }
 265
 266                         /* Enable sdio_bus_auto_switch */
 267                         if (CHECK_PID(chip, 0x5288)) {
 268                                 retval = rtsx_write_register(chip, 0xFE5A,
 269                                                              0x08, 0x08);
 270                                 if (retval) {
 271                                         rtsx_trace(chip);
 272                                         return retval;
 273                                 }
 274                         } else if (CHECK_PID(chip, 0x5208)) {
 275                                 retval = rtsx_write_register(chip, 0xFE70,
 276                                                              0x80, 0x80);
 277                                 if (retval) {
 278                                         rtsx_trace(chip);
 279                                         return retval;
 280                                 }
 281                         }
 282
 283                         chip->chip_insert_with_sdio = 1;
 284                         chip->sd_io = 1;
 285                 }
 286         } else {
 287                 retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
 288                 if (retval) {
 289                         rtsx_trace(chip);
 290                         return retval;
 291                 }
 292
 293                 chip->need_reset |= SD_CARD;
 294         }
 295
 296         return STATUS_SUCCESS;
 297 }
 298 #endif
 299
 300 static int rtsx_reset_aspm(struct rtsx_chip *chip)
 301 {
 302         int ret;
 303
 304         if (chip->dynamic_aspm) {
 305                 if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288))
 306                         return STATUS_SUCCESS;
 307
 308                 ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF,
 309                                         chip->aspm_l0s_l1_en);
 310                 if (ret != STATUS_SUCCESS) {
 311                         rtsx_trace(chip);
 312                         return STATUS_FAIL;
 313                 }
 314
 315                 return STATUS_SUCCESS;
 316         }
 317
 318         if (CHECK_PID(chip, 0x5208)) {
 319                 ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
 320                 if (ret) {
 321                         rtsx_trace(chip);
 322                         return ret;
 323                 }
 324         }
 325         ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
 326         if (ret != STATUS_SUCCESS) {
 327                 rtsx_trace(chip);
 328                 return STATUS_FAIL;
 329         }
 330
 331         chip->aspm_level[0] = chip->aspm_l0s_l1_en;
 332         if (CHK_SDIO_EXIST(chip)) {
 333                 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
 334                 ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
 335                                         0xC0, 0xFF, chip->aspm_l0s_l1_en);
 336                 if (ret != STATUS_SUCCESS) {
 337                         rtsx_trace(chip);
 338                         return STATUS_FAIL;
 339                 }
 340         }
 341
 342         chip->aspm_enabled = 1;
 343
 344         return STATUS_SUCCESS;
 345 }
 346
 347 static int rtsx_enable_pcie_intr(struct rtsx_chip *chip)
 348 {
 349         int ret;
 350
 351         if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) {
 352                 rtsx_enable_bus_int(chip);
 353                 return STATUS_SUCCESS;
 354         }
 355
 356         if (chip->phy_debug_mode) {
 357                 ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0);
 358                 if (ret) {
 359                         rtsx_trace(chip);
 360                         return ret;
 361                 }
 362                 rtsx_disable_bus_int(chip);
 363         } else {
 364                 rtsx_enable_bus_int(chip);
 365         }
 366
 367         if (chip->ic_version >= IC_VER_D) {
 368                 u16 reg;
 369
 370                 ret = rtsx_read_phy_register(chip, 0x00, &reg);
 371                 if (ret != STATUS_SUCCESS) {
 372                         rtsx_trace(chip);
 373                         return STATUS_FAIL;
 374                 }
 375
 376                 reg &= 0xFE7F;
 377                 reg |= 0x80;
 378                 ret = rtsx_write_phy_register(chip, 0x00, reg);
 379                 if (ret != STATUS_SUCCESS) {
 380                         rtsx_trace(chip);
 381                         return STATUS_FAIL;
 382                 }
 383
 384                 ret = rtsx_read_phy_register(chip, 0x1C, &reg);
 385                 if (ret != STATUS_SUCCESS) {
 386                         rtsx_trace(chip);
 387                         return STATUS_FAIL;
 388                 }
 389
 390                 reg &= 0xFFF7;
 391                 ret = rtsx_write_phy_register(chip, 0x1C, reg);
 392                 if (ret != STATUS_SUCCESS) {
 393                         rtsx_trace(chip);
 394                         return STATUS_FAIL;
 395                 }
 396         }
 397
 398         if (chip->driver_first_load && (chip->ic_version < IC_VER_C))
 399                 rtsx_calibration(chip);
 400
 401         return STATUS_SUCCESS;
 402 }
 403
 404 int rtsx_reset_chip(struct rtsx_chip *chip)
 405 {
 406         int retval;
 407
 408         rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
 409
 410         rtsx_disable_aspm(chip);
 411
 412         retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00);
 413         if (retval) {
 414                 rtsx_trace(chip);
 415                 return retval;
 416         }
 417
 418         /* Disable card clock */
 419         retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0);
 420         if (retval) {
 421                 rtsx_trace(chip);
 422                 return retval;
 423         }
 424
 425 #ifdef SUPPORT_OCP
 426         /* SSC power on, OCD power on */
 427         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 428                 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0);
 429                 if (retval) {
 430                         rtsx_trace(chip);
 431                         return retval;
 432                 }
 433         } else {
 434                 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
 435                                              MS_OC_POWER_DOWN);
 436                 if (retval) {
 437                         rtsx_trace(chip);
 438                         return retval;
 439                 }
 440         }
 441
 442         retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK,
 443                                      OCP_TIME_800);
 444         if (retval) {
 445                 rtsx_trace(chip);
 446                 return retval;
 447         }
 448         retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK,
 449                                      OCP_THD_244_946);
 450         if (retval) {
 451                 rtsx_trace(chip);
 452                 return retval;
 453         }
 454         retval = rtsx_write_register(chip, OCPCTL, 0xFF,
 455                                      CARD_OC_INT_EN | CARD_DETECT_EN);
 456         if (retval) {
 457                 rtsx_trace(chip);
 458                 return retval;
 459         }
 460 #else
 461         /* OC power down */
 462         retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
 463                                      OC_POWER_DOWN);
 464         if (retval) {
 465                 rtsx_trace(chip);
 466                 return retval;
 467         }
 468 #endif
 469
 470         if (!CHECK_PID(chip, 0x5288)) {
 471                 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03);
 472                 if (retval) {
 473                         rtsx_trace(chip);
 474                         return retval;
 475                 }
 476         }
 477
 478         /* Turn off LED */
 479         retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03);
 480         if (retval) {
 481                 rtsx_trace(chip);
 482                 return retval;
 483         }
 484
 485         /* Reset delink mode */
 486         retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0);
 487         if (retval) {
 488                 rtsx_trace(chip);
 489                 return retval;
 490         }
 491
 492         /* Card driving select */
 493         retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF,
 494                                      chip->card_drive_sel);
 495         if (retval) {
 496                 rtsx_trace(chip);
 497                 return retval;
 498         }
 499
 500 #ifdef LED_AUTO_BLINK
 501         retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF,
 502                                      LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
 503         if (retval) {
 504                 rtsx_trace(chip);
 505                 return retval;
 506         }
 507 #endif
 508
 509         if (chip->asic_code) {
 510                 /* Enable SSC Clock */
 511                 retval = rtsx_write_register(chip, SSC_CTL1, 0xFF,
 512                                              SSC_8X_EN | SSC_SEL_4M);
 513                 if (retval) {
 514                         rtsx_trace(chip);
 515                         return retval;
 516                 }
 517                 retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12);
 518                 if (retval) {
 519                         rtsx_trace(chip);
 520                         return retval;
 521                 }
 522         }
 523
 524         /* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
 525               0xFE5B
 526               bit[1]    u_cd_rst_core_en        rst_value = 0
 527               bit[2]    u_force_rst_core_en     rst_value = 0
 528               bit[5]    u_mac_phy_rst_n_dbg     rst_value = 1
 529               bit[4]    u_non_sticky_rst_n_dbg  rst_value = 0
 530         */
 531         retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10);
 532         if (retval) {
 533                 rtsx_trace(chip);
 534                 return retval;
 535         }
 536
 537         /* Enable ASPM */
 538         if (chip->aspm_l0s_l1_en) {
 539                 retval = rtsx_reset_aspm(chip);
 540                 if (retval != STATUS_SUCCESS) {
 541                         rtsx_trace(chip);
 542                         return STATUS_FAIL;
 543                 }
 544         } else {
 545                 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 546                         retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
 547                         if (retval != STATUS_SUCCESS) {
 548                                 rtsx_trace(chip);
 549                                 return STATUS_FAIL;
 550                         }
 551                 }
 552                 retval = rtsx_write_config_byte(chip, LCTLR,
 553                                                 chip->aspm_l0s_l1_en);
 554                 if (retval != STATUS_SUCCESS) {
 555                         rtsx_trace(chip);
 556                         return STATUS_FAIL;
 557                 }
 558         }
 559
 560         retval = rtsx_write_config_byte(chip, 0x81, 1);
 561         if (retval != STATUS_SUCCESS) {
 562                 rtsx_trace(chip);
 563                 return STATUS_FAIL;
 564         }
 565
 566         if (CHK_SDIO_EXIST(chip)) {
 567                 retval = rtsx_write_cfg_dw(chip,
 568                                            CHECK_PID(chip, 0x5288) ? 2 : 1,
 569                                            0xC0, 0xFF00, 0x0100);
 570
 571                 if (retval != STATUS_SUCCESS) {
 572                         rtsx_trace(chip);
 573                         return STATUS_FAIL;
 574                 }
 575         }
 576
 577         if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) {
 578                 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
 579                 if (retval != STATUS_SUCCESS) {
 580                         rtsx_trace(chip);
 581                         return STATUS_FAIL;
 582                 }
 583
 584                 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
 585                 if (retval != STATUS_SUCCESS) {
 586                         rtsx_trace(chip);
 587                         return STATUS_FAIL;
 588                 }
 589         }
 590
 591         retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT,
 592                                      LINK_RDY_INT);
 593         if (retval) {
 594                 rtsx_trace(chip);
 595                 return retval;
 596         }
 597
 598         retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 599         if (retval) {
 600                 rtsx_trace(chip);
 601                 return retval;
 602         }
 603
 604         retval = rtsx_enable_pcie_intr(chip);
 605         if (retval != STATUS_SUCCESS) {
 606                 rtsx_trace(chip);
 607                 return STATUS_FAIL;
 608         }
 609
 610         chip->need_reset = 0;
 611
 612         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
 613
 614         if (chip->hw_bypass_sd)
 615                 goto nextcard;
 616         dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
 617                 chip->int_reg);
 618         if (chip->int_reg & SD_EXIST) {
 619 #ifdef HW_AUTO_SWITCH_SD_BUS
 620                 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
 621                         retval = rtsx_pre_handle_sdio_old(chip);
 622                 else
 623                         retval = rtsx_pre_handle_sdio_new(chip);
 624
 625                 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (rtsx_reset_chip)\n",
 626                         (unsigned int)(chip->need_reset));
 627 #else  /* HW_AUTO_SWITCH_SD_BUS */
 628                 retval = rtsx_pre_handle_sdio_old(chip);
 629 #endif  /* HW_AUTO_SWITCH_SD_BUS */
 630                 if (retval != STATUS_SUCCESS) {
 631                         rtsx_trace(chip);
 632                         return STATUS_FAIL;
 633                 }
 634
 635         } else {
 636                 chip->sd_io = 0;
 637                 retval = rtsx_write_register(chip, SDIO_CTRL,
 638                                              SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
 639                 if (retval) {
 640                         rtsx_trace(chip);
 641                         return retval;
 642                 }
 643         }
 644
 645 nextcard:
 646         if (chip->int_reg & XD_EXIST)
 647                 chip->need_reset |= XD_CARD;
 648         if (chip->int_reg & MS_EXIST)
 649                 chip->need_reset |= MS_CARD;
 650         if (chip->int_reg & CARD_EXIST) {
 651                 retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB,
 652                                              SSC_RSTB);
 653                 if (retval) {
 654                         rtsx_trace(chip);
 655                         return retval;
 656                 }
 657         }
 658
 659         dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
 660                 (unsigned int)(chip->need_reset));
 661
 662         retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00);
 663         if (retval) {
 664                 rtsx_trace(chip);
 665                 return retval;
 666         }
 667
 668         if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
 669                 /* Turn off main power when entering S3/S4 state */
 670                 retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03,
 671                                              0x03);
 672                 if (retval) {
 673                         rtsx_trace(chip);
 674                         return retval;
 675                 }
 676         }
 677
 678         if (chip->remote_wakeup_en && !chip->auto_delink_en) {
 679                 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07);
 680                 if (retval) {
 681                         rtsx_trace(chip);
 682                         return retval;
 683                 }
 684                 if (chip->aux_pwr_exist) {
 685                         retval = rtsx_write_register(chip, PME_FORCE_CTL,
 686                                                      0xFF, 0x33);
 687                         if (retval) {
 688                                 rtsx_trace(chip);
 689                                 return retval;
 690                         }
 691                 }
 692         } else {
 693                 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04);
 694                 if (retval) {
 695                         rtsx_trace(chip);
 696                         return retval;
 697                 }
 698                 retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30);
 699                 if (retval) {
 700                         rtsx_trace(chip);
 701                         return retval;
 702                 }
 703         }
 704
 705         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
 706                 retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14);
 707                 if (retval) {
 708                         rtsx_trace(chip);
 709                         return retval;
 710                 }
 711         }
 712
 713         if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 714                 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
 715                 if (retval != STATUS_SUCCESS) {
 716                         rtsx_trace(chip);
 717                         return STATUS_FAIL;
 718                 }
 719         }
 720
 721         if (chip->ft2_fast_mode) {
 722                 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
 723                                              MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
 724                 if (retval) {
 725                         rtsx_trace(chip);
 726                         return retval;
 727                 }
 728                 udelay(chip->pmos_pwr_on_interval);
 729                 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
 730                                              MS_POWER_ON | SD_POWER_ON);
 731                 if (retval) {
 732                         rtsx_trace(chip);
 733                         return retval;
 734                 }
 735
 736                 wait_timeout(200);
 737         }
 738
 739         /* Reset card */
 740         rtsx_reset_detected_cards(chip, 0);
 741
 742         chip->driver_first_load = 0;
 743
 744         return STATUS_SUCCESS;
 745 }
 746
 747 static inline int check_sd_speed_prior(u32 sd_speed_prior)
 748 {
 749         bool fake_para = false;
 750         int i;
 751
 752         for (i = 0; i < 4; i++) {
 753                 u8 tmp = (u8)(sd_speed_prior >> (i*8));
 754
 755                 if ((tmp < 0x01) || (tmp > 0x04)) {
 756                         fake_para = true;
 757                         break;
 758                 }
 759         }
 760
 761         return !fake_para;
 762 }
 763
 764 static inline int check_sd_current_prior(u32 sd_current_prior)
 765 {
 766         bool fake_para = false;
 767         int i;
 768
 769         for (i = 0; i < 4; i++) {
 770                 u8 tmp = (u8)(sd_current_prior >> (i*8));
 771
 772                 if (tmp > 0x03) {
 773                         fake_para = true;
 774                         break;
 775                 }
 776         }
 777
 778         return !fake_para;
 779 }
 780
 781 static int rts5208_init(struct rtsx_chip *chip)
 782 {
 783         int retval;
 784         u16 reg = 0;
 785         u8 val = 0;
 786
 787         retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
 788         if (retval) {
 789                 rtsx_trace(chip);
 790                 return retval;
 791         }
 792         retval = rtsx_read_register(chip, CLK_SEL, &val);
 793         if (retval) {
 794                 rtsx_trace(chip);
 795                 return retval;
 796         }
 797         chip->asic_code = val == 0 ? 1 : 0;
 798
 799         if (chip->asic_code) {
 800                 retval = rtsx_read_phy_register(chip, 0x1C, &reg);
 801                 if (retval != STATUS_SUCCESS) {
 802                         rtsx_trace(chip);
 803                         return STATUS_FAIL;
 804                 }
 805
 806                 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n",
 807                         reg);
 808                 chip->ic_version = (reg >> 4) & 0x07;
 809                 chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0;
 810
 811         } else {
 812                 retval = rtsx_read_register(chip, 0xFE80, &val);
 813                 if (retval) {
 814                         rtsx_trace(chip);
 815                         return retval;
 816                 }
 817                 chip->ic_version = val;
 818                 chip->phy_debug_mode = 0;
 819         }
 820
 821         retval = rtsx_read_register(chip, PDINFO, &val);
 822         if (retval) {
 823                 rtsx_trace(chip);
 824                 return retval;
 825         }
 826         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 827         chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
 828
 829         retval = rtsx_read_register(chip, 0xFE50, &val);
 830         if (retval) {
 831                 rtsx_trace(chip);
 832                 return retval;
 833         }
 834         chip->hw_bypass_sd = val & 0x01 ? 1 : 0;
 835
 836         rtsx_read_config_byte(chip, 0x0E, &val);
 837         if (val & 0x80)
 838                 SET_SDIO_EXIST(chip);
 839         else
 840                 CLR_SDIO_EXIST(chip);
 841
 842         if (chip->use_hw_setting) {
 843                 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
 844                 if (retval) {
 845                         rtsx_trace(chip);
 846                         return retval;
 847                 }
 848                 chip->auto_delink_en = val & 0x80 ? 1 : 0;
 849         }
 850
 851         return STATUS_SUCCESS;
 852 }
 853
 854 static int rts5288_init(struct rtsx_chip *chip)
 855 {
 856         int retval;
 857         u8 val = 0, max_func;
 858         u32 lval = 0;
 859
 860         retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
 861         if (retval) {
 862                 rtsx_trace(chip);
 863                 return retval;
 864         }
 865         retval = rtsx_read_register(chip, CLK_SEL, &val);
 866         if (retval) {
 867                 rtsx_trace(chip);
 868                 return retval;
 869         }
 870         chip->asic_code = val == 0 ? 1 : 0;
 871
 872         chip->ic_version = 0;
 873         chip->phy_debug_mode = 0;
 874
 875         retval = rtsx_read_register(chip, PDINFO, &val);
 876         if (retval) {
 877                 rtsx_trace(chip);
 878                 return retval;
 879         }
 880         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 881         chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
 882
 883         retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val);
 884         if (retval) {
 885                 rtsx_trace(chip);
 886                 return retval;
 887         }
 888         dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
 889         chip->baro_pkg = val & 0x04 ? QFN : LQFP;
 890
 891         retval = rtsx_read_register(chip, 0xFE5A, &val);
 892         if (retval) {
 893                 rtsx_trace(chip);
 894                 return retval;
 895         }
 896         chip->hw_bypass_sd = val & 0x10 ? 1 : 0;
 897
 898         retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
 899         if (retval != STATUS_SUCCESS) {
 900                 rtsx_trace(chip);
 901                 return STATUS_FAIL;
 902         }
 903
 904         max_func = (u8)((lval >> 29) & 0x07);
 905         dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
 906         if (max_func == 0x02)
 907                 SET_SDIO_EXIST(chip);
 908         else
 909                 CLR_SDIO_EXIST(chip);
 910
 911         if (chip->use_hw_setting) {
 912                 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
 913                 if (retval) {
 914                         rtsx_trace(chip);
 915                         return retval;
 916                 }
 917                 chip->auto_delink_en = val & 0x80 ? 1 : 0;
 918
 919                 if (CHECK_BARO_PKG(chip, LQFP))
 920                         chip->lun_mode = SD_MS_1LUN;
 921                 else
 922                         chip->lun_mode = DEFAULT_SINGLE;
 923         }
 924
 925         return STATUS_SUCCESS;
 926 }
 927
 928 int rtsx_init_chip(struct rtsx_chip *chip)
 929 {
 930         struct sd_info *sd_card = &chip->sd_card;
 931         struct xd_info *xd_card = &chip->xd_card;
 932         struct ms_info *ms_card = &chip->ms_card;
 933         int retval;
 934         unsigned int i;
 935
 936         dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
 937                 chip->vendor_id, chip->product_id);
 938
 939         chip->ic_version = 0;
 940
 941 #ifdef _MSG_TRACE
 942         chip->msg_idx = 0;
 943 #endif
 944
 945         memset(xd_card, 0, sizeof(struct xd_info));
 946         memset(sd_card, 0, sizeof(struct sd_info));
 947         memset(ms_card, 0, sizeof(struct ms_info));
 948
 949         chip->xd_reset_counter = 0;
 950         chip->sd_reset_counter = 0;
 951         chip->ms_reset_counter = 0;
 952
 953         chip->xd_show_cnt = MAX_SHOW_CNT;
 954         chip->sd_show_cnt = MAX_SHOW_CNT;
 955         chip->ms_show_cnt = MAX_SHOW_CNT;
 956
 957         chip->sd_io = 0;
 958         chip->auto_delink_cnt = 0;
 959         chip->auto_delink_allowed = 1;
 960         rtsx_set_stat(chip, RTSX_STAT_INIT);
 961
 962         chip->aspm_enabled = 0;
 963         chip->chip_insert_with_sdio = 0;
 964         chip->sdio_aspm = 0;
 965         chip->sdio_idle = 0;
 966         chip->sdio_counter = 0;
 967         chip->cur_card = 0;
 968         chip->phy_debug_mode = 0;
 969         chip->sdio_func_exist = 0;
 970         memset(chip->sdio_raw_data, 0, 12);
 971
 972         for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
 973                 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
 974                 chip->rw_fail_cnt[i] = 0;
 975         }
 976
 977         if (!check_sd_speed_prior(chip->sd_speed_prior))
 978                 chip->sd_speed_prior = 0x01040203;
 979
 980         dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
 981                 chip->sd_speed_prior);
 982
 983         if (!check_sd_current_prior(chip->sd_current_prior))
 984                 chip->sd_current_prior = 0x00010203;
 985
 986         dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
 987                 chip->sd_current_prior);
 988
 989         if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
 990                 chip->sd_ddr_tx_phase = 0;
 991
 992         if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
 993                 chip->mmc_ddr_tx_phase = 0;
 994
 995         retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0);
 996         if (retval) {
 997                 rtsx_trace(chip);
 998                 return retval;
 999         }
1000         wait_timeout(200);
1001         retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07);
1002         if (retval) {
1003                 rtsx_trace(chip);
1004                 return retval;
1005         }
1006         dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
1007                 chip->use_hw_setting);
1008
1009         if (CHECK_PID(chip, 0x5208)) {
1010                 retval = rts5208_init(chip);
1011                 if (retval != STATUS_SUCCESS) {
1012                         rtsx_trace(chip);
1013                         return STATUS_FAIL;
1014                 }
1015
1016         } else if (CHECK_PID(chip, 0x5288)) {
1017                 retval = rts5288_init(chip);
1018                 if (retval != STATUS_SUCCESS) {
1019                         rtsx_trace(chip);
1020                         return STATUS_FAIL;
1021                 }
1022         }
1023
1024         if (chip->ss_en == 2)
1025                 chip->ss_en = 0;
1026
1027         dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
1028         dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
1029         dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
1030                 chip->phy_debug_mode);
1031         dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
1032                 chip->aux_pwr_exist);
1033         dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
1034                 chip->sdio_func_exist);
1035         dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
1036                 chip->hw_bypass_sd);
1037         dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
1038                 chip->aspm_l0s_l1_en);
1039         dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
1040         dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
1041                 chip->auto_delink_en);
1042         dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
1043         dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
1044
1045         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1046                 chip->card2lun[SD_CARD] = 0;
1047                 chip->card2lun[MS_CARD] = 1;
1048                 chip->card2lun[XD_CARD] = 0xFF;
1049                 chip->lun2card[0] = SD_CARD;
1050                 chip->lun2card[1] = MS_CARD;
1051                 chip->max_lun = 1;
1052                 SET_SDIO_IGNORED(chip);
1053         } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
1054                 chip->card2lun[SD_CARD] = 0;
1055                 chip->card2lun[MS_CARD] = 0;
1056                 chip->card2lun[XD_CARD] = 0xFF;
1057                 chip->lun2card[0] = SD_CARD | MS_CARD;
1058                 chip->max_lun = 0;
1059         } else {
1060                 chip->card2lun[XD_CARD] = 0;
1061                 chip->card2lun[SD_CARD] = 0;
1062                 chip->card2lun[MS_CARD] = 0;
1063                 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
1064                 chip->max_lun = 0;
1065         }
1066
1067         retval = rtsx_reset_chip(chip);
1068         if (retval != STATUS_SUCCESS) {
1069                 rtsx_trace(chip);
1070                 return STATUS_FAIL;
1071         }
1072
1073         return STATUS_SUCCESS;
1074 }
1075
1076 void rtsx_release_chip(struct rtsx_chip *chip)
1077 {
1078         xd_free_l2p_tbl(chip);
1079         ms_free_l2p_tbl(chip);
1080         chip->card_exist = 0;
1081         chip->card_ready = 0;
1082 }
1083
1084 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1085 static inline void rtsx_blink_led(struct rtsx_chip *chip)
1086 {
1087         if (chip->card_exist && chip->blink_led) {
1088                 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
1089                         chip->led_toggle_counter++;
1090                 } else {
1091                         chip->led_toggle_counter = 0;
1092                         toggle_gpio(chip, LED_GPIO);
1093                 }
1094         }
1095 }
1096 #endif
1097
1098 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
1099 {
1100         bool reg_changed, maybe_support_aspm;
1101         u32 tmp = 0;
1102         u8 reg0 = 0, reg1 = 0;
1103
1104         maybe_support_aspm = false;
1105         reg_changed = false;
1106         rtsx_read_config_byte(chip, LCTLR, &reg0);
1107         if (chip->aspm_level[0] != reg0) {
1108                 reg_changed = true;
1109                 chip->aspm_level[0] = reg0;
1110         }
1111         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1112                 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
1113                 reg1 = (u8)tmp;
1114                 if (chip->aspm_level[1] != reg1) {
1115                         reg_changed = true;
1116                         chip->aspm_level[1] = reg1;
1117                 }
1118
1119                 if ((reg0 & 0x03) && (reg1 & 0x03))
1120                         maybe_support_aspm = true;
1121
1122         } else {
1123                 if (reg0 & 0x03)
1124                         maybe_support_aspm = true;
1125         }
1126
1127         if (reg_changed) {
1128                 if (maybe_support_aspm)
1129                         chip->aspm_l0s_l1_en = 0x03;
1130
1131                 dev_dbg(rtsx_dev(chip), "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
1132                         chip->aspm_level[0], chip->aspm_level[1]);
1133
1134                 if (chip->aspm_l0s_l1_en) {
1135                         chip->aspm_enabled = 1;
1136                 } else {
1137                         chip->aspm_enabled = 0;
1138                         chip->sdio_aspm = 0;
1139                 }
1140                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
1141                                     0x30 | chip->aspm_level[0] |
1142                                     (chip->aspm_level[1] << 2));
1143         }
1144 }
1145
1146 void rtsx_polling_func(struct rtsx_chip *chip)
1147 {
1148 #ifdef SUPPORT_SD_LOCK
1149         struct sd_info *sd_card = &chip->sd_card;
1150 #endif
1151         bool ss_allowed;
1152
1153         if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
1154                 return;
1155
1156         if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
1157                 goto delink_stage;
1158
1159         if (chip->polling_config) {
1160                 u8 val;
1161
1162                 rtsx_read_config_byte(chip, 0, &val);
1163         }
1164
1165         if (rtsx_chk_stat(chip, RTSX_STAT_SS))
1166                 return;
1167
1168 #ifdef SUPPORT_OCP
1169         if (chip->ocp_int) {
1170                 rtsx_read_register(chip, OCPSTAT, &chip->ocp_stat);
1171
1172                 if (chip->card_exist & SD_CARD)
1173                         sd_power_off_card3v3(chip);
1174                 else if (chip->card_exist & MS_CARD)
1175                         ms_power_off_card3v3(chip);
1176                 else if (chip->card_exist & XD_CARD)
1177                         xd_power_off_card3v3(chip);
1178
1179                 chip->ocp_int = 0;
1180         }
1181 #endif
1182
1183 #ifdef SUPPORT_SD_LOCK
1184         if (sd_card->sd_erase_status) {
1185                 if (chip->card_exist & SD_CARD) {
1186                         u8 val;
1187
1188                         rtsx_read_register(chip, 0xFD30, &val);
1189                         if (val & 0x02) {
1190                                 sd_card->sd_erase_status = SD_NOT_ERASE;
1191                                 sd_card->sd_lock_notify = 1;
1192                                 chip->need_reinit |= SD_CARD;
1193                         }
1194                 } else {
1195                         sd_card->sd_erase_status = SD_NOT_ERASE;
1196                 }
1197         }
1198 #endif
1199
1200         rtsx_init_cards(chip);
1201
1202         if (chip->ss_en) {
1203                 ss_allowed = true;
1204
1205                 if (CHECK_PID(chip, 0x5288)) {
1206                         ss_allowed = false;
1207                 } else {
1208                         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1209                                 u32 val;
1210
1211                                 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
1212                                 if (val & 0x07)
1213                                         ss_allowed = false;
1214                         }
1215                 }
1216         } else {
1217                 ss_allowed = false;
1218         }
1219
1220         if (ss_allowed && !chip->sd_io) {
1221                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1222                         chip->ss_counter = 0;
1223                 } else {
1224                         if (chip->ss_counter <
1225                                 (chip->ss_idle_period / POLLING_INTERVAL)) {
1226                                 chip->ss_counter++;
1227                         } else {
1228                                 rtsx_exclusive_enter_ss(chip);
1229                                 return;
1230                         }
1231                 }
1232         }
1233
1234         if (CHECK_PID(chip, 0x5208)) {
1235                 rtsx_monitor_aspm_config(chip);
1236
1237 #ifdef SUPPORT_SDIO_ASPM
1238                 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) &&
1239                     chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
1240                         if (chip->sd_io) {
1241                                 dynamic_configure_sdio_aspm(chip);
1242                         } else {
1243                                 if (!chip->sdio_aspm) {
1244                                         dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
1245                                         rtsx_write_register(chip,
1246                                                 ASPM_FORCE_CTL, 0xFC,
1247                                                 0x30 |
1248                                                 (chip->aspm_level[1] << 2));
1249                                         chip->sdio_aspm = 1;
1250                                 }
1251                         }
1252                 }
1253 #endif
1254         }
1255
1256         if (chip->idle_counter < IDLE_MAX_COUNT) {
1257                 chip->idle_counter++;
1258         } else {
1259                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1260                         dev_dbg(rtsx_dev(chip), "Idle state!\n");
1261                         rtsx_set_stat(chip, RTSX_STAT_IDLE);
1262
1263 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1264                         chip->led_toggle_counter = 0;
1265 #endif
1266                         rtsx_force_power_on(chip, SSC_PDCTL);
1267
1268                         turn_off_led(chip, LED_GPIO);
1269
1270                         if (chip->auto_power_down && !chip->card_ready &&
1271                             !chip->sd_io)
1272                                 rtsx_force_power_down(chip,
1273                                                       SSC_PDCTL | OC_PDCTL);
1274                 }
1275         }
1276
1277         switch (rtsx_get_stat(chip)) {
1278         case RTSX_STAT_RUN:
1279 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1280                 rtsx_blink_led(chip);
1281 #endif
1282                 do_remaining_work(chip);
1283                 break;
1284
1285         case RTSX_STAT_IDLE:
1286                 if (chip->sd_io && !chip->sd_int)
1287                         try_to_switch_sdio_ctrl(chip);
1288
1289                 rtsx_enable_aspm(chip);
1290                 break;
1291
1292         default:
1293                 break;
1294         }
1295
1296 #ifdef SUPPORT_OCP
1297         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1298                 if (chip->ocp_stat &
1299                         (SD_OC_NOW | SD_OC_EVER | MS_OC_NOW | MS_OC_EVER))
1300                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1301                                 chip->ocp_stat);
1302
1303                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1304                         if (chip->card_exist & SD_CARD) {
1305                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
1306                                                     0);
1307                                 card_power_off(chip, SD_CARD);
1308                                 chip->card_fail |= SD_CARD;
1309                         }
1310                 }
1311                 if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) {
1312                         if (chip->card_exist & MS_CARD) {
1313                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,
1314                                                     0);
1315                                 card_power_off(chip, MS_CARD);
1316                                 chip->card_fail |= MS_CARD;
1317                         }
1318                 }
1319         } else {
1320                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1321                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1322                                 chip->ocp_stat);
1323                         if (chip->card_exist & SD_CARD) {
1324                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
1325                                                     0);
1326                                 chip->card_fail |= SD_CARD;
1327                         } else if (chip->card_exist & MS_CARD) {
1328                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,
1329                                                     0);
1330                                 chip->card_fail |= MS_CARD;
1331                         } else if (chip->card_exist & XD_CARD) {
1332                                 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN,
1333                                                     0);
1334                                 chip->card_fail |= XD_CARD;
1335                         }
1336                         card_power_off(chip, SD_CARD);
1337                 }
1338         }
1339 #endif
1340
1341 delink_stage:
1342         if (chip->auto_delink_en && chip->auto_delink_allowed &&
1343             !chip->card_ready && !chip->card_ejected && !chip->sd_io) {
1344                 int enter_L1 = chip->auto_delink_in_L1 && (
1345                         chip->aspm_l0s_l1_en || chip->ss_en);
1346                 int delink_stage1_cnt = chip->delink_stage1_step;
1347                 int delink_stage2_cnt = delink_stage1_cnt +
1348                         chip->delink_stage2_step;
1349                 int delink_stage3_cnt = delink_stage2_cnt +
1350                         chip->delink_stage3_step;
1351
1352                 if (chip->auto_delink_cnt <= delink_stage3_cnt) {
1353                         if (chip->auto_delink_cnt == delink_stage1_cnt) {
1354                                 rtsx_set_stat(chip, RTSX_STAT_DELINK);
1355
1356                                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1357                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1358
1359                                 if (chip->card_exist) {
1360                                         dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n");
1361
1362                                         if (enter_L1)
1363                                                 rtsx_write_register(chip,
1364                                                               HOST_SLEEP_STATE,
1365                                                               0x03, 1);
1366
1367                                         rtsx_write_register(chip,
1368                                                             CHANGE_LINK_STATE,
1369                                                             0x0A, 0x0A);
1370
1371                                         if (enter_L1)
1372                                                 rtsx_enter_L1(chip);
1373
1374                                         chip->auto_delink_cnt =
1375                                                 delink_stage3_cnt + 1;
1376                                 } else {
1377                                         dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n");
1378
1379                                         if (enter_L1)
1380                                                 rtsx_write_register(chip,
1381                                                               HOST_SLEEP_STATE,
1382                                                               0x03, 1);
1383
1384                                         rtsx_write_register(chip,
1385                                                             CHANGE_LINK_STATE,
1386                                                             0x02, 0x02);
1387
1388                                         if (enter_L1)
1389                                                 rtsx_enter_L1(chip);
1390                                 }
1391                         }
1392
1393                         if (chip->auto_delink_cnt == delink_stage2_cnt) {
1394                                 dev_dbg(rtsx_dev(chip), "Try to do force delink\n");
1395
1396                                 if (enter_L1)
1397                                         rtsx_exit_L1(chip);
1398
1399                                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1400                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1401
1402                                 rtsx_write_register(chip, CHANGE_LINK_STATE,
1403                                                     0x0A, 0x0A);
1404                         }
1405
1406                         chip->auto_delink_cnt++;
1407                 }
1408         } else {
1409                 chip->auto_delink_cnt = 0;
1410         }
1411 }
1412
1413 void rtsx_undo_delink(struct rtsx_chip *chip)
1414 {
1415         chip->auto_delink_allowed = 0;
1416         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00);
1417 }
1418
1419 /**
1420  * rtsx_stop_cmd - stop command transfer and DMA transfer
1421  * @chip: Realtek's card reader chip
1422  * @card: flash card type
1423  *
1424  * Stop command transfer and DMA transfer.
1425  * This function is called in error handler.
1426  */
1427 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1428 {
1429         int i;
1430
1431         for (i = 0; i <= 8; i++) {
1432                 int addr = RTSX_HCBAR + i * 4;
1433                 u32 reg;
1434
1435                 reg = rtsx_readl(chip, addr);
1436                 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg);
1437         }
1438         rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1439         rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1440
1441         for (i = 0; i < 16; i++) {
1442                 u16 addr = 0xFE20 + (u16)i;
1443                 u8 val;
1444
1445                 rtsx_read_register(chip, addr, &val);
1446                 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val);
1447         }
1448
1449         rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1450         rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1451 }
1452
1453 #define MAX_RW_REG_CNT          1024
1454
1455 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1456 {
1457         int i;
1458         u32 val = 3 << 30;
1459
1460         val |= (u32)(addr & 0x3FFF) << 16;
1461         val |= (u32)mask << 8;
1462         val |= (u32)data;
1463
1464         rtsx_writel(chip, RTSX_HAIMR, val);
1465
1466         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1467                 val = rtsx_readl(chip, RTSX_HAIMR);
1468                 if ((val & (1 << 31)) == 0) {
1469                         if (data != (u8)val) {
1470                                 rtsx_trace(chip);
1471                                 return STATUS_FAIL;
1472                         }
1473
1474                         return STATUS_SUCCESS;
1475                 }
1476         }
1477
1478         rtsx_trace(chip);
1479         return STATUS_TIMEDOUT;
1480 }
1481
1482 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1483 {
1484         u32 val = 2 << 30;
1485         int i;
1486
1487         if (data)
1488                 *data = 0;
1489
1490         val |= (u32)(addr & 0x3FFF) << 16;
1491
1492         rtsx_writel(chip, RTSX_HAIMR, val);
1493
1494         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1495                 val = rtsx_readl(chip, RTSX_HAIMR);
1496                 if ((val & (1 << 31)) == 0)
1497                         break;
1498         }
1499
1500         if (i >= MAX_RW_REG_CNT) {
1501                 rtsx_trace(chip);
1502                 return STATUS_TIMEDOUT;
1503         }
1504
1505         if (data)
1506                 *data = (u8)(val & 0xFF);
1507
1508         return STATUS_SUCCESS;
1509 }
1510
1511 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask,
1512                       u32 val)
1513 {
1514         int retval;
1515         u8 mode = 0, tmp;
1516         int i;
1517
1518         for (i = 0; i < 4; i++) {
1519                 if (mask & 0xFF) {
1520                         retval = rtsx_write_register(chip, CFGDATA0 + i,
1521                                                      0xFF,
1522                                                      (u8)(val & mask & 0xFF));
1523                         if (retval) {
1524                                 rtsx_trace(chip);
1525                                 return retval;
1526                         }
1527                         mode |= (1 << i);
1528                 }
1529                 mask >>= 8;
1530                 val >>= 8;
1531         }
1532
1533         if (mode) {
1534                 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1535                 if (retval) {
1536                         rtsx_trace(chip);
1537                         return retval;
1538                 }
1539                 retval = rtsx_write_register(chip, CFGADDR1, 0xFF,
1540                                              (u8)(addr >> 8));
1541                 if (retval) {
1542                         rtsx_trace(chip);
1543                         return retval;
1544                 }
1545
1546                 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1547                                              0x80 | mode | ((func_no & 0x03) << 4));
1548                 if (retval) {
1549                         rtsx_trace(chip);
1550                         return retval;
1551                 }
1552
1553                 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1554                         retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1555                         if (retval) {
1556                                 rtsx_trace(chip);
1557                                 return retval;
1558                         }
1559                         if ((tmp & 0x80) == 0)
1560                                 break;
1561                 }
1562         }
1563
1564         return STATUS_SUCCESS;
1565 }
1566
1567 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1568 {
1569         int retval;
1570         int i;
1571         u8 tmp;
1572         u32 data = 0;
1573
1574         retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1575         if (retval) {
1576                 rtsx_trace(chip);
1577                 return retval;
1578         }
1579         retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1580         if (retval) {
1581                 rtsx_trace(chip);
1582                 return retval;
1583         }
1584         retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1585                                      0x80 | ((func_no & 0x03) << 4));
1586         if (retval) {
1587                 rtsx_trace(chip);
1588                 return retval;
1589         }
1590
1591         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1592                 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1593                 if (retval) {
1594                         rtsx_trace(chip);
1595                         return retval;
1596                 }
1597                 if ((tmp & 0x80) == 0)
1598                         break;
1599         }
1600
1601         for (i = 0; i < 4; i++) {
1602                 retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp);
1603                 if (retval) {
1604                         rtsx_trace(chip);
1605                         return retval;
1606                 }
1607                 data |= (u32)tmp << (i * 8);
1608         }
1609
1610         if (val)
1611                 *val = data;
1612
1613         return STATUS_SUCCESS;
1614 }
1615
1616 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1617                        int len)
1618 {
1619         u32 *data, *mask;
1620         u16 offset = addr % 4;
1621         u16 aligned_addr = addr - offset;
1622         int dw_len, i, j;
1623         int retval;
1624
1625         if (!buf) {
1626                 rtsx_trace(chip);
1627                 return STATUS_NOMEM;
1628         }
1629
1630         if ((len + offset) % 4)
1631                 dw_len = (len + offset) / 4 + 1;
1632         else
1633                 dw_len = (len + offset) / 4;
1634
1635         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1636
1637         data = vzalloc(dw_len * 4);
1638         if (!data) {
1639                 rtsx_trace(chip);
1640                 return STATUS_NOMEM;
1641         }
1642
1643         mask = vzalloc(dw_len * 4);
1644         if (!mask) {
1645                 vfree(data);
1646                 rtsx_trace(chip);
1647                 return STATUS_NOMEM;
1648         }
1649
1650         j = 0;
1651         for (i = 0; i < len; i++) {
1652                 mask[j] |= 0xFF << (offset * 8);
1653                 data[j] |= buf[i] << (offset * 8);
1654                 if (++offset == 4) {
1655                         j++;
1656                         offset = 0;
1657                 }
1658         }
1659
1660         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask,
1661                              dw_len * 4);
1662         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data,
1663                              dw_len * 4);
1664
1665         for (i = 0; i < dw_len; i++) {
1666                 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4,
1667                                            mask[i], data[i]);
1668                 if (retval != STATUS_SUCCESS) {
1669                         vfree(data);
1670                         vfree(mask);
1671                         rtsx_trace(chip);
1672                         return STATUS_FAIL;
1673                 }
1674         }
1675
1676         vfree(data);
1677         vfree(mask);
1678
1679         return STATUS_SUCCESS;
1680 }
1681
1682 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1683                       int len)
1684 {
1685         u32 *data;
1686         u16 offset = addr % 4;
1687         u16 aligned_addr = addr - offset;
1688         int dw_len, i, j;
1689         int retval;
1690
1691         if ((len + offset) % 4)
1692                 dw_len = (len + offset) / 4 + 1;
1693         else
1694                 dw_len = (len + offset) / 4;
1695
1696         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1697
1698         data = vmalloc(dw_len * 4);
1699         if (!data) {
1700                 rtsx_trace(chip);
1701                 return STATUS_NOMEM;
1702         }
1703
1704         for (i = 0; i < dw_len; i++) {
1705                 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4,
1706                                           data + i);
1707                 if (retval != STATUS_SUCCESS) {
1708                         vfree(data);
1709                         rtsx_trace(chip);
1710                         return STATUS_FAIL;
1711                 }
1712         }
1713
1714         if (buf) {
1715                 j = 0;
1716
1717                 for (i = 0; i < len; i++) {
1718                         buf[i] = (u8)(data[j] >> (offset * 8));
1719                         if (++offset == 4) {
1720                                 j++;
1721                                 offset = 0;
1722                         }
1723                 }
1724         }
1725
1726         vfree(data);
1727
1728         return STATUS_SUCCESS;
1729 }
1730
1731 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1732 {
1733         int retval;
1734         bool finished = false;
1735         int i;
1736         u8 tmp;
1737
1738         retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val);
1739         if (retval) {
1740                 rtsx_trace(chip);
1741                 return retval;
1742         }
1743         retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1744         if (retval) {
1745                 rtsx_trace(chip);
1746                 return retval;
1747         }
1748         retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1749         if (retval) {
1750                 rtsx_trace(chip);
1751                 return retval;
1752         }
1753         retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81);
1754         if (retval) {
1755                 rtsx_trace(chip);
1756                 return retval;
1757         }
1758
1759         for (i = 0; i < 100000; i++) {
1760                 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1761                 if (retval) {
1762                         rtsx_trace(chip);
1763                         return retval;
1764                 }
1765                 if (!(tmp & 0x80)) {
1766                         finished = true;
1767                         break;
1768                 }
1769         }
1770
1771         if (!finished) {
1772                 rtsx_trace(chip);
1773                 return STATUS_FAIL;
1774         }
1775
1776         return STATUS_SUCCESS;
1777 }
1778
1779 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1780 {
1781         int retval;
1782         bool finished = false;
1783         int i;
1784         u16 data = 0;
1785         u8 tmp;
1786
1787         retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1788         if (retval) {
1789                 rtsx_trace(chip);
1790                 return retval;
1791         }
1792         retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80);
1793         if (retval) {
1794                 rtsx_trace(chip);
1795                 return retval;
1796         }
1797
1798         for (i = 0; i < 100000; i++) {
1799                 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1800                 if (retval) {
1801                         rtsx_trace(chip);
1802                         return retval;
1803                 }
1804                 if (!(tmp & 0x80)) {
1805                         finished = true;
1806                         break;
1807                 }
1808         }
1809
1810         if (!finished) {
1811                 rtsx_trace(chip);
1812                 return STATUS_FAIL;
1813         }
1814
1815         retval = rtsx_read_register(chip, PHYDATA0, &tmp);
1816         if (retval) {
1817                 rtsx_trace(chip);
1818                 return retval;
1819         }
1820         data = tmp;
1821         retval = rtsx_read_register(chip, PHYDATA1, &tmp);
1822         if (retval) {
1823                 rtsx_trace(chip);
1824                 return retval;
1825         }
1826         data |= (u16)tmp << 8;
1827
1828         if (val)
1829                 *val = data;
1830
1831         return STATUS_SUCCESS;
1832 }
1833
1834 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1835 {
1836         int retval;
1837         int i;
1838         u8 data = 0;
1839
1840         retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr);
1841         if (retval) {
1842                 rtsx_trace(chip);
1843                 return retval;
1844         }
1845
1846         for (i = 0; i < 100; i++) {
1847                 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1848                 if (retval) {
1849                         rtsx_trace(chip);
1850                         return retval;
1851                 }
1852                 if (!(data & 0x80))
1853                         break;
1854                 udelay(1);
1855         }
1856
1857         if (data & 0x80) {
1858                 rtsx_trace(chip);
1859                 return STATUS_TIMEDOUT;
1860         }
1861
1862         retval = rtsx_read_register(chip, EFUSE_DATA, &data);
1863         if (retval) {
1864                 rtsx_trace(chip);
1865                 return retval;
1866         }
1867         if (val)
1868                 *val = data;
1869
1870         return STATUS_SUCCESS;
1871 }
1872
1873 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1874 {
1875         int retval;
1876         int i, j;
1877         u8 data = 0, tmp = 0xFF;
1878
1879         for (i = 0; i < 8; i++) {
1880                 if (val & (u8)(1 << i))
1881                         continue;
1882
1883                 tmp &= (~(u8)(1 << i));
1884                 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr);
1885
1886                 retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp);
1887                 if (retval) {
1888                         rtsx_trace(chip);
1889                         return retval;
1890                 }
1891                 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF,
1892                                              0xA0 | addr);
1893                 if (retval) {
1894                         rtsx_trace(chip);
1895                         return retval;
1896                 }
1897
1898                 for (j = 0; j < 100; j++) {
1899                         retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1900                         if (retval) {
1901                                 rtsx_trace(chip);
1902                                 return retval;
1903                         }
1904                         if (!(data & 0x80))
1905                                 break;
1906                         wait_timeout(3);
1907                 }
1908
1909                 if (data & 0x80) {
1910                         rtsx_trace(chip);
1911                         return STATUS_TIMEDOUT;
1912                 }
1913
1914                 wait_timeout(5);
1915         }
1916
1917         return STATUS_SUCCESS;
1918 }
1919
1920 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1921 {
1922         int retval;
1923         u16 value;
1924
1925         retval = rtsx_read_phy_register(chip, reg, &value);
1926         if (retval != STATUS_SUCCESS) {
1927                 rtsx_trace(chip);
1928                 return STATUS_FAIL;
1929         }
1930
1931         if (value & (1 << bit)) {
1932                 value &= ~(1 << bit);
1933                 retval = rtsx_write_phy_register(chip, reg, value);
1934                 if (retval != STATUS_SUCCESS) {
1935                         rtsx_trace(chip);
1936                         return STATUS_FAIL;
1937                 }
1938         }
1939
1940         return STATUS_SUCCESS;
1941 }
1942
1943 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1944 {
1945         int retval;
1946         u16 value;
1947
1948         retval = rtsx_read_phy_register(chip, reg, &value);
1949         if (retval != STATUS_SUCCESS) {
1950                 rtsx_trace(chip);
1951                 return STATUS_FAIL;
1952         }
1953
1954         if ((value & (1 << bit)) == 0) {
1955                 value |= (1 << bit);
1956                 retval = rtsx_write_phy_register(chip, reg, value);
1957                 if (retval != STATUS_SUCCESS) {
1958                         rtsx_trace(chip);
1959                         return STATUS_FAIL;
1960                 }
1961         }
1962
1963         return STATUS_SUCCESS;
1964 }
1965
1966 int rtsx_check_link_ready(struct rtsx_chip *chip)
1967 {
1968         int retval;
1969         u8 val;
1970
1971         retval = rtsx_read_register(chip, IRQSTAT0, &val);
1972         if (retval) {
1973                 rtsx_trace(chip);
1974                 return retval;
1975         }
1976
1977         dev_dbg(rtsx_dev(chip), "IRQSTAT0: 0x%x\n", val);
1978         if (val & LINK_RDY_INT) {
1979                 dev_dbg(rtsx_dev(chip), "Delinked!\n");
1980                 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1981                 return STATUS_FAIL;
1982         }
1983
1984         return STATUS_SUCCESS;
1985 }
1986
1987 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1988 {
1989         u32 ultmp;
1990
1991         dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n",
1992                 chip->product_id, dstate);
1993
1994         if (CHK_SDIO_EXIST(chip)) {
1995                 u8 func_no;
1996
1997                 if (CHECK_PID(chip, 0x5288))
1998                         func_no = 2;
1999                 else
2000                         func_no = 1;
2001
2002                 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
2003                 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n",
2004                         (int)func_no, ultmp);
2005                 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
2006         }
2007
2008         rtsx_write_config_byte(chip, 0x44, dstate);
2009         rtsx_write_config_byte(chip, 0x45, 0);
2010 }
2011
2012 void rtsx_enter_L1(struct rtsx_chip *chip)
2013 {
2014         rtsx_handle_pm_dstate(chip, 2);
2015 }
2016
2017 void rtsx_exit_L1(struct rtsx_chip *chip)
2018 {
2019         rtsx_write_config_byte(chip, 0x44, 0);
2020         rtsx_write_config_byte(chip, 0x45, 0);
2021 }
2022
2023 void rtsx_enter_ss(struct rtsx_chip *chip)
2024 {
2025         dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n");
2026
2027         rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
2028
2029         if (chip->power_down_in_ss) {
2030                 rtsx_power_off_card(chip);
2031                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2032         }
2033
2034         if (CHK_SDIO_EXIST(chip))
2035                 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2036                                   0xC0, 0xFF00, 0x0100);
2037
2038         if (chip->auto_delink_en) {
2039                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
2040         } else {
2041                 if (!chip->phy_debug_mode) {
2042                         u32 tmp;
2043
2044                         tmp = rtsx_readl(chip, RTSX_BIER);
2045                         tmp |= CARD_INT;
2046                         rtsx_writel(chip, RTSX_BIER, tmp);
2047                 }
2048
2049                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
2050         }
2051
2052         rtsx_enter_L1(chip);
2053
2054         RTSX_CLR_DELINK(chip);
2055         rtsx_set_stat(chip, RTSX_STAT_SS);
2056 }
2057
2058 void rtsx_exit_ss(struct rtsx_chip *chip)
2059 {
2060         dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n");
2061
2062         rtsx_exit_L1(chip);
2063
2064         if (chip->power_down_in_ss) {
2065                 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
2066                 udelay(1000);
2067         }
2068
2069         if (RTSX_TST_DELINK(chip)) {
2070                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2071                 rtsx_reinit_cards(chip, 1);
2072                 RTSX_CLR_DELINK(chip);
2073         } else if (chip->power_down_in_ss) {
2074                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2075                 rtsx_reinit_cards(chip, 0);
2076         }
2077 }
2078
2079 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
2080 {
2081         u32 status, int_enable;
2082         bool exit_ss = false;
2083 #ifdef SUPPORT_OCP
2084         u32 ocp_int = 0;
2085
2086         ocp_int = OC_INT;
2087 #endif
2088
2089         if (chip->ss_en) {
2090                 chip->ss_counter = 0;
2091                 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
2092                         exit_ss = true;
2093                         rtsx_exit_L1(chip);
2094                         rtsx_set_stat(chip, RTSX_STAT_RUN);
2095                 }
2096         }
2097
2098         int_enable = rtsx_readl(chip, RTSX_BIER);
2099         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
2100
2101         if (((chip->int_reg & int_enable) == 0) ||
2102             (chip->int_reg == 0xFFFFFFFF))
2103                 return STATUS_FAIL;
2104
2105         status = chip->int_reg &= (int_enable | 0x7FFFFF);
2106
2107         if (status & CARD_INT) {
2108                 chip->auto_delink_cnt = 0;
2109
2110                 if (status & SD_INT) {
2111                         if (status & SD_EXIST) {
2112                                 set_bit(SD_NR, &chip->need_reset);
2113                         } else {
2114                                 set_bit(SD_NR, &chip->need_release);
2115                                 chip->sd_reset_counter = 0;
2116                                 chip->sd_show_cnt = 0;
2117                                 clear_bit(SD_NR, &chip->need_reset);
2118                         }
2119                 } else {
2120                         /* If multi-luns, it's possible that
2121                            when plugging/unplugging one card
2122                            there is another card which still
2123                            exists in the slot. In this case,
2124                            all existed cards should be reset.
2125                         */
2126                         if (exit_ss && (status & SD_EXIST))
2127                                 set_bit(SD_NR, &chip->need_reinit);
2128                 }
2129                 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
2130                         if (status & XD_INT) {
2131                                 if (status & XD_EXIST) {
2132                                         set_bit(XD_NR, &chip->need_reset);
2133                                 } else {
2134                                         set_bit(XD_NR, &chip->need_release);
2135                                         chip->xd_reset_counter = 0;
2136                                         chip->xd_show_cnt = 0;
2137                                         clear_bit(XD_NR, &chip->need_reset);
2138                                 }
2139                         } else {
2140                                 if (exit_ss && (status & XD_EXIST))
2141                                         set_bit(XD_NR, &chip->need_reinit);
2142                         }
2143                 }
2144                 if (status & MS_INT) {
2145                         if (status & MS_EXIST) {
2146                                 set_bit(MS_NR, &chip->need_reset);
2147                         } else {
2148                                 set_bit(MS_NR, &chip->need_release);
2149                                 chip->ms_reset_counter = 0;
2150                                 chip->ms_show_cnt = 0;
2151                                 clear_bit(MS_NR, &chip->need_reset);
2152                         }
2153                 } else {
2154                         if (exit_ss && (status & MS_EXIST))
2155                                 set_bit(MS_NR, &chip->need_reinit);
2156                 }
2157         }
2158
2159 #ifdef SUPPORT_OCP
2160         chip->ocp_int = ocp_int & status;
2161 #endif
2162
2163         if (chip->sd_io && (chip->int_reg & DATA_DONE_INT))
2164                 chip->int_reg &= ~(u32)DATA_DONE_INT;
2165
2166         return STATUS_SUCCESS;
2167 }
2168
2169 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
2170 {
2171         int retval;
2172
2173         dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat);
2174
2175         rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
2176
2177         retval = rtsx_force_power_on(chip, SSC_PDCTL);
2178         if (retval != STATUS_SUCCESS)
2179                 return;
2180
2181         rtsx_release_cards(chip);
2182         rtsx_disable_bus_int(chip);
2183         turn_off_led(chip, LED_GPIO);
2184
2185 #ifdef HW_AUTO_SWITCH_SD_BUS
2186         if (chip->sd_io) {
2187                 chip->sdio_in_charge = 1;
2188                 if (CHECK_PID(chip, 0x5208)) {
2189                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2190                         /* Enable sdio_bus_auto_switch */
2191                         rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
2192                 } else if (CHECK_PID(chip, 0x5288)) {
2193                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2194                         /* Enable sdio_bus_auto_switch */
2195                         rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
2196                 }
2197         }
2198 #endif
2199
2200         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
2201                 /* u_force_clkreq_0 */
2202                 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2203         }
2204
2205         if (pm_stat == PM_S1) {
2206                 dev_dbg(rtsx_dev(chip), "Host enter S1\n");
2207                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2208                                     HOST_ENTER_S1);
2209         } else if (pm_stat == PM_S3) {
2210                 if (chip->s3_pwr_off_delay > 0)
2211                         wait_timeout(chip->s3_pwr_off_delay);
2212
2213                 dev_dbg(rtsx_dev(chip), "Host enter S3\n");
2214                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2215                                     HOST_ENTER_S3);
2216         }
2217
2218         if (chip->do_delink_before_power_down && chip->auto_delink_en)
2219                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
2220
2221         rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2222
2223         chip->cur_clk = 0;
2224         chip->cur_card = 0;
2225         chip->card_exist = 0;
2226 }
2227
2228 void rtsx_enable_aspm(struct rtsx_chip *chip)
2229 {
2230         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && !chip->aspm_enabled) {
2231                 dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n");
2232                 chip->aspm_enabled = 1;
2233
2234                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2235                         rtsx_write_phy_register(chip, 0x07, 0);
2236                 if (CHECK_PID(chip, 0x5208)) {
2237                         rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
2238                                             0x30 | chip->aspm_level[0]);
2239                 } else {
2240                         rtsx_write_config_byte(chip, LCTLR,
2241                                                chip->aspm_l0s_l1_en);
2242                 }
2243
2244                 if (CHK_SDIO_EXIST(chip)) {
2245                         u16 val = chip->aspm_l0s_l1_en | 0x0100;
2246
2247                         rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2248                                           0xC0, 0xFFF, val);
2249                 }
2250         }
2251 }
2252
2253 void rtsx_disable_aspm(struct rtsx_chip *chip)
2254 {
2255         if (CHECK_PID(chip, 0x5208))
2256                 rtsx_monitor_aspm_config(chip);
2257
2258         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && chip->aspm_enabled) {
2259                 dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n");
2260                 chip->aspm_enabled = 0;
2261
2262                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2263                         rtsx_write_phy_register(chip, 0x07, 0x0129);
2264                 if (CHECK_PID(chip, 0x5208))
2265                         rtsx_write_register(chip, ASPM_FORCE_CTL,
2266                                             0xF3, 0x30);
2267                 else
2268                         rtsx_write_config_byte(chip, LCTLR, 0x00);
2269
2270                 wait_timeout(1);
2271         }
2272 }
2273
2274 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2275 {
2276         int retval;
2277         int i, j;
2278         u16 reg_addr;
2279         u8 *ptr;
2280
2281         if (!buf) {
2282                 rtsx_trace(chip);
2283                 return STATUS_ERROR;
2284         }
2285
2286         ptr = buf;
2287         reg_addr = PPBUF_BASE2;
2288         for (i = 0; i < buf_len/256; i++) {
2289                 rtsx_init_cmd(chip);
2290
2291                 for (j = 0; j < 256; j++)
2292                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2293
2294                 retval = rtsx_send_cmd(chip, 0, 250);
2295                 if (retval < 0) {
2296                         rtsx_trace(chip);
2297                         return STATUS_FAIL;
2298                 }
2299
2300                 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
2301                 ptr += 256;
2302         }
2303
2304         if (buf_len%256) {
2305                 rtsx_init_cmd(chip);
2306
2307                 for (j = 0; j < buf_len%256; j++)
2308                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2309
2310                 retval = rtsx_send_cmd(chip, 0, 250);
2311                 if (retval < 0) {
2312                         rtsx_trace(chip);
2313                         return STATUS_FAIL;
2314                 }
2315         }
2316
2317         memcpy(ptr, rtsx_get_cmd_data(chip), buf_len%256);
2318
2319         return STATUS_SUCCESS;
2320 }
2321
2322 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2323 {
2324         int retval;
2325         int i, j;
2326         u16 reg_addr;
2327         u8 *ptr;
2328
2329         if (!buf) {
2330                 rtsx_trace(chip);
2331                 return STATUS_ERROR;
2332         }
2333
2334         ptr = buf;
2335         reg_addr = PPBUF_BASE2;
2336         for (i = 0; i < buf_len/256; i++) {
2337                 rtsx_init_cmd(chip);
2338
2339                 for (j = 0; j < 256; j++) {
2340                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2341                                      *ptr);
2342                         ptr++;
2343                 }
2344
2345                 retval = rtsx_send_cmd(chip, 0, 250);
2346                 if (retval < 0) {
2347                         rtsx_trace(chip);
2348                         return STATUS_FAIL;
2349                 }
2350         }
2351
2352         if (buf_len%256) {
2353                 rtsx_init_cmd(chip);
2354
2355                 for (j = 0; j < buf_len%256; j++) {
2356                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2357                                      *ptr);
2358                         ptr++;
2359                 }
2360
2361                 retval = rtsx_send_cmd(chip, 0, 250);
2362                 if (retval < 0) {
2363                         rtsx_trace(chip);
2364                         return STATUS_FAIL;
2365                 }
2366         }
2367
2368         return STATUS_SUCCESS;
2369 }
2370
2371 int rtsx_check_chip_exist(struct rtsx_chip *chip)
2372 {
2373         if (rtsx_readl(chip, 0) == 0xFFFFFFFF) {
2374                 rtsx_trace(chip);
2375                 return STATUS_FAIL;
2376         }
2377
2378         return STATUS_SUCCESS;
2379 }
2380
2381 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
2382 {
2383         int retval;
2384         u8 mask = 0;
2385
2386         if (ctl & SSC_PDCTL)
2387                 mask |= SSC_POWER_DOWN;
2388
2389 #ifdef SUPPORT_OCP
2390         if (ctl & OC_PDCTL) {
2391                 mask |= SD_OC_POWER_DOWN;
2392                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2393                         mask |= MS_OC_POWER_DOWN;
2394         }
2395 #endif
2396
2397         if (mask) {
2398                 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
2399                 if (retval != STATUS_SUCCESS) {
2400                         rtsx_trace(chip);
2401                         return STATUS_FAIL;
2402                 }
2403
2404                 if (CHECK_PID(chip, 0x5288))
2405                         wait_timeout(200);
2406         }
2407
2408         return STATUS_SUCCESS;
2409 }
2410
2411 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
2412 {
2413         int retval;
2414         u8 mask = 0, val = 0;
2415
2416         if (ctl & SSC_PDCTL)
2417                 mask |= SSC_POWER_DOWN;
2418
2419 #ifdef SUPPORT_OCP
2420         if (ctl & OC_PDCTL) {
2421                 mask |= SD_OC_POWER_DOWN;
2422                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2423                         mask |= MS_OC_POWER_DOWN;
2424         }
2425 #endif
2426
2427         if (mask) {
2428                 val = mask;
2429                 retval = rtsx_write_register(chip, FPDCTL, mask, val);
2430                 if (retval != STATUS_SUCCESS) {
2431                         rtsx_trace(chip);
2432                         return STATUS_FAIL;
2433                 }
2434         }
2435
2436         return STATUS_SUCCESS;
2437 }