kernel/drivers/staging/rtl8723au/include/rtl8723a_hal.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15 #ifndef __RTL8723A_HAL_H__
  16 #define __RTL8723A_HAL_H__
  17
  18 #include "rtl8723a_spec.h"
  19 #include "rtl8723a_pg.h"
  20 #include "Hal8723APhyReg.h"
  21 #include "Hal8723APhyCfg.h"
  22 #include "rtl8723a_rf.h"
  23 #include "rtl8723a_bt_intf.h"
  24 #ifdef CONFIG_8723AU_BT_COEXIST
  25 #include "rtl8723a_bt-coexist.h"
  26 #endif
  27 #include "rtl8723a_dm.h"
  28 #include "rtl8723a_recv.h"
  29 #include "rtl8723a_xmit.h"
  30 #include "rtl8723a_cmd.h"
  31 #include "rtl8723a_sreset.h"
  32 #include "rtw_efuse.h"
  33 #include "rtw_eeprom.h"
  34
  35 #include "odm_precomp.h"
  36 #include "odm.h"
  37
  38
  39 /* 2TODO: We should define 8192S firmware related macro settings here!! */
  40 #define RTL819X_DEFAULT_RF_TYPE                 RF_1T2R
  41 #define RTL819X_TOTAL_RF_PATH                           2
  42
  43 /*  */
  44 /*              RTL8723S From header */
  45 /*  */
  46
  47 /*  Fw Array */
  48 #define Rtl8723_FwImageArray                            Rtl8723UFwImgArray
  49 #define Rtl8723_FwUMCBCutImageArrayWithBT               Rtl8723UFwUMCBCutImgArrayWithBT
  50 #define Rtl8723_FwUMCBCutImageArrayWithoutBT    Rtl8723UFwUMCBCutImgArrayWithoutBT
  51
  52 #define Rtl8723_ImgArrayLength                          Rtl8723UImgArrayLength
  53 #define Rtl8723_UMCBCutImgArrayWithBTLength             Rtl8723UUMCBCutImgArrayWithBTLength
  54 #define Rtl8723_UMCBCutImgArrayWithoutBTLength  Rtl8723UUMCBCutImgArrayWithoutBTLength
  55
  56 #define Rtl8723_PHY_REG_Array_PG                        Rtl8723UPHY_REG_Array_PG
  57 #define Rtl8723_PHY_REG_Array_PGLength          Rtl8723UPHY_REG_Array_PGLength
  58
  59 #define Rtl8723_FwUMCBCutMPImageArray           Rtl8723SFwUMCBCutMPImgAr
  60 #define Rtl8723_UMCBCutMPImgArrayLength         Rtl8723SUMCBCutMPImgArrayLength
  61
  62 #define DRVINFO_SZ                              4 /*  unit is 8bytes */
  63 #define PageNum_128(_Len)               (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
  64
  65 #define FW_8723A_SIZE                   0x8000
  66 #define FW_8723A_START_ADDRESS  0x1000
  67 #define FW_8723A_END_ADDRESS            0x1FFF /* 0x5FFF */
  68
  69 #define MAX_PAGE_SIZE                   4096    /*  @ page : 4k bytes */
  70
  71 #define IS_FW_HEADER_EXIST(_pFwHdr)     ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
  72                                                                         (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
  73                                                                         (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
  74
  75 /*  */
  76 /*  This structure must be cared byte-ordering */
  77 /*  */
  78 /*  Added by tynli. 2009.12.04. */
  79 struct rt_8723a_firmware_hdr {
  80         /*  8-byte alinment required */
  81
  82         /*  LONG WORD 0 ---- */
  83         u16             Signature;      /*  92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
  84         u8              Category;       /*  AP/NIC and USB/PCI */
  85         u8              Function;       /*  Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
  86         u16             Version;                /*  FW Version */
  87         u8              Subversion;     /*  FW Subversion, default 0x00 */
  88         u16             Rsvd1;
  89
  90
  91         /*  LONG WORD 1 ---- */
  92         u8              Month;  /*  Release time Month field */
  93         u8              Date;   /*  Release time Date field */
  94         u8              Hour;   /*  Release time Hour field */
  95         u8              Minute; /*  Release time Minute field */
  96         u16             RamCodeSize;    /*  The size of RAM code */
  97         u16             Rsvd2;
  98
  99         /*  LONG WORD 2 ---- */
 100         u32             SvnIdx; /*  The SVN entry index */
 101         u32             Rsvd3;
 102
 103         /*  LONG WORD 3 ---- */
 104         u32             Rsvd4;
 105         u32             Rsvd5;
 106 };
 107
 108 #define DRIVER_EARLY_INT_TIME           0x05
 109 #define BCN_DMA_ATIME_INT_TIME          0x02
 110
 111
 112 /*  BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
 113 #define MAX_TX_QUEUE            9
 114
 115 #define TX_SELE_HQ                      BIT(0)          /*  High Queue */
 116 #define TX_SELE_LQ                      BIT(1)          /*  Low Queue */
 117 #define TX_SELE_NQ                      BIT(2)          /*  Normal Queue */
 118
 119 /*  Note: We will divide number of page equally for each queue other than public queue! */
 120 #define TX_TOTAL_PAGE_NUMBER    0xF8
 121 #define TX_PAGE_BOUNDARY                (TX_TOTAL_PAGE_NUMBER + 1)
 122
 123 /*  For Normal Chip Setting */
 124 /*  (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
 125 #define NORMAL_PAGE_NUM_PUBQ    0xE7
 126 #define NORMAL_PAGE_NUM_HPQ             0x0C
 127 #define NORMAL_PAGE_NUM_LPQ             0x02
 128 #define NORMAL_PAGE_NUM_NPQ             0x02
 129
 130 /*  For Test Chip Setting */
 131 /*  (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
 132 #define TEST_PAGE_NUM_PUBQ              0x7E
 133
 134 /*  For Test Chip Setting */
 135 #define WMM_TEST_TX_TOTAL_PAGE_NUMBER   0xF5
 136 #define WMM_TEST_TX_PAGE_BOUNDARY               (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
 137
 138 #define WMM_TEST_PAGE_NUM_PUBQ          0xA3
 139 #define WMM_TEST_PAGE_NUM_HPQ           0x29
 140 #define WMM_TEST_PAGE_NUM_LPQ           0x29
 141
 142 /*  Note: For Normal Chip Setting, modify later */
 143 #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
 144 #define WMM_NORMAL_TX_PAGE_BOUNDARY             (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
 145
 146 #define WMM_NORMAL_PAGE_NUM_PUBQ        0xB0
 147 #define WMM_NORMAL_PAGE_NUM_HPQ         0x29
 148 #define WMM_NORMAL_PAGE_NUM_LPQ         0x1C
 149 #define WMM_NORMAL_PAGE_NUM_NPQ         0x1C
 150
 151
 152 /*  */
 153 /*      Chip specific */
 154 /*  */
 155 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 156 #define CHIP_BONDING_92C_1T2R                   0x1
 157 #define CHIP_BONDING_88C_USB_MCARD              0x2
 158 #define CHIP_BONDING_88C_USB_HP                 0x1
 159
 160 #include "HalVerDef.h"
 161 #include "hal_com.h"
 162
 163 /*  */
 164 /*      Channel Plan */
 165 /*  */
 166 enum ChannelPlan
 167 {
 168         CHPL_FCC        = 0,
 169         CHPL_IC         = 1,
 170         CHPL_ETSI       = 2,
 171         CHPL_SPAIN      = 3,
 172         CHPL_FRANCE     = 4,
 173         CHPL_MKK        = 5,
 174         CHPL_MKK1       = 6,
 175         CHPL_ISRAEL     = 7,
 176         CHPL_TELEC      = 8,
 177         CHPL_GLOBAL     = 9,
 178         CHPL_WORLD      = 10,
 179 };
 180
 181 #define EFUSE_REAL_CONTENT_LEN          512
 182 #define EFUSE_MAP_LEN                           128
 183 #define EFUSE_MAX_SECTION                       16
 184 #define EFUSE_IC_ID_OFFSET                      506     /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
 185 #define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 186 /*  */
 187 /*  <Roger_Notes> */
 188 /*  To prevent out of boundary programming case, */
 189 /*  leave 1byte and program full section */
 190 /*  9bytes + 1byt + 5bytes and pre 1byte. */
 191 /*  For worst case: */
 192 /*  | 1byte|----8bytes----|1byte|--5bytes--| */
 193 /*  |         |            Reserved(14bytes)          | */
 194 /*  */
 195
 196 /*  PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
 197 #define EFUSE_OOB_PROTECT_BYTES                 15
 198
 199 #define EFUSE_REAL_CONTENT_LEN_8723A    512
 200 #define EFUSE_MAP_LEN_8723A                             256
 201 #define EFUSE_MAX_SECTION_8723A                 32
 202
 203 /*  */
 204 /*                      EFUSE for BT definition */
 205 /*  */
 206 #define EFUSE_BT_REAL_BANK_CONTENT_LEN  512
 207 #define EFUSE_BT_REAL_CONTENT_LEN               1536    /*  512*3 */
 208 #define EFUSE_BT_MAP_LEN                                1024    /*  1k bytes */
 209 #define EFUSE_BT_MAX_SECTION                    128             /*  1024/8 */
 210
 211 #define EFUSE_PROTECT_BYTES_BANK                16
 212
 213 /*  */
 214 /*  <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */
 215 /*  */
 216 enum RT_MULTI_FUNC {
 217         RT_MULTI_FUNC_NONE = 0x00,
 218         RT_MULTI_FUNC_WIFI = 0x01,
 219         RT_MULTI_FUNC_BT = 0x02,
 220         RT_MULTI_FUNC_GPS = 0x04,
 221 };
 222
 223 /*  */
 224 /*  <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */
 225 /*  */
 226 enum RT_POLARITY_CTL {
 227         RT_POLARITY_LOW_ACT = 0,
 228         RT_POLARITY_HIGH_ACT = 1,
 229 };
 230
 231 /*  For RTL8723 regulator mode. by tynli. 2011.01.14. */
 232 enum RT_REGULATOR_MODE {
 233         RT_SWITCHING_REGULATOR = 0,
 234         RT_LDO_REGULATOR = 1,
 235 };
 236
 237 /*  Description: Determine the types of C2H events that are the same in driver and Fw. */
 238 /*  Fisrt constructed by tynli. 2009.10.09. */
 239 enum {
 240         C2H_DBG = 0,
 241         C2H_TSF = 1,
 242         C2H_AP_RPT_RSP = 2,
 243         C2H_CCX_TX_RPT = 3,     /*  The FW notify the report of the specific tx packet. */
 244         C2H_BT_RSSI = 4,
 245         C2H_BT_OP_MODE = 5,
 246         C2H_EXT_RA_RPT = 6,
 247         C2H_HW_INFO_EXCH = 10,
 248         C2H_C2H_H2C_TEST = 11,
 249         C2H_BT_INFO = 12,
 250         C2H_BT_MP_INFO = 15,
 251         MAX_C2HEVENT
 252 };
 253
 254 struct hal_data_8723a {
 255         struct hal_version              VersionID;
 256         enum rt_customer_id CustomerID;
 257
 258         u16     FirmwareVersion;
 259         u16     FirmwareVersionRev;
 260         u16     FirmwareSubVersion;
 261         u16     FirmwareSignature;
 262
 263         /* current WIFI_PHY values */
 264         u32     ReceiveConfig;
 265         enum WIRELESS_MODE              CurrentWirelessMode;
 266         enum ht_channel_width   CurrentChannelBW;
 267         u8      CurrentChannel;
 268         u8      nCur40MhzPrimeSC;/*  Control channel sub-carrier */
 269
 270         u16     BasicRateSet;
 271
 272         /* rf_ctrl */
 273         u8      rf_type;
 274         u8      NumTotalRFPath;
 275
 276         u8      BoardType;
 277         u8      CrystalCap;
 278         /*  */
 279         /*  EEPROM setting. */
 280         /*  */
 281         u8      EEPROMVersion;
 282         u8      EEPROMCustomerID;
 283         u8      EEPROMSubCustomerID;
 284         u8      EEPROMRegulatory;
 285         u8      EEPROMThermalMeter;
 286         u8      EEPROMBluetoothCoexist;
 287         u8      EEPROMBluetoothType;
 288         u8      EEPROMBluetoothAntNum;
 289         u8      EEPROMBluetoothAntIsolation;
 290         u8      EEPROMBluetoothRadioShared;
 291
 292         u8      bTXPowerDataReadFromEEPORM;
 293         u8      bAPKThermalMeterIgnore;
 294
 295         u8      bIQKInitialized;
 296         u8      bAntennaDetected;
 297
 298         u8      TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 299         u8      TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];     /*  For HT 40MHZ pwr */
 300         u8      TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];     /*  For HT 40MHZ pwr */
 301         u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/*  HT 20<->40 Pwr diff */
 302         u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/*  For HT<->legacy pwr diff */
 303         /*  For power group */
 304         u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 305         u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 306
 307         u8      LegacyHTTxPowerDiff;/*  Legacy to HT rate power diff */
 308
 309         /*  Read/write are allow for following hardware information variables */
 310         u8      framesync;
 311         u32     framesyncC34;
 312         u8      framesyncMonitor;
 313         u8      pwrGroupCnt;
 314         u32     MCSTxPowerLevelOriginalOffset[7][16];
 315         u32     CCKTxPowerLevelOriginalOffset;
 316
 317         u32     AntennaTxPath;                                  /*  Antenna path Tx */
 318         u32     AntennaRxPath;                                  /*  Antenna path Rx */
 319         u8      ExternalPA;
 320
 321         u8      bLedOpenDrain; /*  Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
 322
 323         u8      b1x1RecvCombine;        /*  for 1T1R receive combining */
 324
 325         /*  For EDCA Turbo mode */
 326
 327         u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
 328
 329         /* vivi, for tx power tracking, 20080407 */
 330         /* u16  TSSI_13dBm; */
 331         /* u32  Pwr_Track; */
 332         /*  The current Tx Power Level */
 333         u8      CurrentCckTxPwrIdx;
 334         u8      CurrentOfdm24GTxPwrIdx;
 335
 336         struct bb_reg_define    PHYRegDef[4];   /* Radio A/B/C/D */
 337
 338         bool            bRFPathRxEnable[4];     /*  We support 4 RF path now. */
 339
 340         u32     RfRegChnlVal[2];
 341
 342         u8      bCckHighPower;
 343
 344         /* RDG enable */
 345         bool     bRDGEnable;
 346
 347         /* for host message to fw */
 348         u8      LastHMEBoxNum;
 349
 350         u8      RegTxPause;
 351         /*  Beacon function related global variable. */
 352         u8      RegFwHwTxQCtrl;
 353         u8      RegReg542;
 354
 355         struct dm_priv  dmpriv;
 356         struct dm_odm_t         odmpriv;
 357         struct sreset_priv srestpriv;
 358
 359 #ifdef CONFIG_8723AU_BT_COEXIST
 360         u8                              bBTMode;
 361         /*  BT only. */
 362         struct bt_30info                BtInfo;
 363         /*  For bluetooth co-existance */
 364         struct bt_coexist_str   bt_coexist;
 365 #endif
 366
 367         u8      bDumpRxPkt;/* for debug */
 368         u8      FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */
 369
 370         /*  2010/08/09 MH Add CU power down mode. */
 371         u8      pwrdown;
 372
 373         u8      OutEpQueueSel;
 374         u8      OutEpNumber;
 375
 376         /*  */
 377         /*  Add For EEPROM Efuse switch and  Efuse Shadow map Setting */
 378         /*  */
 379         u8                      EepromOrEfuse;
 380         u16                     EfuseUsedBytes;
 381         u16                     BTEfuseUsedBytes;
 382
 383         /*  Interrupt relatd register information. */
 384         u32                     SysIntrStatus;
 385         u32                     SysIntrMask;
 386
 387         /*  */
 388         /*  2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an */
 389         /*  independent file in the future. */
 390         /*  */
 391         /* 8723-----------------------------------------*/
 392         enum RT_MULTI_FUNC      MultiFunc; /*  For multi-function consideration. */
 393         enum RT_POLARITY_CTL    PolarityCtl; /*  For Wifi PDn Polarity control. */
 394         enum RT_REGULATOR_MODE  RegulatorMode; /*  switching regulator or LDO */
 395         /* 8723-----------------------------------------
 396          *  2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an */
 397         /*  independent file in the future. */
 398
 399         /*  Interrupt related register information. */
 400         u32     IntArray[2];
 401         u32     IntrMask[2];
 402 };
 403
 404 #define GET_HAL_DATA(__pAdapter)        ((struct hal_data_8723a *)((__pAdapter)->HalData))
 405 #define GET_RF_TYPE(priv)                       (GET_HAL_DATA(priv)->rf_type)
 406
 407 #define INCLUDE_MULTI_FUNC_BT(_Adapter)         (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
 408 #define INCLUDE_MULTI_FUNC_GPS(_Adapter)        (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
 409
 410 struct rxreport_8723a {
 411         u32 pktlen:14;
 412         u32 crc32:1;
 413         u32 icverr:1;
 414         u32 drvinfosize:4;
 415         u32 security:3;
 416         u32 qos:1;
 417         u32 shift:2;
 418         u32 physt:1;
 419         u32 swdec:1;
 420         u32 ls:1;
 421         u32 fs:1;
 422         u32 eor:1;
 423         u32 own:1;
 424
 425         u32 macid:5;
 426         u32 tid:4;
 427         u32 hwrsvd:4;
 428         u32 amsdu:1;
 429         u32 paggr:1;
 430         u32 faggr:1;
 431         u32 a1fit:4;
 432         u32 a2fit:4;
 433         u32 pam:1;
 434         u32 pwr:1;
 435         u32 md:1;
 436         u32 mf:1;
 437         u32 type:2;
 438         u32 mc:1;
 439         u32 bc:1;
 440
 441         u32 seq:12;
 442         u32 frag:4;
 443         u32 nextpktlen:14;
 444         u32 nextind:1;
 445         u32 rsvd0831:1;
 446
 447         u32 rxmcs:6;
 448         u32 rxht:1;
 449         u32 gf:1;
 450         u32 splcp:1;
 451         u32 bw:1;
 452         u32 htc:1;
 453         u32 eosp:1;
 454         u32 bssidfit:2;
 455         u32 rsvd1214:16;
 456         u32 unicastwake:1;
 457         u32 magicwake:1;
 458
 459         u32 pattern0match:1;
 460         u32 pattern1match:1;
 461         u32 pattern2match:1;
 462         u32 pattern3match:1;
 463         u32 pattern4match:1;
 464         u32 pattern5match:1;
 465         u32 pattern6match:1;
 466         u32 pattern7match:1;
 467         u32 pattern8match:1;
 468         u32 pattern9match:1;
 469         u32 patternamatch:1;
 470         u32 patternbmatch:1;
 471         u32 patterncmatch:1;
 472         u32 rsvd1613:19;
 473
 474         u32 tsfl;
 475
 476         u32 bassn:12;
 477         u32 bavld:1;
 478         u32 rsvd2413:19;
 479 };
 480
 481 /*  rtl8723a_hal_init.c */
 482 s32 rtl8723a_FirmwareDownload(struct rtw_adapter *padapter);
 483 void rtl8723a_FirmwareSelfReset(struct rtw_adapter *padapter);
 484 void rtl8723a_InitializeFirmwareVars(struct rtw_adapter *padapter);
 485
 486 void rtl8723a_InitAntenna_Selection(struct rtw_adapter *padapter);
 487 void rtl8723a_DeinitAntenna_Selection(struct rtw_adapter *padapter);
 488 void rtl8723a_CheckAntenna_Selection(struct rtw_adapter *padapter);
 489 void rtl8723a_init_default_value(struct rtw_adapter *padapter);
 490
 491 s32 InitLLTTable23a(struct rtw_adapter *padapter, u32 boundary);
 492
 493 s32 CardDisableHWSM(struct rtw_adapter *padapter, u8 resetMCU);
 494 s32 CardDisableWithoutHWSM(struct rtw_adapter *padapter);
 495
 496 /*  EFuse */
 497 u8 GetEEPROMSize8723A(struct rtw_adapter *padapter);
 498 void Hal_InitPGData(struct rtw_adapter *padapter, u8 *PROMContent);
 499 void Hal_EfuseParseIDCode(struct rtw_adapter *padapter, u8 *hwinfo);
 500 void Hal_EfuseParsetxpowerinfo_8723A(struct rtw_adapter *padapter, u8 *PROMContent, bool AutoLoadFail);
 501 void Hal_EfuseParseBTCoexistInfo_8723A(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 502 void Hal_EfuseParseEEPROMVer(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 503 void rtl8723a_EfuseParseChnlPlan(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 504 void Hal_EfuseParseCustomerID(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 505 void Hal_EfuseParseAntennaDiversity(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 506 void Hal_EfuseParseRateIndicationOption(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 507 void Hal_EfuseParseXtal_8723A(struct rtw_adapter *pAdapter, u8 *hwinfo, u8 AutoLoadFail);
 508 void Hal_EfuseParseThermalMeter_8723A(struct rtw_adapter *padapter, u8 *hwinfo, bool AutoLoadFail);
 509
 510 /*  register */
 511 void SetBcnCtrlReg23a(struct rtw_adapter *padapter, u8 SetBits, u8 ClearBits);
 512 void rtl8723a_InitBeaconParameters(struct rtw_adapter *padapter);
 513
 514 void rtl8723a_start_thread(struct rtw_adapter *padapter);
 515 void rtl8723a_stop_thread(struct rtw_adapter *padapter);
 516
 517 bool c2h_id_filter_ccx_8723a(u8 id);
 518 int c2h_handler_8723a(struct rtw_adapter *padapter, struct c2h_evt_hdr *c2h_evt);
 519
 520 void rtl8723a_read_adapter_info(struct rtw_adapter *Adapter);
 521 void rtl8723a_read_chip_version(struct rtw_adapter *padapter);
 522 void rtl8723a_notch_filter(struct rtw_adapter *adapter, bool enable);
 523 void rtl8723a_SetBeaconRelatedRegisters(struct rtw_adapter *padapter);
 524 void rtl8723a_SetHalODMVar(struct rtw_adapter *Adapter,
 525                            enum hal_odm_variable eVariable,
 526                            void *pValue1, bool bSet);
 527 void
 528 rtl8723a_readefuse(struct rtw_adapter *padapter,
 529                    u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf);
 530 u16 rtl8723a_EfuseGetCurrentSize_WiFi(struct rtw_adapter *padapter);
 531 u16 rtl8723a_EfuseGetCurrentSize_BT(struct rtw_adapter *padapter);
 532 void rtl8723a_update_ramask(struct rtw_adapter *padapter,
 533                             u32 mac_id, u8 rssi_level);
 534
 535 #endif