kernel/drivers/staging/rtl8192u/r819xU_phy.c

   1 #include "r8192U.h"
   2 #include "r8192U_hw.h"
   3 #include "r819xU_phy.h"
   4 #include "r819xU_phyreg.h"
   5 #include "r8190_rtl8256.h"
   6 #include "r8192U_dm.h"
   7 #include "r819xU_firmware_img.h"
   8
   9 #include "dot11d.h"
  10 #include <linux/bitops.h>
  11
  12 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  13         0,
  14         0x085c, /* 2412 1  */
  15         0x08dc, /* 2417 2  */
  16         0x095c, /* 2422 3  */
  17         0x09dc, /* 2427 4  */
  18         0x0a5c, /* 2432 5  */
  19         0x0adc, /* 2437 6  */
  20         0x0b5c, /* 2442 7  */
  21         0x0bdc, /* 2447 8  */
  22         0x0c5c, /* 2452 9  */
  23         0x0cdc, /* 2457 10 */
  24         0x0d5c, /* 2462 11 */
  25         0x0ddc, /* 2467 12 */
  26         0x0e5c, /* 2472 13 */
  27         0x0f72, /* 2484    */
  28 };
  29
  30
  31 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
  32 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
  33 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
  34 #define rtl819XRadioA_Array  Rtl8192UsbRadioA_Array
  35 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
  36 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
  37 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
  38 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
  39
  40 /******************************************************************************
  41  * function: This function reads BB parameters from header file we generate,
  42  *           and does register read/write
  43  * input:    u32        bitmask  //taget bit pos in the addr to be modified
  44  * output:   none
  45  * return:   u32        return the shift bit position of the mask
  46  ******************************************************************************/
  47 static u32 rtl8192_CalculateBitShift(u32 bitmask)
  48 {
  49         u32 i;
  50
  51         i = ffs(bitmask) - 1;
  52         return i;
  53 }
  54
  55 /******************************************************************************
  56  * function:  This function checks different RF type to execute legal judgement.
  57  *            If RF Path is illegal, we will return false.
  58  * input:     net_device         *dev
  59  *            u32                eRFPath
  60  * output:    none
  61  * return:    0(illegal, false), 1(legal, true)
  62  *****************************************************************************/
  63 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
  64 {
  65         u8 ret = 1;
  66         struct r8192_priv *priv = ieee80211_priv(dev);
  67
  68         if (priv->rf_type == RF_2T4R) {
  69                 ret = 0;
  70         } else if (priv->rf_type == RF_1T2R) {
  71                 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
  72                         ret = 1;
  73                 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
  74                         ret = 0;
  75         }
  76         return ret;
  77 }
  78
  79 /******************************************************************************
  80  * function:  This function sets specific bits to BB register
  81  * input:     net_device *dev
  82  *            u32        reg_addr   //target addr to be modified
  83  *            u32        bitmask    //taget bit pos to be modified
  84  *            u32        data       //value to be write
  85  * output:    none
  86  * return:    none
  87  * notice:
  88  ******************************************************************************/
  89 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
  90                       u32 data)
  91 {
  92
  93         u32 reg, bitshift;
  94
  95         if (bitmask != bMaskDWord) {
  96                 read_nic_dword(dev, reg_addr, &reg);
  97                 bitshift = rtl8192_CalculateBitShift(bitmask);
  98                 reg &= ~bitmask;
  99                 reg |= data << bitshift;
 100                 write_nic_dword(dev, reg_addr, reg);
 101         } else {
 102                 write_nic_dword(dev, reg_addr, data);
 103         }
 104 }
 105
 106 /******************************************************************************
 107  * function:  This function reads specific bits from BB register
 108  * input:     net_device        *dev
 109  *            u32               reg_addr   //target addr to be readback
 110  *            u32               bitmask    //taget bit pos to be readback
 111  * output:    none
 112  * return:    u32               data       //the readback register value
 113  * notice:
 114  ******************************************************************************/
 115 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
 116 {
 117         u32 reg, bitshift;
 118
 119         read_nic_dword(dev, reg_addr, &reg);
 120         bitshift = rtl8192_CalculateBitShift(bitmask);
 121
 122         return (reg & bitmask) >> bitshift;
 123 }
 124
 125 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 126                               u32 offset);
 127
 128 static void phy_FwRFSerialWrite(struct net_device *dev,
 129                                 RF90_RADIO_PATH_E eRFPath, u32  offset,
 130                                 u32  data);
 131
 132 /******************************************************************************
 133  * function:  This function reads register from RF chip
 134  * input:     net_device        *dev
 135  *            RF90_RADIO_PATH_E eRFPath    //radio path of A/B/C/D
 136  *            u32               offset     //target address to be read
 137  * output:    none
 138  * return:    u32               readback value
 139  * notice:    There are three types of serial operations:
 140  *            (1) Software serial write.
 141  *            (2)Hardware LSSI-Low Speed Serial Interface.
 142  *            (3)Hardware HSSI-High speed serial write.
 143  *            Driver here need to implement (1) and (2)
 144  *            ---need more spec for this information.
 145  ******************************************************************************/
 146 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
 147                                     RF90_RADIO_PATH_E eRFPath, u32 offset)
 148 {
 149         struct r8192_priv *priv = ieee80211_priv(dev);
 150         u32 ret = 0;
 151         u32 new_offset = 0;
 152         BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
 153
 154         rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
 155         /* Make sure RF register offset is correct */
 156         offset &= 0x3f;
 157
 158         /* Switch page for 8256 RF IC */
 159         if (priv->rf_chip == RF_8256) {
 160                 if (offset >= 31) {
 161                         priv->RfReg0Value[eRFPath] |= 0x140;
 162                         /* Switch to Reg_Mode2 for Reg 31-45 */
 163                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 164                                          bMaskDWord,
 165                                          priv->RfReg0Value[eRFPath]<<16);
 166                         /* Modify offset */
 167                         new_offset = offset - 30;
 168                 } else if (offset >= 16) {
 169                         priv->RfReg0Value[eRFPath] |= 0x100;
 170                         priv->RfReg0Value[eRFPath] &= (~0x40);
 171                         /* Switch to Reg_Mode1 for Reg16-30 */
 172                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 173                                          bMaskDWord,
 174                                          priv->RfReg0Value[eRFPath]<<16);
 175
 176                         new_offset = offset - 15;
 177                 } else {
 178                         new_offset = offset;
 179                 }
 180         } else {
 181                 RT_TRACE((COMP_PHY|COMP_ERR),
 182                          "check RF type here, need to be 8256\n");
 183                 new_offset = offset;
 184         }
 185         /* Put desired read addr to LSSI control Register */
 186         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
 187                          new_offset);
 188         /* Issue a posedge trigger */
 189         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 190         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 191
 192
 193         /* TODO: we should not delay such a long time. Ask for help from SD3 */
 194         usleep_range(1000, 1000);
 195
 196         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
 197                                  bLSSIReadBackData);
 198
 199
 200         /* Switch back to Reg_Mode0 */
 201         if (priv->rf_chip == RF_8256) {
 202                 priv->RfReg0Value[eRFPath] &= 0xebf;
 203
 204                 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
 205                                  priv->RfReg0Value[eRFPath] << 16);
 206         }
 207
 208         return ret;
 209 }
 210
 211 /******************************************************************************
 212  * function:  This function writes data to RF register
 213  * input:     net_device        *dev
 214  *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
 215  *            u32               offset   //target address to be written
 216  *            u32               data     //the new register data to be written
 217  * output:    none
 218  * return:    none
 219  * notice:    For RF8256 only.
 220  * ===========================================================================
 221  * Reg Mode     RegCTL[1]       RegCTL[0]               Note
 222  *              (Reg00[12])     (Reg00[10])
 223  * ===========================================================================
 224  * Reg_Mode0    0               x                       Reg 0 ~ 15(0x0 ~ 0xf)
 225  * ---------------------------------------------------------------------------
 226  * Reg_Mode1    1               0                       Reg 16 ~ 30(0x1 ~ 0xf)
 227  * ---------------------------------------------------------------------------
 228  * Reg_Mode2    1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 229  * ---------------------------------------------------------------------------
 230  *****************************************************************************/
 231 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
 232                                       RF90_RADIO_PATH_E eRFPath, u32 offset,
 233                                       u32 data)
 234 {
 235         struct r8192_priv *priv = ieee80211_priv(dev);
 236         u32 DataAndAddr = 0, new_offset = 0;
 237         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 238
 239         offset &= 0x3f;
 240         if (priv->rf_chip == RF_8256) {
 241
 242                 if (offset >= 31) {
 243                         priv->RfReg0Value[eRFPath] |= 0x140;
 244                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 245                                          bMaskDWord,
 246                                          priv->RfReg0Value[eRFPath] << 16);
 247                         new_offset = offset - 30;
 248                 } else if (offset >= 16) {
 249                         priv->RfReg0Value[eRFPath] |= 0x100;
 250                         priv->RfReg0Value[eRFPath] &= (~0x40);
 251                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 252                                          bMaskDWord,
 253                                          priv->RfReg0Value[eRFPath]<<16);
 254                         new_offset = offset - 15;
 255                 } else {
 256                         new_offset = offset;
 257                 }
 258         } else {
 259                 RT_TRACE((COMP_PHY|COMP_ERR),
 260                          "check RF type here, need to be 8256\n");
 261                 new_offset = offset;
 262         }
 263
 264         /* Put write addr in [5:0] and write data in [31:16] */
 265         DataAndAddr = (data<<16) | (new_offset&0x3f);
 266
 267         /* Write operation */
 268         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 269
 270
 271         if (offset == 0x0)
 272                 priv->RfReg0Value[eRFPath] = data;
 273
 274         /* Switch back to Reg_Mode0 */
 275         if (priv->rf_chip == RF_8256) {
 276                 if (offset != 0) {
 277                         priv->RfReg0Value[eRFPath] &= 0xebf;
 278                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 279                                          bMaskDWord,
 280                                          priv->RfReg0Value[eRFPath] << 16);
 281                 }
 282         }
 283 }
 284
 285 /******************************************************************************
 286  * function:  This function set specific bits to RF register
 287  * input:     net_device        dev
 288  *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
 289  *            u32               reg_addr //target addr to be modified
 290  *            u32               bitmask  //taget bit pos to be modified
 291  *            u32               data     //value to be written
 292  * output:    none
 293  * return:    none
 294  * notice:
 295  *****************************************************************************/
 296 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 297                           u32 reg_addr, u32 bitmask, u32 data)
 298 {
 299         struct r8192_priv *priv = ieee80211_priv(dev);
 300         u32 reg, bitshift;
 301
 302         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 303                 return;
 304
 305         if (priv->Rf_Mode == RF_OP_By_FW) {
 306                 if (bitmask != bMask12Bits) {
 307                         /* RF data is 12 bits only */
 308                         reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
 309                         bitshift =  rtl8192_CalculateBitShift(bitmask);
 310                         reg &= ~bitmask;
 311                         reg |= data << bitshift;
 312
 313                         phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg);
 314                 } else {
 315                         phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data);
 316                 }
 317
 318                 udelay(200);
 319
 320         } else {
 321                 if (bitmask != bMask12Bits) {
 322                         /* RF data is 12 bits only */
 323                         reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
 324                         bitshift =  rtl8192_CalculateBitShift(bitmask);
 325                         reg &= ~bitmask;
 326                         reg |= data << bitshift;
 327
 328                         rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg);
 329                 } else {
 330                         rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data);
 331                 }
 332         }
 333 }
 334
 335 /******************************************************************************
 336  * function:  This function reads specific bits from RF register
 337  * input:     net_device        *dev
 338  *            u32               reg_addr //target addr to be readback
 339  *            u32               bitmask  //taget bit pos to be readback
 340  * output:    none
 341  * return:    u32               data     //the readback register value
 342  * notice:
 343  *****************************************************************************/
 344 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 345                            u32 reg_addr, u32 bitmask)
 346 {
 347         u32 reg, bitshift;
 348         struct r8192_priv *priv = ieee80211_priv(dev);
 349
 350
 351         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 352                 return 0;
 353         if (priv->Rf_Mode == RF_OP_By_FW) {
 354                 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
 355                 udelay(200);
 356         } else {
 357                 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
 358         }
 359         bitshift =  rtl8192_CalculateBitShift(bitmask);
 360         reg = (reg & bitmask) >> bitshift;
 361         return reg;
 362
 363 }
 364
 365 /******************************************************************************
 366  * function:  We support firmware to execute RF-R/W.
 367  * input:     net_device        *dev
 368  *            RF90_RADIO_PATH_E eRFPath
 369  *            u32               offset
 370  * output:    none
 371  * return:    u32
 372  * notice:
 373  ****************************************************************************/
 374 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 375                               u32 offset)
 376 {
 377         u32             reg = 0;
 378         u32             data = 0;
 379         u8              time = 0;
 380         u32             tmp;
 381
 382         /* Firmware RF Write control.
 383          * We can not execute the scheme in the initial step.
 384          * Otherwise, RF-R/W will waste much time.
 385          * This is only for site survey. */
 386         /* 1. Read operation need not insert data. bit 0-11 */
 387         /* 2. Write RF register address. bit 12-19 */
 388         data |= ((offset&0xFF)<<12);
 389         /* 3. Write RF path.  bit 20-21 */
 390         data |= ((eRFPath&0x3)<<20);
 391         /* 4. Set RF read indicator. bit 22=0 */
 392         /* 5. Trigger Fw to operate the command. bit 31 */
 393         data |= 0x80000000;
 394         /* 6. We can not execute read operation if bit 31 is 1. */
 395         read_nic_dword(dev, QPNR, &tmp);
 396         while (tmp & 0x80000000) {
 397                 /* If FW can not finish RF-R/W for more than ?? times.
 398                    We must reset FW. */
 399                 if (time++ < 100) {
 400                         udelay(10);
 401                         read_nic_dword(dev, QPNR, &tmp);
 402                 } else {
 403                         break;
 404                 }
 405         }
 406         /* 7. Execute read operation. */
 407         write_nic_dword(dev, QPNR, data);
 408         /* 8. Check if firmware send back RF content. */
 409         read_nic_dword(dev, QPNR, &tmp);
 410         while (tmp & 0x80000000) {
 411                 /* If FW can not finish RF-R/W for more than ?? times.
 412                    We must reset FW. */
 413                 if (time++ < 100) {
 414                         udelay(10);
 415                         read_nic_dword(dev, QPNR, &tmp);
 416                 } else {
 417                         return 0;
 418                 }
 419         }
 420         read_nic_dword(dev, RF_DATA, &reg);
 421
 422         return reg;
 423 }
 424
 425 /******************************************************************************
 426  * function:  We support firmware to execute RF-R/W.
 427  * input:     net_device        *dev
 428  *            RF90_RADIO_PATH_E eRFPath
 429  *            u32               offset
 430  *            u32               data
 431  * output:    none
 432  * return:    none
 433  * notice:
 434  ****************************************************************************/
 435 static void phy_FwRFSerialWrite(struct net_device *dev,
 436                                 RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
 437 {
 438         u8      time = 0;
 439         u32     tmp;
 440
 441         /* Firmware RF Write control.
 442          * We can not execute the scheme in the initial step.
 443          * Otherwise, RF-R/W will waste much time.
 444          * This is only for site survey. */
 445
 446         /* 1. Set driver write bit and 12 bit data. bit 0-11 */
 447         /* 2. Write RF register address. bit 12-19 */
 448         data |= ((offset&0xFF)<<12);
 449         /* 3. Write RF path.  bit 20-21 */
 450         data |= ((eRFPath&0x3)<<20);
 451         /* 4. Set RF write indicator. bit 22=1 */
 452         data |= 0x400000;
 453         /* 5. Trigger Fw to operate the command. bit 31=1 */
 454         data |= 0x80000000;
 455
 456         /* 6. Write operation. We can not write if bit 31 is 1. */
 457         read_nic_dword(dev, QPNR, &tmp);
 458         while (tmp & 0x80000000) {
 459                 /* If FW can not finish RF-R/W for more than ?? times.
 460                    We must reset FW. */
 461                 if (time++ < 100) {
 462                         udelay(10);
 463                         read_nic_dword(dev, QPNR, &tmp);
 464                 } else {
 465                         break;
 466                 }
 467         }
 468         /* 7. No matter check bit. We always force the write.
 469            Because FW will not accept the command. */
 470         write_nic_dword(dev, QPNR, data);
 471         /* According to test, we must delay 20us to wait firmware
 472            to finish RF write operation. */
 473         /* We support delay in firmware side now. */
 474 }
 475
 476 /******************************************************************************
 477  * function:  This function reads BB parameters from header file we generate,
 478  *            and do register read/write
 479  * input:     net_device        *dev
 480  * output:    none
 481  * return:    none
 482  * notice:    BB parameters may change all the time, so please make
 483  *            sure it has been synced with the newest.
 484  *****************************************************************************/
 485 void rtl8192_phy_configmac(struct net_device *dev)
 486 {
 487         u32 dwArrayLen = 0, i;
 488         u32 *pdwArray = NULL;
 489         struct r8192_priv *priv = ieee80211_priv(dev);
 490
 491         if (priv->btxpowerdata_readfromEEPORM) {
 492                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
 493                 dwArrayLen = MACPHY_Array_PGLength;
 494                 pdwArray = rtl819XMACPHY_Array_PG;
 495
 496         } else {
 497                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
 498                 dwArrayLen = MACPHY_ArrayLength;
 499                 pdwArray = rtl819XMACPHY_Array;
 500         }
 501         for (i = 0; i < dwArrayLen; i = i+3) {
 502                 if (pdwArray[i] == 0x318)
 503                         pdwArray[i+2] = 0x00000800;
 504
 505                 RT_TRACE(COMP_DBG,
 506                          "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
 507                          pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 508                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
 509                                  pdwArray[i+2]);
 510         }
 511 }
 512
 513 /******************************************************************************
 514  * function:  This function does dirty work
 515  * input:     net_device        *dev
 516  *            u8                ConfigType
 517  * output:    none
 518  * return:    none
 519  * notice:    BB parameters may change all the time, so please make
 520  *            sure it has been synced with the newest.
 521  *****************************************************************************/
 522 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
 523 {
 524         u32 i;
 525
 526 #ifdef TO_DO_LIST
 527         u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
 528
 529         if (Adapter->bInHctTest) {
 530                 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
 531                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
 532                 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
 533                 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
 534         }
 535 #endif
 536         if (ConfigType == BaseBand_Config_PHY_REG) {
 537                 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
 538                         rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i],
 539                                          bMaskDWord,
 540                                          rtl819XPHY_REG_1T2RArray[i+1]);
 541                         RT_TRACE(COMP_DBG,
 542                                  "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
 543                                  i, rtl819XPHY_REG_1T2RArray[i],
 544                                  rtl819XPHY_REG_1T2RArray[i+1]);
 545                 }
 546         } else if (ConfigType == BaseBand_Config_AGC_TAB) {
 547                 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
 548                         rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i],
 549                                          bMaskDWord, rtl819XAGCTAB_Array[i+1]);
 550                         RT_TRACE(COMP_DBG,
 551                                  "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n",
 552                                  i, rtl819XAGCTAB_Array[i],
 553                                  rtl819XAGCTAB_Array[i+1]);
 554                 }
 555         }
 556 }
 557
 558 /******************************************************************************
 559  * function:  This function initializes Register definition offset for
 560  *            Radio Path A/B/C/D
 561  * input:     net_device        *dev
 562  * output:    none
 563  * return:    none
 564  * notice:    Initialization value here is constant and it should never
 565  *            be changed
 566  *****************************************************************************/
 567 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
 568 {
 569         struct r8192_priv *priv = ieee80211_priv(dev);
 570
 571         /* RF Interface Software Control */
 572         /* 16 LSBs if read 32-bit from 0x870 */
 573         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 574         /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 575         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 576         /* 16 LSBs if read 32-bit from 0x874 */
 577         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 578         /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
 579         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 580
 581         /* RF Interface Readback Value */
 582         /* 16 LSBs if read 32-bit from 0x8E0 */
 583         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 584         /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
 585         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 586         /* 16 LSBs if read 32-bit from 0x8E4 */
 587         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 588         /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
 589         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 590
 591         /* RF Interface Output (and Enable) */
 592         /* 16 LSBs if read 32-bit from 0x860 */
 593         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
 594         /* 16 LSBs if read 32-bit from 0x864 */
 595         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
 596         /* 16 LSBs if read 32-bit from 0x868 */
 597         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
 598         /* 16 LSBs if read 32-bit from 0x86C */
 599         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
 600
 601         /* RF Interface (Output and) Enable */
 602         /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 603         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
 604         /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 605         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
 606         /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
 607         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
 608         /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
 609         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
 610
 611         /* Addr of LSSI. Write RF register by driver */
 612         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
 613         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 614         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
 615         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 616
 617         /* RF parameter */
 618         /* BB Band Select */
 619         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 620         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 621         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 622         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 623
 624         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 625         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
 626         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
 627         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
 628         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
 629
 630         /* Tranceiver A~D HSSI Parameter-1 */
 631         /* wire control parameter1 */
 632         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
 633         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
 634         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
 635         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
 636
 637         /* Tranceiver A~D HSSI Parameter-2 */
 638         /* wire control parameter2 */
 639         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
 640         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
 641         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
 642         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
 643
 644         /* RF Switch Control */
 645         /* TR/Ant switch control */
 646         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 647         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 648         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 649         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 650
 651         /* AGC control 1 */
 652         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 653         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 654         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 655         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 656
 657         /* AGC control 2 */
 658         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 659         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 660         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 661         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 662
 663         /* RX AFE control 1 */
 664         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 665         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 666         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 667         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 668
 669         /* RX AFE control 1 */
 670         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 671         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 672         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 673         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 674
 675         /* Tx AFE control 1 */
 676         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 677         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 678         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 679         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 680
 681         /* Tx AFE control 2 */
 682         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 683         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 684         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 685         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 686
 687         /* Tranceiver LSSI Readback */
 688         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 689         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 690         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 691         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 692 }
 693
 694 /******************************************************************************
 695  * function:  This function is to write register and then readback to make
 696  *            sure whether BB and RF is OK
 697  * input:     net_device        *dev
 698  *            HW90_BLOCK_E      CheckBlock
 699  *            RF90_RADIO_PATH_E eRFPath  //only used when checkblock is
 700  *                                       //HW90_BLOCK_RF
 701  * output:    none
 702  * return:    return whether BB and RF is ok (0:OK, 1:Fail)
 703  * notice:    This function may be removed in the ASIC
 704  ******************************************************************************/
 705 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
 706                             RF90_RADIO_PATH_E eRFPath)
 707 {
 708         u8 ret = 0;
 709         u32 i, CheckTimes = 4, reg = 0;
 710         u32 WriteAddr[4];
 711         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
 712
 713         /* Initialize register address offset to be checked */
 714         WriteAddr[HW90_BLOCK_MAC] = 0x100;
 715         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
 716         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
 717         WriteAddr[HW90_BLOCK_RF] = 0x3;
 718         RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
 719         for (i = 0; i < CheckTimes; i++) {
 720
 721                 /* Write data to register and readback */
 722                 switch (CheckBlock) {
 723                 case HW90_BLOCK_MAC:
 724                         RT_TRACE(COMP_ERR,
 725                                  "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
 726                         break;
 727
 728                 case HW90_BLOCK_PHY0:
 729                 case HW90_BLOCK_PHY1:
 730                         write_nic_dword(dev, WriteAddr[CheckBlock],
 731                                         WriteData[i]);
 732                         read_nic_dword(dev, WriteAddr[CheckBlock], &reg);
 733                         break;
 734
 735                 case HW90_BLOCK_RF:
 736                         WriteData[i] &= 0xfff;
 737                         rtl8192_phy_SetRFReg(dev, eRFPath,
 738                                              WriteAddr[HW90_BLOCK_RF],
 739                                              bMask12Bits, WriteData[i]);
 740                         /* TODO: we should not delay for such a long time.
 741                            Ask SD3 */
 742                         usleep_range(1000, 1000);
 743                         reg = rtl8192_phy_QueryRFReg(dev, eRFPath,
 744                                                      WriteAddr[HW90_BLOCK_RF],
 745                                                      bMask12Bits);
 746                         usleep_range(1000, 1000);
 747                         break;
 748
 749                 default:
 750                         ret = 1;
 751                         break;
 752                 }
 753
 754
 755                 /* Check whether readback data is correct */
 756                 if (reg != WriteData[i]) {
 757                         RT_TRACE((COMP_PHY|COMP_ERR),
 758                                  "error reg: %x, WriteData: %x\n",
 759                                  reg, WriteData[i]);
 760                         ret = 1;
 761                         break;
 762                 }
 763         }
 764
 765         return ret;
 766 }
 767
 768 /******************************************************************************
 769  * function:  This function initializes BB&RF
 770  * input:     net_device        *dev
 771  * output:    none
 772  * return:    none
 773  * notice:    Initialization value may change all the time, so please make
 774  *            sure it has been synced with the newest.
 775  ******************************************************************************/
 776 static void rtl8192_BB_Config_ParaFile(struct net_device *dev)
 777 {
 778         struct r8192_priv *priv = ieee80211_priv(dev);
 779         u8 reg_u8 = 0, eCheckItem = 0, status = 0;
 780         u32 reg_u32 = 0;
 781
 782         /**************************************
 783          * <1> Initialize BaseBand
 784          *************************************/
 785
 786         /* --set BB Global Reset-- */
 787         read_nic_byte(dev, BB_GLOBAL_RESET, &reg_u8);
 788         write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
 789         mdelay(50);
 790         /* ---set BB reset Active--- */
 791         read_nic_dword(dev, CPU_GEN, &reg_u32);
 792         write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
 793
 794         /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
 795         /* TODO: this function should be removed on ASIC */
 796         for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0;
 797              eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
 798                 /* don't care RF path */
 799                 status = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem,
 800                                                   (RF90_RADIO_PATH_E)0);
 801                 if (status != 0) {
 802                         RT_TRACE((COMP_ERR | COMP_PHY),
 803                                  "PHY_RF8256_Config(): Check PHY%d Fail!!\n",
 804                                  eCheckItem-1);
 805                         return;
 806                 }
 807         }
 808         /* ---- Set CCK and OFDM Block "OFF"---- */
 809         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
 810         /* ----BB Register Initilazation---- */
 811         /* ==m==>Set PHY REG From Header<==m== */
 812         rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 813
 814         /* ----Set BB reset de-Active---- */
 815         read_nic_dword(dev, CPU_GEN, &reg_u32);
 816         write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
 817
 818         /* ----BB AGC table Initialization---- */
 819         /* ==m==>Set PHY REG From Header<==m== */
 820         rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
 821
 822         /* ----Enable XSTAL ---- */
 823         write_nic_byte_E(dev, 0x5e, 0x00);
 824         if (priv->card_8192_version == (u8)VERSION_819xU_A) {
 825                 /* Antenna gain offset from B/C/D to A */
 826                 reg_u32 = priv->AntennaTxPwDiff[1]<<4 |
 827                            priv->AntennaTxPwDiff[0];
 828                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
 829                                  reg_u32);
 830
 831                 /* XSTALLCap */
 832                 reg_u32 = priv->CrystalCap & 0xf;
 833                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
 834                                  reg_u32);
 835         }
 836
 837         /* Check if the CCK HighPower is turned ON.
 838            This is used to calculate PWDB. */
 839         priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
 840                                                      rFPGA0_XA_HSSIParameter2,
 841                                                      0x200);
 842 }
 843
 844 /******************************************************************************
 845  * function:  This function initializes BB&RF
 846  * input:     net_device        *dev
 847  * output:    none
 848  * return:    none
 849  * notice:    Initialization value may change all the time, so please make
 850  *            sure it has been synced with the newest.
 851  *****************************************************************************/
 852 void rtl8192_BBConfig(struct net_device *dev)
 853 {
 854         rtl8192_InitBBRFRegDef(dev);
 855         /* config BB&RF. As hardCode based initialization has not been well
 856          * implemented, so use file first.
 857          * FIXME: should implement it for hardcode? */
 858         rtl8192_BB_Config_ParaFile(dev);
 859 }
 860
 861
 862 /******************************************************************************
 863  * function:  This function obtains the initialization value of Tx power Level
 864  *            offset
 865  * input:     net_device        *dev
 866  * output:    none
 867  * return:    none
 868  *****************************************************************************/
 869 void rtl8192_phy_getTxPower(struct net_device *dev)
 870 {
 871         struct r8192_priv *priv = ieee80211_priv(dev);
 872         u8 tmp;
 873
 874         read_nic_dword(dev, rTxAGC_Rate18_06,
 875                        &priv->MCSTxPowerLevelOriginalOffset[0]);
 876         read_nic_dword(dev, rTxAGC_Rate54_24,
 877                        &priv->MCSTxPowerLevelOriginalOffset[1]);
 878         read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
 879                        &priv->MCSTxPowerLevelOriginalOffset[2]);
 880         read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
 881                        &priv->MCSTxPowerLevelOriginalOffset[3]);
 882         read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
 883                        &priv->MCSTxPowerLevelOriginalOffset[4]);
 884         read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
 885                        &priv->MCSTxPowerLevelOriginalOffset[5]);
 886
 887         /* Read rx initial gain */
 888         read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
 889         read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
 890         read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
 891         read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
 892         RT_TRACE(COMP_INIT,
 893                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
 894                  priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
 895                  priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 896
 897         /* Read framesync */
 898         read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
 899         read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
 900         priv->framesyncC34 = tmp;
 901         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
 902                 rOFDM0_RxDetector3, priv->framesync);
 903
 904         /* Read SIFS (save the value read fome MACPHY_REG.txt) */
 905         read_nic_word(dev, SIFS, &priv->SifsTime);
 906 }
 907
 908 /******************************************************************************
 909  * function:  This function sets the initialization value of Tx power Level
 910  *            offset
 911  * input:     net_device        *dev
 912  *            u8                channel
 913  * output:    none
 914  * return:    none
 915  ******************************************************************************/
 916 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 917 {
 918         struct r8192_priv *priv = ieee80211_priv(dev);
 919         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 920         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 921
 922         switch (priv->rf_chip) {
 923         case RF_8256:
 924                 /* need further implement */
 925                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
 926                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 927                 break;
 928         default:
 929                 RT_TRACE((COMP_PHY|COMP_ERR),
 930                          "error RF chipID(8225 or 8258) in function %s()\n",
 931                          __func__);
 932                 break;
 933         }
 934 }
 935
 936 /******************************************************************************
 937  * function:  This function checks Rf chip to do RF config
 938  * input:     net_device        *dev
 939  * output:    none
 940  * return:    only 8256 is supported
 941  ******************************************************************************/
 942 void rtl8192_phy_RFConfig(struct net_device *dev)
 943 {
 944         struct r8192_priv *priv = ieee80211_priv(dev);
 945
 946         switch (priv->rf_chip) {
 947         case RF_8256:
 948                 PHY_RF8256_Config(dev);
 949                 break;
 950         default:
 951                 RT_TRACE(COMP_ERR, "error chip id\n");
 952                 break;
 953         }
 954 }
 955
 956 /******************************************************************************
 957  * function:  This function updates Initial gain
 958  * input:     net_device        *dev
 959  * output:    none
 960  * return:    As Windows has not implemented this, wait for complement
 961  ******************************************************************************/
 962 void rtl8192_phy_updateInitGain(struct net_device *dev)
 963 {
 964 }
 965
 966 /******************************************************************************
 967  * function:  This function read RF parameters from general head file,
 968  *            and do RF 3-wire
 969  * input:     net_device        *dev
 970  *            RF90_RADIO_PATH_E eRFPath
 971  * output:    none
 972  * return:    return code show if RF configuration is successful(0:pass, 1:fail)
 973  * notice:    Delay may be required for RF configuration
 974  *****************************************************************************/
 975 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
 976                                       RF90_RADIO_PATH_E eRFPath)
 977 {
 978
 979         int i;
 980
 981         switch (eRFPath) {
 982         case RF90_PATH_A:
 983                 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
 984
 985                         if (rtl819XRadioA_Array[i] == 0xfe) {
 986                                 mdelay(100);
 987                                 continue;
 988                         }
 989                         rtl8192_phy_SetRFReg(dev, eRFPath,
 990                                              rtl819XRadioA_Array[i],
 991                                              bMask12Bits,
 992                                              rtl819XRadioA_Array[i+1]);
 993                         mdelay(1);
 994
 995                 }
 996                 break;
 997         case RF90_PATH_B:
 998                 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
 999
1000                         if (rtl819XRadioB_Array[i] == 0xfe) {
1001                                 mdelay(100);
1002                                 continue;
1003                         }
1004                         rtl8192_phy_SetRFReg(dev, eRFPath,
1005                                              rtl819XRadioB_Array[i],
1006                                              bMask12Bits,
1007                                              rtl819XRadioB_Array[i+1]);
1008                         mdelay(1);
1009
1010                 }
1011                 break;
1012         case RF90_PATH_C:
1013                 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
1014
1015                         if (rtl819XRadioC_Array[i] == 0xfe) {
1016                                 mdelay(100);
1017                                 continue;
1018                         }
1019                         rtl8192_phy_SetRFReg(dev, eRFPath,
1020                                              rtl819XRadioC_Array[i],
1021                                              bMask12Bits,
1022                                              rtl819XRadioC_Array[i+1]);
1023                         mdelay(1);
1024
1025                 }
1026                 break;
1027         case RF90_PATH_D:
1028                 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
1029
1030                         if (rtl819XRadioD_Array[i] == 0xfe) {
1031                                 mdelay(100);
1032                                 continue;
1033                         }
1034                         rtl8192_phy_SetRFReg(dev, eRFPath,
1035                                              rtl819XRadioD_Array[i],
1036                                              bMask12Bits,
1037                                              rtl819XRadioD_Array[i+1]);
1038                         mdelay(1);
1039
1040                 }
1041                 break;
1042         default:
1043                 break;
1044         }
1045
1046         return 0;
1047
1048 }
1049
1050 /******************************************************************************
1051  * function:  This function sets Tx Power of the channel
1052  * input:     net_device        *dev
1053  *            u8                channel
1054  * output:    none
1055  * return:    none
1056  * notice:
1057  ******************************************************************************/
1058 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1059 {
1060         struct r8192_priv *priv = ieee80211_priv(dev);
1061         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
1062         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1063
1064         switch (priv->rf_chip) {
1065         case RF_8225:
1066 #ifdef TO_DO_LIST
1067                 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1068                 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1069 #endif
1070                 break;
1071
1072         case RF_8256:
1073                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1074                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1075                 break;
1076
1077         case RF_8258:
1078                 break;
1079         default:
1080                 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
1081                 break;
1082         }
1083 }
1084
1085 /******************************************************************************
1086  * function:  This function sets RF state on or off
1087  * input:     net_device         *dev
1088  *            RT_RF_POWER_STATE  eRFPowerState  //Power State to set
1089  * output:    none
1090  * return:    none
1091  * notice:
1092  *****************************************************************************/
1093 bool rtl8192_SetRFPowerState(struct net_device *dev,
1094                              RT_RF_POWER_STATE eRFPowerState)
1095 {
1096         bool                            bResult = true;
1097         struct r8192_priv *priv = ieee80211_priv(dev);
1098
1099         if (eRFPowerState == priv->ieee80211->eRFPowerState)
1100                 return false;
1101
1102         if (priv->SetRFPowerStateInProgress)
1103                 return false;
1104
1105         priv->SetRFPowerStateInProgress = true;
1106
1107         switch (priv->rf_chip) {
1108         case RF_8256:
1109                 switch (eRFPowerState) {
1110                 case eRfOn:
1111                         /* RF-A, RF-B */
1112                         /* enable RF-Chip A/B - 0x860[4] */
1113                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1114                                          0x1);
1115                         /* analog to digital on - 0x88c[9:8] */
1116                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1117                                          0x3);
1118                         /* digital to analog on - 0x880[4:3] */
1119                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1120                                          0x3);
1121                         /* rx antenna on - 0xc04[1:0] */
1122                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1123                         /* rx antenna on - 0xd04[1:0] */
1124                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1125                         /* analog to digital part2 on - 0x880[6:5] */
1126                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1127                                          0x3);
1128
1129                         break;
1130
1131                 case eRfSleep:
1132
1133                         break;
1134
1135                 case eRfOff:
1136                         /* RF-A, RF-B */
1137                         /* disable RF-Chip A/B - 0x860[4] */
1138                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1139                                          0x0);
1140                         /* analog to digital off, for power save */
1141                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1142                                          0x0); /* 0x88c[11:8] */
1143                         /* digital to analog off, for power save - 0x880[4:3] */
1144                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1145                                          0x0);
1146                         /* rx antenna off - 0xc04[3:0] */
1147                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1148                         /* rx antenna off - 0xd04[3:0] */
1149                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1150                         /* analog to digital part2 off, for power save */
1151                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1152                                          0x0); /* 0x880[6:5] */
1153
1154                         break;
1155
1156                 default:
1157                         bResult = false;
1158                         RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1159                                  __func__, eRFPowerState);
1160                         break;
1161                 }
1162                 break;
1163         default:
1164                 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1165                 break;
1166         }
1167 #ifdef TO_DO_LIST
1168         if (bResult) {
1169                 /* Update current RF state variable. */
1170                 pHalData->eRFPowerState = eRFPowerState;
1171                 switch (pHalData->RFChipID) {
1172                 case RF_8256:
1173                         switch (pHalData->eRFPowerState) {
1174                         case eRfOff:
1175                                 /* If Rf off reason is from IPS,
1176                                    LED should blink with no link */
1177                                 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS)
1178                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1179                                 else
1180                                         /* Turn off LED if RF is not ON. */
1181                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1182                                 break;
1183
1184                         case eRfOn:
1185                                 /* Turn on RF we are still linked, which might
1186                                    happen when we quickly turn off and on HW RF.
1187                                  */
1188                                 if (pMgntInfo->bMediaConnect)
1189                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1190                                 else
1191                                         /* Turn off LED if RF is not ON. */
1192                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1193                                 break;
1194
1195                         default:
1196                                 break;
1197                         }
1198                         break;
1199
1200                 default:
1201                         RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n",
1202                                  __func__);
1203                         break;
1204                 }
1205
1206         }
1207 #endif
1208         priv->SetRFPowerStateInProgress = false;
1209
1210         return bResult;
1211 }
1212
1213 /******************************************************************************
1214  * function:  This function sets command table variable (struct SwChnlCmd).
1215  * input:     SwChnlCmd      *CmdTable    //table to be set
1216  *            u32            CmdTableIdx  //variable index in table to be set
1217  *            u32            CmdTableSz   //table size
1218  *            SwChnlCmdID    CmdID        //command ID to set
1219  *            u32            Para1
1220  *            u32            Para2
1221  *            u32            msDelay
1222  * output:
1223  * return:    true if finished, false otherwise
1224  * notice:
1225  ******************************************************************************/
1226 static u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx,
1227                                         u32 CmdTableSz, SwChnlCmdID CmdID,
1228                                         u32 Para1, u32 Para2, u32 msDelay)
1229 {
1230         SwChnlCmd *pCmd;
1231
1232         if (CmdTable == NULL) {
1233                 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
1234                 return false;
1235         }
1236         if (CmdTableIdx >= CmdTableSz) {
1237                 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1238                          __func__, CmdTableIdx, CmdTableSz);
1239                 return false;
1240         }
1241
1242         pCmd = CmdTable + CmdTableIdx;
1243         pCmd->CmdID = CmdID;
1244         pCmd->Para1 = Para1;
1245         pCmd->Para2 = Para2;
1246         pCmd->msDelay = msDelay;
1247
1248         return true;
1249 }
1250
1251 /******************************************************************************
1252  * function:  This function sets channel step by step
1253  * input:     net_device        *dev
1254  *            u8                channel
1255  *            u8                *stage   //3 stages
1256  *            u8                *step
1257  *            u32               *delay   //whether need to delay
1258  * output:    store new stage, step and delay for next step
1259  *            (combine with function above)
1260  * return:    true if finished, false otherwise
1261  * notice:    Wait for simpler function to replace it
1262  *****************************************************************************/
1263 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
1264                                        u8 *stage, u8 *step, u32 *delay)
1265 {
1266         struct r8192_priv *priv = ieee80211_priv(dev);
1267         SwChnlCmd       PreCommonCmd[MAX_PRECMD_CNT];
1268         u32             PreCommonCmdCnt;
1269         SwChnlCmd       PostCommonCmd[MAX_POSTCMD_CNT];
1270         u32             PostCommonCmdCnt;
1271         SwChnlCmd       RfDependCmd[MAX_RFDEPENDCMD_CNT];
1272         u32             RfDependCmdCnt;
1273         SwChnlCmd       *CurrentCmd = NULL;
1274         u8              eRFPath;
1275
1276         RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
1277                  __func__, *stage, *step, channel);
1278         if (!IsLegalChannel(priv->ieee80211, channel)) {
1279                 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
1280                 /* return true to tell upper caller function this channel
1281                    setting is finished! Or it will in while loop. */
1282                 return true;
1283         }
1284         /* FIXME: need to check whether channel is legal or not here */
1285
1286
1287         /* <1> Fill up pre common command. */
1288         PreCommonCmdCnt = 0;
1289         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1290                                       MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
1291                                       0, 0, 0);
1292         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1293                                       MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
1294
1295         /* <2> Fill up post common command. */
1296         PostCommonCmdCnt = 0;
1297
1298         rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1299                                       MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
1300
1301         /* <3> Fill up RF dependent command. */
1302         RfDependCmdCnt = 0;
1303         switch (priv->rf_chip) {
1304         case RF_8225:
1305                 if (!(channel >= 1 && channel <= 14)) {
1306                         RT_TRACE(COMP_ERR,
1307                                  "illegal channel for Zebra 8225: %d\n",
1308                                  channel);
1309                         return true;
1310                 }
1311                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1312                                               MAX_RFDEPENDCMD_CNT,
1313                                               CmdID_RF_WriteReg,
1314                                               rZebra1_Channel,
1315                                               RF_CHANNEL_TABLE_ZEBRA[channel],
1316                                               10);
1317                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1318                                               MAX_RFDEPENDCMD_CNT,
1319                                               CmdID_End, 0, 0, 0);
1320                 break;
1321
1322         case RF_8256:
1323                 /* TEST!! This is not the table for 8256!! */
1324                 if (!(channel >= 1 && channel <= 14)) {
1325                         RT_TRACE(COMP_ERR,
1326                                  "illegal channel for Zebra 8256: %d\n",
1327                                  channel);
1328                         return true;
1329                 }
1330                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1331                                               MAX_RFDEPENDCMD_CNT,
1332                                               CmdID_RF_WriteReg,
1333                                               rZebra1_Channel, channel, 10);
1334                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1335                                               MAX_RFDEPENDCMD_CNT,
1336                                               CmdID_End, 0, 0, 0);
1337                 break;
1338
1339         case RF_8258:
1340                 break;
1341
1342         default:
1343                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1344                 return true;
1345         }
1346
1347
1348         do {
1349                 switch (*stage) {
1350                 case 0:
1351                         CurrentCmd = &PreCommonCmd[*step];
1352                         break;
1353                 case 1:
1354                         CurrentCmd = &RfDependCmd[*step];
1355                         break;
1356                 case 2:
1357                         CurrentCmd = &PostCommonCmd[*step];
1358                         break;
1359                 }
1360
1361                 if (CurrentCmd->CmdID == CmdID_End) {
1362                         if ((*stage) == 2) {
1363                                 (*delay) = CurrentCmd->msDelay;
1364                                 return true;
1365                         }
1366                         (*stage)++;
1367                         (*step) = 0;
1368                         continue;
1369                 }
1370
1371                 switch (CurrentCmd->CmdID) {
1372                 case CmdID_SetTxPowerLevel:
1373                         if (priv->card_8192_version == (u8)VERSION_819xU_A)
1374                                 /* consider it later! */
1375                                 rtl8192_SetTxPowerLevel(dev, channel);
1376                         break;
1377                 case CmdID_WritePortUlong:
1378                         write_nic_dword(dev, CurrentCmd->Para1,
1379                                         CurrentCmd->Para2);
1380                         break;
1381                 case CmdID_WritePortUshort:
1382                         write_nic_word(dev, CurrentCmd->Para1,
1383                                        (u16)CurrentCmd->Para2);
1384                         break;
1385                 case CmdID_WritePortUchar:
1386                         write_nic_byte(dev, CurrentCmd->Para1,
1387                                        (u8)CurrentCmd->Para2);
1388                         break;
1389                 case CmdID_RF_WriteReg:
1390                         for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
1391                                 rtl8192_phy_SetRFReg(dev,
1392                                                      (RF90_RADIO_PATH_E)eRFPath,
1393                                                      CurrentCmd->Para1,
1394                                                      bZebra1_ChannelNum,
1395                                                      CurrentCmd->Para2);
1396                         }
1397                         break;
1398                 default:
1399                         break;
1400                 }
1401
1402                 break;
1403         } while (true);
1404
1405         (*delay) = CurrentCmd->msDelay;
1406         (*step)++;
1407         return false;
1408 }
1409
1410 /******************************************************************************
1411  * function:  This function does actually set channel work
1412  * input:     net_device        *dev
1413  *            u8                channel
1414  * output:    none
1415  * return:    none
1416  * notice:    We should not call this function directly
1417  *****************************************************************************/
1418 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1419 {
1420         struct r8192_priv *priv = ieee80211_priv(dev);
1421         u32     delay = 0;
1422
1423         while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1424                                              &priv->SwChnlStep, &delay)) {
1425                 if (!priv->up)
1426                         break;
1427         }
1428 }
1429
1430 /******************************************************************************
1431  * function:  Callback routine of the work item for switch channel.
1432  * input:     net_device        *dev
1433  *
1434  * output:    none
1435  * return:    none
1436  *****************************************************************************/
1437 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1438 {
1439
1440         struct r8192_priv *priv = ieee80211_priv(dev);
1441
1442         RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1443                  priv->chan);
1444
1445
1446         rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1447
1448         RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1449 }
1450
1451 /******************************************************************************
1452  * function:  This function scheduled actual work item to set channel
1453  * input:     net_device        *dev
1454  *            u8                channel   //channel to set
1455  * output:    none
1456  * return:    return code show if workitem is scheduled (1:pass, 0:fail)
1457  * notice:    Delay may be required for RF configuration
1458  ******************************************************************************/
1459 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1460 {
1461         struct r8192_priv *priv = ieee80211_priv(dev);
1462
1463         RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1464                  priv->SwChnlInProgress);
1465         if (!priv->up)
1466                 return false;
1467         if (priv->SwChnlInProgress)
1468                 return false;
1469
1470         /* -------------------------------------------- */
1471         switch (priv->ieee80211->mode) {
1472         case WIRELESS_MODE_A:
1473         case WIRELESS_MODE_N_5G:
1474                 if (channel <= 14) {
1475                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1476                         return false;
1477                 }
1478                 break;
1479         case WIRELESS_MODE_B:
1480                 if (channel > 14) {
1481                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1482                         return false;
1483                 }
1484                 break;
1485         case WIRELESS_MODE_G:
1486         case WIRELESS_MODE_N_24G:
1487                 if (channel > 14) {
1488                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1489                         return false;
1490                 }
1491                 break;
1492         }
1493         /* -------------------------------------------- */
1494
1495         priv->SwChnlInProgress = true;
1496         if (channel == 0)
1497                 channel = 1;
1498
1499         priv->chan = channel;
1500
1501         priv->SwChnlStage = 0;
1502         priv->SwChnlStep = 0;
1503         if (priv->up)
1504                 rtl8192_SwChnl_WorkItem(dev);
1505
1506         priv->SwChnlInProgress = false;
1507         return true;
1508 }
1509
1510 /******************************************************************************
1511  * function:  Callback routine of the work item for set bandwidth mode.
1512  * input:     net_device         *dev
1513  * output:    none
1514  * return:    none
1515  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1516  *            test whether current work in the queue or not.//do I?
1517  *****************************************************************************/
1518 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1519 {
1520
1521         struct r8192_priv *priv = ieee80211_priv(dev);
1522         u8 regBwOpMode;
1523
1524         RT_TRACE(COMP_SWBW, "%s()  Switch to %s bandwidth\n", __func__,
1525                  priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1526
1527
1528         if (priv->rf_chip == RF_PSEUDO_11N) {
1529                 priv->SetBWModeInProgress = false;
1530                 return;
1531         }
1532
1533         /* <1> Set MAC register */
1534         read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
1535
1536         switch (priv->CurrentChannelBW) {
1537         case HT_CHANNEL_WIDTH_20:
1538                 regBwOpMode |= BW_OPMODE_20MHZ;
1539                 /* We have not verify whether this register works */
1540                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1541                 break;
1542
1543         case HT_CHANNEL_WIDTH_20_40:
1544                 regBwOpMode &= ~BW_OPMODE_20MHZ;
1545                 /* We have not verify whether this register works */
1546                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1547                 break;
1548
1549         default:
1550                 RT_TRACE(COMP_ERR,
1551                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1552                          priv->CurrentChannelBW);
1553                 break;
1554         }
1555
1556         /* <2> Set PHY related register */
1557         switch (priv->CurrentChannelBW) {
1558         case HT_CHANNEL_WIDTH_20:
1559                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1560                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1561                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1562                                  0x00100000, 1);
1563
1564                 /* Correct the tx power for CCK rate in 20M. */
1565                 priv->cck_present_attentuation =
1566                         priv->cck_present_attentuation_20Mdefault +
1567                         priv->cck_present_attentuation_difference;
1568
1569                 if (priv->cck_present_attentuation > 22)
1570                         priv->cck_present_attentuation = 22;
1571                 if (priv->cck_present_attentuation < 0)
1572                         priv->cck_present_attentuation = 0;
1573                 RT_TRACE(COMP_INIT,
1574                          "20M, pHalData->CCKPresentAttentuation = %d\n",
1575                          priv->cck_present_attentuation);
1576
1577                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1578                         priv->bcck_in_ch14 = true;
1579                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1580                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1581                         priv->bcck_in_ch14 = false;
1582                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1583                 } else {
1584                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1585                 }
1586
1587                 break;
1588         case HT_CHANNEL_WIDTH_20_40:
1589                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1590                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1591                 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1592                                  priv->nCur40MhzPrimeSC>>1);
1593                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1594                 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1595                                  priv->nCur40MhzPrimeSC);
1596                 priv->cck_present_attentuation =
1597                         priv->cck_present_attentuation_40Mdefault +
1598                         priv->cck_present_attentuation_difference;
1599
1600                 if (priv->cck_present_attentuation > 22)
1601                         priv->cck_present_attentuation = 22;
1602                 if (priv->cck_present_attentuation < 0)
1603                         priv->cck_present_attentuation = 0;
1604
1605                 RT_TRACE(COMP_INIT,
1606                          "40M, pHalData->CCKPresentAttentuation = %d\n",
1607                          priv->cck_present_attentuation);
1608                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1609                         priv->bcck_in_ch14 = true;
1610                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1611                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1612                         priv->bcck_in_ch14 = false;
1613                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1614                 } else {
1615                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1616                 }
1617
1618                 break;
1619         default:
1620                 RT_TRACE(COMP_ERR,
1621                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1622                          priv->CurrentChannelBW);
1623                 break;
1624
1625         }
1626         /* Skip over setting of J-mode in BB register here.
1627            Default value is "None J mode". */
1628
1629         /* <3> Set RF related register */
1630         switch (priv->rf_chip) {
1631         case RF_8225:
1632 #ifdef TO_DO_LIST
1633                 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1634 #endif
1635                 break;
1636
1637         case RF_8256:
1638                 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1639                 break;
1640
1641         case RF_8258:
1642                 break;
1643
1644         case RF_PSEUDO_11N:
1645                 break;
1646
1647         default:
1648                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1649                 break;
1650         }
1651         priv->SetBWModeInProgress = false;
1652
1653         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1654                  atomic_read(&priv->ieee80211->atm_swbw));
1655 }
1656
1657 /******************************************************************************
1658  * function:  This function schedules bandwidth switch work.
1659  * input:     struct net_deviceq   *dev
1660  *            HT_CHANNEL_WIDTH     bandwidth  //20M or 40M
1661  *            HT_EXTCHNL_OFFSET    offset     //Upper, Lower, or Don't care
1662  * output:    none
1663  * return:    none
1664  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1665  *            test whether current work in the queue or not.//do I?
1666  *****************************************************************************/
1667 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
1668                        HT_EXTCHNL_OFFSET offset)
1669 {
1670         struct r8192_priv *priv = ieee80211_priv(dev);
1671
1672         if (priv->SetBWModeInProgress)
1673                 return;
1674         priv->SetBWModeInProgress = true;
1675
1676         priv->CurrentChannelBW = bandwidth;
1677
1678         if (offset == HT_EXTCHNL_OFFSET_LOWER)
1679                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1680         else if (offset == HT_EXTCHNL_OFFSET_UPPER)
1681                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1682         else
1683                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1684
1685         rtl8192_SetBWModeWorkItem(dev);
1686
1687 }
1688
1689 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1690 {
1691         struct r8192_priv *priv = ieee80211_priv(dev);
1692
1693         priv->InitialGainOperateType = Operation;
1694
1695         if (priv->up)
1696                 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
1697 }
1698
1699 void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1700 {
1701         struct delayed_work *dwork = container_of(work, struct delayed_work,
1702                                                   work);
1703         struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1704                                                initialgain_operate_wq);
1705         struct net_device *dev = priv->ieee80211->dev;
1706 #define SCAN_RX_INITIAL_GAIN    0x17
1707 #define POWER_DETECTION_TH      0x08
1708         u32     bitmask;
1709         u8      initial_gain;
1710         u8      Operation;
1711
1712         Operation = priv->InitialGainOperateType;
1713
1714         switch (Operation) {
1715         case IG_Backup:
1716                 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1717                 initial_gain = SCAN_RX_INITIAL_GAIN;
1718                 bitmask = bMaskByte0;
1719                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1720                         /* FW DIG OFF */
1721                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1722                 priv->initgain_backup.xaagccore1 =
1723                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1724                 priv->initgain_backup.xbagccore1 =
1725                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1726                 priv->initgain_backup.xcagccore1 =
1727                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1728                 priv->initgain_backup.xdagccore1 =
1729                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1730                 bitmask = bMaskByte2;
1731                 priv->initgain_backup.cca =
1732                         (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1733
1734                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1735                          priv->initgain_backup.xaagccore1);
1736                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1737                          priv->initgain_backup.xbagccore1);
1738                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1739                          priv->initgain_backup.xcagccore1);
1740                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1741                          priv->initgain_backup.xdagccore1);
1742                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1743                          priv->initgain_backup.cca);
1744
1745                 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1746                          initial_gain);
1747                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1748                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1749                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1750                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1751                 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1752                          POWER_DETECTION_TH);
1753                 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1754                 break;
1755         case IG_Restore:
1756                 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1757                 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1758                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1759                         /* FW DIG OFF */
1760                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1761
1762                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1763                                  (u32)priv->initgain_backup.xaagccore1);
1764                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1765                                  (u32)priv->initgain_backup.xbagccore1);
1766                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1767                                  (u32)priv->initgain_backup.xcagccore1);
1768                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1769                                  (u32)priv->initgain_backup.xdagccore1);
1770                 bitmask  = bMaskByte2;
1771                 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1772                                  (u32)priv->initgain_backup.cca);
1773
1774                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1775                          priv->initgain_backup.xaagccore1);
1776                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1777                          priv->initgain_backup.xbagccore1);
1778                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1779                          priv->initgain_backup.xcagccore1);
1780                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1781                          priv->initgain_backup.xdagccore1);
1782                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1783                          priv->initgain_backup.cca);
1784
1785                 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
1786
1787                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1788                         /* FW DIG ON */
1789                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1790                 break;
1791         default:
1792                 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1793                 break;
1794         }
1795 }