kernel/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * Based on the r8180 driver, which is:
   5  * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * The full GNU General Public License is included in this distribution in the
  16  * file called LICENSE.
  17  *
  18  * Contact Information:
  19  * wlanfae <wlanfae@realtek.com>
  20 ******************************************************************************/
  21 #include "rtl_core.h"
  22 #include "r8192E_phy.h"
  23 #include "r8192E_phyreg.h"
  24 #include "r8190P_rtl8256.h"
  25 #include "r8192E_cmdpkt.h"
  26 #include "rtl_dm.h"
  27 #include "rtl_wx.h"
  28
  29 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
  30                              EDCAPARA_VO};
  31
  32 void rtl92e_start_beacon(struct net_device *dev)
  33 {
  34         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
  35         struct rtllib_network *net = &priv->rtllib->current_network;
  36         u16 BcnTimeCfg = 0;
  37         u16 BcnCW = 6;
  38         u16 BcnIFS = 0xf;
  39
  40         rtl92e_irq_disable(dev);
  41
  42         rtl92e_writew(dev, ATIMWND, 2);
  43
  44         rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
  45         rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
  46         rtl92e_writew(dev, BCN_DMATIME, 256);
  47
  48         rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
  49
  50         BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
  51         BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
  52         rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
  53         rtl92e_irq_enable(dev);
  54 }
  55
  56 static void _rtl92e_update_msr(struct net_device *dev)
  57 {
  58         struct r8192_priv *priv = rtllib_priv(dev);
  59         u8 msr;
  60         enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
  61
  62         msr  = rtl92e_readb(dev, MSR);
  63         msr &= ~MSR_LINK_MASK;
  64
  65         switch (priv->rtllib->iw_mode) {
  66         case IW_MODE_INFRA:
  67                 if (priv->rtllib->state == RTLLIB_LINKED)
  68                         msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
  69                 else
  70                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  71                 LedAction = LED_CTL_LINK;
  72                 break;
  73         case IW_MODE_ADHOC:
  74                 if (priv->rtllib->state == RTLLIB_LINKED)
  75                         msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
  76                 else
  77                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  78                 break;
  79         case IW_MODE_MASTER:
  80                 if (priv->rtllib->state == RTLLIB_LINKED)
  81                         msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
  82                 else
  83                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  84                 break;
  85         default:
  86                 break;
  87         }
  88
  89         rtl92e_writeb(dev, MSR, msr);
  90         if (priv->rtllib->LedControlHandler)
  91                 priv->rtllib->LedControlHandler(dev, LedAction);
  92 }
  93
  94 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val)
  95 {
  96         struct r8192_priv *priv = rtllib_priv(dev);
  97
  98         switch (variable) {
  99         case HW_VAR_BSSID:
 100                 rtl92e_writel(dev, BSSIDR, ((u32 *)(val))[0]);
 101                 rtl92e_writew(dev, BSSIDR+2, ((u16 *)(val+2))[0]);
 102                 break;
 103
 104         case HW_VAR_MEDIA_STATUS:
 105         {
 106                 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
 107                 u8 btMsr = rtl92e_readb(dev, MSR);
 108
 109                 btMsr &= 0xfc;
 110
 111                 switch (OpMode) {
 112                 case RT_OP_MODE_INFRASTRUCTURE:
 113                         btMsr |= MSR_INFRA;
 114                         break;
 115
 116                 case RT_OP_MODE_IBSS:
 117                         btMsr |= MSR_ADHOC;
 118                         break;
 119
 120                 case RT_OP_MODE_AP:
 121                         btMsr |= MSR_AP;
 122                         break;
 123
 124                 default:
 125                         btMsr |= MSR_NOLINK;
 126                         break;
 127                 }
 128
 129                 rtl92e_writeb(dev, MSR, btMsr);
 130
 131         }
 132         break;
 133
 134         case HW_VAR_CECHK_BSSID:
 135         {
 136                 u32     RegRCR, Type;
 137
 138                 Type = ((u8 *)(val))[0];
 139                 RegRCR = rtl92e_readl(dev, RCR);
 140                 priv->ReceiveConfig = RegRCR;
 141
 142                 if (Type == true)
 143                         RegRCR |= (RCR_CBSSID);
 144                 else if (Type == false)
 145                         RegRCR &= (~RCR_CBSSID);
 146
 147                 rtl92e_writel(dev, RCR, RegRCR);
 148                 priv->ReceiveConfig = RegRCR;
 149
 150         }
 151         break;
 152
 153         case HW_VAR_SLOT_TIME:
 154
 155                 priv->slot_time = val[0];
 156                 rtl92e_writeb(dev, SLOT_TIME, val[0]);
 157
 158                 break;
 159
 160         case HW_VAR_ACK_PREAMBLE:
 161         {
 162                 u32 regTmp;
 163
 164                 priv->short_preamble = (bool)(*(u8 *)val);
 165                 regTmp = priv->basic_rate;
 166                 if (priv->short_preamble)
 167                         regTmp |= BRSR_AckShortPmb;
 168                 rtl92e_writel(dev, RRSR, regTmp);
 169                 break;
 170         }
 171
 172         case HW_VAR_CPU_RST:
 173                 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]);
 174                 break;
 175
 176         case HW_VAR_AC_PARAM:
 177         {
 178                 u8      pAcParam = *((u8 *)val);
 179                 u32     eACI = pAcParam;
 180                 u8              u1bAIFS;
 181                 u32             u4bAcParam;
 182                 u8 mode = priv->rtllib->mode;
 183                 struct rtllib_qos_parameters *qop =
 184                          &priv->rtllib->current_network.qos_data.parameters;
 185
 186                 u1bAIFS = qop->aifs[pAcParam] *
 187                           ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
 188
 189                 rtl92e_dm_init_edca_turbo(dev);
 190
 191                 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
 192                               AC_PARAM_TXOP_LIMIT_OFFSET) |
 193                                 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
 194                                  AC_PARAM_ECW_MAX_OFFSET) |
 195                                 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
 196                                  AC_PARAM_ECW_MIN_OFFSET) |
 197                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
 198
 199                 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
 200                          __func__, eACI, u4bAcParam);
 201                 switch (eACI) {
 202                 case AC1_BK:
 203                         rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam);
 204                         break;
 205
 206                 case AC0_BE:
 207                         rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam);
 208                         break;
 209
 210                 case AC2_VI:
 211                         rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam);
 212                         break;
 213
 214                 case AC3_VO:
 215                         rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam);
 216                         break;
 217
 218                 default:
 219                         netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
 220                                     eACI);
 221                         break;
 222                 }
 223                 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
 224                                               (u8 *)(&pAcParam));
 225                 break;
 226         }
 227
 228         case HW_VAR_ACM_CTRL:
 229         {
 230                 struct rtllib_qos_parameters *qos_parameters =
 231                          &priv->rtllib->current_network.qos_data.parameters;
 232                 u8 pAcParam = *((u8 *)val);
 233                 u32 eACI = pAcParam;
 234                 union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
 235                                               (qos_parameters->aifs[0]);
 236                 u8 acm = pAciAifsn->f.acm;
 237                 u8 AcmCtrl = rtl92e_readb(dev, AcmHwCtrl);
 238
 239                 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
 240                          __func__, eACI);
 241                 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
 242
 243                 if (acm) {
 244                         switch (eACI) {
 245                         case AC0_BE:
 246                                 AcmCtrl |= AcmHw_BeqEn;
 247                                 break;
 248
 249                         case AC2_VI:
 250                                 AcmCtrl |= AcmHw_ViqEn;
 251                                 break;
 252
 253                         case AC3_VO:
 254                                 AcmCtrl |= AcmHw_VoqEn;
 255                                 break;
 256
 257                         default:
 258                                 RT_TRACE(COMP_QOS,
 259                                          "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n",
 260                                          eACI);
 261                                 break;
 262                         }
 263                 } else {
 264                         switch (eACI) {
 265                         case AC0_BE:
 266                                 AcmCtrl &= (~AcmHw_BeqEn);
 267                                 break;
 268
 269                         case AC2_VI:
 270                                 AcmCtrl &= (~AcmHw_ViqEn);
 271                                 break;
 272
 273                         case AC3_VO:
 274                                 AcmCtrl &= (~AcmHw_BeqEn);
 275                                 break;
 276
 277                         default:
 278                                 break;
 279                         }
 280                 }
 281
 282                 RT_TRACE(COMP_QOS,
 283                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 284                          AcmCtrl);
 285                 rtl92e_writeb(dev, AcmHwCtrl, AcmCtrl);
 286                 break;
 287         }
 288
 289         case HW_VAR_SIFS:
 290                 rtl92e_writeb(dev, SIFS, val[0]);
 291                 rtl92e_writeb(dev, SIFS+1, val[0]);
 292                 break;
 293
 294         case HW_VAR_RF_TIMING:
 295         {
 296                 u8 Rf_Timing = *((u8 *)val);
 297
 298                 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing);
 299                 break;
 300         }
 301
 302         default:
 303                 break;
 304         }
 305
 306 }
 307
 308 static void _rtl92e_read_eeprom_info(struct net_device *dev)
 309 {
 310         struct r8192_priv *priv = rtllib_priv(dev);
 311         const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
 312         u8 tempval;
 313         u8 ICVer8192, ICVer8256;
 314         u16 i, usValue, IC_Version;
 315         u16 EEPROMId;
 316
 317         RT_TRACE(COMP_INIT, "====> _rtl92e_read_eeprom_info\n");
 318
 319         EEPROMId = rtl92e_eeprom_read(dev, 0);
 320         if (EEPROMId != RTL8190_EEPROM_ID) {
 321                 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
 322                            EEPROMId);
 323                 priv->AutoloadFailFlag = true;
 324         } else {
 325                 priv->AutoloadFailFlag = false;
 326         }
 327
 328         if (!priv->AutoloadFailFlag) {
 329                 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1);
 330                 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1);
 331
 332                 usValue = rtl92e_eeprom_read(dev,
 333                                              (u16)(EEPROM_Customer_ID>>1)) >> 8;
 334                 priv->eeprom_CustomerID = (u8)(usValue & 0xff);
 335                 usValue = rtl92e_eeprom_read(dev,
 336                                              EEPROM_ICVersion_ChannelPlan>>1);
 337                 priv->eeprom_ChannelPlan = usValue&0xff;
 338                 IC_Version = (usValue & 0xff00)>>8;
 339
 340                 ICVer8192 = (IC_Version&0xf);
 341                 ICVer8256 = (IC_Version & 0xf0)>>4;
 342                 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
 343                 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
 344                 if (ICVer8192 == 0x2) {
 345                         if (ICVer8256 == 0x5)
 346                                 priv->card_8192_version = VERSION_8190_BE;
 347                 }
 348                 switch (priv->card_8192_version) {
 349                 case VERSION_8190_BD:
 350                 case VERSION_8190_BE:
 351                         break;
 352                 default:
 353                         priv->card_8192_version = VERSION_8190_BD;
 354                         break;
 355                 }
 356                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
 357                           priv->card_8192_version);
 358         } else {
 359                 priv->card_8192_version = VERSION_8190_BD;
 360                 priv->eeprom_vid = 0;
 361                 priv->eeprom_did = 0;
 362                 priv->eeprom_CustomerID = 0;
 363                 priv->eeprom_ChannelPlan = 0;
 364                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
 365         }
 366
 367         RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
 368         RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
 369         RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
 370                  priv->eeprom_CustomerID);
 371
 372         if (!priv->AutoloadFailFlag) {
 373                 for (i = 0; i < 6; i += 2) {
 374                         usValue = rtl92e_eeprom_read(dev,
 375                                  (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1));
 376                         *(u16 *)(&dev->dev_addr[i]) = usValue;
 377                 }
 378         } else {
 379                 ether_addr_copy(dev->dev_addr, bMac_Tmp_Addr);
 380         }
 381
 382         RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
 383                  dev->dev_addr);
 384
 385         if (priv->card_8192_version > VERSION_8190_BD)
 386                 priv->bTXPowerDataReadFromEEPORM = true;
 387         else
 388                 priv->bTXPowerDataReadFromEEPORM = false;
 389
 390         priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
 391
 392         if (priv->card_8192_version > VERSION_8190_BD) {
 393                 if (!priv->AutoloadFailFlag) {
 394                         tempval = (rtl92e_eeprom_read(dev,
 395                                                       (EEPROM_RFInd_PowerDiff >> 1))) & 0xff;
 396                         priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
 397
 398                         if (tempval&0x80)
 399                                 priv->rf_type = RF_1T2R;
 400                         else
 401                                 priv->rf_type = RF_2T4R;
 402                 } else {
 403                         priv->EEPROMLegacyHTTxPowerDiff = 0x04;
 404                 }
 405                 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
 406                         priv->EEPROMLegacyHTTxPowerDiff);
 407
 408                 if (!priv->AutoloadFailFlag)
 409                         priv->EEPROMThermalMeter = (u8)(((rtl92e_eeprom_read(dev,
 410                                                    (EEPROM_ThermalMeter>>1))) &
 411                                                    0xff00)>>8);
 412                 else
 413                         priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
 414                 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
 415                          priv->EEPROMThermalMeter);
 416                 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
 417
 418                 if (priv->epromtype == EEPROM_93C46) {
 419                         if (!priv->AutoloadFailFlag) {
 420                                 usValue = rtl92e_eeprom_read(dev,
 421                                           EEPROM_TxPwDiff_CrystalCap >> 1);
 422                                 priv->EEPROMAntPwDiff = (usValue&0x0fff);
 423                                 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
 424                                                          >> 12);
 425                         } else {
 426                                 priv->EEPROMAntPwDiff =
 427                                          EEPROM_Default_AntTxPowerDiff;
 428                                 priv->EEPROMCrystalCap =
 429                                          EEPROM_Default_TxPwDiff_CrystalCap;
 430                         }
 431                         RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
 432                                  priv->EEPROMAntPwDiff);
 433                         RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
 434                                  priv->EEPROMCrystalCap);
 435
 436                         for (i = 0; i < 14; i += 2) {
 437                                 if (!priv->AutoloadFailFlag)
 438                                         usValue = rtl92e_eeprom_read(dev,
 439                                                   (u16)((EEPROM_TxPwIndex_CCK +
 440                                                   i) >> 1));
 441                                 else
 442                                         usValue = EEPROM_Default_TxPower;
 443                                 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
 444                                                                  usValue;
 445                                 RT_TRACE(COMP_INIT,
 446                                          "CCK Tx Power Level, Index %d = 0x%02x\n",
 447                                          i, priv->EEPROMTxPowerLevelCCK[i]);
 448                                 RT_TRACE(COMP_INIT,
 449                                          "CCK Tx Power Level, Index %d = 0x%02x\n",
 450                                          i+1, priv->EEPROMTxPowerLevelCCK[i+1]);
 451                         }
 452                         for (i = 0; i < 14; i += 2) {
 453                                 if (!priv->AutoloadFailFlag)
 454                                         usValue = rtl92e_eeprom_read(dev,
 455                                                 (u16)((EEPROM_TxPwIndex_OFDM_24G
 456                                                 + i) >> 1));
 457                                 else
 458                                         usValue = EEPROM_Default_TxPower;
 459                                 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
 460                                                          = usValue;
 461                                 RT_TRACE(COMP_INIT,
 462                                          "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
 463                                          i, priv->EEPROMTxPowerLevelOFDM24G[i]);
 464                                 RT_TRACE(COMP_INIT,
 465                                          "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
 466                                          i + 1,
 467                                          priv->EEPROMTxPowerLevelOFDM24G[i+1]);
 468                         }
 469                 }
 470                 if (priv->epromtype == EEPROM_93C46) {
 471                         for (i = 0; i < 14; i++) {
 472                                 priv->TxPowerLevelCCK[i] =
 473                                          priv->EEPROMTxPowerLevelCCK[i];
 474                                 priv->TxPowerLevelOFDM24G[i] =
 475                                          priv->EEPROMTxPowerLevelOFDM24G[i];
 476                         }
 477                         priv->LegacyHTTxPowerDiff =
 478                                          priv->EEPROMLegacyHTTxPowerDiff;
 479                         priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff &
 480                                                     0xf);
 481                         priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff &
 482                                                         0xf0) >> 4;
 483                         priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff &
 484                                                         0xf00) >> 8;
 485                         priv->CrystalCap = priv->EEPROMCrystalCap;
 486                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 487                                                  0xf);
 488                         priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
 489                                                      0xf0) >> 4;
 490                 } else if (priv->epromtype == EEPROM_93C56) {
 491
 492                         for (i = 0; i < 3; i++) {
 493                                 priv->TxPowerLevelCCK_A[i] =
 494                                          priv->EEPROMRfACCKChnl1TxPwLevel[0];
 495                                 priv->TxPowerLevelOFDM24G_A[i] =
 496                                          priv->EEPROMRfAOfdmChnlTxPwLevel[0];
 497                                 priv->TxPowerLevelCCK_C[i] =
 498                                          priv->EEPROMRfCCCKChnl1TxPwLevel[0];
 499                                 priv->TxPowerLevelOFDM24G_C[i] =
 500                                          priv->EEPROMRfCOfdmChnlTxPwLevel[0];
 501                         }
 502                         for (i = 3; i < 9; i++) {
 503                                 priv->TxPowerLevelCCK_A[i]  =
 504                                          priv->EEPROMRfACCKChnl1TxPwLevel[1];
 505                                 priv->TxPowerLevelOFDM24G_A[i] =
 506                                          priv->EEPROMRfAOfdmChnlTxPwLevel[1];
 507                                 priv->TxPowerLevelCCK_C[i] =
 508                                          priv->EEPROMRfCCCKChnl1TxPwLevel[1];
 509                                 priv->TxPowerLevelOFDM24G_C[i] =
 510                                          priv->EEPROMRfCOfdmChnlTxPwLevel[1];
 511                         }
 512                         for (i = 9; i < 14; i++) {
 513                                 priv->TxPowerLevelCCK_A[i]  =
 514                                          priv->EEPROMRfACCKChnl1TxPwLevel[2];
 515                                 priv->TxPowerLevelOFDM24G_A[i] =
 516                                          priv->EEPROMRfAOfdmChnlTxPwLevel[2];
 517                                 priv->TxPowerLevelCCK_C[i] =
 518                                          priv->EEPROMRfCCCKChnl1TxPwLevel[2];
 519                                 priv->TxPowerLevelOFDM24G_C[i] =
 520                                          priv->EEPROMRfCOfdmChnlTxPwLevel[2];
 521                         }
 522                         for (i = 0; i < 14; i++)
 523                                 RT_TRACE(COMP_INIT,
 524                                          "priv->TxPowerLevelCCK_A[%d] = 0x%x\n",
 525                                          i, priv->TxPowerLevelCCK_A[i]);
 526                         for (i = 0; i < 14; i++)
 527                                 RT_TRACE(COMP_INIT,
 528                                          "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n",
 529                                          i, priv->TxPowerLevelOFDM24G_A[i]);
 530                         for (i = 0; i < 14; i++)
 531                                 RT_TRACE(COMP_INIT,
 532                                          "priv->TxPowerLevelCCK_C[%d] = 0x%x\n",
 533                                          i, priv->TxPowerLevelCCK_C[i]);
 534                         for (i = 0; i < 14; i++)
 535                                 RT_TRACE(COMP_INIT,
 536                                          "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n",
 537                                          i, priv->TxPowerLevelOFDM24G_C[i]);
 538                         priv->LegacyHTTxPowerDiff =
 539                                  priv->EEPROMLegacyHTTxPowerDiff;
 540                         priv->AntennaTxPwDiff[0] = 0;
 541                         priv->AntennaTxPwDiff[1] = 0;
 542                         priv->AntennaTxPwDiff[2] = 0;
 543                         priv->CrystalCap = priv->EEPROMCrystalCap;
 544                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 545                                                  0xf);
 546                         priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
 547                                                      0xf0) >> 4;
 548                 }
 549         }
 550
 551         if (priv->rf_type == RF_1T2R) {
 552                 /* no matter what checkpatch says, the braces are needed */
 553                 RT_TRACE(COMP_INIT, "\n1T2R config\n");
 554         } else if (priv->rf_type == RF_2T4R) {
 555                 RT_TRACE(COMP_INIT, "\n2T4R config\n");
 556         }
 557
 558         rtl92e_init_adaptive_rate(dev);
 559
 560         priv->rf_chip = RF_8256;
 561
 562         if (priv->RegChannelPlan == 0xf)
 563                 priv->ChannelPlan = priv->eeprom_ChannelPlan;
 564         else
 565                 priv->ChannelPlan = priv->RegChannelPlan;
 566
 567         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 568                 priv->CustomerID =  RT_CID_DLINK;
 569
 570         switch (priv->eeprom_CustomerID) {
 571         case EEPROM_CID_DEFAULT:
 572                 priv->CustomerID = RT_CID_DEFAULT;
 573                 break;
 574         case EEPROM_CID_CAMEO:
 575                 priv->CustomerID = RT_CID_819x_CAMEO;
 576                 break;
 577         case  EEPROM_CID_RUNTOP:
 578                 priv->CustomerID = RT_CID_819x_RUNTOP;
 579                 break;
 580         case EEPROM_CID_NetCore:
 581                 priv->CustomerID = RT_CID_819x_Netcore;
 582                 break;
 583         case EEPROM_CID_TOSHIBA:
 584                 priv->CustomerID = RT_CID_TOSHIBA;
 585                 if (priv->eeprom_ChannelPlan&0x80)
 586                         priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
 587                 else
 588                         priv->ChannelPlan = 0x0;
 589                 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
 590                         priv->ChannelPlan);
 591                 break;
 592         case EEPROM_CID_Nettronix:
 593                 priv->ScanDelay = 100;
 594                 priv->CustomerID = RT_CID_Nettronix;
 595                 break;
 596         case EEPROM_CID_Pronet:
 597                 priv->CustomerID = RT_CID_PRONET;
 598                 break;
 599         case EEPROM_CID_DLINK:
 600                 priv->CustomerID = RT_CID_DLINK;
 601                 break;
 602
 603         case EEPROM_CID_WHQL:
 604                 break;
 605         default:
 606                 break;
 607         }
 608
 609         if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
 610                 priv->ChannelPlan = 0;
 611         priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
 612
 613         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 614                 priv->rtllib->bSupportRemoteWakeUp = true;
 615         else
 616                 priv->rtllib->bSupportRemoteWakeUp = false;
 617
 618         RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
 619         RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
 620         RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
 621 }
 622
 623 void rtl92e_get_eeprom_size(struct net_device *dev)
 624 {
 625         u16 curCR;
 626         struct r8192_priv *priv = rtllib_priv(dev);
 627
 628         RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
 629         curCR = rtl92e_readl(dev, EPROM_CMD);
 630         RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
 631                  curCR);
 632         priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
 633                           EEPROM_93C46;
 634         RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
 635                  priv->epromtype);
 636         _rtl92e_read_eeprom_info(dev);
 637 }
 638
 639 static void _rtl92e_hwconfig(struct net_device *dev)
 640 {
 641         u32 regRATR = 0, regRRSR = 0;
 642         u8 regBwOpMode = 0, regTmp = 0;
 643         struct r8192_priv *priv = rtllib_priv(dev);
 644
 645         switch (priv->rtllib->mode) {
 646         case WIRELESS_MODE_B:
 647                 regBwOpMode = BW_OPMODE_20MHZ;
 648                 regRATR = RATE_ALL_CCK;
 649                 regRRSR = RATE_ALL_CCK;
 650                 break;
 651         case WIRELESS_MODE_A:
 652                 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
 653                 regRATR = RATE_ALL_OFDM_AG;
 654                 regRRSR = RATE_ALL_OFDM_AG;
 655                 break;
 656         case WIRELESS_MODE_G:
 657                 regBwOpMode = BW_OPMODE_20MHZ;
 658                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 659                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 660                 break;
 661         case WIRELESS_MODE_AUTO:
 662         case WIRELESS_MODE_N_24G:
 663                 regBwOpMode = BW_OPMODE_20MHZ;
 664                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 665                                   RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 666                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 667                 break;
 668         case WIRELESS_MODE_N_5G:
 669                 regBwOpMode = BW_OPMODE_5G;
 670                 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
 671                           RATE_ALL_OFDM_2SS;
 672                 regRRSR = RATE_ALL_OFDM_AG;
 673                 break;
 674         default:
 675                 regBwOpMode = BW_OPMODE_20MHZ;
 676                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 677                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 678                 break;
 679         }
 680
 681         rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
 682         {
 683                 u32 ratr_value = 0;
 684
 685                 ratr_value = regRATR;
 686                 if (priv->rf_type == RF_1T2R)
 687                         ratr_value &= ~(RATE_ALL_OFDM_2SS);
 688                 rtl92e_writel(dev, RATR0, ratr_value);
 689                 rtl92e_writeb(dev, UFWP, 1);
 690         }
 691         regTmp = rtl92e_readb(dev, 0x313);
 692         regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
 693         rtl92e_writel(dev, RRSR, regRRSR);
 694
 695         rtl92e_writew(dev, RETRY_LIMIT,
 696                       priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
 697                       priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
 698 }
 699
 700 bool rtl92e_start_adapter(struct net_device *dev)
 701 {
 702         struct r8192_priv *priv = rtllib_priv(dev);
 703         u32 ulRegRead;
 704         bool rtStatus = true;
 705         u8 tmpvalue;
 706         u8 ICVersion, SwitchingRegulatorOutput;
 707         bool bfirmwareok = true;
 708         u32 tmpRegA, tmpRegC, TempCCk;
 709         int i = 0;
 710         u32 retry_times = 0;
 711
 712         RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
 713         priv->being_init_adapter = true;
 714
 715 start:
 716         rtl92e_reset_desc_ring(dev);
 717         priv->Rf_Mode = RF_OP_By_SW_3wire;
 718         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 719                 rtl92e_writeb(dev, ANAPAR, 0x37);
 720                 mdelay(500);
 721         }
 722         priv->pFirmware->status = FW_STATUS_0_INIT;
 723
 724         if (priv->RegRfOff)
 725                 priv->rtllib->eRFPowerState = eRfOff;
 726
 727         ulRegRead = rtl92e_readl(dev, CPU_GEN);
 728         if (priv->pFirmware->status == FW_STATUS_0_INIT)
 729                 ulRegRead |= CPU_GEN_SYSTEM_RESET;
 730         else if (priv->pFirmware->status == FW_STATUS_5_READY)
 731                 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
 732         else
 733                 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
 734                            __func__, priv->pFirmware->status);
 735
 736         rtl92e_writel(dev, CPU_GEN, ulRegRead);
 737
 738         ICVersion = rtl92e_readb(dev, IC_VERRSION);
 739         if (ICVersion >= 0x4) {
 740                 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR);
 741                 if (SwitchingRegulatorOutput  != 0xb8) {
 742                         rtl92e_writeb(dev, SWREGULATOR, 0xa8);
 743                         mdelay(1);
 744                         rtl92e_writeb(dev, SWREGULATOR, 0xb8);
 745                 }
 746         }
 747         RT_TRACE(COMP_INIT, "BB Config Start!\n");
 748         rtStatus = rtl92e_config_bb(dev);
 749         if (!rtStatus) {
 750                 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
 751                 return rtStatus;
 752         }
 753         RT_TRACE(COMP_INIT, "BB Config Finished!\n");
 754
 755         priv->LoopbackMode = RTL819X_NO_LOOPBACK;
 756         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 757                 ulRegRead = rtl92e_readl(dev, CPU_GEN);
 758                 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
 759                         ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
 760                                      CPU_GEN_NO_LOOPBACK_SET);
 761                 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
 762                         ulRegRead |= CPU_CCK_LOOPBACK;
 763                 else
 764                         netdev_err(dev, "%s: Invalid loopback mode setting.\n",
 765                                    __func__);
 766
 767                 rtl92e_writel(dev, CPU_GEN, ulRegRead);
 768
 769                 udelay(500);
 770         }
 771         _rtl92e_hwconfig(dev);
 772         rtl92e_writeb(dev, CMDR, CR_RE | CR_TE);
 773
 774         rtl92e_writeb(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
 775                                   (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
 776         rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
 777         rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
 778         rtl92e_writel(dev, RCR, priv->ReceiveConfig);
 779
 780         rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
 781                       RSVD_FW_QUEUE_PAGE_BK_SHIFT |
 782                       NUM_OF_PAGE_IN_FW_QUEUE_BE <<
 783                       RSVD_FW_QUEUE_PAGE_BE_SHIFT |
 784                       NUM_OF_PAGE_IN_FW_QUEUE_VI <<
 785                       RSVD_FW_QUEUE_PAGE_VI_SHIFT |
 786                       NUM_OF_PAGE_IN_FW_QUEUE_VO <<
 787                       RSVD_FW_QUEUE_PAGE_VO_SHIFT);
 788         rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
 789                       RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
 790         rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
 791                       NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
 792                       RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
 793                       NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
 794                       RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
 795
 796         rtl92e_tx_enable(dev);
 797         rtl92e_rx_enable(dev);
 798         ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR))  |
 799                      RATE_ALL_OFDM_AG | RATE_ALL_CCK;
 800         rtl92e_writel(dev, RRSR, ulRegRead);
 801         rtl92e_writel(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
 802
 803         rtl92e_writeb(dev, ACK_TIMEOUT, 0x30);
 804
 805         if (priv->ResetProgress == RESET_TYPE_NORESET)
 806                 rtl92e_set_wireless_mode(dev, priv->rtllib->mode);
 807         rtl92e_cam_reset(dev);
 808         {
 809                 u8 SECR_value = 0x0;
 810
 811                 SECR_value |= SCR_TxEncEnable;
 812                 SECR_value |= SCR_RxDecEnable;
 813                 SECR_value |= SCR_NoSKMC;
 814                 rtl92e_writeb(dev, SECR, SECR_value);
 815         }
 816         rtl92e_writew(dev, ATIMWND, 2);
 817         rtl92e_writew(dev, BCN_INTERVAL, 100);
 818         {
 819                 int i;
 820
 821                 for (i = 0; i < QOS_QUEUE_NUM; i++)
 822                         rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332);
 823         }
 824         rtl92e_writeb(dev, 0xbe, 0xc0);
 825
 826         rtl92e_config_mac(dev);
 827
 828         if (priv->card_8192_version > (u8) VERSION_8190_BD) {
 829                 rtl92e_get_tx_power(dev);
 830                 rtl92e_set_tx_power(dev, priv->chan);
 831         }
 832
 833         tmpvalue = rtl92e_readb(dev, IC_VERRSION);
 834         priv->IC_Cut = tmpvalue;
 835         RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
 836         if (priv->IC_Cut >= IC_VersionCut_D) {
 837                 if (priv->IC_Cut == IC_VersionCut_D) {
 838                         /* no matter what checkpatch says, braces are needed */
 839                         RT_TRACE(COMP_INIT, "D-cut\n");
 840                 } else if (priv->IC_Cut == IC_VersionCut_E) {
 841                         RT_TRACE(COMP_INIT, "E-cut\n");
 842                 }
 843         } else {
 844                 RT_TRACE(COMP_INIT, "Before C-cut\n");
 845         }
 846
 847         RT_TRACE(COMP_INIT, "Load Firmware!\n");
 848         bfirmwareok = rtl92e_init_fw(dev);
 849         if (!bfirmwareok) {
 850                 if (retry_times < 10) {
 851                         retry_times++;
 852                         goto start;
 853                 } else {
 854                         rtStatus = false;
 855                         goto end;
 856                 }
 857         }
 858         RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
 859         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 860                 RT_TRACE(COMP_INIT, "RF Config Started!\n");
 861                 rtStatus = rtl92e_config_phy(dev);
 862                 if (!rtStatus) {
 863                         netdev_info(dev, "RF Config failed\n");
 864                         return rtStatus;
 865                 }
 866                 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
 867         }
 868
 869         rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
 870         rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
 871
 872         rtl92e_writeb(dev, 0x87, 0x0);
 873
 874         if (priv->RegRfOff) {
 875                 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
 876                           "%s(): Turn off RF for RegRfOff ----------\n",
 877                           __func__);
 878                 rtl92e_set_rf_state(dev, eRfOff, RF_CHANGE_BY_SW);
 879         } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
 880                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
 881                          "%s(): Turn off RF for RfOffReason(%d) ----------\n",
 882                          __func__, priv->rtllib->RfOffReason);
 883                 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason);
 884         } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
 885                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
 886                          "%s(): Turn off RF for RfOffReason(%d) ----------\n",
 887                          __func__, priv->rtllib->RfOffReason);
 888                 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason);
 889         } else {
 890                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
 891                           __func__);
 892                 priv->rtllib->eRFPowerState = eRfOn;
 893                 priv->rtllib->RfOffReason = 0;
 894         }
 895
 896         if (priv->rtllib->FwRWRF)
 897                 priv->Rf_Mode = RF_OP_By_FW;
 898         else
 899                 priv->Rf_Mode = RF_OP_By_SW_3wire;
 900
 901         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 902                 rtl92e_dm_init_txpower_tracking(dev);
 903
 904                 if (priv->IC_Cut >= IC_VersionCut_D) {
 905                         tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance,
 906                                                     bMaskDWord);
 907                         tmpRegC = rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance,
 908                                                     bMaskDWord);
 909                         for (i = 0; i < TxBBGainTableLength; i++) {
 910                                 if (tmpRegA == dm_tx_bb_gain[i]) {
 911                                         priv->rfa_txpowertrackingindex = (u8)i;
 912                                         priv->rfa_txpowertrackingindex_real =
 913                                                  (u8)i;
 914                                         priv->rfa_txpowertracking_default =
 915                                                  priv->rfa_txpowertrackingindex;
 916                                         break;
 917                                 }
 918                         }
 919
 920                         TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1,
 921                                                     bMaskByte2);
 922
 923                         for (i = 0; i < CCKTxBBGainTableLength; i++) {
 924                                 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
 925                                         priv->CCKPresentAttentuation_20Mdefault = (u8)i;
 926                                         break;
 927                                 }
 928                         }
 929                         priv->CCKPresentAttentuation_40Mdefault = 0;
 930                         priv->CCKPresentAttentuation_difference = 0;
 931                         priv->CCKPresentAttentuation =
 932                                   priv->CCKPresentAttentuation_20Mdefault;
 933                         RT_TRACE(COMP_POWER_TRACKING,
 934                                  "priv->rfa_txpowertrackingindex_initial = %d\n",
 935                                  priv->rfa_txpowertrackingindex);
 936                         RT_TRACE(COMP_POWER_TRACKING,
 937                                  "priv->rfa_txpowertrackingindex_real__initial = %d\n",
 938                                  priv->rfa_txpowertrackingindex_real);
 939                         RT_TRACE(COMP_POWER_TRACKING,
 940                                  "priv->CCKPresentAttentuation_difference_initial = %d\n",
 941                                   priv->CCKPresentAttentuation_difference);
 942                         RT_TRACE(COMP_POWER_TRACKING,
 943                                  "priv->CCKPresentAttentuation_initial = %d\n",
 944                                  priv->CCKPresentAttentuation);
 945                         priv->btxpower_tracking = false;
 946                 }
 947         }
 948         rtl92e_irq_enable(dev);
 949 end:
 950         priv->being_init_adapter = false;
 951         return rtStatus;
 952 }
 953
 954 static void _rtl92e_net_update(struct net_device *dev)
 955 {
 956
 957         struct r8192_priv *priv = rtllib_priv(dev);
 958         struct rtllib_network *net;
 959         u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
 960         u16 rate_config = 0;
 961
 962         net = &priv->rtllib->current_network;
 963         rtl92e_config_rate(dev, &rate_config);
 964         priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
 965          priv->basic_rate = rate_config &= 0x15f;
 966         rtl92e_writel(dev, BSSIDR, ((u32 *)net->bssid)[0]);
 967         rtl92e_writew(dev, BSSIDR+4, ((u16 *)net->bssid)[2]);
 968
 969         if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
 970                 rtl92e_writew(dev, ATIMWND, 2);
 971                 rtl92e_writew(dev, BCN_DMATIME, 256);
 972                 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
 973                 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
 974                 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
 975
 976                 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
 977                 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
 978
 979                 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
 980         }
 981 }
 982
 983 void rtl92e_link_change(struct net_device *dev)
 984 {
 985         struct r8192_priv *priv = rtllib_priv(dev);
 986         struct rtllib_device *ieee = priv->rtllib;
 987
 988         if (!priv->up)
 989                 return;
 990
 991         if (ieee->state == RTLLIB_LINKED) {
 992                 _rtl92e_net_update(dev);
 993                 priv->ops->update_ratr_table(dev);
 994                 if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) ||
 995                     (ieee->pairwise_key_type == KEY_TYPE_WEP104))
 996                         rtl92e_enable_hw_security_config(dev);
 997         } else {
 998                 rtl92e_writeb(dev, 0x173, 0);
 999         }
1000         _rtl92e_update_msr(dev);
1001
1002         if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
1003                 u32 reg = 0;
1004
1005                 reg = rtl92e_readl(dev, RCR);
1006                 if (priv->rtllib->state == RTLLIB_LINKED) {
1007                         if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
1008                                 ;
1009                         else
1010                                 priv->ReceiveConfig = reg |= RCR_CBSSID;
1011                 } else
1012                         priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1013
1014                 rtl92e_writel(dev, RCR, reg);
1015         }
1016 }
1017
1018 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA,
1019                              bool WriteIntoReg)
1020 {
1021         struct r8192_priv *priv = rtllib_priv(dev);
1022
1023         if (bAllowAllDA)
1024                 priv->ReceiveConfig |= RCR_AAP;
1025         else
1026                 priv->ReceiveConfig &= ~RCR_AAP;
1027
1028         if (WriteIntoReg)
1029                 rtl92e_writel(dev, RCR, priv->ReceiveConfig);
1030 }
1031
1032 static u8 _rtl92e_rate_mgn_to_hw(u8 rate)
1033 {
1034         u8  ret = DESC90_RATE1M;
1035
1036         switch (rate) {
1037         case MGN_1M:
1038                 ret = DESC90_RATE1M;
1039                 break;
1040         case MGN_2M:
1041                 ret = DESC90_RATE2M;
1042                 break;
1043         case MGN_5_5M:
1044                 ret = DESC90_RATE5_5M;
1045                 break;
1046         case MGN_11M:
1047                 ret = DESC90_RATE11M;
1048                 break;
1049         case MGN_6M:
1050                 ret = DESC90_RATE6M;
1051                 break;
1052         case MGN_9M:
1053                 ret = DESC90_RATE9M;
1054                 break;
1055         case MGN_12M:
1056                 ret = DESC90_RATE12M;
1057                 break;
1058         case MGN_18M:
1059                 ret = DESC90_RATE18M;
1060                 break;
1061         case MGN_24M:
1062                 ret = DESC90_RATE24M;
1063                 break;
1064         case MGN_36M:
1065                 ret = DESC90_RATE36M;
1066                 break;
1067         case MGN_48M:
1068                 ret = DESC90_RATE48M;
1069                 break;
1070         case MGN_54M:
1071                 ret = DESC90_RATE54M;
1072                 break;
1073         case MGN_MCS0:
1074                 ret = DESC90_RATEMCS0;
1075                 break;
1076         case MGN_MCS1:
1077                 ret = DESC90_RATEMCS1;
1078                 break;
1079         case MGN_MCS2:
1080                 ret = DESC90_RATEMCS2;
1081                 break;
1082         case MGN_MCS3:
1083                 ret = DESC90_RATEMCS3;
1084                 break;
1085         case MGN_MCS4:
1086                 ret = DESC90_RATEMCS4;
1087                 break;
1088         case MGN_MCS5:
1089                 ret = DESC90_RATEMCS5;
1090                 break;
1091         case MGN_MCS6:
1092                 ret = DESC90_RATEMCS6;
1093                 break;
1094         case MGN_MCS7:
1095                 ret = DESC90_RATEMCS7;
1096                 break;
1097         case MGN_MCS8:
1098                 ret = DESC90_RATEMCS8;
1099                 break;
1100         case MGN_MCS9:
1101                 ret = DESC90_RATEMCS9;
1102                 break;
1103         case MGN_MCS10:
1104                 ret = DESC90_RATEMCS10;
1105                 break;
1106         case MGN_MCS11:
1107                 ret = DESC90_RATEMCS11;
1108                 break;
1109         case MGN_MCS12:
1110                 ret = DESC90_RATEMCS12;
1111                 break;
1112         case MGN_MCS13:
1113                 ret = DESC90_RATEMCS13;
1114                 break;
1115         case MGN_MCS14:
1116                 ret = DESC90_RATEMCS14;
1117                 break;
1118         case MGN_MCS15:
1119                 ret = DESC90_RATEMCS15;
1120                 break;
1121         case (0x80|0x20):
1122                 ret = DESC90_RATEMCS32;
1123                 break;
1124         default:
1125                 break;
1126         }
1127         return ret;
1128 }
1129
1130 static u8 _rtl92e_hw_queue_to_fw_queue(struct net_device *dev, u8 QueueID,
1131                                        u8 priority)
1132 {
1133         u8 QueueSelect = 0x0;
1134
1135         switch (QueueID) {
1136         case BE_QUEUE:
1137                 QueueSelect = QSLT_BE;
1138                 break;
1139
1140         case BK_QUEUE:
1141                 QueueSelect = QSLT_BK;
1142                 break;
1143
1144         case VO_QUEUE:
1145                 QueueSelect = QSLT_VO;
1146                 break;
1147
1148         case VI_QUEUE:
1149                 QueueSelect = QSLT_VI;
1150                 break;
1151         case MGNT_QUEUE:
1152                 QueueSelect = QSLT_MGNT;
1153                 break;
1154         case BEACON_QUEUE:
1155                 QueueSelect = QSLT_BEACON;
1156                 break;
1157         case TXCMD_QUEUE:
1158                 QueueSelect = QSLT_CMD;
1159                 break;
1160         case HIGH_QUEUE:
1161                 QueueSelect = QSLT_HIGH;
1162                 break;
1163         default:
1164                 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
1165                             __func__, QueueID);
1166                 break;
1167         }
1168         return QueueSelect;
1169 }
1170
1171 static u8 _rtl92e_query_is_short(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
1172 {
1173         u8   tmp_Short;
1174
1175         tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
1176                         ((tcb_desc->bUseShortPreamble) ? 1 : 0);
1177         if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
1178                 tmp_Short = 0;
1179
1180         return tmp_Short;
1181 }
1182
1183 void  rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc,
1184                           struct cb_desc *cb_desc, struct sk_buff *skb)
1185 {
1186         struct r8192_priv *priv = rtllib_priv(dev);
1187         dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1188                          PCI_DMA_TODEVICE);
1189         struct tx_fwinfo_8190pci *pTxFwInfo = NULL;
1190
1191         pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1192         memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1193         pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1194         pTxFwInfo->TxRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->data_rate);
1195         pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1196         pTxFwInfo->Short = _rtl92e_query_is_short(pTxFwInfo->TxHT,
1197                                                   pTxFwInfo->TxRate, cb_desc);
1198
1199         if (pci_dma_mapping_error(priv->pdev, mapping))
1200                 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1201         if (cb_desc->bAMPDUEnable) {
1202                 pTxFwInfo->AllowAggregation = 1;
1203                 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1204                 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1205         } else {
1206                 pTxFwInfo->AllowAggregation = 0;
1207                 pTxFwInfo->RxMF = 0;
1208                 pTxFwInfo->RxAMD = 0;
1209         }
1210
1211         pTxFwInfo->RtsEnable =  (cb_desc->bRTSEnable) ? 1 : 0;
1212         pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1213         pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1214         pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1215         pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->rts_rate);
1216         pTxFwInfo->RtsBandwidth = 0;
1217         pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1218         pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1219                           (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1220                           (cb_desc->bRTSUseShortGI ? 1 : 0);
1221         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1222                 if (cb_desc->bPacketBW) {
1223                         pTxFwInfo->TxBandwidth = 1;
1224                         pTxFwInfo->TxSubCarrier = 0;
1225                 } else {
1226                         pTxFwInfo->TxBandwidth = 0;
1227                         pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1228                 }
1229         } else {
1230                 pTxFwInfo->TxBandwidth = 0;
1231                 pTxFwInfo->TxSubCarrier = 0;
1232         }
1233
1234         memset((u8 *)pdesc, 0, 12);
1235         pdesc->LINIP = 0;
1236         pdesc->CmdInit = 1;
1237         pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1238         pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1239
1240         pdesc->SecCAMID = 0;
1241         pdesc->RATid = cb_desc->RATRIndex;
1242
1243
1244         pdesc->NoEnc = 1;
1245         pdesc->SecType = 0x0;
1246         if (cb_desc->bHwSec) {
1247                 static u8 tmp;
1248
1249                 if (!tmp) {
1250                         RT_TRACE(COMP_DBG, "==>================hw sec\n");
1251                         tmp = 1;
1252                 }
1253                 switch (priv->rtllib->pairwise_key_type) {
1254                 case KEY_TYPE_WEP40:
1255                 case KEY_TYPE_WEP104:
1256                         pdesc->SecType = 0x1;
1257                         pdesc->NoEnc = 0;
1258                         break;
1259                 case KEY_TYPE_TKIP:
1260                         pdesc->SecType = 0x2;
1261                         pdesc->NoEnc = 0;
1262                         break;
1263                 case KEY_TYPE_CCMP:
1264                         pdesc->SecType = 0x3;
1265                         pdesc->NoEnc = 0;
1266                         break;
1267                 case KEY_TYPE_NA:
1268                         pdesc->SecType = 0x0;
1269                         pdesc->NoEnc = 1;
1270                         break;
1271                 }
1272         }
1273
1274         pdesc->PktId = 0x0;
1275
1276         pdesc->QueueSelect = _rtl92e_hw_queue_to_fw_queue(dev,
1277                                                           cb_desc->queue_index,
1278                                                           cb_desc->priority);
1279         pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1280
1281         pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1282         pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1283
1284         pdesc->FirstSeg = 1;
1285         pdesc->LastSeg = 1;
1286         pdesc->TxBufferSize = skb->len;
1287
1288         pdesc->TxBuffAddr = mapping;
1289 }
1290
1291 void  rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry,
1292                               struct cb_desc *cb_desc, struct sk_buff *skb)
1293 {
1294         struct r8192_priv *priv = rtllib_priv(dev);
1295         dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1296                          PCI_DMA_TODEVICE);
1297
1298         if (pci_dma_mapping_error(priv->pdev, mapping))
1299                 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1300         memset(entry, 0, 12);
1301         entry->LINIP = cb_desc->bLastIniPkt;
1302         entry->FirstSeg = 1;
1303         entry->LastSeg = 1;
1304         if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1305                 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1306         } else {
1307                 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1308
1309                 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1310                 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1311                 entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1312                                       entry_tmp->Offset);
1313                 entry_tmp->QueueSelect = QSLT_CMD;
1314                 entry_tmp->TxFWInfoSize = 0x08;
1315                 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1316         }
1317         entry->TxBufferSize = skb->len;
1318         entry->TxBuffAddr = mapping;
1319         entry->OWN = 1;
1320 }
1321
1322 static u8 _rtl92e_rate_hw_to_mgn(bool bIsHT, u8 rate)
1323 {
1324         u8  ret_rate = 0x02;
1325
1326         if (!bIsHT) {
1327                 switch (rate) {
1328                 case DESC90_RATE1M:
1329                         ret_rate = MGN_1M;
1330                         break;
1331                 case DESC90_RATE2M:
1332                         ret_rate = MGN_2M;
1333                         break;
1334                 case DESC90_RATE5_5M:
1335                         ret_rate = MGN_5_5M;
1336                         break;
1337                 case DESC90_RATE11M:
1338                         ret_rate = MGN_11M;
1339                         break;
1340                 case DESC90_RATE6M:
1341                         ret_rate = MGN_6M;
1342                         break;
1343                 case DESC90_RATE9M:
1344                         ret_rate = MGN_9M;
1345                         break;
1346                 case DESC90_RATE12M:
1347                         ret_rate = MGN_12M;
1348                         break;
1349                 case DESC90_RATE18M:
1350                         ret_rate = MGN_18M;
1351                         break;
1352                 case DESC90_RATE24M:
1353                         ret_rate = MGN_24M;
1354                         break;
1355                 case DESC90_RATE36M:
1356                         ret_rate = MGN_36M;
1357                         break;
1358                 case DESC90_RATE48M:
1359                         ret_rate = MGN_48M;
1360                         break;
1361                 case DESC90_RATE54M:
1362                         ret_rate = MGN_54M;
1363                         break;
1364
1365                 default:
1366                         RT_TRACE(COMP_RECV,
1367                                  "_rtl92e_rate_hw_to_mgn(): Non supportedRate [%x], bIsHT = %d!!!\n",
1368                                  rate, bIsHT);
1369                         break;
1370                 }
1371
1372         } else {
1373                 switch (rate) {
1374                 case DESC90_RATEMCS0:
1375                         ret_rate = MGN_MCS0;
1376                         break;
1377                 case DESC90_RATEMCS1:
1378                         ret_rate = MGN_MCS1;
1379                         break;
1380                 case DESC90_RATEMCS2:
1381                         ret_rate = MGN_MCS2;
1382                         break;
1383                 case DESC90_RATEMCS3:
1384                         ret_rate = MGN_MCS3;
1385                         break;
1386                 case DESC90_RATEMCS4:
1387                         ret_rate = MGN_MCS4;
1388                         break;
1389                 case DESC90_RATEMCS5:
1390                         ret_rate = MGN_MCS5;
1391                         break;
1392                 case DESC90_RATEMCS6:
1393                         ret_rate = MGN_MCS6;
1394                         break;
1395                 case DESC90_RATEMCS7:
1396                         ret_rate = MGN_MCS7;
1397                         break;
1398                 case DESC90_RATEMCS8:
1399                         ret_rate = MGN_MCS8;
1400                         break;
1401                 case DESC90_RATEMCS9:
1402                         ret_rate = MGN_MCS9;
1403                         break;
1404                 case DESC90_RATEMCS10:
1405                         ret_rate = MGN_MCS10;
1406                         break;
1407                 case DESC90_RATEMCS11:
1408                         ret_rate = MGN_MCS11;
1409                         break;
1410                 case DESC90_RATEMCS12:
1411                         ret_rate = MGN_MCS12;
1412                         break;
1413                 case DESC90_RATEMCS13:
1414                         ret_rate = MGN_MCS13;
1415                         break;
1416                 case DESC90_RATEMCS14:
1417                         ret_rate = MGN_MCS14;
1418                         break;
1419                 case DESC90_RATEMCS15:
1420                         ret_rate = MGN_MCS15;
1421                         break;
1422                 case DESC90_RATEMCS32:
1423                         ret_rate = (0x80|0x20);
1424                         break;
1425
1426                 default:
1427                         RT_TRACE(COMP_RECV,
1428                                  "_rtl92e_rate_hw_to_mgn(): Non supported Rate [%x], bIsHT = %d!!!\n",
1429                                  rate, bIsHT);
1430                         break;
1431                 }
1432         }
1433
1434         return ret_rate;
1435 }
1436
1437 static long _rtl92e_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1438 {
1439         long retsig;
1440
1441         if (currsig >= 61 && currsig <= 100)
1442                 retsig = 90 + ((currsig - 60) / 4);
1443         else if (currsig >= 41 && currsig <= 60)
1444                 retsig = 78 + ((currsig - 40) / 2);
1445         else if (currsig >= 31 && currsig <= 40)
1446                 retsig = 66 + (currsig - 30);
1447         else if (currsig >= 21 && currsig <= 30)
1448                 retsig = 54 + (currsig - 20);
1449         else if (currsig >= 5 && currsig <= 20)
1450                 retsig = 42 + (((currsig - 5) * 2) / 3);
1451         else if (currsig == 4)
1452                 retsig = 36;
1453         else if (currsig == 3)
1454                 retsig = 27;
1455         else if (currsig == 2)
1456                 retsig = 18;
1457         else if (currsig == 1)
1458                 retsig = 9;
1459         else
1460                 retsig = currsig;
1461
1462         return retsig;
1463 }
1464
1465
1466 #define  rx_hal_is_cck_rate(_pdrvinfo)\
1467                         ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1468                         _pdrvinfo->RxRate == DESC90_RATE2M ||\
1469                         _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1470                         _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1471                         !_pdrvinfo->RxHT)
1472
1473 static void _rtl92e_query_rxphystatus(
1474         struct r8192_priv *priv,
1475         struct rtllib_rx_stats *pstats,
1476         struct rx_desc  *pdesc,
1477         struct rx_fwinfo   *pdrvinfo,
1478         struct rtllib_rx_stats *precord_stats,
1479         bool bpacket_match_bssid,
1480         bool bpacket_toself,
1481         bool bPacketBeacon,
1482         bool bToSelfBA
1483         )
1484 {
1485         struct phy_sts_ofdm_819xpci *pofdm_buf;
1486         struct phy_sts_cck_819xpci *pcck_buf;
1487         struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1488         u8 *prxpkt;
1489         u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1490         char rx_pwr[4], rx_pwr_all = 0;
1491         char rx_snrX, rx_evmX;
1492         u8 evm, pwdb_all;
1493         u32 RSSI, total_rssi = 0;
1494         u8 is_cck_rate = 0;
1495         u8 rf_rx_num = 0;
1496         static  u8 check_reg824;
1497         static  u32 reg824_bit9;
1498
1499         priv->stats.numqry_phystatus++;
1500
1501         is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1502         memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1503         pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1504                                     bpacket_match_bssid;
1505         pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1506         pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1507         pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1508         pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1509         if (check_reg824 == 0) {
1510                 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev,
1511                                                 rFPGA0_XA_HSSIParameter2,
1512                                                 0x200);
1513                 check_reg824 = 1;
1514         }
1515
1516
1517         prxpkt = (u8 *)pdrvinfo;
1518
1519         prxpkt += sizeof(struct rx_fwinfo);
1520
1521         pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1522         pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1523
1524         pstats->RxMIMOSignalQuality[0] = -1;
1525         pstats->RxMIMOSignalQuality[1] = -1;
1526         precord_stats->RxMIMOSignalQuality[0] = -1;
1527         precord_stats->RxMIMOSignalQuality[1] = -1;
1528
1529         if (is_cck_rate) {
1530                 u8 report;
1531
1532                 priv->stats.numqry_phystatusCCK++;
1533                 if (!reg824_bit9) {
1534                         report = pcck_buf->cck_agc_rpt & 0xc0;
1535                         report >>= 6;
1536                         switch (report) {
1537                         case 0x3:
1538                                 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1539                                              0x3e);
1540                                 break;
1541                         case 0x2:
1542                                 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1543                                              0x3e);
1544                                 break;
1545                         case 0x1:
1546                                 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1547                                              0x3e);
1548                                 break;
1549                         case 0x0:
1550                                 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1551                                 break;
1552                         }
1553                 } else {
1554                         report = pcck_buf->cck_agc_rpt & 0x60;
1555                         report >>= 5;
1556                         switch (report) {
1557                         case 0x3:
1558                                 rx_pwr_all = -35 -
1559                                         ((pcck_buf->cck_agc_rpt &
1560                                         0x1f) << 1);
1561                                 break;
1562                         case 0x2:
1563                                 rx_pwr_all = -23 -
1564                                         ((pcck_buf->cck_agc_rpt &
1565                                          0x1f) << 1);
1566                                 break;
1567                         case 0x1:
1568                                 rx_pwr_all = -11 -
1569                                          ((pcck_buf->cck_agc_rpt &
1570                                          0x1f) << 1);
1571                                 break;
1572                         case 0x0:
1573                                 rx_pwr_all = -8 -
1574                                          ((pcck_buf->cck_agc_rpt &
1575                                          0x1f) << 1);
1576                                 break;
1577                         }
1578                 }
1579
1580                 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1581                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1582                 pstats->RecvSignalPower = rx_pwr_all;
1583
1584                 if (bpacket_match_bssid) {
1585                         u8      sq;
1586
1587                         if (pstats->RxPWDBAll > 40) {
1588                                 sq = 100;
1589                         } else {
1590                                 sq = pcck_buf->sq_rpt;
1591
1592                                 if (pcck_buf->sq_rpt > 64)
1593                                         sq = 0;
1594                                 else if (pcck_buf->sq_rpt < 20)
1595                                         sq = 100;
1596                                 else
1597                                         sq = ((64-sq) * 100) / 44;
1598                         }
1599                         pstats->SignalQuality = sq;
1600                         precord_stats->SignalQuality = sq;
1601                         pstats->RxMIMOSignalQuality[0] = sq;
1602                         precord_stats->RxMIMOSignalQuality[0] = sq;
1603                         pstats->RxMIMOSignalQuality[1] = -1;
1604                         precord_stats->RxMIMOSignalQuality[1] = -1;
1605                 }
1606         } else {
1607                 priv->stats.numqry_phystatusHT++;
1608                 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1609                         if (priv->brfpath_rxenable[i])
1610                                 rf_rx_num++;
1611
1612                         rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1613                                      2) - 110;
1614
1615                         tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1616                         rx_snrX = (char)(tmp_rxsnr);
1617                         rx_snrX /= 2;
1618                         priv->stats.rxSNRdB[i] = (long)rx_snrX;
1619
1620                         RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]);
1621                         if (priv->brfpath_rxenable[i])
1622                                 total_rssi += RSSI;
1623
1624                         if (bpacket_match_bssid) {
1625                                 pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1626                                 precord_stats->RxMIMOSignalStrength[i] =
1627                                                                 (u8) RSSI;
1628                         }
1629                 }
1630
1631
1632                 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1633                 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1634
1635                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1636                 pstats->RxPower = precord_stats->RxPower =      rx_pwr_all;
1637                 pstats->RecvSignalPower = rx_pwr_all;
1638                 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1639                     pdrvinfo->RxRate <= DESC90_RATEMCS15)
1640                         max_spatial_stream = 2;
1641                 else
1642                         max_spatial_stream = 1;
1643
1644                 for (i = 0; i < max_spatial_stream; i++) {
1645                         tmp_rxevm = pofdm_buf->rxevm_X[i];
1646                         rx_evmX = (char)(tmp_rxevm);
1647
1648                         rx_evmX /= 2;
1649
1650                         evm = rtl92e_evm_db_to_percent(rx_evmX);
1651                         if (bpacket_match_bssid) {
1652                                 if (i == 0) {
1653                                         pstats->SignalQuality = (u8)(evm &
1654                                                                  0xff);
1655                                         precord_stats->SignalQuality = (u8)(evm
1656                                                                         & 0xff);
1657                                 }
1658                                 pstats->RxMIMOSignalQuality[i] = (u8)(evm &
1659                                                                  0xff);
1660                                 precord_stats->RxMIMOSignalQuality[i] = (u8)(evm
1661                                                                         & 0xff);
1662                         }
1663                 }
1664
1665
1666                 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1667                 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1668                         &rxsc_sgien_exflg;
1669                 if (pdrvinfo->BW)
1670                         priv->stats.received_bwtype[1+prxsc->rxsc]++;
1671                 else
1672                         priv->stats.received_bwtype[0]++;
1673         }
1674
1675         if (is_cck_rate) {
1676                 pstats->SignalStrength = precord_stats->SignalStrength =
1677                                          (u8)(_rtl92e_signal_scale_mapping(priv,
1678                                          (long)pwdb_all));
1679
1680         } else {
1681                 if (rf_rx_num != 0)
1682                         pstats->SignalStrength = precord_stats->SignalStrength =
1683                                          (u8)(_rtl92e_signal_scale_mapping(priv,
1684                                          (long)(total_rssi /= rf_rx_num)));
1685         }
1686 }
1687
1688 static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1689                                     struct rtllib_rx_stats *prev_st,
1690                                     struct rtllib_rx_stats *curr_st)
1691 {
1692         bool bcheck = false;
1693         u8      rfpath;
1694         u32 ij, tmp_val;
1695         static u32 slide_rssi_index, slide_rssi_statistics;
1696         static u32 slide_evm_index, slide_evm_statistics;
1697         static u32 last_rssi, last_evm;
1698         static u32 slide_beacon_adc_pwdb_index;
1699         static u32 slide_beacon_adc_pwdb_statistics;
1700         static u32 last_beacon_adc_pwdb;
1701         struct rtllib_hdr_3addr *hdr;
1702         u16 sc;
1703         unsigned int frag, seq;
1704
1705         hdr = (struct rtllib_hdr_3addr *)buffer;
1706         sc = le16_to_cpu(hdr->seq_ctl);
1707         frag = WLAN_GET_SEQ_FRAG(sc);
1708         seq = WLAN_GET_SEQ_SEQ(sc);
1709         curr_st->Seq_Num = seq;
1710         if (!prev_st->bIsAMPDU)
1711                 bcheck = true;
1712
1713         if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1714                 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1715                 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1716                 priv->stats.slide_rssi_total -= last_rssi;
1717         }
1718         priv->stats.slide_rssi_total += prev_st->SignalStrength;
1719
1720         priv->stats.slide_signal_strength[slide_rssi_index++] =
1721                                          prev_st->SignalStrength;
1722         if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1723                 slide_rssi_index = 0;
1724
1725         tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1726         priv->stats.signal_strength = rtl92e_translate_to_dbm(priv,
1727                                                               (u8)tmp_val);
1728         curr_st->rssi = priv->stats.signal_strength;
1729         if (!prev_st->bPacketMatchBSSID) {
1730                 if (!prev_st->bToSelfBA)
1731                         return;
1732         }
1733
1734         if (!bcheck)
1735                 return;
1736
1737         priv->stats.num_process_phyinfo++;
1738         if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1739                 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1740                         if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath))
1741                                 continue;
1742                         RT_TRACE(COMP_DBG,
1743                                  "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath]  = %d\n",
1744                                  prev_st->RxMIMOSignalStrength[rfpath]);
1745                         if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1746                                 priv->stats.rx_rssi_percentage[rfpath] =
1747                                          prev_st->RxMIMOSignalStrength[rfpath];
1748                         }
1749                         if (prev_st->RxMIMOSignalStrength[rfpath]  >
1750                             priv->stats.rx_rssi_percentage[rfpath]) {
1751                                 priv->stats.rx_rssi_percentage[rfpath] =
1752                                         ((priv->stats.rx_rssi_percentage[rfpath]
1753                                         * (RX_SMOOTH - 1)) +
1754                                         (prev_st->RxMIMOSignalStrength
1755                                         [rfpath])) / (RX_SMOOTH);
1756                                 priv->stats.rx_rssi_percentage[rfpath] =
1757                                          priv->stats.rx_rssi_percentage[rfpath]
1758                                          + 1;
1759                         } else {
1760                                 priv->stats.rx_rssi_percentage[rfpath] =
1761                                    ((priv->stats.rx_rssi_percentage[rfpath] *
1762                                    (RX_SMOOTH-1)) +
1763                                    (prev_st->RxMIMOSignalStrength[rfpath])) /
1764                                    (RX_SMOOTH);
1765                         }
1766                         RT_TRACE(COMP_DBG,
1767                                  "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath]  = %d\n",
1768                                  priv->stats.rx_rssi_percentage[rfpath]);
1769                 }
1770         }
1771
1772
1773         if (prev_st->bPacketBeacon) {
1774                 if (slide_beacon_adc_pwdb_statistics++ >=
1775                     PHY_Beacon_RSSI_SLID_WIN_MAX) {
1776                         slide_beacon_adc_pwdb_statistics =
1777                                          PHY_Beacon_RSSI_SLID_WIN_MAX;
1778                         last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1779                                                [slide_beacon_adc_pwdb_index];
1780                         priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1781                 }
1782                 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1783                 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1784                                                          prev_st->RxPWDBAll;
1785                 slide_beacon_adc_pwdb_index++;
1786                 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1787                         slide_beacon_adc_pwdb_index = 0;
1788                 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1789                                      slide_beacon_adc_pwdb_statistics;
1790                 if (prev_st->RxPWDBAll >= 3)
1791                         prev_st->RxPWDBAll -= 3;
1792         }
1793
1794         RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
1795                                 prev_st->bIsCCK ? "CCK" : "OFDM",
1796                                 prev_st->RxPWDBAll);
1797
1798         if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1799             prev_st->bToSelfBA) {
1800                 if (priv->undecorated_smoothed_pwdb < 0)
1801                         priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1802                 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1803                         priv->undecorated_smoothed_pwdb =
1804                                         (((priv->undecorated_smoothed_pwdb) *
1805                                         (RX_SMOOTH-1)) +
1806                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1807                         priv->undecorated_smoothed_pwdb =
1808                                          priv->undecorated_smoothed_pwdb + 1;
1809                 } else {
1810                         priv->undecorated_smoothed_pwdb =
1811                                         (((priv->undecorated_smoothed_pwdb) *
1812                                         (RX_SMOOTH-1)) +
1813                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1814                 }
1815                 rtl92e_update_rx_statistics(priv, prev_st);
1816         }
1817
1818         if (prev_st->SignalQuality != 0) {
1819                 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1820                     prev_st->bToSelfBA) {
1821                         if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1822                                 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1823                                 last_evm =
1824                                          priv->stats.slide_evm[slide_evm_index];
1825                                 priv->stats.slide_evm_total -= last_evm;
1826                         }
1827
1828                         priv->stats.slide_evm_total += prev_st->SignalQuality;
1829
1830                         priv->stats.slide_evm[slide_evm_index++] =
1831                                                  prev_st->SignalQuality;
1832                         if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1833                                 slide_evm_index = 0;
1834
1835                         tmp_val = priv->stats.slide_evm_total /
1836                                   slide_evm_statistics;
1837                         priv->stats.signal_quality = tmp_val;
1838                         priv->stats.last_signal_strength_inpercent = tmp_val;
1839                 }
1840
1841                 if (prev_st->bPacketToSelf ||
1842                     prev_st->bPacketBeacon ||
1843                     prev_st->bToSelfBA) {
1844                         for (ij = 0; ij < 2; ij++) {
1845                                 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1846                                         if (priv->stats.rx_evm_percentage[ij] == 0)
1847                                                 priv->stats.rx_evm_percentage[ij] =
1848                                                    prev_st->RxMIMOSignalQuality[ij];
1849                                         priv->stats.rx_evm_percentage[ij] =
1850                                           ((priv->stats.rx_evm_percentage[ij] *
1851                                           (RX_SMOOTH - 1)) +
1852                                           (prev_st->RxMIMOSignalQuality[ij])) /
1853                                           (RX_SMOOTH);
1854                                 }
1855                         }
1856                 }
1857         }
1858 }
1859
1860 static void _rtl92e_translate_rx_signal_stats(struct net_device *dev,
1861                                               struct sk_buff *skb,
1862                                               struct rtllib_rx_stats *pstats,
1863                                               struct rx_desc *pdesc,
1864                                               struct rx_fwinfo *pdrvinfo)
1865 {
1866         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1867         bool bpacket_match_bssid, bpacket_toself;
1868         bool bPacketBeacon = false;
1869         struct rtllib_hdr_3addr *hdr;
1870         bool bToSelfBA = false;
1871         static struct rtllib_rx_stats  previous_stats;
1872         u16 fc, type;
1873         u8 *tmp_buf;
1874         u8 *praddr;
1875
1876         tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1877
1878         hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1879         fc = le16_to_cpu(hdr->frame_ctl);
1880         type = WLAN_FC_GET_TYPE(fc);
1881         praddr = hdr->addr1;
1882
1883         bpacket_match_bssid =
1884                 ((type != RTLLIB_FTYPE_CTL) &&
1885                  ether_addr_equal(priv->rtllib->current_network.bssid,
1886                                   (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1887                                   (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1888                                   hdr->addr3) &&
1889                  (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1890         bpacket_toself = bpacket_match_bssid &&         /* check this */
1891                          ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1892         if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1893                 bPacketBeacon = true;
1894         if (bpacket_match_bssid)
1895                 priv->stats.numpacket_matchbssid++;
1896         if (bpacket_toself)
1897                 priv->stats.numpacket_toself++;
1898         _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1899         _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1900                                   &previous_stats, bpacket_match_bssid,
1901                                   bpacket_toself, bPacketBeacon, bToSelfBA);
1902         rtl92e_copy_mpdu_stats(pstats, &previous_stats);
1903 }
1904
1905 static void _rtl92e_update_received_rate_histogram_stats(
1906                                            struct net_device *dev,
1907                                            struct rtllib_rx_stats *pstats)
1908 {
1909         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1910         u32 rcvType = 1;
1911         u32 rateIndex;
1912         u32 preamble_guardinterval;
1913
1914         if (pstats->bCRC)
1915                 rcvType = 2;
1916         else if (pstats->bICV)
1917                 rcvType = 3;
1918
1919         if (pstats->bShortPreamble)
1920                 preamble_guardinterval = 1;
1921         else
1922                 preamble_guardinterval = 0;
1923
1924         switch (pstats->rate) {
1925         case MGN_1M:
1926                 rateIndex = 0;
1927                 break;
1928         case MGN_2M:
1929                 rateIndex = 1;
1930                  break;
1931         case MGN_5_5M:
1932                 rateIndex = 2;
1933                 break;
1934         case MGN_11M:
1935                 rateIndex = 3;
1936                 break;
1937         case MGN_6M:
1938                 rateIndex = 4;
1939                 break;
1940         case MGN_9M:
1941                 rateIndex = 5;
1942                 break;
1943         case MGN_12M:
1944                 rateIndex = 6;
1945                 break;
1946         case MGN_18M:
1947                 rateIndex = 7;
1948                  break;
1949         case MGN_24M:
1950                 rateIndex = 8;
1951                 break;
1952         case MGN_36M:
1953                 rateIndex = 9;
1954                 break;
1955         case MGN_48M:
1956                 rateIndex = 10;
1957                 break;
1958         case MGN_54M:
1959                 rateIndex = 11;
1960                 break;
1961         case MGN_MCS0:
1962                 rateIndex = 12;
1963                 break;
1964         case MGN_MCS1:
1965                 rateIndex = 13;
1966                 break;
1967         case MGN_MCS2:
1968                 rateIndex = 14;
1969                 break;
1970         case MGN_MCS3:
1971                 rateIndex = 15;
1972                 break;
1973         case MGN_MCS4:
1974                 rateIndex = 16;
1975                 break;
1976         case MGN_MCS5:
1977                 rateIndex = 17;
1978                 break;
1979         case MGN_MCS6:
1980                 rateIndex = 18;
1981                 break;
1982         case MGN_MCS7:
1983                 rateIndex = 19;
1984                 break;
1985         case MGN_MCS8:
1986                 rateIndex = 20;
1987                 break;
1988         case MGN_MCS9:
1989                 rateIndex = 21;
1990                 break;
1991         case MGN_MCS10:
1992                 rateIndex = 22;
1993                 break;
1994         case MGN_MCS11:
1995                 rateIndex = 23;
1996                 break;
1997         case MGN_MCS12:
1998                 rateIndex = 24;
1999                 break;
2000         case MGN_MCS13:
2001                 rateIndex = 25;
2002                 break;
2003         case MGN_MCS14:
2004                 rateIndex = 26;
2005                 break;
2006         case MGN_MCS15:
2007                 rateIndex = 27;
2008                 break;
2009         default:
2010                 rateIndex = 28;
2011                 break;
2012         }
2013         priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
2014         priv->stats.received_rate_histogram[0][rateIndex]++;
2015         priv->stats.received_rate_histogram[rcvType][rateIndex]++;
2016 }
2017
2018 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats,
2019                          struct rx_desc *pdesc, struct sk_buff *skb)
2020 {
2021         struct r8192_priv *priv = rtllib_priv(dev);
2022         struct rx_fwinfo *pDrvInfo = NULL;
2023
2024         stats->bICV = pdesc->ICV;
2025         stats->bCRC = pdesc->CRC32;
2026         stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2027
2028         stats->Length = pdesc->Length;
2029         if (stats->Length < 24)
2030                 stats->bHwError |= 1;
2031
2032         if (stats->bHwError) {
2033                 stats->bShift = false;
2034
2035                 if (pdesc->CRC32) {
2036                         if (pdesc->Length < 500)
2037                                 priv->stats.rxcrcerrmin++;
2038                         else if (pdesc->Length > 1000)
2039                                 priv->stats.rxcrcerrmax++;
2040                         else
2041                                 priv->stats.rxcrcerrmid++;
2042                 }
2043                 return false;
2044         }
2045
2046         stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2047         stats->RxBufShift = ((pdesc->Shift)&0x03);
2048         stats->Decrypted = !pdesc->SWDec;
2049
2050         pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
2051
2052         stats->rate = _rtl92e_rate_hw_to_mgn((bool)pDrvInfo->RxHT,
2053                                              (u8)pDrvInfo->RxRate);
2054         stats->bShortPreamble = pDrvInfo->SPLCP;
2055
2056         _rtl92e_update_received_rate_histogram_stats(dev, stats);
2057
2058         stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2059         stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2060                             (pDrvInfo->FirstAGGR == 1);
2061
2062         stats->TimeStampLow = pDrvInfo->TSFL;
2063         stats->TimeStampHigh = rtl92e_readl(dev, TSFR+4);
2064
2065         rtl92e_update_rx_pkt_timestamp(dev, stats);
2066
2067         if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2068                 stats->bShift = 1;
2069
2070         stats->RxIs40MHzPacket = pDrvInfo->BW;
2071
2072         _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo);
2073
2074         if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2075                 RT_TRACE(COMP_RXDESC,
2076                          "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n",
2077                          pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2078         skb_trim(skb, skb->len - 4/*sCrcLng*/);
2079
2080
2081         stats->packetlength = stats->Length-4;
2082         stats->fraglength = stats->packetlength;
2083         stats->fragoffset = 0;
2084         stats->ntotalfrag = 1;
2085         return true;
2086 }
2087
2088 void rtl92e_stop_adapter(struct net_device *dev, bool reset)
2089 {
2090         struct r8192_priv *priv = rtllib_priv(dev);
2091         int i;
2092         u8      OpMode;
2093         u8      u1bTmp;
2094         u32     ulRegRead;
2095
2096         OpMode = RT_OP_MODE_NO_LINK;
2097         priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2098
2099         if (!priv->rtllib->bSupportRemoteWakeUp) {
2100                 u1bTmp = 0x0;
2101                 rtl92e_writeb(dev, CMDR, u1bTmp);
2102         }
2103
2104         mdelay(20);
2105
2106         if (!reset) {
2107                 mdelay(150);
2108
2109                 priv->bHwRfOffAction = 2;
2110
2111                 if (!priv->rtllib->bSupportRemoteWakeUp) {
2112                         rtl92e_set_rf_off(dev);
2113                         ulRegRead = rtl92e_readl(dev, CPU_GEN);
2114                         ulRegRead |= CPU_GEN_SYSTEM_RESET;
2115                         rtl92e_writel(dev, CPU_GEN, ulRegRead);
2116                 } else {
2117                         rtl92e_writel(dev, WFCRC0, 0xffffffff);
2118                         rtl92e_writel(dev, WFCRC1, 0xffffffff);
2119                         rtl92e_writel(dev, WFCRC2, 0xffffffff);
2120
2121
2122                         rtl92e_writeb(dev, PMR, 0x5);
2123                         rtl92e_writeb(dev, MacBlkCtrl, 0xa);
2124                 }
2125         }
2126
2127         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2128                 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2129         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2130                 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
2131
2132         skb_queue_purge(&priv->skb_queue);
2133 }
2134
2135 void rtl92e_update_ratr_table(struct net_device *dev)
2136 {
2137         struct r8192_priv *priv = rtllib_priv(dev);
2138         struct rtllib_device *ieee = priv->rtllib;
2139         u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
2140         u32 ratr_value = 0;
2141         u16 rate_config = 0;
2142         u8 rate_index = 0;
2143
2144         rtl92e_config_rate(dev, &rate_config);
2145         ratr_value = rate_config | *pMcsRate << 12;
2146         switch (ieee->mode) {
2147         case IEEE_A:
2148                 ratr_value &= 0x00000FF0;
2149                 break;
2150         case IEEE_B:
2151                 ratr_value &= 0x0000000F;
2152                 break;
2153         case IEEE_G:
2154         case IEEE_G|IEEE_B:
2155                 ratr_value &= 0x00000FF7;
2156                 break;
2157         case IEEE_N_24G:
2158         case IEEE_N_5G:
2159                 if (ieee->pHTInfo->PeerMimoPs == 0) {
2160                         ratr_value &= 0x0007F007;
2161                 } else {
2162                         if (priv->rf_type == RF_1T2R)
2163                                 ratr_value &= 0x000FF007;
2164                         else
2165                                 ratr_value &= 0x0F81F007;
2166                 }
2167                 break;
2168         default:
2169                 break;
2170         }
2171         ratr_value &= 0x0FFFFFFF;
2172         if (ieee->pHTInfo->bCurTxBW40MHz &&
2173             ieee->pHTInfo->bCurShortGI40MHz)
2174                 ratr_value |= 0x80000000;
2175         else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2176                   ieee->pHTInfo->bCurShortGI20MHz)
2177                 ratr_value |= 0x80000000;
2178         rtl92e_writel(dev, RATR0+rate_index*4, ratr_value);
2179         rtl92e_writeb(dev, UFWP, 1);
2180 }
2181
2182 void
2183 rtl92e_init_variables(struct net_device  *dev)
2184 {
2185         struct r8192_priv *priv = rtllib_priv(dev);
2186
2187         strcpy(priv->nick, "rtl8192E");
2188
2189         priv->rtllib->softmac_features  = IEEE_SOFTMAC_SCAN |
2190                 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2191                 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2192
2193         priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2194
2195         priv->ShortRetryLimit = 0x30;
2196         priv->LongRetryLimit = 0x30;
2197
2198         priv->ReceiveConfig = RCR_ADD3  |
2199                 RCR_AMF | RCR_ADF |
2200                 RCR_AICV |
2201                 RCR_AB | RCR_AM | RCR_APM |
2202                 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2203                 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2204
2205         priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2206                             IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2207                             IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2208                             IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2209                             IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2210                             IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2211
2212         priv->PwrDomainProtect = false;
2213
2214         priv->bfirst_after_down = false;
2215 }
2216
2217 void rtl92e_enable_irq(struct net_device *dev)
2218 {
2219         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2220
2221         priv->irq_enabled = 1;
2222
2223         rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]);
2224
2225 }
2226
2227 void rtl92e_disable_irq(struct net_device *dev)
2228 {
2229         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2230
2231         rtl92e_writel(dev, INTA_MASK, 0);
2232
2233         priv->irq_enabled = 0;
2234 }
2235
2236 void rtl92e_clear_irq(struct net_device *dev)
2237 {
2238         u32 tmp = 0;
2239
2240         tmp = rtl92e_readl(dev, ISR);
2241         rtl92e_writel(dev, ISR, tmp);
2242 }
2243
2244
2245 void rtl92e_enable_rx(struct net_device *dev)
2246 {
2247         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2248
2249         rtl92e_writel(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2250 }
2251
2252 static const u32 TX_DESC_BASE[] = {
2253         BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2254 };
2255
2256 void rtl92e_enable_tx(struct net_device *dev)
2257 {
2258         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2259         u32 i;
2260
2261         for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2262                 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2263 }
2264
2265
2266 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta, u32 *p_intb)
2267 {
2268         *p_inta = rtl92e_readl(dev, ISR);
2269         rtl92e_writel(dev, ISR, *p_inta);
2270 }
2271
2272 bool rtl92e_is_rx_stuck(struct net_device *dev)
2273 {
2274         struct r8192_priv *priv = rtllib_priv(dev);
2275         u16               RegRxCounter = rtl92e_readw(dev, 0x130);
2276         bool              bStuck = false;
2277         static u8         rx_chk_cnt;
2278         u32             SlotIndex = 0, TotalRxStuckCount = 0;
2279         u8              i;
2280         u8              SilentResetRxSoltNum = 4;
2281
2282         RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2283                  __func__, RegRxCounter, priv->RxCounter);
2284
2285         rx_chk_cnt++;
2286         if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2287                 rx_chk_cnt = 0;
2288         } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2289           && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2290           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2291           || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2292           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2293                 if (rx_chk_cnt < 2)
2294                         return bStuck;
2295                 rx_chk_cnt = 0;
2296         } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2297                   (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2298                 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2299                  (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2300                 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2301                 if (rx_chk_cnt < 4)
2302                         return bStuck;
2303                 rx_chk_cnt = 0;
2304         } else {
2305                 if (rx_chk_cnt < 8)
2306                         return bStuck;
2307                 rx_chk_cnt = 0;
2308         }
2309
2310
2311         SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2312
2313         if (priv->RxCounter == RegRxCounter) {
2314                 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2315
2316                 for (i = 0; i < SilentResetRxSoltNum; i++)
2317                         TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2318
2319                 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2320                         bStuck = true;
2321                         for (i = 0; i < SilentResetRxSoltNum; i++)
2322                                 TotalRxStuckCount +=
2323                                          priv->SilentResetRxStuckEvent[i];
2324                 }
2325
2326
2327         } else {
2328                 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2329         }
2330
2331         priv->RxCounter = RegRxCounter;
2332
2333         return bStuck;
2334 }
2335
2336 bool rtl92e_is_tx_stuck(struct net_device *dev)
2337 {
2338         struct r8192_priv *priv = rtllib_priv(dev);
2339         bool    bStuck = false;
2340         u16     RegTxCounter = rtl92e_readw(dev, 0x128);
2341
2342         RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
2343                  __func__, RegTxCounter, priv->TxCounter);
2344
2345         if (priv->TxCounter == RegTxCounter)
2346                 bStuck = true;
2347
2348         priv->TxCounter = RegTxCounter;
2349
2350         return bStuck;
2351 }
2352
2353 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev)
2354 {
2355         struct r8192_priv *priv = rtllib_priv(dev);
2356         struct rtllib_device *ieee = priv->rtllib;
2357
2358         if (ieee->rtllib_ap_sec_type &&
2359            (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2360                                      SEC_ALG_TKIP))) {
2361                 return false;
2362         } else {
2363                 return true;
2364         }
2365 }
2366
2367 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev)
2368 {
2369         struct r8192_priv *priv = rtllib_priv(dev);
2370         struct rtllib_device *ieee = priv->rtllib;
2371
2372         return ieee->bHalfWirelessN24GMode;
2373 }