kernel/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * Based on the r8180 driver, which is:
   5  * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  18  *
  19  * The full GNU General Public License is included in this distribution in the
  20  * file called LICENSE.
  21  *
  22  * Contact Information:
  23  * wlanfae <wlanfae@realtek.com>
  24 ******************************************************************************/
  25 #include "rtl_core.h"
  26 #include "r8192E_phy.h"
  27 #include "r8192E_phyreg.h"
  28 #include "r8190P_rtl8256.h"
  29 #include "r8192E_cmdpkt.h"
  30 #include "rtl_dm.h"
  31 #include "rtl_wx.h"
  32
  33 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI, EDCAPARA_VO};
  34
  35 void rtl8192e_start_beacon(struct net_device *dev)
  36 {
  37         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
  38         struct rtllib_network *net = &priv->rtllib->current_network;
  39         u16 BcnTimeCfg = 0;
  40         u16 BcnCW = 6;
  41         u16 BcnIFS = 0xf;
  42
  43         DMESG("Enabling beacon TX");
  44         rtl8192_irq_disable(dev);
  45
  46         write_nic_word(dev, ATIMWND, 2);
  47
  48         write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
  49         write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
  50         write_nic_word(dev, BCN_DMATIME, 256);
  51
  52         write_nic_byte(dev, BCN_ERR_THRESH, 100);
  53
  54         BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
  55         BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
  56         write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
  57         rtl8192_irq_enable(dev);
  58 }
  59
  60 static void rtl8192e_update_msr(struct net_device *dev)
  61 {
  62         struct r8192_priv *priv = rtllib_priv(dev);
  63         u8 msr;
  64         enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
  65
  66         msr  = read_nic_byte(dev, MSR);
  67         msr &= ~MSR_LINK_MASK;
  68
  69         switch (priv->rtllib->iw_mode) {
  70         case IW_MODE_INFRA:
  71                 if (priv->rtllib->state == RTLLIB_LINKED)
  72                         msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
  73                 else
  74                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  75                 LedAction = LED_CTL_LINK;
  76                 break;
  77         case IW_MODE_ADHOC:
  78                 if (priv->rtllib->state == RTLLIB_LINKED)
  79                         msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
  80                 else
  81                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  82                 break;
  83         case IW_MODE_MASTER:
  84                 if (priv->rtllib->state == RTLLIB_LINKED)
  85                         msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
  86                 else
  87                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  88                 break;
  89         default:
  90                 break;
  91         }
  92
  93         write_nic_byte(dev, MSR, msr);
  94         if (priv->rtllib->LedControlHandler)
  95                 priv->rtllib->LedControlHandler(dev, LedAction);
  96 }
  97
  98 void rtl8192e_SetHwReg(struct net_device *dev, u8 variable, u8 *val)
  99 {
 100         struct r8192_priv *priv = rtllib_priv(dev);
 101
 102         switch (variable) {
 103         case HW_VAR_BSSID:
 104                 write_nic_dword(dev, BSSIDR, ((u32 *)(val))[0]);
 105                 write_nic_word(dev, BSSIDR+2, ((u16 *)(val+2))[0]);
 106                 break;
 107
 108         case HW_VAR_MEDIA_STATUS:
 109         {
 110                 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
 111                 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
 112                 u8              btMsr = read_nic_byte(dev, MSR);
 113
 114                 btMsr &= 0xfc;
 115
 116                 switch (OpMode) {
 117                 case RT_OP_MODE_INFRASTRUCTURE:
 118                         btMsr |= MSR_INFRA;
 119                         LedAction = LED_CTL_LINK;
 120                         break;
 121
 122                 case RT_OP_MODE_IBSS:
 123                         btMsr |= MSR_ADHOC;
 124                         break;
 125
 126                 case RT_OP_MODE_AP:
 127                         btMsr |= MSR_AP;
 128                         LedAction = LED_CTL_LINK;
 129                         break;
 130
 131                 default:
 132                         btMsr |= MSR_NOLINK;
 133                         break;
 134                 }
 135
 136                 write_nic_byte(dev, MSR, btMsr);
 137
 138         }
 139         break;
 140
 141         case HW_VAR_CECHK_BSSID:
 142         {
 143                 u32     RegRCR, Type;
 144
 145                 Type = ((u8 *)(val))[0];
 146                 RegRCR = read_nic_dword(dev, RCR);
 147                 priv->ReceiveConfig = RegRCR;
 148
 149                 if (Type == true)
 150                         RegRCR |= (RCR_CBSSID);
 151                 else if (Type == false)
 152                         RegRCR &= (~RCR_CBSSID);
 153
 154                 write_nic_dword(dev, RCR, RegRCR);
 155                 priv->ReceiveConfig = RegRCR;
 156
 157         }
 158         break;
 159
 160         case HW_VAR_SLOT_TIME:
 161
 162                 priv->slot_time = val[0];
 163                 write_nic_byte(dev, SLOT_TIME, val[0]);
 164
 165                 break;
 166
 167         case HW_VAR_ACK_PREAMBLE:
 168         {
 169                 u32 regTmp;
 170
 171                 priv->short_preamble = (bool)(*(u8 *)val);
 172                 regTmp = priv->basic_rate;
 173                 if (priv->short_preamble)
 174                         regTmp |= BRSR_AckShortPmb;
 175                 write_nic_dword(dev, RRSR, regTmp);
 176                 break;
 177         }
 178
 179         case HW_VAR_CPU_RST:
 180                 write_nic_dword(dev, CPU_GEN, ((u32 *)(val))[0]);
 181                 break;
 182
 183         case HW_VAR_AC_PARAM:
 184         {
 185                 u8      pAcParam = *((u8 *)val);
 186                 u32     eACI = pAcParam;
 187                 u8              u1bAIFS;
 188                 u32             u4bAcParam;
 189                 u8 mode = priv->rtllib->mode;
 190                 struct rtllib_qos_parameters *qos_parameters =
 191                          &priv->rtllib->current_network.qos_data.parameters;
 192
 193                 u1bAIFS = qos_parameters->aifs[pAcParam] *
 194                           ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
 195
 196                 dm_init_edca_turbo(dev);
 197
 198                 u4bAcParam = (((le16_to_cpu(
 199                                         qos_parameters->tx_op_limit[pAcParam])) <<
 200                              AC_PARAM_TXOP_LIMIT_OFFSET) |
 201                              ((le16_to_cpu(qos_parameters->cw_max[pAcParam])) <<
 202                              AC_PARAM_ECW_MAX_OFFSET) |
 203                              ((le16_to_cpu(qos_parameters->cw_min[pAcParam])) <<
 204                              AC_PARAM_ECW_MIN_OFFSET) |
 205                              (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
 206
 207                 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
 208                          __func__, eACI, u4bAcParam);
 209                 switch (eACI) {
 210                 case AC1_BK:
 211                         write_nic_dword(dev, EDCAPARA_BK, u4bAcParam);
 212                         break;
 213
 214                 case AC0_BE:
 215                         write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
 216                         break;
 217
 218                 case AC2_VI:
 219                         write_nic_dword(dev, EDCAPARA_VI, u4bAcParam);
 220                         break;
 221
 222                 case AC3_VO:
 223                         write_nic_dword(dev, EDCAPARA_VO, u4bAcParam);
 224                         break;
 225
 226                 default:
 227                         netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
 228                                     eACI);
 229                         break;
 230                 }
 231                 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
 232                                               (u8 *)(&pAcParam));
 233                 break;
 234         }
 235
 236         case HW_VAR_ACM_CTRL:
 237         {
 238                 struct rtllib_qos_parameters *qos_parameters =
 239                          &priv->rtllib->current_network.qos_data.parameters;
 240                 u8 pAcParam = *((u8 *)val);
 241                 u32 eACI = pAcParam;
 242                 union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
 243                                               (qos_parameters->aifs[0]);
 244                 u8 acm = pAciAifsn->f.acm;
 245                 u8 AcmCtrl = read_nic_byte(dev, AcmHwCtrl);
 246
 247                 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
 248                          __func__, eACI);
 249                 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
 250
 251                 if (acm) {
 252                         switch (eACI) {
 253                         case AC0_BE:
 254                                 AcmCtrl |= AcmHw_BeqEn;
 255                                 break;
 256
 257                         case AC2_VI:
 258                                 AcmCtrl |= AcmHw_ViqEn;
 259                                 break;
 260
 261                         case AC3_VO:
 262                                 AcmCtrl |= AcmHw_VoqEn;
 263                                 break;
 264
 265                         default:
 266                                 RT_TRACE(COMP_QOS,
 267                                          "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n",
 268                                          eACI);
 269                                 break;
 270                         }
 271                 } else {
 272                         switch (eACI) {
 273                         case AC0_BE:
 274                                 AcmCtrl &= (~AcmHw_BeqEn);
 275                                 break;
 276
 277                         case AC2_VI:
 278                                 AcmCtrl &= (~AcmHw_ViqEn);
 279                                 break;
 280
 281                         case AC3_VO:
 282                                 AcmCtrl &= (~AcmHw_BeqEn);
 283                                 break;
 284
 285                         default:
 286                                 break;
 287                         }
 288                 }
 289
 290                 RT_TRACE(COMP_QOS,
 291                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 292                          AcmCtrl);
 293                 write_nic_byte(dev, AcmHwCtrl, AcmCtrl);
 294                 break;
 295         }
 296
 297         case HW_VAR_SIFS:
 298                 write_nic_byte(dev, SIFS, val[0]);
 299                 write_nic_byte(dev, SIFS+1, val[0]);
 300                 break;
 301
 302         case HW_VAR_RF_TIMING:
 303         {
 304                 u8 Rf_Timing = *((u8 *)val);
 305
 306                 write_nic_byte(dev, rFPGA0_RFTiming1, Rf_Timing);
 307                 break;
 308         }
 309
 310         default:
 311                 break;
 312         }
 313
 314 }
 315
 316 static void rtl8192_read_eeprom_info(struct net_device *dev)
 317 {
 318         struct r8192_priv *priv = rtllib_priv(dev);
 319
 320         u8 tempval;
 321         u8 ICVer8192, ICVer8256;
 322         u16 i, usValue, IC_Version;
 323         u16 EEPROMId;
 324         u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
 325
 326         RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n");
 327
 328         EEPROMId = eprom_read(dev, 0);
 329         if (EEPROMId != RTL8190_EEPROM_ID) {
 330                 RT_TRACE(COMP_ERR, "EEPROM ID is invalid:%x, %x\n",
 331                          EEPROMId, RTL8190_EEPROM_ID);
 332                 priv->AutoloadFailFlag = true;
 333         } else {
 334                 priv->AutoloadFailFlag = false;
 335         }
 336
 337         if (!priv->AutoloadFailFlag) {
 338                 priv->eeprom_vid = eprom_read(dev, EEPROM_VID >> 1);
 339                 priv->eeprom_did = eprom_read(dev, EEPROM_DID >> 1);
 340
 341                 usValue = eprom_read(dev, (u16)(EEPROM_Customer_ID>>1)) >> 8;
 342                 priv->eeprom_CustomerID = (u8)(usValue & 0xff);
 343                 usValue = eprom_read(dev, EEPROM_ICVersion_ChannelPlan>>1);
 344                 priv->eeprom_ChannelPlan = usValue&0xff;
 345                 IC_Version = (usValue & 0xff00)>>8;
 346
 347                 ICVer8192 = (IC_Version&0xf);
 348                 ICVer8256 = (IC_Version & 0xf0)>>4;
 349                 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
 350                 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
 351                 if (ICVer8192 == 0x2) {
 352                         if (ICVer8256 == 0x5)
 353                                 priv->card_8192_version = VERSION_8190_BE;
 354                 }
 355                 switch (priv->card_8192_version) {
 356                 case VERSION_8190_BD:
 357                 case VERSION_8190_BE:
 358                         break;
 359                 default:
 360                         priv->card_8192_version = VERSION_8190_BD;
 361                         break;
 362                 }
 363                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
 364                           priv->card_8192_version);
 365         } else {
 366                 priv->card_8192_version = VERSION_8190_BD;
 367                 priv->eeprom_vid = 0;
 368                 priv->eeprom_did = 0;
 369                 priv->eeprom_CustomerID = 0;
 370                 priv->eeprom_ChannelPlan = 0;
 371                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
 372         }
 373
 374         RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
 375         RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
 376         RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
 377                  priv->eeprom_CustomerID);
 378
 379         if (!priv->AutoloadFailFlag) {
 380                 for (i = 0; i < 6; i += 2) {
 381                         usValue = eprom_read(dev,
 382                                  (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1));
 383                         *(u16 *)(&dev->dev_addr[i]) = usValue;
 384                 }
 385         } else {
 386                 memcpy(dev->dev_addr, bMac_Tmp_Addr, 6);
 387         }
 388
 389         RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
 390                  dev->dev_addr);
 391
 392         if (priv->card_8192_version > VERSION_8190_BD)
 393                 priv->bTXPowerDataReadFromEEPORM = true;
 394         else
 395                 priv->bTXPowerDataReadFromEEPORM = false;
 396
 397         priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
 398
 399         if (priv->card_8192_version > VERSION_8190_BD) {
 400                 if (!priv->AutoloadFailFlag) {
 401                         tempval = (eprom_read(dev, (EEPROM_RFInd_PowerDiff >>
 402                                               1))) & 0xff;
 403                         priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
 404
 405                         if (tempval&0x80)
 406                                 priv->rf_type = RF_1T2R;
 407                         else
 408                                 priv->rf_type = RF_2T4R;
 409                 } else {
 410                         priv->EEPROMLegacyHTTxPowerDiff = 0x04;
 411                 }
 412                 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
 413                         priv->EEPROMLegacyHTTxPowerDiff);
 414
 415                 if (!priv->AutoloadFailFlag)
 416                         priv->EEPROMThermalMeter = (u8)(((eprom_read(dev,
 417                                                    (EEPROM_ThermalMeter>>1))) &
 418                                                    0xff00)>>8);
 419                 else
 420                         priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
 421                 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
 422                          priv->EEPROMThermalMeter);
 423                 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
 424
 425                 if (priv->epromtype == EEPROM_93C46) {
 426                         if (!priv->AutoloadFailFlag) {
 427                                 usValue = eprom_read(dev,
 428                                           EEPROM_TxPwDiff_CrystalCap >> 1);
 429                                 priv->EEPROMAntPwDiff = (usValue&0x0fff);
 430                                 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
 431                                                          >> 12);
 432                         } else {
 433                                 priv->EEPROMAntPwDiff =
 434                                          EEPROM_Default_AntTxPowerDiff;
 435                                 priv->EEPROMCrystalCap =
 436                                          EEPROM_Default_TxPwDiff_CrystalCap;
 437                         }
 438                         RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
 439                                  priv->EEPROMAntPwDiff);
 440                         RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
 441                                  priv->EEPROMCrystalCap);
 442
 443                         for (i = 0; i < 14; i += 2) {
 444                                 if (!priv->AutoloadFailFlag)
 445                                         usValue = eprom_read(dev,
 446                                                   (u16)((EEPROM_TxPwIndex_CCK +
 447                                                   i) >> 1));
 448                                 else
 449                                         usValue = EEPROM_Default_TxPower;
 450                                 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
 451                                                                  usValue;
 452                                 RT_TRACE(COMP_INIT,
 453                                          "CCK Tx Power Level, Index %d = 0x%02x\n",
 454                                          i, priv->EEPROMTxPowerLevelCCK[i]);
 455                                 RT_TRACE(COMP_INIT,
 456                                          "CCK Tx Power Level, Index %d = 0x%02x\n",
 457                                          i+1, priv->EEPROMTxPowerLevelCCK[i+1]);
 458                         }
 459                         for (i = 0; i < 14; i += 2) {
 460                                 if (!priv->AutoloadFailFlag)
 461                                         usValue = eprom_read(dev,
 462                                                 (u16)((EEPROM_TxPwIndex_OFDM_24G
 463                                                 + i) >> 1));
 464                                 else
 465                                         usValue = EEPROM_Default_TxPower;
 466                                 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
 467                                                          = usValue;
 468                                 RT_TRACE(COMP_INIT,
 469                                          "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
 470                                          i, priv->EEPROMTxPowerLevelOFDM24G[i]);
 471                                 RT_TRACE(COMP_INIT,
 472                                          "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
 473                                          i + 1,
 474                                          priv->EEPROMTxPowerLevelOFDM24G[i+1]);
 475                         }
 476                 }
 477                 if (priv->epromtype == EEPROM_93C46) {
 478                         for (i = 0; i < 14; i++) {
 479                                 priv->TxPowerLevelCCK[i] =
 480                                          priv->EEPROMTxPowerLevelCCK[i];
 481                                 priv->TxPowerLevelOFDM24G[i] =
 482                                          priv->EEPROMTxPowerLevelOFDM24G[i];
 483                         }
 484                         priv->LegacyHTTxPowerDiff =
 485                                          priv->EEPROMLegacyHTTxPowerDiff;
 486                         priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff &
 487                                                     0xf);
 488                         priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff &
 489                                                         0xf0) >> 4;
 490                         priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff &
 491                                                         0xf00) >> 8;
 492                         priv->CrystalCap = priv->EEPROMCrystalCap;
 493                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 494                                                  0xf);
 495                         priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
 496                                                      0xf0) >> 4;
 497                 } else if (priv->epromtype == EEPROM_93C56) {
 498
 499                         for (i = 0; i < 3; i++) {
 500                                 priv->TxPowerLevelCCK_A[i] =
 501                                          priv->EEPROMRfACCKChnl1TxPwLevel[0];
 502                                 priv->TxPowerLevelOFDM24G_A[i] =
 503                                          priv->EEPROMRfAOfdmChnlTxPwLevel[0];
 504                                 priv->TxPowerLevelCCK_C[i] =
 505                                          priv->EEPROMRfCCCKChnl1TxPwLevel[0];
 506                                 priv->TxPowerLevelOFDM24G_C[i] =
 507                                          priv->EEPROMRfCOfdmChnlTxPwLevel[0];
 508                         }
 509                         for (i = 3; i < 9; i++) {
 510                                 priv->TxPowerLevelCCK_A[i]  =
 511                                          priv->EEPROMRfACCKChnl1TxPwLevel[1];
 512                                 priv->TxPowerLevelOFDM24G_A[i] =
 513                                          priv->EEPROMRfAOfdmChnlTxPwLevel[1];
 514                                 priv->TxPowerLevelCCK_C[i] =
 515                                          priv->EEPROMRfCCCKChnl1TxPwLevel[1];
 516                                 priv->TxPowerLevelOFDM24G_C[i] =
 517                                          priv->EEPROMRfCOfdmChnlTxPwLevel[1];
 518                         }
 519                         for (i = 9; i < 14; i++) {
 520                                 priv->TxPowerLevelCCK_A[i]  =
 521                                          priv->EEPROMRfACCKChnl1TxPwLevel[2];
 522                                 priv->TxPowerLevelOFDM24G_A[i] =
 523                                          priv->EEPROMRfAOfdmChnlTxPwLevel[2];
 524                                 priv->TxPowerLevelCCK_C[i] =
 525                                          priv->EEPROMRfCCCKChnl1TxPwLevel[2];
 526                                 priv->TxPowerLevelOFDM24G_C[i] =
 527                                          priv->EEPROMRfCOfdmChnlTxPwLevel[2];
 528                         }
 529                         for (i = 0; i < 14; i++)
 530                                 RT_TRACE(COMP_INIT,
 531                                          "priv->TxPowerLevelCCK_A[%d] = 0x%x\n",
 532                                          i, priv->TxPowerLevelCCK_A[i]);
 533                         for (i = 0; i < 14; i++)
 534                                 RT_TRACE(COMP_INIT,
 535                                          "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n",
 536                                          i, priv->TxPowerLevelOFDM24G_A[i]);
 537                         for (i = 0; i < 14; i++)
 538                                 RT_TRACE(COMP_INIT,
 539                                          "priv->TxPowerLevelCCK_C[%d] = 0x%x\n",
 540                                          i, priv->TxPowerLevelCCK_C[i]);
 541                         for (i = 0; i < 14; i++)
 542                                 RT_TRACE(COMP_INIT,
 543                                          "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n",
 544                                          i, priv->TxPowerLevelOFDM24G_C[i]);
 545                         priv->LegacyHTTxPowerDiff =
 546                                  priv->EEPROMLegacyHTTxPowerDiff;
 547                         priv->AntennaTxPwDiff[0] = 0;
 548                         priv->AntennaTxPwDiff[1] = 0;
 549                         priv->AntennaTxPwDiff[2] = 0;
 550                         priv->CrystalCap = priv->EEPROMCrystalCap;
 551                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 552                                                  0xf);
 553                         priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
 554                                                      0xf0) >> 4;
 555                 }
 556         }
 557
 558         if (priv->rf_type == RF_1T2R) {
 559                 /* no matter what checkpatch says, the braces are needed */
 560                 RT_TRACE(COMP_INIT, "\n1T2R config\n");
 561         } else if (priv->rf_type == RF_2T4R) {
 562                 RT_TRACE(COMP_INIT, "\n2T4R config\n");
 563         }
 564
 565         init_rate_adaptive(dev);
 566
 567         priv->rf_chip = RF_8256;
 568
 569         if (priv->RegChannelPlan == 0xf)
 570                 priv->ChannelPlan = priv->eeprom_ChannelPlan;
 571         else
 572                 priv->ChannelPlan = priv->RegChannelPlan;
 573
 574         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 575                 priv->CustomerID =  RT_CID_DLINK;
 576
 577         switch (priv->eeprom_CustomerID) {
 578         case EEPROM_CID_DEFAULT:
 579                 priv->CustomerID = RT_CID_DEFAULT;
 580                 break;
 581         case EEPROM_CID_CAMEO:
 582                 priv->CustomerID = RT_CID_819x_CAMEO;
 583                 break;
 584         case  EEPROM_CID_RUNTOP:
 585                 priv->CustomerID = RT_CID_819x_RUNTOP;
 586                 break;
 587         case EEPROM_CID_NetCore:
 588                 priv->CustomerID = RT_CID_819x_Netcore;
 589                 break;
 590         case EEPROM_CID_TOSHIBA:
 591                 priv->CustomerID = RT_CID_TOSHIBA;
 592                 if (priv->eeprom_ChannelPlan&0x80)
 593                         priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
 594                 else
 595                         priv->ChannelPlan = 0x0;
 596                 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
 597                         priv->ChannelPlan);
 598                 break;
 599         case EEPROM_CID_Nettronix:
 600                 priv->ScanDelay = 100;
 601                 priv->CustomerID = RT_CID_Nettronix;
 602                 break;
 603         case EEPROM_CID_Pronet:
 604                 priv->CustomerID = RT_CID_PRONET;
 605                 break;
 606         case EEPROM_CID_DLINK:
 607                 priv->CustomerID = RT_CID_DLINK;
 608                 break;
 609
 610         case EEPROM_CID_WHQL:
 611                 break;
 612         default:
 613                 break;
 614         }
 615
 616         if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
 617                 priv->ChannelPlan = 0;
 618         priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
 619
 620         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 621                 priv->rtllib->bSupportRemoteWakeUp = true;
 622         else
 623                 priv->rtllib->bSupportRemoteWakeUp = false;
 624
 625         RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
 626         RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
 627         RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
 628 }
 629
 630 void rtl8192_get_eeprom_size(struct net_device *dev)
 631 {
 632         u16 curCR;
 633         struct r8192_priv *priv = rtllib_priv(dev);
 634
 635         RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
 636         curCR = read_nic_dword(dev, EPROM_CMD);
 637         RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
 638                  curCR);
 639         priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
 640                           EEPROM_93C46;
 641         RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
 642                  priv->epromtype);
 643         rtl8192_read_eeprom_info(dev);
 644 }
 645
 646 static void rtl8192_hwconfig(struct net_device *dev)
 647 {
 648         u32 regRATR = 0, regRRSR = 0;
 649         u8 regBwOpMode = 0, regTmp = 0;
 650         struct r8192_priv *priv = rtllib_priv(dev);
 651
 652         switch (priv->rtllib->mode) {
 653         case WIRELESS_MODE_B:
 654                 regBwOpMode = BW_OPMODE_20MHZ;
 655                 regRATR = RATE_ALL_CCK;
 656                 regRRSR = RATE_ALL_CCK;
 657                 break;
 658         case WIRELESS_MODE_A:
 659                 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
 660                 regRATR = RATE_ALL_OFDM_AG;
 661                 regRRSR = RATE_ALL_OFDM_AG;
 662                 break;
 663         case WIRELESS_MODE_G:
 664                 regBwOpMode = BW_OPMODE_20MHZ;
 665                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 666                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 667                 break;
 668         case WIRELESS_MODE_AUTO:
 669         case WIRELESS_MODE_N_24G:
 670                 regBwOpMode = BW_OPMODE_20MHZ;
 671                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 672                                   RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 673                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 674                 break;
 675         case WIRELESS_MODE_N_5G:
 676                 regBwOpMode = BW_OPMODE_5G;
 677                 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
 678                           RATE_ALL_OFDM_2SS;
 679                 regRRSR = RATE_ALL_OFDM_AG;
 680                 break;
 681         default:
 682                 regBwOpMode = BW_OPMODE_20MHZ;
 683                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 684                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 685                 break;
 686         }
 687
 688         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
 689         {
 690                 u32 ratr_value = 0;
 691
 692                 ratr_value = regRATR;
 693                 if (priv->rf_type == RF_1T2R)
 694                         ratr_value &= ~(RATE_ALL_OFDM_2SS);
 695                 write_nic_dword(dev, RATR0, ratr_value);
 696                 write_nic_byte(dev, UFWP, 1);
 697         }
 698         regTmp = read_nic_byte(dev, 0x313);
 699         regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
 700         write_nic_dword(dev, RRSR, regRRSR);
 701
 702         write_nic_word(dev, RETRY_LIMIT,
 703                         priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
 704                         priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
 705 }
 706
 707 bool rtl8192_adapter_start(struct net_device *dev)
 708 {
 709         struct r8192_priv *priv = rtllib_priv(dev);
 710         u32 ulRegRead;
 711         bool rtStatus = true;
 712         u8 tmpvalue;
 713         u8 ICVersion, SwitchingRegulatorOutput;
 714         bool bfirmwareok = true;
 715         u32 tmpRegA, tmpRegC, TempCCk;
 716         int i = 0;
 717         u32 retry_times = 0;
 718
 719         RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
 720         priv->being_init_adapter = true;
 721
 722 start:
 723         rtl8192_pci_resetdescring(dev);
 724         priv->Rf_Mode = RF_OP_By_SW_3wire;
 725         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 726                 write_nic_byte(dev, ANAPAR, 0x37);
 727                 mdelay(500);
 728         }
 729         priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
 730
 731         if (priv->RegRfOff)
 732                 priv->rtllib->eRFPowerState = eRfOff;
 733
 734         ulRegRead = read_nic_dword(dev, CPU_GEN);
 735         if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
 736                 ulRegRead |= CPU_GEN_SYSTEM_RESET;
 737         else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY)
 738                 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
 739         else
 740                 RT_TRACE(COMP_ERR,
 741                          "ERROR in %s(): undefined firmware state(%d)\n",
 742                          __func__,   priv->pFirmware->firmware_status);
 743
 744         write_nic_dword(dev, CPU_GEN, ulRegRead);
 745
 746         ICVersion = read_nic_byte(dev, IC_VERRSION);
 747         if (ICVersion >= 0x4) {
 748                 SwitchingRegulatorOutput = read_nic_byte(dev, SWREGULATOR);
 749                 if (SwitchingRegulatorOutput  != 0xb8) {
 750                         write_nic_byte(dev, SWREGULATOR, 0xa8);
 751                         mdelay(1);
 752                         write_nic_byte(dev, SWREGULATOR, 0xb8);
 753                 }
 754         }
 755         RT_TRACE(COMP_INIT, "BB Config Start!\n");
 756         rtStatus = rtl8192_BBConfig(dev);
 757         if (!rtStatus) {
 758                 RT_TRACE(COMP_ERR, "BB Config failed\n");
 759                 return rtStatus;
 760         }
 761         RT_TRACE(COMP_INIT, "BB Config Finished!\n");
 762
 763         priv->LoopbackMode = RTL819X_NO_LOOPBACK;
 764         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 765                 ulRegRead = read_nic_dword(dev, CPU_GEN);
 766                 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
 767                         ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
 768                                      CPU_GEN_NO_LOOPBACK_SET);
 769                 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
 770                         ulRegRead |= CPU_CCK_LOOPBACK;
 771                 else
 772                         RT_TRACE(COMP_ERR,
 773                                  "Serious error: wrong loopback mode setting\n");
 774
 775                 write_nic_dword(dev, CPU_GEN, ulRegRead);
 776
 777                 udelay(500);
 778         }
 779         rtl8192_hwconfig(dev);
 780         write_nic_byte(dev, CMDR, CR_RE | CR_TE);
 781
 782         write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
 783                        (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
 784         write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
 785         write_nic_word(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
 786         write_nic_dword(dev, RCR, priv->ReceiveConfig);
 787
 788         write_nic_dword(dev, RQPN1,  NUM_OF_PAGE_IN_FW_QUEUE_BK <<
 789                         RSVD_FW_QUEUE_PAGE_BK_SHIFT |
 790                         NUM_OF_PAGE_IN_FW_QUEUE_BE <<
 791                         RSVD_FW_QUEUE_PAGE_BE_SHIFT |
 792                         NUM_OF_PAGE_IN_FW_QUEUE_VI <<
 793                         RSVD_FW_QUEUE_PAGE_VI_SHIFT |
 794                         NUM_OF_PAGE_IN_FW_QUEUE_VO <<
 795                         RSVD_FW_QUEUE_PAGE_VO_SHIFT);
 796         write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
 797                         RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
 798         write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
 799                         NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
 800                         RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
 801                         NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
 802                         RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
 803
 804         rtl8192_tx_enable(dev);
 805         rtl8192_rx_enable(dev);
 806         ulRegRead = (0xFFF00000 & read_nic_dword(dev, RRSR))  |
 807                      RATE_ALL_OFDM_AG | RATE_ALL_CCK;
 808         write_nic_dword(dev, RRSR, ulRegRead);
 809         write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
 810
 811         write_nic_byte(dev, ACK_TIMEOUT, 0x30);
 812
 813         if (priv->ResetProgress == RESET_TYPE_NORESET)
 814                 rtl8192_SetWirelessMode(dev, priv->rtllib->mode);
 815         CamResetAllEntry(dev);
 816         {
 817                 u8 SECR_value = 0x0;
 818
 819                 SECR_value |= SCR_TxEncEnable;
 820                 SECR_value |= SCR_RxDecEnable;
 821                 SECR_value |= SCR_NoSKMC;
 822                 write_nic_byte(dev, SECR, SECR_value);
 823         }
 824         write_nic_word(dev, ATIMWND, 2);
 825         write_nic_word(dev, BCN_INTERVAL, 100);
 826         {
 827                 int i;
 828
 829                 for (i = 0; i < QOS_QUEUE_NUM; i++)
 830                         write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332);
 831         }
 832         write_nic_byte(dev, 0xbe, 0xc0);
 833
 834         rtl8192_phy_configmac(dev);
 835
 836         if (priv->card_8192_version > (u8) VERSION_8190_BD) {
 837                 rtl8192_phy_getTxPower(dev);
 838                 rtl8192_phy_setTxPower(dev, priv->chan);
 839         }
 840
 841         tmpvalue = read_nic_byte(dev, IC_VERRSION);
 842         priv->IC_Cut = tmpvalue;
 843         RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
 844         if (priv->IC_Cut >= IC_VersionCut_D) {
 845                 if (priv->IC_Cut == IC_VersionCut_D) {
 846                         /* no matter what checkpatch says, braces are needed */
 847                         RT_TRACE(COMP_INIT, "D-cut\n");
 848                 } else if (priv->IC_Cut == IC_VersionCut_E) {
 849                         RT_TRACE(COMP_INIT, "E-cut\n");
 850                 }
 851         } else {
 852                 RT_TRACE(COMP_INIT, "Before C-cut\n");
 853         }
 854
 855         RT_TRACE(COMP_INIT, "Load Firmware!\n");
 856         bfirmwareok = init_firmware(dev);
 857         if (!bfirmwareok) {
 858                 if (retry_times < 10) {
 859                         retry_times++;
 860                         goto start;
 861                 } else {
 862                         rtStatus = false;
 863                         goto end;
 864                 }
 865         }
 866         RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
 867         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 868                 RT_TRACE(COMP_INIT, "RF Config Started!\n");
 869                 rtStatus = rtl8192_phy_RFConfig(dev);
 870                 if (!rtStatus) {
 871                         RT_TRACE(COMP_ERR, "RF Config failed\n");
 872                         return rtStatus;
 873                 }
 874                 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
 875         }
 876         rtl8192_phy_updateInitGain(dev);
 877
 878         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
 879         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
 880
 881         write_nic_byte(dev, 0x87, 0x0);
 882
 883         if (priv->RegRfOff) {
 884                 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
 885                           "%s(): Turn off RF for RegRfOff ----------\n",
 886                           __func__);
 887                 MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW, true);
 888         } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
 889                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
 890                          "%s(): Turn off RF for RfOffReason(%d) ----------\n",
 891                          __func__, priv->rtllib->RfOffReason);
 892                 MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
 893                                     true);
 894         } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
 895                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
 896                          "%s(): Turn off RF for RfOffReason(%d) ----------\n",
 897                          __func__, priv->rtllib->RfOffReason);
 898                 MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
 899                                     true);
 900         } else {
 901                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
 902                           __func__);
 903                 priv->rtllib->eRFPowerState = eRfOn;
 904                 priv->rtllib->RfOffReason = 0;
 905         }
 906
 907         if (priv->rtllib->FwRWRF)
 908                 priv->Rf_Mode = RF_OP_By_FW;
 909         else
 910                 priv->Rf_Mode = RF_OP_By_SW_3wire;
 911
 912         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 913                 dm_initialize_txpower_tracking(dev);
 914
 915                 if (priv->IC_Cut >= IC_VersionCut_D) {
 916                         tmpRegA = rtl8192_QueryBBReg(dev,
 917                                   rOFDM0_XATxIQImbalance, bMaskDWord);
 918                         tmpRegC = rtl8192_QueryBBReg(dev,
 919                                   rOFDM0_XCTxIQImbalance, bMaskDWord);
 920                         for (i = 0; i < TxBBGainTableLength; i++) {
 921                                 if (tmpRegA ==
 922                                     priv->txbbgain_table[i].txbbgain_value) {
 923                                         priv->rfa_txpowertrackingindex = (u8)i;
 924                                         priv->rfa_txpowertrackingindex_real =
 925                                                  (u8)i;
 926                                         priv->rfa_txpowertracking_default =
 927                                                  priv->rfa_txpowertrackingindex;
 928                                         break;
 929                                 }
 930                         }
 931
 932                         TempCCk = rtl8192_QueryBBReg(dev,
 933                                   rCCK0_TxFilter1, bMaskByte2);
 934
 935                         for (i = 0; i < CCKTxBBGainTableLength; i++) {
 936                                 if (TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0]) {
 937                                         priv->CCKPresentAttentuation_20Mdefault = (u8)i;
 938                                         break;
 939                                 }
 940                         }
 941                         priv->CCKPresentAttentuation_40Mdefault = 0;
 942                         priv->CCKPresentAttentuation_difference = 0;
 943                         priv->CCKPresentAttentuation =
 944                                   priv->CCKPresentAttentuation_20Mdefault;
 945                         RT_TRACE(COMP_POWER_TRACKING,
 946                                  "priv->rfa_txpowertrackingindex_initial = %d\n",
 947                                  priv->rfa_txpowertrackingindex);
 948                         RT_TRACE(COMP_POWER_TRACKING,
 949                                  "priv->rfa_txpowertrackingindex_real__initial = %d\n",
 950                                  priv->rfa_txpowertrackingindex_real);
 951                         RT_TRACE(COMP_POWER_TRACKING,
 952                                  "priv->CCKPresentAttentuation_difference_initial = %d\n",
 953                                   priv->CCKPresentAttentuation_difference);
 954                         RT_TRACE(COMP_POWER_TRACKING,
 955                                  "priv->CCKPresentAttentuation_initial = %d\n",
 956                                  priv->CCKPresentAttentuation);
 957                         priv->btxpower_tracking = false;
 958                 }
 959         }
 960         rtl8192_irq_enable(dev);
 961 end:
 962         priv->being_init_adapter = false;
 963         return rtStatus;
 964 }
 965
 966 static void rtl8192_net_update(struct net_device *dev)
 967 {
 968
 969         struct r8192_priv *priv = rtllib_priv(dev);
 970         struct rtllib_network *net;
 971         u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
 972         u16 rate_config = 0;
 973
 974         net = &priv->rtllib->current_network;
 975         rtl8192_config_rate(dev, &rate_config);
 976         priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
 977          priv->basic_rate = rate_config &= 0x15f;
 978         write_nic_dword(dev, BSSIDR, ((u32 *)net->bssid)[0]);
 979         write_nic_word(dev, BSSIDR+4, ((u16 *)net->bssid)[2]);
 980
 981         if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
 982                 write_nic_word(dev, ATIMWND, 2);
 983                 write_nic_word(dev, BCN_DMATIME, 256);
 984                 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
 985                 write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
 986                 write_nic_byte(dev, BCN_ERR_THRESH, 100);
 987
 988                 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
 989                 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
 990
 991                 write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
 992         }
 993 }
 994
 995 void rtl8192_link_change(struct net_device *dev)
 996 {
 997         struct r8192_priv *priv = rtllib_priv(dev);
 998         struct rtllib_device *ieee = priv->rtllib;
 999
1000         if (!priv->up)
1001                 return;
1002
1003         if (ieee->state == RTLLIB_LINKED) {
1004                 rtl8192_net_update(dev);
1005                 priv->ops->update_ratr_table(dev);
1006                 if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
1007                     (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
1008                         EnableHWSecurityConfig8192(dev);
1009         } else {
1010                 write_nic_byte(dev, 0x173, 0);
1011         }
1012         rtl8192e_update_msr(dev);
1013
1014         if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
1015                 u32 reg = 0;
1016
1017                 reg = read_nic_dword(dev, RCR);
1018                 if (priv->rtllib->state == RTLLIB_LINKED) {
1019                         if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
1020                                 ;
1021                         else
1022                                 priv->ReceiveConfig = reg |= RCR_CBSSID;
1023                 } else
1024                         priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1025
1026                 write_nic_dword(dev, RCR, reg);
1027         }
1028 }
1029
1030 void rtl8192_AllowAllDestAddr(struct net_device *dev,
1031                               bool bAllowAllDA, bool WriteIntoReg)
1032 {
1033         struct r8192_priv *priv = rtllib_priv(dev);
1034
1035         if (bAllowAllDA)
1036                 priv->ReceiveConfig |= RCR_AAP;
1037         else
1038                 priv->ReceiveConfig &= ~RCR_AAP;
1039
1040         if (WriteIntoReg)
1041                 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1042 }
1043
1044 static u8 MRateToHwRate8190Pci(u8 rate)
1045 {
1046         u8  ret = DESC90_RATE1M;
1047
1048         switch (rate) {
1049         case MGN_1M:
1050                 ret = DESC90_RATE1M;
1051                 break;
1052         case MGN_2M:
1053                 ret = DESC90_RATE2M;
1054                 break;
1055         case MGN_5_5M:
1056                 ret = DESC90_RATE5_5M;
1057                 break;
1058         case MGN_11M:
1059                 ret = DESC90_RATE11M;
1060                 break;
1061         case MGN_6M:
1062                 ret = DESC90_RATE6M;
1063                 break;
1064         case MGN_9M:
1065                 ret = DESC90_RATE9M;
1066                 break;
1067         case MGN_12M:
1068                 ret = DESC90_RATE12M;
1069                 break;
1070         case MGN_18M:
1071                 ret = DESC90_RATE18M;
1072                 break;
1073         case MGN_24M:
1074                 ret = DESC90_RATE24M;
1075                 break;
1076         case MGN_36M:
1077                 ret = DESC90_RATE36M;
1078                 break;
1079         case MGN_48M:
1080                 ret = DESC90_RATE48M;
1081                 break;
1082         case MGN_54M:
1083                 ret = DESC90_RATE54M;
1084                 break;
1085         case MGN_MCS0:
1086                 ret = DESC90_RATEMCS0;
1087                 break;
1088         case MGN_MCS1:
1089                 ret = DESC90_RATEMCS1;
1090                 break;
1091         case MGN_MCS2:
1092                 ret = DESC90_RATEMCS2;
1093                 break;
1094         case MGN_MCS3:
1095                 ret = DESC90_RATEMCS3;
1096                 break;
1097         case MGN_MCS4:
1098                 ret = DESC90_RATEMCS4;
1099                 break;
1100         case MGN_MCS5:
1101                 ret = DESC90_RATEMCS5;
1102                 break;
1103         case MGN_MCS6:
1104                 ret = DESC90_RATEMCS6;
1105                 break;
1106         case MGN_MCS7:
1107                 ret = DESC90_RATEMCS7;
1108                 break;
1109         case MGN_MCS8:
1110                 ret = DESC90_RATEMCS8;
1111                 break;
1112         case MGN_MCS9:
1113                 ret = DESC90_RATEMCS9;
1114                 break;
1115         case MGN_MCS10:
1116                 ret = DESC90_RATEMCS10;
1117                 break;
1118         case MGN_MCS11:
1119                 ret = DESC90_RATEMCS11;
1120                 break;
1121         case MGN_MCS12:
1122                 ret = DESC90_RATEMCS12;
1123                 break;
1124         case MGN_MCS13:
1125                 ret = DESC90_RATEMCS13;
1126                 break;
1127         case MGN_MCS14:
1128                 ret = DESC90_RATEMCS14;
1129                 break;
1130         case MGN_MCS15:
1131                 ret = DESC90_RATEMCS15;
1132                 break;
1133         case (0x80|0x20):
1134                 ret = DESC90_RATEMCS32;
1135                 break;
1136         default:
1137                 break;
1138         }
1139         return ret;
1140 }
1141
1142 static u8 rtl8192_MapHwQueueToFirmwareQueue(u8 QueueID, u8 priority)
1143 {
1144         u8 QueueSelect = 0x0;
1145
1146         switch (QueueID) {
1147         case BE_QUEUE:
1148                 QueueSelect = QSLT_BE;
1149                 break;
1150
1151         case BK_QUEUE:
1152                 QueueSelect = QSLT_BK;
1153                 break;
1154
1155         case VO_QUEUE:
1156                 QueueSelect = QSLT_VO;
1157                 break;
1158
1159         case VI_QUEUE:
1160                 QueueSelect = QSLT_VI;
1161                 break;
1162         case MGNT_QUEUE:
1163                 QueueSelect = QSLT_MGNT;
1164                 break;
1165         case BEACON_QUEUE:
1166                 QueueSelect = QSLT_BEACON;
1167                 break;
1168         case TXCMD_QUEUE:
1169                 QueueSelect = QSLT_CMD;
1170                 break;
1171         case HIGH_QUEUE:
1172                 QueueSelect = QSLT_HIGH;
1173                 break;
1174         default:
1175                 RT_TRACE(COMP_ERR,
1176                          "TransmitTCB(): Impossible Queue Selection: %d\n",
1177                          QueueID);
1178                 break;
1179         }
1180         return QueueSelect;
1181 }
1182
1183 void  rtl8192_tx_fill_desc(struct net_device *dev, struct tx_desc *pdesc,
1184                            struct cb_desc *cb_desc, struct sk_buff *skb)
1185 {
1186         struct r8192_priv *priv = rtllib_priv(dev);
1187         dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1188                          PCI_DMA_TODEVICE);
1189         struct tx_fwinfo_8190pci *pTxFwInfo = NULL;
1190
1191         pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1192         memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1193         pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1194         pTxFwInfo->TxRate = MRateToHwRate8190Pci((u8)cb_desc->data_rate);
1195         pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1196         pTxFwInfo->Short = rtl8192_QueryIsShort(pTxFwInfo->TxHT,
1197                                                 pTxFwInfo->TxRate,
1198                                                 cb_desc);
1199
1200         if (pci_dma_mapping_error(priv->pdev, mapping))
1201                 RT_TRACE(COMP_ERR, "DMA Mapping error\n");
1202         if (cb_desc->bAMPDUEnable) {
1203                 pTxFwInfo->AllowAggregation = 1;
1204                 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1205                 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1206         } else {
1207                 pTxFwInfo->AllowAggregation = 0;
1208                 pTxFwInfo->RxMF = 0;
1209                 pTxFwInfo->RxAMD = 0;
1210         }
1211
1212         pTxFwInfo->RtsEnable =  (cb_desc->bRTSEnable) ? 1 : 0;
1213         pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1214         pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1215         pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1216         pTxFwInfo->RtsRate = MRateToHwRate8190Pci((u8)cb_desc->rts_rate);
1217         pTxFwInfo->RtsBandwidth = 0;
1218         pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1219         pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1220                           (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1221                           (cb_desc->bRTSUseShortGI ? 1 : 0);
1222         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1223                 if (cb_desc->bPacketBW) {
1224                         pTxFwInfo->TxBandwidth = 1;
1225                         pTxFwInfo->TxSubCarrier = 0;
1226                 } else {
1227                         pTxFwInfo->TxBandwidth = 0;
1228                         pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1229                 }
1230         } else {
1231                 pTxFwInfo->TxBandwidth = 0;
1232                 pTxFwInfo->TxSubCarrier = 0;
1233         }
1234
1235         memset((u8 *)pdesc, 0, 12);
1236         pdesc->LINIP = 0;
1237         pdesc->CmdInit = 1;
1238         pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1239         pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1240
1241         pdesc->SecCAMID = 0;
1242         pdesc->RATid = cb_desc->RATRIndex;
1243
1244
1245         pdesc->NoEnc = 1;
1246         pdesc->SecType = 0x0;
1247         if (cb_desc->bHwSec) {
1248                 static u8 tmp;
1249
1250                 if (!tmp) {
1251                         RT_TRACE(COMP_DBG, "==>================hw sec\n");
1252                         tmp = 1;
1253                 }
1254                 switch (priv->rtllib->pairwise_key_type) {
1255                 case KEY_TYPE_WEP40:
1256                 case KEY_TYPE_WEP104:
1257                         pdesc->SecType = 0x1;
1258                         pdesc->NoEnc = 0;
1259                         break;
1260                 case KEY_TYPE_TKIP:
1261                         pdesc->SecType = 0x2;
1262                         pdesc->NoEnc = 0;
1263                         break;
1264                 case KEY_TYPE_CCMP:
1265                         pdesc->SecType = 0x3;
1266                         pdesc->NoEnc = 0;
1267                         break;
1268                 case KEY_TYPE_NA:
1269                         pdesc->SecType = 0x0;
1270                         pdesc->NoEnc = 1;
1271                         break;
1272                 }
1273         }
1274
1275         pdesc->PktId = 0x0;
1276
1277         pdesc->QueueSelect = rtl8192_MapHwQueueToFirmwareQueue(
1278                                                 cb_desc->queue_index,
1279                                                 cb_desc->priority);
1280         pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1281
1282         pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1283         pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1284
1285         pdesc->FirstSeg = 1;
1286         pdesc->LastSeg = 1;
1287         pdesc->TxBufferSize = skb->len;
1288
1289         pdesc->TxBuffAddr = mapping;
1290 }
1291
1292 void  rtl8192_tx_fill_cmd_desc(struct net_device *dev,
1293                                struct tx_desc_cmd *entry,
1294                                struct cb_desc *cb_desc, struct sk_buff *skb)
1295 {
1296         struct r8192_priv *priv = rtllib_priv(dev);
1297         dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1298                          PCI_DMA_TODEVICE);
1299
1300         if (pci_dma_mapping_error(priv->pdev, mapping))
1301                 RT_TRACE(COMP_ERR, "DMA Mapping error\n");
1302         memset(entry, 0, 12);
1303         entry->LINIP = cb_desc->bLastIniPkt;
1304         entry->FirstSeg = 1;
1305         entry->LastSeg = 1;
1306         if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1307                 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1308         } else {
1309                 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1310
1311                 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1312                 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1313                 entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1314                                       entry_tmp->Offset);
1315                 entry_tmp->QueueSelect = QSLT_CMD;
1316                 entry_tmp->TxFWInfoSize = 0x08;
1317                 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1318         }
1319         entry->TxBufferSize = skb->len;
1320         entry->TxBuffAddr = mapping;
1321         entry->OWN = 1;
1322 }
1323
1324 static u8 HwRateToMRate90(bool bIsHT, u8 rate)
1325 {
1326         u8  ret_rate = 0x02;
1327
1328         if (!bIsHT) {
1329                 switch (rate) {
1330                 case DESC90_RATE1M:
1331                         ret_rate = MGN_1M;
1332                         break;
1333                 case DESC90_RATE2M:
1334                         ret_rate = MGN_2M;
1335                         break;
1336                 case DESC90_RATE5_5M:
1337                         ret_rate = MGN_5_5M;
1338                         break;
1339                 case DESC90_RATE11M:
1340                         ret_rate = MGN_11M;
1341                         break;
1342                 case DESC90_RATE6M:
1343                         ret_rate = MGN_6M;
1344                         break;
1345                 case DESC90_RATE9M:
1346                         ret_rate = MGN_9M;
1347                         break;
1348                 case DESC90_RATE12M:
1349                         ret_rate = MGN_12M;
1350                         break;
1351                 case DESC90_RATE18M:
1352                         ret_rate = MGN_18M;
1353                         break;
1354                 case DESC90_RATE24M:
1355                         ret_rate = MGN_24M;
1356                         break;
1357                 case DESC90_RATE36M:
1358                         ret_rate = MGN_36M;
1359                         break;
1360                 case DESC90_RATE48M:
1361                         ret_rate = MGN_48M;
1362                         break;
1363                 case DESC90_RATE54M:
1364                         ret_rate = MGN_54M;
1365                         break;
1366
1367                 default:
1368                         RT_TRACE(COMP_RECV,
1369                                  "HwRateToMRate90(): Non supportedRate [%x], bIsHT = %d!!!\n",
1370                                  rate, bIsHT);
1371                         break;
1372                 }
1373
1374         } else {
1375                 switch (rate) {
1376                 case DESC90_RATEMCS0:
1377                         ret_rate = MGN_MCS0;
1378                         break;
1379                 case DESC90_RATEMCS1:
1380                         ret_rate = MGN_MCS1;
1381                         break;
1382                 case DESC90_RATEMCS2:
1383                         ret_rate = MGN_MCS2;
1384                         break;
1385                 case DESC90_RATEMCS3:
1386                         ret_rate = MGN_MCS3;
1387                         break;
1388                 case DESC90_RATEMCS4:
1389                         ret_rate = MGN_MCS4;
1390                         break;
1391                 case DESC90_RATEMCS5:
1392                         ret_rate = MGN_MCS5;
1393                         break;
1394                 case DESC90_RATEMCS6:
1395                         ret_rate = MGN_MCS6;
1396                         break;
1397                 case DESC90_RATEMCS7:
1398                         ret_rate = MGN_MCS7;
1399                         break;
1400                 case DESC90_RATEMCS8:
1401                         ret_rate = MGN_MCS8;
1402                         break;
1403                 case DESC90_RATEMCS9:
1404                         ret_rate = MGN_MCS9;
1405                         break;
1406                 case DESC90_RATEMCS10:
1407                         ret_rate = MGN_MCS10;
1408                         break;
1409                 case DESC90_RATEMCS11:
1410                         ret_rate = MGN_MCS11;
1411                         break;
1412                 case DESC90_RATEMCS12:
1413                         ret_rate = MGN_MCS12;
1414                         break;
1415                 case DESC90_RATEMCS13:
1416                         ret_rate = MGN_MCS13;
1417                         break;
1418                 case DESC90_RATEMCS14:
1419                         ret_rate = MGN_MCS14;
1420                         break;
1421                 case DESC90_RATEMCS15:
1422                         ret_rate = MGN_MCS15;
1423                         break;
1424                 case DESC90_RATEMCS32:
1425                         ret_rate = (0x80|0x20);
1426                         break;
1427
1428                 default:
1429                         RT_TRACE(COMP_RECV,
1430                                  "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",
1431                                  rate, bIsHT);
1432                         break;
1433                 }
1434         }
1435
1436         return ret_rate;
1437 }
1438
1439 static long rtl8192_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1440 {
1441         long retsig;
1442
1443         if (currsig >= 61 && currsig <= 100)
1444                 retsig = 90 + ((currsig - 60) / 4);
1445         else if (currsig >= 41 && currsig <= 60)
1446                 retsig = 78 + ((currsig - 40) / 2);
1447         else if (currsig >= 31 && currsig <= 40)
1448                 retsig = 66 + (currsig - 30);
1449         else if (currsig >= 21 && currsig <= 30)
1450                 retsig = 54 + (currsig - 20);
1451         else if (currsig >= 5 && currsig <= 20)
1452                 retsig = 42 + (((currsig - 5) * 2) / 3);
1453         else if (currsig == 4)
1454                 retsig = 36;
1455         else if (currsig == 3)
1456                 retsig = 27;
1457         else if (currsig == 2)
1458                 retsig = 18;
1459         else if (currsig == 1)
1460                 retsig = 9;
1461         else
1462                 retsig = currsig;
1463
1464         return retsig;
1465 }
1466
1467
1468 #define  rx_hal_is_cck_rate(_pdrvinfo)\
1469                         ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1470                         _pdrvinfo->RxRate == DESC90_RATE2M ||\
1471                         _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1472                         _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1473                         !_pdrvinfo->RxHT)
1474
1475 static void rtl8192_query_rxphystatus(
1476         struct r8192_priv *priv,
1477         struct rtllib_rx_stats *pstats,
1478         struct rx_desc  *pdesc,
1479         struct rx_fwinfo   *pdrvinfo,
1480         struct rtllib_rx_stats *precord_stats,
1481         bool bpacket_match_bssid,
1482         bool bpacket_toself,
1483         bool bPacketBeacon,
1484         bool bToSelfBA
1485         )
1486 {
1487         struct phy_sts_ofdm_819xpci *pofdm_buf;
1488         struct phy_sts_cck_819xpci *pcck_buf;
1489         struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1490         u8 *prxpkt;
1491         u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1492         char rx_pwr[4], rx_pwr_all = 0;
1493         char rx_snrX, rx_evmX;
1494         u8 evm, pwdb_all;
1495         u32 RSSI, total_rssi = 0;
1496         u8 is_cck_rate = 0;
1497         u8 rf_rx_num = 0;
1498         static  u8 check_reg824;
1499         static  u32 reg824_bit9;
1500
1501         priv->stats.numqry_phystatus++;
1502
1503         is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1504         memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1505         pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1506                                     bpacket_match_bssid;
1507         pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1508         pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1509         pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1510         pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1511         if (check_reg824 == 0) {
1512                 reg824_bit9 = rtl8192_QueryBBReg(priv->rtllib->dev,
1513                               rFPGA0_XA_HSSIParameter2, 0x200);
1514                 check_reg824 = 1;
1515         }
1516
1517
1518         prxpkt = (u8 *)pdrvinfo;
1519
1520         prxpkt += sizeof(struct rx_fwinfo);
1521
1522         pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1523         pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1524
1525         pstats->RxMIMOSignalQuality[0] = -1;
1526         pstats->RxMIMOSignalQuality[1] = -1;
1527         precord_stats->RxMIMOSignalQuality[0] = -1;
1528         precord_stats->RxMIMOSignalQuality[1] = -1;
1529
1530         if (is_cck_rate) {
1531                 u8 report;
1532
1533                 priv->stats.numqry_phystatusCCK++;
1534                 if (!reg824_bit9) {
1535                         report = pcck_buf->cck_agc_rpt & 0xc0;
1536                         report >>= 6;
1537                         switch (report) {
1538                         case 0x3:
1539                                 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1540                                              0x3e);
1541                                 break;
1542                         case 0x2:
1543                                 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1544                                              0x3e);
1545                                 break;
1546                         case 0x1:
1547                                 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1548                                              0x3e);
1549                                 break;
1550                         case 0x0:
1551                                 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1552                                 break;
1553                         }
1554                 } else {
1555                         report = pcck_buf->cck_agc_rpt & 0x60;
1556                         report >>= 5;
1557                         switch (report) {
1558                         case 0x3:
1559                                 rx_pwr_all = -35 -
1560                                         ((pcck_buf->cck_agc_rpt &
1561                                         0x1f) << 1);
1562                                 break;
1563                         case 0x2:
1564                                 rx_pwr_all = -23 -
1565                                         ((pcck_buf->cck_agc_rpt &
1566                                          0x1f) << 1);
1567                                 break;
1568                         case 0x1:
1569                                 rx_pwr_all = -11 -
1570                                          ((pcck_buf->cck_agc_rpt &
1571                                          0x1f) << 1);
1572                                 break;
1573                         case 0x0:
1574                                 rx_pwr_all = -8 -
1575                                          ((pcck_buf->cck_agc_rpt &
1576                                          0x1f) << 1);
1577                                 break;
1578                         }
1579                 }
1580
1581                 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1582                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1583                 pstats->RecvSignalPower = rx_pwr_all;
1584
1585                 if (bpacket_match_bssid) {
1586                         u8      sq;
1587
1588                         if (pstats->RxPWDBAll > 40) {
1589                                 sq = 100;
1590                         } else {
1591                                 sq = pcck_buf->sq_rpt;
1592
1593                                 if (pcck_buf->sq_rpt > 64)
1594                                         sq = 0;
1595                                 else if (pcck_buf->sq_rpt < 20)
1596                                         sq = 100;
1597                                 else
1598                                         sq = ((64-sq) * 100) / 44;
1599                         }
1600                         pstats->SignalQuality = sq;
1601                         precord_stats->SignalQuality = sq;
1602                         pstats->RxMIMOSignalQuality[0] = sq;
1603                         precord_stats->RxMIMOSignalQuality[0] = sq;
1604                         pstats->RxMIMOSignalQuality[1] = -1;
1605                         precord_stats->RxMIMOSignalQuality[1] = -1;
1606                 }
1607         } else {
1608                 priv->stats.numqry_phystatusHT++;
1609                 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1610                         if (priv->brfpath_rxenable[i])
1611                                 rf_rx_num++;
1612
1613                         rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1614                                      2) - 110;
1615
1616                         tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1617                         rx_snrX = (char)(tmp_rxsnr);
1618                         rx_snrX /= 2;
1619                         priv->stats.rxSNRdB[i] = (long)rx_snrX;
1620
1621                         RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
1622                         if (priv->brfpath_rxenable[i])
1623                                 total_rssi += RSSI;
1624
1625                         if (bpacket_match_bssid) {
1626                                 pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1627                                 precord_stats->RxMIMOSignalStrength[i] =
1628                                                                 (u8) RSSI;
1629                         }
1630                 }
1631
1632
1633                 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1634                 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1635
1636                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1637                 pstats->RxPower = precord_stats->RxPower =      rx_pwr_all;
1638                 pstats->RecvSignalPower = rx_pwr_all;
1639                 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1640                     pdrvinfo->RxRate <= DESC90_RATEMCS15)
1641                         max_spatial_stream = 2;
1642                 else
1643                         max_spatial_stream = 1;
1644
1645                 for (i = 0; i < max_spatial_stream; i++) {
1646                         tmp_rxevm = pofdm_buf->rxevm_X[i];
1647                         rx_evmX = (char)(tmp_rxevm);
1648
1649                         rx_evmX /= 2;
1650
1651                         evm = rtl819x_evm_dbtopercentage(rx_evmX);
1652                         if (bpacket_match_bssid) {
1653                                 if (i == 0) {
1654                                         pstats->SignalQuality = (u8)(evm &
1655                                                                  0xff);
1656                                         precord_stats->SignalQuality = (u8)(evm
1657                                                                         & 0xff);
1658                                 }
1659                                 pstats->RxMIMOSignalQuality[i] = (u8)(evm &
1660                                                                  0xff);
1661                                 precord_stats->RxMIMOSignalQuality[i] = (u8)(evm
1662                                                                         & 0xff);
1663                         }
1664                 }
1665
1666
1667                 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1668                 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1669                         &rxsc_sgien_exflg;
1670                 if (pdrvinfo->BW)
1671                         priv->stats.received_bwtype[1+prxsc->rxsc]++;
1672                 else
1673                         priv->stats.received_bwtype[0]++;
1674         }
1675
1676         if (is_cck_rate) {
1677                 pstats->SignalStrength = precord_stats->SignalStrength =
1678                                          (u8)(rtl8192_signal_scale_mapping(priv,
1679                                          (long)pwdb_all));
1680
1681         } else {
1682                 if (rf_rx_num != 0)
1683                         pstats->SignalStrength = precord_stats->SignalStrength =
1684                                          (u8)(rtl8192_signal_scale_mapping(priv,
1685                                          (long)(total_rssi /= rf_rx_num)));
1686         }
1687 }
1688
1689 static void rtl8192_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1690                                     struct rtllib_rx_stats *prev_st,
1691                                     struct rtllib_rx_stats *curr_st)
1692 {
1693         bool bcheck = false;
1694         u8      rfpath;
1695         u32 ij, tmp_val;
1696         static u32 slide_rssi_index, slide_rssi_statistics;
1697         static u32 slide_evm_index, slide_evm_statistics;
1698         static u32 last_rssi, last_evm;
1699         static u32 slide_beacon_adc_pwdb_index;
1700         static u32 slide_beacon_adc_pwdb_statistics;
1701         static u32 last_beacon_adc_pwdb;
1702         struct rtllib_hdr_3addr *hdr;
1703         u16 sc;
1704         unsigned int frag, seq;
1705
1706         hdr = (struct rtllib_hdr_3addr *)buffer;
1707         sc = le16_to_cpu(hdr->seq_ctl);
1708         frag = WLAN_GET_SEQ_FRAG(sc);
1709         seq = WLAN_GET_SEQ_SEQ(sc);
1710         curr_st->Seq_Num = seq;
1711         if (!prev_st->bIsAMPDU)
1712                 bcheck = true;
1713
1714         if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1715                 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1716                 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1717                 priv->stats.slide_rssi_total -= last_rssi;
1718         }
1719         priv->stats.slide_rssi_total += prev_st->SignalStrength;
1720
1721         priv->stats.slide_signal_strength[slide_rssi_index++] =
1722                                          prev_st->SignalStrength;
1723         if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1724                 slide_rssi_index = 0;
1725
1726         tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1727         priv->stats.signal_strength = rtl819x_translate_todbm(priv,
1728                                       (u8)tmp_val);
1729         curr_st->rssi = priv->stats.signal_strength;
1730         if (!prev_st->bPacketMatchBSSID) {
1731                 if (!prev_st->bToSelfBA)
1732                         return;
1733         }
1734
1735         if (!bcheck)
1736                 return;
1737
1738         rtl819x_process_cck_rxpathsel(priv, prev_st);
1739
1740         priv->stats.num_process_phyinfo++;
1741         if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1742                 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1743                         if (!rtl8192_phy_CheckIsLegalRFPath(priv->rtllib->dev,
1744                             rfpath))
1745                                 continue;
1746                         RT_TRACE(COMP_DBG,
1747                                  "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath]  = %d\n",
1748                                  prev_st->RxMIMOSignalStrength[rfpath]);
1749                         if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1750                                 priv->stats.rx_rssi_percentage[rfpath] =
1751                                          prev_st->RxMIMOSignalStrength[rfpath];
1752                         }
1753                         if (prev_st->RxMIMOSignalStrength[rfpath]  >
1754                             priv->stats.rx_rssi_percentage[rfpath]) {
1755                                 priv->stats.rx_rssi_percentage[rfpath] =
1756                                         ((priv->stats.rx_rssi_percentage[rfpath]
1757                                         * (RX_SMOOTH - 1)) +
1758                                         (prev_st->RxMIMOSignalStrength
1759                                         [rfpath])) / (RX_SMOOTH);
1760                                 priv->stats.rx_rssi_percentage[rfpath] =
1761                                          priv->stats.rx_rssi_percentage[rfpath]
1762                                          + 1;
1763                         } else {
1764                                 priv->stats.rx_rssi_percentage[rfpath] =
1765                                    ((priv->stats.rx_rssi_percentage[rfpath] *
1766                                    (RX_SMOOTH-1)) +
1767                                    (prev_st->RxMIMOSignalStrength[rfpath])) /
1768                                    (RX_SMOOTH);
1769                         }
1770                         RT_TRACE(COMP_DBG,
1771                                  "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath]  = %d\n",
1772                                  priv->stats.rx_rssi_percentage[rfpath]);
1773                 }
1774         }
1775
1776
1777         if (prev_st->bPacketBeacon) {
1778                 if (slide_beacon_adc_pwdb_statistics++ >=
1779                     PHY_Beacon_RSSI_SLID_WIN_MAX) {
1780                         slide_beacon_adc_pwdb_statistics =
1781                                          PHY_Beacon_RSSI_SLID_WIN_MAX;
1782                         last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1783                                                [slide_beacon_adc_pwdb_index];
1784                         priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1785                 }
1786                 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1787                 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1788                                                          prev_st->RxPWDBAll;
1789                 slide_beacon_adc_pwdb_index++;
1790                 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1791                         slide_beacon_adc_pwdb_index = 0;
1792                 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1793                                      slide_beacon_adc_pwdb_statistics;
1794                 if (prev_st->RxPWDBAll >= 3)
1795                         prev_st->RxPWDBAll -= 3;
1796         }
1797
1798         RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
1799                                 prev_st->bIsCCK ? "CCK" : "OFDM",
1800                                 prev_st->RxPWDBAll);
1801
1802         if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1803             prev_st->bToSelfBA) {
1804                 if (priv->undecorated_smoothed_pwdb < 0)
1805                         priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1806                 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1807                         priv->undecorated_smoothed_pwdb =
1808                                         (((priv->undecorated_smoothed_pwdb) *
1809                                         (RX_SMOOTH-1)) +
1810                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1811                         priv->undecorated_smoothed_pwdb =
1812                                          priv->undecorated_smoothed_pwdb + 1;
1813                 } else {
1814                         priv->undecorated_smoothed_pwdb =
1815                                         (((priv->undecorated_smoothed_pwdb) *
1816                                         (RX_SMOOTH-1)) +
1817                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1818                 }
1819                 rtl819x_update_rxsignalstatistics8190pci(priv, prev_st);
1820         }
1821
1822         if (prev_st->SignalQuality != 0) {
1823                 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1824                     prev_st->bToSelfBA) {
1825                         if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1826                                 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1827                                 last_evm =
1828                                          priv->stats.slide_evm[slide_evm_index];
1829                                 priv->stats.slide_evm_total -= last_evm;
1830                         }
1831
1832                         priv->stats.slide_evm_total += prev_st->SignalQuality;
1833
1834                         priv->stats.slide_evm[slide_evm_index++] =
1835                                                  prev_st->SignalQuality;
1836                         if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1837                                 slide_evm_index = 0;
1838
1839                         tmp_val = priv->stats.slide_evm_total /
1840                                   slide_evm_statistics;
1841                         priv->stats.signal_quality = tmp_val;
1842                         priv->stats.last_signal_strength_inpercent = tmp_val;
1843                 }
1844
1845                 if (prev_st->bPacketToSelf ||
1846                     prev_st->bPacketBeacon ||
1847                     prev_st->bToSelfBA) {
1848                         for (ij = 0; ij < 2; ij++) {
1849                                 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1850                                         if (priv->stats.rx_evm_percentage[ij] == 0)
1851                                                 priv->stats.rx_evm_percentage[ij] =
1852                                                    prev_st->RxMIMOSignalQuality[ij];
1853                                         priv->stats.rx_evm_percentage[ij] =
1854                                           ((priv->stats.rx_evm_percentage[ij] *
1855                                           (RX_SMOOTH - 1)) +
1856                                           (prev_st->RxMIMOSignalQuality[ij])) /
1857                                           (RX_SMOOTH);
1858                                 }
1859                         }
1860                 }
1861         }
1862 }
1863
1864 static void rtl8192_TranslateRxSignalStuff(struct net_device *dev,
1865                                            struct sk_buff *skb,
1866                                            struct rtllib_rx_stats *pstats,
1867                                            struct rx_desc *pdesc,
1868                                            struct rx_fwinfo *pdrvinfo)
1869 {
1870         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1871         bool bpacket_match_bssid, bpacket_toself;
1872         bool bPacketBeacon = false;
1873         struct rtllib_hdr_3addr *hdr;
1874         bool bToSelfBA = false;
1875         static struct rtllib_rx_stats  previous_stats;
1876         u16 fc, type;
1877         u8 *tmp_buf;
1878         u8 *praddr;
1879
1880         tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1881
1882         hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1883         fc = le16_to_cpu(hdr->frame_ctl);
1884         type = WLAN_FC_GET_TYPE(fc);
1885         praddr = hdr->addr1;
1886
1887         bpacket_match_bssid =
1888                 ((RTLLIB_FTYPE_CTL != type) &&
1889                  ether_addr_equal(priv->rtllib->current_network.bssid,
1890                                   (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1891                                   (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1892                                   hdr->addr3) &&
1893                  (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1894         bpacket_toself = bpacket_match_bssid &&         /* check this */
1895                          ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1896         if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1897                 bPacketBeacon = true;
1898         if (bpacket_match_bssid)
1899                 priv->stats.numpacket_matchbssid++;
1900         if (bpacket_toself)
1901                 priv->stats.numpacket_toself++;
1902         rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1903         rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1904                                   &previous_stats, bpacket_match_bssid,
1905                                   bpacket_toself, bPacketBeacon, bToSelfBA);
1906         rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
1907 }
1908
1909 static void rtl8192_UpdateReceivedRateHistogramStatistics(
1910                                            struct net_device *dev,
1911                                            struct rtllib_rx_stats *pstats)
1912 {
1913         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1914         u32 rcvType = 1;
1915         u32 rateIndex;
1916         u32 preamble_guardinterval;
1917
1918         if (pstats->bCRC)
1919                 rcvType = 2;
1920         else if (pstats->bICV)
1921                 rcvType = 3;
1922
1923         if (pstats->bShortPreamble)
1924                 preamble_guardinterval = 1;
1925         else
1926                 preamble_guardinterval = 0;
1927
1928         switch (pstats->rate) {
1929         case MGN_1M:
1930                 rateIndex = 0;
1931                 break;
1932         case MGN_2M:
1933                 rateIndex = 1;
1934                  break;
1935         case MGN_5_5M:
1936                 rateIndex = 2;
1937                 break;
1938         case MGN_11M:
1939                 rateIndex = 3;
1940                 break;
1941         case MGN_6M:
1942                 rateIndex = 4;
1943                 break;
1944         case MGN_9M:
1945                 rateIndex = 5;
1946                 break;
1947         case MGN_12M:
1948                 rateIndex = 6;
1949                 break;
1950         case MGN_18M:
1951                 rateIndex = 7;
1952                  break;
1953         case MGN_24M:
1954                 rateIndex = 8;
1955                 break;
1956         case MGN_36M:
1957                 rateIndex = 9;
1958                 break;
1959         case MGN_48M:
1960                 rateIndex = 10;
1961                 break;
1962         case MGN_54M:
1963                 rateIndex = 11;
1964                 break;
1965         case MGN_MCS0:
1966                 rateIndex = 12;
1967                 break;
1968         case MGN_MCS1:
1969                 rateIndex = 13;
1970                 break;
1971         case MGN_MCS2:
1972                 rateIndex = 14;
1973                 break;
1974         case MGN_MCS3:
1975                 rateIndex = 15;
1976                 break;
1977         case MGN_MCS4:
1978                 rateIndex = 16;
1979                 break;
1980         case MGN_MCS5:
1981                 rateIndex = 17;
1982                 break;
1983         case MGN_MCS6:
1984                 rateIndex = 18;
1985                 break;
1986         case MGN_MCS7:
1987                 rateIndex = 19;
1988                 break;
1989         case MGN_MCS8:
1990                 rateIndex = 20;
1991                 break;
1992         case MGN_MCS9:
1993                 rateIndex = 21;
1994                 break;
1995         case MGN_MCS10:
1996                 rateIndex = 22;
1997                 break;
1998         case MGN_MCS11:
1999                 rateIndex = 23;
2000                 break;
2001         case MGN_MCS12:
2002                 rateIndex = 24;
2003                 break;
2004         case MGN_MCS13:
2005                 rateIndex = 25;
2006                 break;
2007         case MGN_MCS14:
2008                 rateIndex = 26;
2009                 break;
2010         case MGN_MCS15:
2011                 rateIndex = 27;
2012                 break;
2013         default:
2014                 rateIndex = 28;
2015                 break;
2016         }
2017         priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
2018         priv->stats.received_rate_histogram[0][rateIndex]++;
2019         priv->stats.received_rate_histogram[rcvType][rateIndex]++;
2020 }
2021
2022 bool rtl8192_rx_query_status_desc(struct net_device *dev,
2023                                   struct rtllib_rx_stats *stats,
2024                                   struct rx_desc *pdesc,
2025                                   struct sk_buff *skb)
2026 {
2027         struct r8192_priv *priv = rtllib_priv(dev);
2028         struct rx_fwinfo *pDrvInfo = NULL;
2029
2030         stats->bICV = pdesc->ICV;
2031         stats->bCRC = pdesc->CRC32;
2032         stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2033
2034         stats->Length = pdesc->Length;
2035         if (stats->Length < 24)
2036                 stats->bHwError |= 1;
2037
2038         if (stats->bHwError) {
2039                 stats->bShift = false;
2040
2041                 if (pdesc->CRC32) {
2042                         if (pdesc->Length < 500)
2043                                 priv->stats.rxcrcerrmin++;
2044                         else if (pdesc->Length > 1000)
2045                                 priv->stats.rxcrcerrmax++;
2046                         else
2047                                 priv->stats.rxcrcerrmid++;
2048                 }
2049                 return false;
2050         }
2051
2052         stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2053         stats->RxBufShift = ((pdesc->Shift)&0x03);
2054         stats->Decrypted = !pdesc->SWDec;
2055
2056         pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
2057
2058         stats->rate = HwRateToMRate90((bool)pDrvInfo->RxHT,
2059                                      (u8)pDrvInfo->RxRate);
2060         stats->bShortPreamble = pDrvInfo->SPLCP;
2061
2062         rtl8192_UpdateReceivedRateHistogramStatistics(dev, stats);
2063
2064         stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2065         stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2066                             (pDrvInfo->FirstAGGR == 1);
2067
2068         stats->TimeStampLow = pDrvInfo->TSFL;
2069         stats->TimeStampHigh = read_nic_dword(dev, TSFR+4);
2070
2071         rtl819x_UpdateRxPktTimeStamp(dev, stats);
2072
2073         if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2074                 stats->bShift = 1;
2075
2076         stats->RxIs40MHzPacket = pDrvInfo->BW;
2077
2078         rtl8192_TranslateRxSignalStuff(dev, skb, stats, pdesc,
2079                                        pDrvInfo);
2080
2081         if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2082                 RT_TRACE(COMP_RXDESC,
2083                          "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n",
2084                          pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2085         skb_trim(skb, skb->len - 4/*sCrcLng*/);
2086
2087
2088         stats->packetlength = stats->Length-4;
2089         stats->fraglength = stats->packetlength;
2090         stats->fragoffset = 0;
2091         stats->ntotalfrag = 1;
2092         return true;
2093 }
2094
2095 void rtl8192_halt_adapter(struct net_device *dev, bool reset)
2096 {
2097         struct r8192_priv *priv = rtllib_priv(dev);
2098         int i;
2099         u8      OpMode;
2100         u8      u1bTmp;
2101         u32     ulRegRead;
2102
2103         OpMode = RT_OP_MODE_NO_LINK;
2104         priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2105
2106         if (!priv->rtllib->bSupportRemoteWakeUp) {
2107                 u1bTmp = 0x0;
2108                 write_nic_byte(dev, CMDR, u1bTmp);
2109         }
2110
2111         mdelay(20);
2112
2113         if (!reset) {
2114                 mdelay(150);
2115
2116                 priv->bHwRfOffAction = 2;
2117
2118                 if (!priv->rtllib->bSupportRemoteWakeUp) {
2119                         PHY_SetRtl8192eRfOff(dev);
2120                         ulRegRead = read_nic_dword(dev, CPU_GEN);
2121                         ulRegRead |= CPU_GEN_SYSTEM_RESET;
2122                         write_nic_dword(dev, CPU_GEN, ulRegRead);
2123                 } else {
2124                         write_nic_dword(dev, WFCRC0, 0xffffffff);
2125                         write_nic_dword(dev, WFCRC1, 0xffffffff);
2126                         write_nic_dword(dev, WFCRC2, 0xffffffff);
2127
2128
2129                         write_nic_byte(dev, PMR, 0x5);
2130                         write_nic_byte(dev, MacBlkCtrl, 0xa);
2131                 }
2132         }
2133
2134         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2135                 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2136         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2137                 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
2138
2139         skb_queue_purge(&priv->skb_queue);
2140 }
2141
2142 void rtl8192_update_ratr_table(struct net_device *dev)
2143 {
2144         struct r8192_priv *priv = rtllib_priv(dev);
2145         struct rtllib_device *ieee = priv->rtllib;
2146         u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
2147         u32 ratr_value = 0;
2148         u16 rate_config = 0;
2149         u8 rate_index = 0;
2150
2151         rtl8192_config_rate(dev, &rate_config);
2152         ratr_value = rate_config | *pMcsRate << 12;
2153         switch (ieee->mode) {
2154         case IEEE_A:
2155                 ratr_value &= 0x00000FF0;
2156                 break;
2157         case IEEE_B:
2158                 ratr_value &= 0x0000000F;
2159                 break;
2160         case IEEE_G:
2161         case IEEE_G|IEEE_B:
2162                 ratr_value &= 0x00000FF7;
2163                 break;
2164         case IEEE_N_24G:
2165         case IEEE_N_5G:
2166                 if (ieee->pHTInfo->PeerMimoPs == 0) {
2167                         ratr_value &= 0x0007F007;
2168                 } else {
2169                         if (priv->rf_type == RF_1T2R)
2170                                 ratr_value &= 0x000FF007;
2171                         else
2172                                 ratr_value &= 0x0F81F007;
2173                 }
2174                 break;
2175         default:
2176                 break;
2177         }
2178         ratr_value &= 0x0FFFFFFF;
2179         if (ieee->pHTInfo->bCurTxBW40MHz &&
2180             ieee->pHTInfo->bCurShortGI40MHz)
2181                 ratr_value |= 0x80000000;
2182         else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2183                   ieee->pHTInfo->bCurShortGI20MHz)
2184                 ratr_value |= 0x80000000;
2185         write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
2186         write_nic_byte(dev, UFWP, 1);
2187 }
2188
2189 void
2190 rtl8192_InitializeVariables(struct net_device  *dev)
2191 {
2192         struct r8192_priv *priv = rtllib_priv(dev);
2193
2194         strcpy(priv->nick, "rtl8192E");
2195
2196         priv->rtllib->softmac_features  = IEEE_SOFTMAC_SCAN |
2197                 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2198                 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2199
2200         priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2201
2202         priv->ShortRetryLimit = 0x30;
2203         priv->LongRetryLimit = 0x30;
2204
2205         priv->EarlyRxThreshold = 7;
2206         priv->pwrGroupCnt = 0;
2207
2208         priv->bIgnoreSilentReset = false;
2209         priv->enable_gpio0 = 0;
2210
2211         priv->TransmitConfig = 0;
2212
2213         priv->ReceiveConfig = RCR_ADD3  |
2214                 RCR_AMF | RCR_ADF |
2215                 RCR_AICV |
2216                 RCR_AB | RCR_AM | RCR_APM |
2217                 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2218                 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2219
2220         priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2221                             IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2222                             IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2223                             IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2224                             IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2225                             IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2226
2227
2228         priv->MidHighPwrTHR_L1 = 0x3B;
2229         priv->MidHighPwrTHR_L2 = 0x40;
2230         priv->PwrDomainProtect = false;
2231
2232         priv->bfirst_after_down = false;
2233 }
2234
2235 void rtl8192_EnableInterrupt(struct net_device *dev)
2236 {
2237         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2238
2239         priv->irq_enabled = 1;
2240
2241         write_nic_dword(dev, INTA_MASK, priv->irq_mask[0]);
2242
2243 }
2244
2245 void rtl8192_DisableInterrupt(struct net_device *dev)
2246 {
2247         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2248
2249         write_nic_dword(dev, INTA_MASK, 0);
2250
2251         priv->irq_enabled = 0;
2252 }
2253
2254 void rtl8192_ClearInterrupt(struct net_device *dev)
2255 {
2256         u32 tmp = 0;
2257
2258         tmp = read_nic_dword(dev, ISR);
2259         write_nic_dword(dev, ISR, tmp);
2260 }
2261
2262
2263 void rtl8192_enable_rx(struct net_device *dev)
2264 {
2265         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2266
2267         write_nic_dword(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2268 }
2269
2270 static const u32 TX_DESC_BASE[] = {
2271         BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2272 };
2273
2274 void rtl8192_enable_tx(struct net_device *dev)
2275 {
2276         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2277         u32 i;
2278
2279         for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2280                 write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2281 }
2282
2283
2284 void rtl8192_interrupt_recognized(struct net_device *dev, u32 *p_inta,
2285                                   u32 *p_intb)
2286 {
2287         *p_inta = read_nic_dword(dev, ISR);
2288         write_nic_dword(dev, ISR, *p_inta);
2289 }
2290
2291 bool rtl8192_HalRxCheckStuck(struct net_device *dev)
2292 {
2293         struct r8192_priv *priv = rtllib_priv(dev);
2294         u16               RegRxCounter = read_nic_word(dev, 0x130);
2295         bool              bStuck = false;
2296         static u8         rx_chk_cnt;
2297         u32             SlotIndex = 0, TotalRxStuckCount = 0;
2298         u8              i;
2299         u8              SilentResetRxSoltNum = 4;
2300
2301         RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2302                  __func__, RegRxCounter, priv->RxCounter);
2303
2304         rx_chk_cnt++;
2305         if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2306                 rx_chk_cnt = 0;
2307         } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2308           && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2309           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2310           || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2311           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2312                 if (rx_chk_cnt < 2)
2313                         return bStuck;
2314                 rx_chk_cnt = 0;
2315         } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2316                   (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2317                 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2318                  (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2319                 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2320                 if (rx_chk_cnt < 4)
2321                         return bStuck;
2322                 rx_chk_cnt = 0;
2323         } else {
2324                 if (rx_chk_cnt < 8)
2325                         return bStuck;
2326                 rx_chk_cnt = 0;
2327         }
2328
2329
2330         SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2331
2332         if (priv->RxCounter == RegRxCounter) {
2333                 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2334
2335                 for (i = 0; i < SilentResetRxSoltNum; i++)
2336                         TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2337
2338                 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2339                         bStuck = true;
2340                         for (i = 0; i < SilentResetRxSoltNum; i++)
2341                                 TotalRxStuckCount +=
2342                                          priv->SilentResetRxStuckEvent[i];
2343                 }
2344
2345
2346         } else {
2347                 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2348         }
2349
2350         priv->RxCounter = RegRxCounter;
2351
2352         return bStuck;
2353 }
2354
2355 bool rtl8192_HalTxCheckStuck(struct net_device *dev)
2356 {
2357         struct r8192_priv *priv = rtllib_priv(dev);
2358         bool    bStuck = false;
2359         u16     RegTxCounter = read_nic_word(dev, 0x128);
2360
2361         RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
2362                  __func__, RegTxCounter, priv->TxCounter);
2363
2364         if (priv->TxCounter == RegTxCounter)
2365                 bStuck = true;
2366
2367         priv->TxCounter = RegTxCounter;
2368
2369         return bStuck;
2370 }
2371
2372 bool rtl8192_GetNmodeSupportBySecCfg(struct net_device *dev)
2373 {
2374         struct r8192_priv *priv = rtllib_priv(dev);
2375         struct rtllib_device *ieee = priv->rtllib;
2376
2377         if (ieee->rtllib_ap_sec_type &&
2378            (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2379                                      SEC_ALG_TKIP))) {
2380                 return false;
2381         } else {
2382                 return true;
2383         }
2384 }
2385
2386 bool rtl8192_GetHalfNmodeSupportByAPs(struct net_device *dev)
2387 {
2388         bool Reval;
2389         struct r8192_priv *priv = rtllib_priv(dev);
2390         struct rtllib_device *ieee = priv->rtllib;
2391
2392         if (ieee->bHalfWirelessN24GMode == true)
2393                 Reval = true;
2394         else
2395                 Reval =  false;
2396
2397         return Reval;
2398 }
2399
2400 u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
2401 {
2402         u8   tmp_Short;
2403
2404         tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
2405                         ((tcb_desc->bUseShortPreamble) ? 1 : 0);
2406         if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
2407                 tmp_Short = 0;
2408
2409         return tmp_Short;
2410 }
2411
2412 void ActUpdateChannelAccessSetting(struct net_device *dev,
2413         enum wireless_mode WirelessMode,
2414         struct channel_access_setting *ChnlAccessSetting)
2415 {
2416 }