kernel/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.h

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * You should have received a copy of the GNU General Public License along with
  10  * this program; if not, write to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  12  *
  13  * The full GNU General Public License is included in this distribution in the
  14  * file called LICENSE.
  15  *
  16  * Contact Information:
  17  * wlanfae <wlanfae@realtek.com>
  18 ******************************************************************************/
  19 #ifndef R819XUSB_CMDPKT_H
  20 #define R819XUSB_CMDPKT_H
  21 #define CMPK_RX_TX_FB_SIZE              sizeof(struct cmpk_txfb)
  22 #define CMPK_TX_SET_CONFIG_SIZE         sizeof(struct cmpk_set_cfg)
  23 #define CMPK_BOTH_QUERY_CONFIG_SIZE     sizeof(struct cmpk_set_cfg)
  24 #define CMPK_RX_TX_STS_SIZE             sizeof(struct cmpk_tx_status)
  25 #define CMPK_RX_DBG_MSG_SIZE            sizeof(struct cmpk_rx_dbginfo)
  26 #define CMPK_TX_RAHIS_SIZE              sizeof(struct cmpk_tx_rahis)
  27
  28 #define ISR_TxBcnOk                     BIT27
  29 #define ISR_TxBcnErr                    BIT26
  30 #define ISR_BcnTimerIntr                BIT13
  31
  32
  33 struct cmpk_txfb {
  34         u8      element_id;
  35         u8      length;
  36         u8      TID:4;
  37         u8      fail_reason:3;
  38         u8      tok:1;
  39         u8      reserve1:4;
  40         u8      pkt_type:2;
  41         u8      bandwidth:1;
  42         u8      qos_pkt:1;
  43
  44         u8      reserve2;
  45         u8      retry_cnt;
  46         u16     pkt_id;
  47
  48         u16     seq_num;
  49         u8      s_rate;
  50         u8      f_rate;
  51
  52         u8      s_rts_rate;
  53         u8      f_rts_rate;
  54         u16     pkt_length;
  55
  56         u16     reserve3;
  57         u16     duration;
  58 };
  59
  60 struct cmpk_intr_sta {
  61         u8      element_id;
  62         u8      length;
  63         u16     reserve;
  64         u32     interrupt_status;
  65 };
  66
  67
  68 struct cmpk_set_cfg {
  69         u8      element_id;
  70         u8      length;
  71         u16     reserve1;
  72         u8      cfg_reserve1:3;
  73         u8      cfg_size:2;
  74         u8      cfg_type:2;
  75         u8      cfg_action:1;
  76         u8      cfg_reserve2;
  77         u8      cfg_page:4;
  78         u8      cfg_reserve3:4;
  79         u8      cfg_offset;
  80         u32     value;
  81         u32     mask;
  82 };
  83
  84 #define         cmpk_query_cfg_t        struct cmpk_set_cfg
  85
  86 struct cmpk_tx_status {
  87         u16     reserve1;
  88         u8      length;
  89         u8      element_id;
  90
  91         u16     txfail;
  92         u16     txok;
  93
  94         u16     txmcok;
  95         u16     txretry;
  96
  97         u16  txucok;
  98         u16     txbcok;
  99
 100         u16     txbcfail;
 101         u16     txmcfail;
 102
 103         u16     reserve2;
 104         u16     txucfail;
 105
 106         u32     txmclength;
 107         u32     txbclength;
 108         u32     txuclength;
 109
 110         u16     reserve3_23;
 111         u8      reserve3_1;
 112         u8      rate;
 113 } __packed;
 114
 115 struct cmpk_rx_dbginfo {
 116         u16     reserve1;
 117         u8      length;
 118         u8      element_id;
 119
 120
 121 };
 122
 123 struct cmpk_tx_rahis {
 124         u8      element_id;
 125         u8      length;
 126         u16     reserved1;
 127
 128         u16     cck[4];
 129
 130         u16     ofdm[8];
 131
 132
 133
 134
 135
 136         u16     ht_mcs[4][16];
 137
 138 } __packed;
 139
 140 enum cmpk_element {
 141         RX_TX_FEEDBACK = 0,
 142         RX_INTERRUPT_STATUS             = 1,
 143         TX_SET_CONFIG                   = 2,
 144         BOTH_QUERY_CONFIG               = 3,
 145         RX_TX_STATUS                    = 4,
 146         RX_DBGINFO_FEEDBACK             = 5,
 147         RX_TX_PER_PKT_FEEDBACK          = 6,
 148         RX_TX_RATE_HISTORY              = 7,
 149         RX_CMD_ELE_MAX
 150 };
 151
 152 extern  u32 cmpk_message_handle_rx(struct net_device *dev,
 153                                    struct rtllib_rx_stats *pstats);
 154 extern bool cmpk_message_handle_tx(struct net_device *dev,
 155                                    u8 *codevirtualaddress, u32 packettype,
 156                                    u32 buffer_len);
 157
 158
 159 #endif