kernel/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * The full GNU General Public License is included in this distribution in the
  10  * file called LICENSE.
  11  *
  12  * Contact Information:
  13  * wlanfae <wlanfae@realtek.com>
  14 ******************************************************************************/
  15
  16 #include "rtl_core.h"
  17 #include "r8192E_phyreg.h"
  18 #include "r8192E_phy.h"
  19 #include "r8190P_rtl8256.h"
  20
  21 void rtl92e_set_bandwidth(struct net_device *dev,
  22                           enum ht_channel_width Bandwidth)
  23 {
  24         u8      eRFPath;
  25         struct r8192_priv *priv = rtllib_priv(dev);
  26
  27         if (priv->card_8192_version != VERSION_8190_BD &&
  28             priv->card_8192_version != VERSION_8190_BE) {
  29                 netdev_warn(dev, "%s(): Unknown HW version.\n", __func__);
  30                 return;
  31         }
  32
  33         for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) {
  34                 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
  35                         continue;
  36
  37                 switch (Bandwidth) {
  38                 case HT_CHANNEL_WIDTH_20:
  39                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  40                                           0x0b, bMask12Bits, 0x100);
  41                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  42                                           0x2c, bMask12Bits, 0x3d7);
  43                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  44                                           0x0e, bMask12Bits, 0x021);
  45                         break;
  46                 case HT_CHANNEL_WIDTH_20_40:
  47                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  48                                           0x0b, bMask12Bits, 0x300);
  49                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  50                                           0x2c, bMask12Bits, 0x3ff);
  51                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  52                                           0x0e, bMask12Bits, 0x0e1);
  53                         break;
  54                 default:
  55                         netdev_err(dev, "%s(): Unknown bandwidth: %#X\n",
  56                                    __func__, Bandwidth);
  57                         break;
  58
  59                 }
  60         }
  61 }
  62
  63 bool rtl92e_config_rf(struct net_device *dev)
  64 {
  65         u32     u4RegValue = 0;
  66         u8      eRFPath;
  67         bool rtStatus = true;
  68         struct bb_reg_definition *pPhyReg;
  69         struct r8192_priv *priv = rtllib_priv(dev);
  70         u32     RegOffSetToBeCheck = 0x3;
  71         u32     RegValueToBeCheck = 0x7f1;
  72         u32     RF3_Final_Value = 0;
  73         u8      ConstRetryTimes = 5, RetryTimes = 5;
  74         u8 ret = 0;
  75
  76         priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
  77
  78         for (eRFPath = (enum rf90_radio_path)RF90_PATH_A;
  79              eRFPath < priv->NumTotalRFPath; eRFPath++) {
  80                 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
  81                         continue;
  82
  83                 pPhyReg = &priv->PHYRegDef[eRFPath];
  84
  85
  86                 switch (eRFPath) {
  87                 case RF90_PATH_A:
  88                 case RF90_PATH_C:
  89                         u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
  90                                                        bRFSI_RFENV);
  91                         break;
  92                 case RF90_PATH_B:
  93                 case RF90_PATH_D:
  94                         u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
  95                                                        bRFSI_RFENV<<16);
  96                         break;
  97                 }
  98
  99                 rtl92e_set_bb_reg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
 100
 101                 rtl92e_set_bb_reg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
 102
 103                 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
 104                                   b3WireAddressLength, 0x0);
 105                 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
 106                                   b3WireDataLength, 0x0);
 107
 108                 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 0x0,
 109                                   bMask12Bits, 0xbf);
 110
 111                 rtStatus = rtl92e_check_bb_and_rf(dev, HW90_BLOCK_RF,
 112                                                   (enum rf90_radio_path)eRFPath);
 113                 if (!rtStatus) {
 114                         netdev_err(dev, "%s(): Failed to check RF Path %d.\n",
 115                                    __func__, eRFPath);
 116                         goto fail;
 117                 }
 118
 119                 RetryTimes = ConstRetryTimes;
 120                 RF3_Final_Value = 0;
 121                 while (RF3_Final_Value != RegValueToBeCheck &&
 122                        RetryTimes != 0) {
 123                         ret = rtl92e_config_rf_path(dev,
 124                                                 (enum rf90_radio_path)eRFPath);
 125                         RF3_Final_Value = rtl92e_get_rf_reg(dev,
 126                                                 (enum rf90_radio_path)eRFPath,
 127                                                 RegOffSetToBeCheck,
 128                                                 bMask12Bits);
 129                         RT_TRACE(COMP_RF,
 130                                  "RF %d %d register final value: %x\n",
 131                                  eRFPath, RegOffSetToBeCheck,
 132                                  RF3_Final_Value);
 133                         RetryTimes--;
 134                 }
 135
 136                 switch (eRFPath) {
 137                 case RF90_PATH_A:
 138                 case RF90_PATH_C:
 139                         rtl92e_set_bb_reg(dev, pPhyReg->rfintfs, bRFSI_RFENV,
 140                                           u4RegValue);
 141                         break;
 142                 case RF90_PATH_B:
 143                 case RF90_PATH_D:
 144                         rtl92e_set_bb_reg(dev, pPhyReg->rfintfs,
 145                                           bRFSI_RFENV<<16, u4RegValue);
 146                         break;
 147                 }
 148
 149                 if (ret) {
 150                         netdev_err(dev,
 151                                    "%s(): Failed to initialize RF Path %d.\n",
 152                                    __func__, eRFPath);
 153                         goto fail;
 154                 }
 155
 156         }
 157
 158         RT_TRACE(COMP_PHY, "PHY Initialization Success\n");
 159         return true;
 160
 161 fail:
 162         return false;
 163 }
 164
 165 void rtl92e_set_cck_tx_power(struct net_device *dev, u8 powerlevel)
 166 {
 167         u32     TxAGC = 0;
 168         struct r8192_priv *priv = rtllib_priv(dev);
 169
 170         TxAGC = powerlevel;
 171         if (priv->bDynamicTxLowPower) {
 172                 if (priv->CustomerID == RT_CID_819x_Netcore)
 173                         TxAGC = 0x22;
 174                 else
 175                         TxAGC += priv->CckPwEnl;
 176         }
 177         if (TxAGC > 0x24)
 178                 TxAGC = 0x24;
 179         rtl92e_set_bb_reg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 180 }
 181
 182
 183 void rtl92e_set_ofdm_tx_power(struct net_device *dev, u8 powerlevel)
 184 {
 185         struct r8192_priv *priv = rtllib_priv(dev);
 186         u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
 187         u8 index = 0;
 188         u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
 189         u8 byte0, byte1, byte2, byte3;
 190
 191         powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff;
 192         powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
 193                      (powerBase0 << 8) | powerBase0;
 194         powerBase1 = powerlevel;
 195         powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) |
 196                      (powerBase1 << 8) | powerBase1;
 197
 198         for (index = 0; index < 6; index++) {
 199                 writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] +
 200                            ((index < 2) ? powerBase0 : powerBase1));
 201                 byte0 = (u8)(writeVal & 0x7f);
 202                 byte1 = (u8)((writeVal & 0x7f00)>>8);
 203                 byte2 = (u8)((writeVal & 0x7f0000)>>16);
 204                 byte3 = (u8)((writeVal & 0x7f000000)>>24);
 205                 if (byte0 > 0x24)
 206                         byte0 = 0x24;
 207                 if (byte1 > 0x24)
 208                         byte1 = 0x24;
 209                 if (byte2 > 0x24)
 210                         byte2 = 0x24;
 211                 if (byte3 > 0x24)
 212                         byte3 = 0x24;
 213
 214                 if (index == 3) {
 215                         writeVal_tmp = (byte3 << 24) | (byte2 << 16) |
 216                                        (byte1 << 8) | byte0;
 217                         priv->Pwr_Track = writeVal_tmp;
 218                 }
 219
 220                 if (priv->bDynamicTxHighPower)
 221                         writeVal = 0x03030303;
 222                 else
 223                         writeVal = (byte3 << 24) | (byte2 << 16) |
 224                                    (byte1 << 8) | byte0;
 225                 rtl92e_set_bb_reg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
 226         }
 227
 228 }