kernel/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * You should have received a copy of the GNU General Public License along with
  10  * this program; if not, write to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  12  *
  13  * The full GNU General Public License is included in this distribution in the
  14  * file called LICENSE.
  15  *
  16  * Contact Information:
  17  * wlanfae <wlanfae@realtek.com>
  18 ******************************************************************************/
  19
  20 #include "rtl_core.h"
  21 #include "r8192E_phyreg.h"
  22 #include "r8192E_phy.h"
  23 #include "r8190P_rtl8256.h"
  24
  25 void PHY_SetRF8256Bandwidth(struct net_device *dev,
  26                             enum ht_channel_width Bandwidth)
  27 {
  28         u8      eRFPath;
  29         struct r8192_priv *priv = rtllib_priv(dev);
  30
  31         for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) {
  32                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
  33                                 continue;
  34
  35                 switch (Bandwidth) {
  36                 case HT_CHANNEL_WIDTH_20:
  37                         if (priv->card_8192_version == VERSION_8190_BD ||
  38                             priv->card_8192_version == VERSION_8190_BE) {
  39                                 rtl8192_phy_SetRFReg(dev,
  40                                                 (enum rf90_radio_path)eRFPath,
  41                                                 0x0b, bMask12Bits, 0x100);
  42                                 rtl8192_phy_SetRFReg(dev,
  43                                                 (enum rf90_radio_path)eRFPath,
  44                                                 0x2c, bMask12Bits, 0x3d7);
  45                                 rtl8192_phy_SetRFReg(dev,
  46                                                 (enum rf90_radio_path)eRFPath,
  47                                                 0x0e, bMask12Bits, 0x021);
  48
  49                         } else {
  50                                 RT_TRACE(COMP_ERR,
  51                                          "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
  52                         }
  53
  54                         break;
  55                 case HT_CHANNEL_WIDTH_20_40:
  56                         if (priv->card_8192_version == VERSION_8190_BD ||
  57                             priv->card_8192_version == VERSION_8190_BE) {
  58                                 rtl8192_phy_SetRFReg(dev,
  59                                                  (enum rf90_radio_path)eRFPath,
  60                                                  0x0b, bMask12Bits, 0x300);
  61                                 rtl8192_phy_SetRFReg(dev,
  62                                                  (enum rf90_radio_path)eRFPath,
  63                                                  0x2c, bMask12Bits, 0x3ff);
  64                                 rtl8192_phy_SetRFReg(dev,
  65                                                  (enum rf90_radio_path)eRFPath,
  66                                                  0x0e, bMask12Bits, 0x0e1);
  67
  68                         } else {
  69                                 RT_TRACE(COMP_ERR,
  70                                          "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
  71                         }
  72
  73
  74                         break;
  75                 default:
  76                         RT_TRACE(COMP_ERR,
  77                                  "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",
  78                                  Bandwidth);
  79                         break;
  80
  81                 }
  82         }
  83 }
  84
  85 bool PHY_RF8256_Config(struct net_device *dev)
  86 {
  87         struct r8192_priv *priv = rtllib_priv(dev);
  88
  89         priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
  90         return phy_RF8256_Config_ParaFile(dev);
  91 }
  92
  93 bool phy_RF8256_Config_ParaFile(struct net_device *dev)
  94 {
  95         u32     u4RegValue = 0;
  96         u8      eRFPath;
  97         bool rtStatus = true;
  98         struct bb_reg_definition *pPhyReg;
  99         struct r8192_priv *priv = rtllib_priv(dev);
 100         u32     RegOffSetToBeCheck = 0x3;
 101         u32     RegValueToBeCheck = 0x7f1;
 102         u32     RF3_Final_Value = 0;
 103         u8      ConstRetryTimes = 5, RetryTimes = 5;
 104         u8 ret = 0;
 105
 106         for (eRFPath = (enum rf90_radio_path)RF90_PATH_A;
 107              eRFPath < priv->NumTotalRFPath; eRFPath++) {
 108                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 109                                 continue;
 110
 111                 pPhyReg = &priv->PHYRegDef[eRFPath];
 112
 113
 114                 switch (eRFPath) {
 115                 case RF90_PATH_A:
 116                 case RF90_PATH_C:
 117                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs,
 118                                                         bRFSI_RFENV);
 119                         break;
 120                 case RF90_PATH_B:
 121                 case RF90_PATH_D:
 122                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs,
 123                                                         bRFSI_RFENV<<16);
 124                         break;
 125                 }
 126
 127                 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
 128
 129                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
 130
 131                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,
 132                                  b3WireAddressLength, 0x0);
 133                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,
 134                                  b3WireDataLength, 0x0);
 135
 136                 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0,
 137                                      bMask12Bits, 0xbf);
 138
 139                 rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF,
 140                                                 (enum rf90_radio_path)eRFPath);
 141                 if (!rtStatus) {
 142                         RT_TRACE(COMP_ERR,
 143                                  "PHY_RF8256_Config():Check Radio[%d] Fail!!\n",
 144                                  eRFPath);
 145                         goto phy_RF8256_Config_ParaFile_Fail;
 146                 }
 147
 148                 RetryTimes = ConstRetryTimes;
 149                 RF3_Final_Value = 0;
 150                 switch (eRFPath) {
 151                 case RF90_PATH_A:
 152                         while (RF3_Final_Value != RegValueToBeCheck &&
 153                                RetryTimes != 0) {
 154                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
 155                                                 (enum rf90_radio_path)eRFPath);
 156                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
 157                                                  (enum rf90_radio_path)eRFPath,
 158                                                  RegOffSetToBeCheck,
 159                                                  bMask12Bits);
 160                                 RT_TRACE(COMP_RF,
 161                                          "RF %d %d register final value: %x\n",
 162                                          eRFPath, RegOffSetToBeCheck,
 163                                          RF3_Final_Value);
 164                                 RetryTimes--;
 165                         }
 166                         break;
 167                 case RF90_PATH_B:
 168                         while (RF3_Final_Value != RegValueToBeCheck &&
 169                                RetryTimes != 0) {
 170                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
 171                                                 (enum rf90_radio_path)eRFPath);
 172                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
 173                                                  (enum rf90_radio_path)eRFPath,
 174                                                  RegOffSetToBeCheck,
 175                                                  bMask12Bits);
 176                                 RT_TRACE(COMP_RF,
 177                                          "RF %d %d register final value: %x\n",
 178                                          eRFPath, RegOffSetToBeCheck,
 179                                          RF3_Final_Value);
 180                                 RetryTimes--;
 181                         }
 182                         break;
 183                 case RF90_PATH_C:
 184                         while (RF3_Final_Value != RegValueToBeCheck &&
 185                                RetryTimes != 0) {
 186                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
 187                                                 (enum rf90_radio_path)eRFPath);
 188                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
 189                                                 (enum rf90_radio_path)eRFPath,
 190                                                 RegOffSetToBeCheck,
 191                                                 bMask12Bits);
 192                                 RT_TRACE(COMP_RF,
 193                                          "RF %d %d register final value: %x\n",
 194                                          eRFPath, RegOffSetToBeCheck,
 195                                          RF3_Final_Value);
 196                                 RetryTimes--;
 197                         }
 198                         break;
 199                 case RF90_PATH_D:
 200                         while (RF3_Final_Value != RegValueToBeCheck &&
 201                                RetryTimes != 0) {
 202                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
 203                                                (enum rf90_radio_path)eRFPath);
 204                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
 205                                                (enum rf90_radio_path)eRFPath,
 206                                                RegOffSetToBeCheck, bMask12Bits);
 207                                 RT_TRACE(COMP_RF,
 208                                          "RF %d %d register final value: %x\n",
 209                                          eRFPath, RegOffSetToBeCheck,
 210                                          RF3_Final_Value);
 211                                 RetryTimes--;
 212                         }
 213                         break;
 214                 }
 215
 216                 switch (eRFPath) {
 217                 case RF90_PATH_A:
 218                 case RF90_PATH_C:
 219                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV,
 220                                          u4RegValue);
 221                         break;
 222                 case RF90_PATH_B:
 223                 case RF90_PATH_D:
 224                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16,
 225                                          u4RegValue);
 226                         break;
 227                 }
 228
 229                 if (ret) {
 230                         RT_TRACE(COMP_ERR,
 231                                  "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!",
 232                                  eRFPath);
 233                         goto phy_RF8256_Config_ParaFile_Fail;
 234                 }
 235
 236         }
 237
 238         RT_TRACE(COMP_PHY, "PHY Initialization Success\n");
 239         return true;
 240
 241 phy_RF8256_Config_ParaFile_Fail:
 242         RT_TRACE(COMP_ERR, "PHY Initialization failed\n");
 243         return false;
 244 }
 245
 246 void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel)
 247 {
 248         u32     TxAGC = 0;
 249         struct r8192_priv *priv = rtllib_priv(dev);
 250
 251         TxAGC = powerlevel;
 252         if (priv->bDynamicTxLowPower) {
 253                 if (priv->CustomerID == RT_CID_819x_Netcore)
 254                         TxAGC = 0x22;
 255                 else
 256                         TxAGC += priv->CckPwEnl;
 257         }
 258         if (TxAGC > 0x24)
 259                 TxAGC = 0x24;
 260         rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 261 }
 262
 263
 264 void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel)
 265 {
 266         struct r8192_priv *priv = rtllib_priv(dev);
 267         u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
 268         u8 index = 0;
 269         u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
 270         u8 byte0, byte1, byte2, byte3;
 271
 272         powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff;
 273         powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
 274                      (powerBase0 << 8) | powerBase0;
 275         powerBase1 = powerlevel;
 276         powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) |
 277                      (powerBase1 << 8) | powerBase1;
 278
 279         for (index = 0; index < 6; index++) {
 280                 writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] +
 281                            ((index < 2) ? powerBase0 : powerBase1));
 282                 byte0 = (u8)(writeVal & 0x7f);
 283                 byte1 = (u8)((writeVal & 0x7f00)>>8);
 284                 byte2 = (u8)((writeVal & 0x7f0000)>>16);
 285                 byte3 = (u8)((writeVal & 0x7f000000)>>24);
 286                 if (byte0 > 0x24)
 287                         byte0 = 0x24;
 288                 if (byte1 > 0x24)
 289                         byte1 = 0x24;
 290                 if (byte2 > 0x24)
 291                         byte2 = 0x24;
 292                 if (byte3 > 0x24)
 293                         byte3 = 0x24;
 294
 295                 if (index == 3) {
 296                         writeVal_tmp = (byte3 << 24) | (byte2 << 16) |
 297                                        (byte1 << 8) | byte0;
 298                         priv->Pwr_Track = writeVal_tmp;
 299                 }
 300
 301                 if (priv->bDynamicTxHighPower)
 302                         writeVal = 0x03030303;
 303                 else
 304                         writeVal = (byte3 << 24) | (byte2 << 16) |
 305                                    (byte1 << 8) | byte0;
 306                 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
 307         }
 308
 309 }