1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 *******************************************************************************/
19 #ifndef __RTL8188E_SPEC_H__
20 #define __RTL8188E_SPEC_H__
22 /* 8192C Regsiter offset definition */
24 #define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */
25 #define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */
27 #define MAC_ADDR_LEN 6
28 /* 8188E PKT_BUFF_ACCESS_CTRL value */
29 #define TXPKT_BUF_SELECT 0x69
30 #define RXPKT_BUF_SELECT 0xA5
31 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
34 /* 0x0000h ~ 0x00FFh System Configuration */
35 #define REG_SYS_ISO_CTRL 0x0000
36 #define REG_SYS_FUNC_EN 0x0002
37 #define REG_APS_FSMCO 0x0004
38 #define REG_SYS_CLKR 0x0008
39 #define REG_9346CR 0x000A
40 #define REG_EE_VPD 0x000C
41 #define REG_AFE_MISC 0x0010
42 #define REG_SPS0_CTRL 0x0011
43 #define REG_SPS_OCP_CFG 0x0018
44 #define REG_RSV_CTRL 0x001C
45 #define REG_RF_CTRL 0x001F
46 #define REG_LDOA15_CTRL 0x0020
47 #define REG_LDOV12D_CTRL 0x0021
48 #define REG_LDOHCI12_CTRL 0x0022
49 #define REG_LPLDO_CTRL 0x0023
50 #define REG_AFE_XTAL_CTRL 0x0024
51 #define REG_AFE_PLL_CTRL 0x0028
52 #define REG_APE_PLL_CTRL_EXT 0x002c
53 #define REG_EFUSE_CTRL 0x0030
54 #define REG_EFUSE_TEST 0x0034
55 #define REG_GPIO_MUXCFG 0x0040
56 #define REG_GPIO_IO_SEL 0x0042
57 #define REG_MAC_PINMUX_CFG 0x0043
58 #define REG_GPIO_PIN_CTRL 0x0044
59 #define REG_GPIO_INTM 0x0048
60 #define REG_LEDCFG0 0x004C
61 #define REG_LEDCFG1 0x004D
62 #define REG_LEDCFG2 0x004E
63 #define REG_LEDCFG3 0x004F
64 #define REG_FSIMR 0x0050
65 #define REG_FSISR 0x0054
66 #define REG_HSIMR 0x0058
67 #define REG_HSISR 0x005c
68 #define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS
69 * Multi-Function GPIO Pin Control. */
70 #define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS
71 * Multi-Function GPIO Select. */
72 #define REG_BB_PAD_CTRL 0x0064
73 #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS
74 * Multi-Function control source. */
75 #define REG_GPIO_OUTPUT 0x006c
76 #define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */
77 #define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */
78 #define REG_MCUFWDL 0x0080
79 #define REG_WOL_EVENT 0x0081 /* RTL8188E */
80 #define REG_MCUTSTCFG 0x0084
81 #define REG_HMEBOX_E0 0x0088
82 #define REG_HMEBOX_E1 0x008A
83 #define REG_HMEBOX_E2 0x008C
84 #define REG_HMEBOX_E3 0x008E
85 #define REG_HMEBOX_EXT_0 0x01F0
86 #define REG_HMEBOX_EXT_1 0x01F4
87 #define REG_HMEBOX_EXT_2 0x01F8
88 #define REG_HMEBOX_EXT_3 0x01FC
89 #define REG_HIMR_88E 0x00B0
90 #define REG_HISR_88E 0x00B4
91 #define REG_HIMRE_88E 0x00B8
92 #define REG_HISRE_88E 0x00BC
93 #define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection
95 #define REG_BIST_SCAN 0x00D0
96 #define REG_BIST_RPT 0x00D4
97 #define REG_BIST_ROM_RPT 0x00D8
98 #define REG_USB_SIE_INTF 0x00E0
99 #define REG_PCIE_MIO_INTF 0x00E4
100 #define REG_PCIE_MIO_INTD 0x00E8
101 #define REG_HPON_FSM 0x00EC
102 #define REG_SYS_CFG 0x00F0
103 #define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */
104 #define REG_TYPE_ID 0x00FC
106 #define REG_MAC_PHY_CTRL_NORMAL 0x00f8
108 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */
109 #define REG_CR 0x0100
110 #define REG_PBP 0x0104
111 #define REG_PKT_BUFF_ACCESS_CTRL 0x0106
112 #define REG_TRXDMA_CTRL 0x010C
113 #define REG_TRXFF_BNDY 0x0114
114 #define REG_TRXFF_STATUS 0x0118
115 #define REG_RXFF_PTR 0x011C
116 /* define REG_HIMR 0x0120 */
117 /* define REG_HISR 0x0124 */
118 #define REG_HIMRE 0x0128
119 #define REG_HISRE 0x012C
120 #define REG_CPWM 0x012F
121 #define REG_FWIMR 0x0130
122 #define REG_FTIMR 0x0138
123 #define REG_FWISR 0x0134
124 #define REG_PKTBUF_DBG_CTRL 0x0140
125 #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL)
126 #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2)
127 #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3)
128 #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2)
129 #define REG_PKTBUF_DBG_DATA_L 0x0144
130 #define REG_PKTBUF_DBG_DATA_H 0x0148
132 #define REG_TC0_CTRL 0x0150
133 #define REG_TC1_CTRL 0x0154
134 #define REG_TC2_CTRL 0x0158
135 #define REG_TC3_CTRL 0x015C
136 #define REG_TC4_CTRL 0x0160
137 #define REG_TCUNIT_BASE 0x0164
138 #define REG_MBIST_START 0x0174
139 #define REG_MBIST_DONE 0x0178
140 #define REG_MBIST_FAIL 0x017C
141 #define REG_32K_CTRL 0x0194 /* RTL8188E */
142 #define REG_C2HEVT_MSG_NORMAL 0x01A0
143 #define REG_C2HEVT_CLEAR 0x01AF
144 #define REG_MCUTST_1 0x01c0
145 #define REG_FMETHR 0x01C8
146 #define REG_HMETFR 0x01CC
147 #define REG_HMEBOX_0 0x01D0
148 #define REG_HMEBOX_1 0x01D4
149 #define REG_HMEBOX_2 0x01D8
150 #define REG_HMEBOX_3 0x01DC
152 #define REG_LLT_INIT 0x01E0
154 /* 0x0200h ~ 0x027Fh TXDMA Configuration */
155 #define REG_RQPN 0x0200
156 #define REG_FIFOPAGE 0x0204
157 #define REG_TDECTRL 0x0208
158 #define REG_TXDMA_OFFSET_CHK 0x020C
159 #define REG_TXDMA_STATUS 0x0210
160 #define REG_RQPN_NPQ 0x0214
162 /* 0x0280h ~ 0x02FFh RXDMA Configuration */
163 #define REG_RXDMA_AGG_PG_TH 0x0280
164 #define REG_RXPKT_NUM 0x0284
165 #define REG_RXDMA_STATUS 0x0288
167 /* 0x0300h ~ 0x03FFh PCIe */
168 #define REG_PCIE_CTRL_REG 0x0300
169 #define REG_INT_MIG 0x0304 /* Interrupt Migration */
170 #define REG_BCNQ_DESA 0x0308 /* TX Beacon Descr Address */
171 #define REG_HQ_DESA 0x0310 /* TX High Queue Descr Addr */
172 #define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descr Addr*/
173 #define REG_VOQ_DESA 0x0320 /* TX VO Queue Descr Addr */
174 #define REG_VIQ_DESA 0x0328 /* TX VI Queue Descr Addr */
175 #define REG_BEQ_DESA 0x0330 /* TX BE Queue Descr Addr */
176 #define REG_BKQ_DESA 0x0338 /* TX BK Queue Descr Addr */
177 #define REG_RX_DESA 0x0340 /* RX Queue Descr Addr */
178 #define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */
179 #define REG_DBG_SEL 0x0360 /* Debug Selection Register */
180 #define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */
181 #define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */
182 #define REG_WATCH_DOG 0x0368
184 /* RTL8723 series ------------------------------ */
185 #define REG_PCIE_HISR 0x03A0
187 /* spec version 11 */
188 /* 0x0400h ~ 0x047Fh Protocol Configuration */
189 #define REG_VOQ_INFORMATION 0x0400
190 #define REG_VIQ_INFORMATION 0x0404
191 #define REG_BEQ_INFORMATION 0x0408
192 #define REG_BKQ_INFORMATION 0x040C
193 #define REG_MGQ_INFORMATION 0x0410
194 #define REG_HGQ_INFORMATION 0x0414
195 #define REG_BCNQ_INFORMATION 0x0418
196 #define REG_TXPKT_EMPTY 0x041A
198 #define REG_CPU_MGQ_INFORMATION 0x041C
199 #define REG_FWHW_TXQ_CTRL 0x0420
200 #define REG_HWSEQ_CTRL 0x0423
201 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424
202 #define REG_TXPKTBUF_MGQ_BDNY 0x0425
203 #define REG_LIFETIME_EN 0x0426
204 #define REG_MULTI_BCNQ_OFFSET 0x0427
205 #define REG_SPEC_SIFS 0x0428
206 #define REG_RL 0x042A
207 #define REG_DARFRC 0x0430
208 #define REG_RARFRC 0x0438
209 #define REG_RRSR 0x0440
210 #define REG_ARFR0 0x0444
211 #define REG_ARFR1 0x0448
212 #define REG_ARFR2 0x044C
213 #define REG_ARFR3 0x0450
214 #define REG_AGGLEN_LMT 0x0458
215 #define REG_AMPDU_MIN_SPACE 0x045C
216 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
217 #define REG_FAST_EDCA_CTRL 0x0460
218 #define REG_RD_RESP_PKT_TH 0x0463
219 #define REG_INIRTS_RATE_SEL 0x0480
220 /* define REG_INIDATA_RATE_SEL 0x0484 */
221 #define REG_POWER_STATUS 0x04A4
222 #define REG_POWER_STAGE1 0x04B4
223 #define REG_POWER_STAGE2 0x04B8
224 #define REG_PKT_VO_VI_LIFE_TIME 0x04C0
225 #define REG_PKT_BE_BK_LIFE_TIME 0x04C2
226 #define REG_STBC_SETTING 0x04C4
227 #define REG_PROT_MODE_CTRL 0x04C8
228 #define REG_MAX_AGGR_NUM 0x04CA
229 #define REG_RTS_MAX_AGGR_NUM 0x04CB
230 #define REG_BAR_MODE_CTRL 0x04CC
231 #define REG_RA_TRY_RATE_AGG_LMT 0x04CF
232 #define REG_EARLY_MODE_CONTROL 0x4D0
233 #define REG_NQOS_SEQ 0x04DC
234 #define REG_QOS_SEQ 0x04DE
235 #define REG_NEED_CPU_HANDLE 0x04E0
236 #define REG_PKT_LOSE_RPT 0x04E1
237 #define REG_PTCL_ERR_STATUS 0x04E2
238 #define REG_TX_RPT_CTRL 0x04EC
239 #define REG_TX_RPT_TIME 0x04F0 /* 2 byte */
240 #define REG_DUMMY 0x04FC
242 /* 0x0500h ~ 0x05FFh EDCA Configuration */
243 #define REG_EDCA_VO_PARAM 0x0500
244 #define REG_EDCA_VI_PARAM 0x0504
245 #define REG_EDCA_BE_PARAM 0x0508
246 #define REG_EDCA_BK_PARAM 0x050C
247 #define REG_BCNTCFG 0x0510
248 #define REG_PIFS 0x0512
249 #define REG_RDG_PIFS 0x0513
250 #define REG_SIFS_CTX 0x0514
251 #define REG_SIFS_TRX 0x0516
252 #define REG_TSFTR_SYN_OFFSET 0x0518
253 #define REG_AGGR_BREAK_TIME 0x051A
254 #define REG_SLOT 0x051B
255 #define REG_TX_PTCL_CTRL 0x0520
256 #define REG_TXPAUSE 0x0522
257 #define REG_DIS_TXREQ_CLR 0x0523
258 #define REG_RD_CTRL 0x0524
259 /* Format for offset 540h-542h: */
260 /* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting
261 * beacon content before TBTT. */
262 /* [7:4]: Reserved. */
263 /* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding
264 * to send the beacon packet. */
265 /* [23:20]: Reserved */
268 /* |<--Setup--|--Hold------------>| */
269 /* --------------|---------------------- */
272 /* Note: We cannot update beacon content to HW or send any AC packets during
273 * the time between Setup and Hold. */
274 #define REG_TBTT_PROHIBIT 0x0540
275 #define REG_RD_NAV_NXT 0x0544
276 #define REG_NAV_PROT_LEN 0x0546
277 #define REG_BCN_CTRL 0x0550
278 #define REG_BCN_CTRL_1 0x0551
279 #define REG_MBID_NUM 0x0552
280 #define REG_DUAL_TSF_RST 0x0553
281 #define REG_BCN_INTERVAL 0x0554
282 #define REG_DRVERLYINT 0x0558
283 #define REG_BCNDMATIM 0x0559
284 #define REG_ATIMWND 0x055A
285 #define REG_BCN_MAX_ERR 0x055D
286 #define REG_RXTSF_OFFSET_CCK 0x055E
287 #define REG_RXTSF_OFFSET_OFDM 0x055F
288 #define REG_TSFTR 0x0560
289 #define REG_TSFTR1 0x0568
290 #define REG_ATIMWND_1 0x0570
291 #define REG_PSTIMER 0x0580
292 #define REG_TIMER0 0x0584
293 #define REG_TIMER1 0x0588
294 #define REG_ACMHWCTRL 0x05C0
296 /* define REG_FW_TSF_SYNC_CNT 0x04A0 */
297 #define REG_FW_RESET_TSF_CNT_1 0x05FC
298 #define REG_FW_RESET_TSF_CNT_0 0x05FD
299 #define REG_FW_BCN_DIS_CNT 0x05FE
301 /* 0x0600h ~ 0x07FFh WMAC Configuration */
302 #define REG_APSD_CTRL 0x0600
303 #define REG_BWOPMODE 0x0603
304 #define REG_TCR 0x0604
305 #define REG_RCR 0x0608
306 #define REG_RX_PKT_LIMIT 0x060C
307 #define REG_RX_DLK_TIME 0x060D
308 #define REG_RX_DRVINFO_SZ 0x060F
310 #define REG_MACID 0x0610
311 #define REG_BSSID 0x0618
312 #define REG_MAR 0x0620
313 #define REG_MBIDCAMCFG 0x0628
315 #define REG_USTIME_EDCA 0x0638
316 #define REG_MAC_SPEC_SIFS 0x063A
318 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */
319 /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
320 #define REG_R2T_SIFS 0x063C
321 /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
322 #define REG_T2T_SIFS 0x063E
323 #define REG_ACKTO 0x0640
324 #define REG_CTS2TO 0x0641
325 #define REG_EIFS 0x0642
328 #define RXERR_TYPE_OFDM_PPDU 0
329 #define RXERR_TYPE_OFDM_false_ALARM 1
330 #define RXERR_TYPE_OFDM_MPDU_OK 2
331 #define RXERR_TYPE_OFDM_MPDU_FAIL 3
332 #define RXERR_TYPE_CCK_PPDU 4
333 #define RXERR_TYPE_CCK_false_ALARM 5
334 #define RXERR_TYPE_CCK_MPDU_OK 6
335 #define RXERR_TYPE_CCK_MPDU_FAIL 7
336 #define RXERR_TYPE_HT_PPDU 8
337 #define RXERR_TYPE_HT_false_ALARM 9
338 #define RXERR_TYPE_HT_MPDU_TOTAL 10
339 #define RXERR_TYPE_HT_MPDU_OK 11
340 #define RXERR_TYPE_HT_MPDU_FAIL 12
341 #define RXERR_TYPE_RX_FULL_DROP 15
343 #define RXERR_COUNTER_MASK 0xFFFFF
344 #define RXERR_RPT_RST BIT(27)
345 #define _RXERR_RPT_SEL(type) ((type) << 28)
348 /* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test.
349 * The default value is always too small, but the WiFi TestPlan test
350 * by 25,000 microseconds of NAV through sending CTS in the air.
351 * We must update this value greater than 25,000 microseconds to pass
352 * the item. The offset of NAV_UPPER in 8192C Spec is incorrect, and
353 * the offset should be 0x0652. */
354 #define REG_NAV_UPPER 0x0652 /* unit of 128 */
357 /* define REG_NAV_CTRL 0x0650 */
358 #define REG_BACAMCMD 0x0654
359 #define REG_BACAMCONTENT 0x0658
360 #define REG_LBDLY 0x0660
361 #define REG_FWDLY 0x0661
362 #define REG_RXERR_RPT 0x0664
363 #define REG_WMAC_TRXPTCL_CTL 0x0668
366 #define REG_CAMCMD 0x0670
367 #define REG_CAMWRITE 0x0674
368 #define REG_CAMREAD 0x0678
369 #define REG_CAMDBG 0x067C
370 #define REG_SECCFG 0x0680
373 #define REG_WOW_CTRL 0x0690
374 #define REG_PS_RX_INFO 0x0692
375 #define REG_UAPSD_TID 0x0693
376 #define REG_WKFMCAM_CMD 0x0698
377 #define REG_WKFMCAM_NUM_88E 0x698
378 #define REG_RXFLTMAP0 0x06A0
379 #define REG_RXFLTMAP1 0x06A2
380 #define REG_RXFLTMAP2 0x06A4
381 #define REG_BCN_PSR_RPT 0x06A8
382 #define REG_BT_COEX_TABLE 0x06C0
384 /* Hardware Port 2 */
385 #define REG_MACID1 0x0700
386 #define REG_BSSID1 0x0708
388 /* 0xFE00h ~ 0xFE55h USB Configuration */
389 #define REG_USB_INFO 0xFE17
390 #define REG_USB_SPECIAL_OPTION 0xFE55
391 #define REG_USB_DMA_AGG_TO 0xFE5B
392 #define REG_USB_AGG_TO 0xFE5C
393 #define REG_USB_AGG_TH 0xFE5D
395 /* For normal chip */
396 #define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */
397 #define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */
398 #define REG_NORMAL_SIE_OPTIONAL 0xFE64
399 #define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */
400 #define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */
401 #define REG_NORMAL_SIE_OPTIONAL2 0xFE6C
402 #define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */
403 #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */
404 #define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */
406 /* TODO: use these definition when using REG_xxx naming rule. */
407 /* NOTE: DO NOT Remove these definition. Use later. */
409 #define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */
410 #define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */
411 #define MSR (REG_CR + 2) /* Media Status reg */
412 #define ISR REG_HISR_88E
413 /* Timing Sync Function Timer Register. */
414 #define TSFR REG_TSFTR
418 /* Redifine MACID register, to compatible prior ICs. */
419 /* MAC ID Register, Offset 0x0050-0x0053 */
420 #define IDR0 REG_MACID
421 /* MAC ID Register, Offset 0x0054-0x0055 */
422 #define IDR4 (REG_MACID + 4)
424 /* 9. Security Control Registers (Offset: ) */
425 /* IN 8190 Data Sheet is called CAMcmd */
426 #define RWCAM REG_CAMCMD
427 /* Software write CAM input content */
428 #define WCAMI REG_CAMWRITE
429 /* Software read/write CAM config */
430 #define RCAMO REG_CAMREAD
431 #define CAMDBG REG_CAMDBG
432 /* Security Configuration Register */
433 #define SECR REG_SECCFG
435 /* Unused register */
436 #define UnusedRegister 0x1BF
437 #define DCAM UnusedRegister
438 #define PSR UnusedRegister
439 #define BBAddr UnusedRegister
440 #define PhyDataR UnusedRegister
442 /* Min Spacing related settings. */
443 #define MAX_MSS_DENSITY_2T 0x13
444 #define MAX_MSS_DENSITY_1T 0x0A
446 /* EEPROM enable when set 1 */
447 #define CmdEEPROM_En BIT(5)
448 /* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */
449 #define CmdEERPOMSEL BIT(4)
450 #define Cmd9346CR_9356SEL BIT(4)
452 /* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */
453 #define GPIOSEL_GPIO 0
454 #define GPIOSEL_ENBT BIT(5)
456 /* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */
457 /* GPIO pins input value */
458 #define GPIO_IN REG_GPIO_PIN_CTRL
459 /* GPIO pins output value */
460 #define GPIO_OUT (REG_GPIO_PIN_CTRL+1)
461 /* GPIO pins output enable when a bit is set to "1"; otherwise,
462 * input is configured. */
463 #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)
464 #define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
466 /* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
467 #define HSIMR_GPIO12_0_INT_EN BIT(0)
468 #define HSIMR_SPS_OCP_INT_EN BIT(5)
469 #define HSIMR_RON_INT_EN BIT(6)
470 #define HSIMR_PDN_INT_EN BIT(7)
471 #define HSIMR_GPIO9_INT_EN BIT(25)
473 /* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
474 #define HSISR_GPIO12_0_INT BIT(0)
475 #define HSISR_SPS_OCP_INT BIT(5)
476 #define HSISR_RON_INT_EN BIT(6)
477 #define HSISR_PDNINT BIT(7)
478 #define HSISR_GPIO9_INT BIT(25)
480 /* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */
484 01: Link in ad hoc network
485 10: Link in infrastructure network
489 #define MSR_NOLINK 0x00
490 #define MSR_ADHOC 0x01
491 #define MSR_INFRA 0x02
494 /* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */
495 #define USB_INTR_CONTENT_C2H_OFFSET 0
496 #define USB_INTR_CONTENT_CPWM1_OFFSET 16
497 #define USB_INTR_CONTENT_CPWM2_OFFSET 20
498 #define USB_INTR_CONTENT_HISR_OFFSET 48
499 #define USB_INTR_CONTENT_HISRE_OFFSET 52
501 /* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */
502 /* IOL config for REG_FDHM0(Reg0x88) */
503 #define CMD_INIT_LLT BIT(0)
504 #define CMD_READ_EFUSE_MAP BIT(1)
505 #define CMD_EFUSE_PATCH BIT(2)
506 #define CMD_IOCONFIG BIT(3)
507 #define CMD_INIT_LLT_ERR BIT(4)
508 #define CMD_READ_EFUSE_MAP_ERR BIT(5)
509 #define CMD_EFUSE_PATCH_ERR BIT(6)
510 #define CMD_IOCONFIG_ERR BIT(7)
512 /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
513 /* 8192C Response Rate Set Register (offset 0x181, 24bits) */
514 #define RRSR_1M BIT(0)
515 #define RRSR_2M BIT(1)
516 #define RRSR_5_5M BIT(2)
517 #define RRSR_11M BIT(3)
518 #define RRSR_6M BIT(4)
519 #define RRSR_9M BIT(5)
520 #define RRSR_12M BIT(6)
521 #define RRSR_18M BIT(7)
522 #define RRSR_24M BIT(8)
523 #define RRSR_36M BIT(9)
524 #define RRSR_48M BIT(10)
525 #define RRSR_54M BIT(11)
526 #define RRSR_MCS0 BIT(12)
527 #define RRSR_MCS1 BIT(13)
528 #define RRSR_MCS2 BIT(14)
529 #define RRSR_MCS3 BIT(15)
530 #define RRSR_MCS4 BIT(16)
531 #define RRSR_MCS5 BIT(17)
532 #define RRSR_MCS6 BIT(18)
533 #define RRSR_MCS7 BIT(19)
535 /* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */
536 /* WOL bit information */
537 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
538 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
540 /* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */
541 #define BW_OPMODE_20MHZ BIT(2)
542 #define BW_OPMODE_5G BIT(1)
544 /* 8192C CAM Config Setting (offset 0x250, 1 byte) */
545 #define CAM_VALID BIT(15)
546 #define CAM_NOTVALID 0x0000
547 #define CAM_USEDK BIT(5)
549 #define CAM_CONTENT_COUNT 8
552 #define CAM_WEP40 0x01
553 #define CAM_TKIP 0x02
555 #define CAM_WEP104 0x05
558 #define TOTAL_CAM_ENTRY 32
559 #define HALF_CAM_ENTRY 16
561 #define CAM_CONFIG_USEDK true
562 #define CAM_CONFIG_NO_USEDK false
564 #define CAM_WRITE BIT(16)
565 #define CAM_READ 0x00000000
566 #define CAM_POLLINIG BIT(31)
568 #define SCR_UseDK 0x01
569 #define SCR_TxSecEnable 0x02
570 #define SCR_RxSecEnable 0x04
572 /* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */
573 #define WOW_PMEN BIT(0) /* Power management Enable. */
574 #define WOW_WOMEN BIT(1) /* WoW function on or off. */
575 #define WOW_MAGIC BIT(2) /* Magic packet */
576 #define WOW_UWF BIT(3) /* Unicast Wakeup frame. */
578 /* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */
579 /* 8188 IMR/ISR bits */
580 #define IMR_DISABLED_88E 0x0
581 /* IMR DW0(0x0060-0063) Bit 0-31 */
582 #define IMR_TXCCK_88E BIT(30) /* TXRPT interrupt when CCX bit of the packet is set */
583 #define IMR_PSTIMEOUT_88E BIT(29) /* Power Save Time Out Interrupt */
584 #define IMR_GTINT4_88E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
585 #define IMR_GTINT3_88E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
586 #define IMR_TBDER_88E BIT(26) /* Transmit Beacon0 Error */
587 #define IMR_TBDOK_88E BIT(25) /* Transmit Beacon0 OK */
588 #define IMR_TSF_BIT32_TOGGLE_88E BIT(24) /* TSF Timer BIT32 toggle indication interrupt */
589 #define IMR_BCNDMAINT0_88E BIT(20) /* Beacon DMA Interrupt 0 */
590 #define IMR_BCNDERR0_88E BIT(16) /* Beacon Queue DMA Error 0 */
591 #define IMR_HSISR_IND_ON_INT_88E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
592 #define IMR_BCNDMAINT_E_88E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
593 #define IMR_ATIMEND_88E BIT(12) /* CTWidnow End or ATIM Window End */
594 #define IMR_HISR1_IND_INT_88E BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */
595 #define IMR_C2HCMD_88E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */
596 #define IMR_CPWM2_88E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */
597 #define IMR_CPWM_88E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */
598 #define IMR_HIGHDOK_88E BIT(7) /* High Queue DMA OK */
599 #define IMR_MGNTDOK_88E BIT(6) /* Management Queue DMA OK */
600 #define IMR_BKDOK_88E BIT(5) /* AC_BK DMA OK */
601 #define IMR_BEDOK_88E BIT(4) /* AC_BE DMA OK */
602 #define IMR_VIDOK_88E BIT(3) /* AC_VI DMA OK */
603 #define IMR_VODOK_88E BIT(2) /* AC_VO DMA OK */
604 #define IMR_RDU_88E BIT(1) /* Rx Descriptor Unavailable */
605 #define IMR_ROK_88E BIT(0) /* Receive DMA OK */
607 /* IMR DW1(0x00B4-00B7) Bit 0-31 */
608 #define IMR_BCNDMAINT7_88E BIT(27) /* Beacon DMA Interrupt 7 */
609 #define IMR_BCNDMAINT6_88E BIT(26) /* Beacon DMA Interrupt 6 */
610 #define IMR_BCNDMAINT5_88E BIT(25) /* Beacon DMA Interrupt 5 */
611 #define IMR_BCNDMAINT4_88E BIT(24) /* Beacon DMA Interrupt 4 */
612 #define IMR_BCNDMAINT3_88E BIT(23) /* Beacon DMA Interrupt 3 */
613 #define IMR_BCNDMAINT2_88E BIT(22) /* Beacon DMA Interrupt 2 */
614 #define IMR_BCNDMAINT1_88E BIT(21) /* Beacon DMA Interrupt 1 */
615 #define IMR_BCNDERR7_88E BIT(20) /* Beacon DMA Error Int 7 */
616 #define IMR_BCNDERR6_88E BIT(19) /* Beacon DMA Error Int 6 */
617 #define IMR_BCNDERR5_88E BIT(18) /* Beacon DMA Error Int 5 */
618 #define IMR_BCNDERR4_88E BIT(17) /* Beacon DMA Error Int 4 */
619 #define IMR_BCNDERR3_88E BIT(16) /* Beacon DMA Error Int 3 */
620 #define IMR_BCNDERR2_88E BIT(15) /* Beacon DMA Error Int 2 */
621 #define IMR_BCNDERR1_88E BIT(14) /* Beacon DMA Error Int 1 */
622 #define IMR_ATIMEND_E_88E BIT(13) /* ATIM Window End Ext for Win7 */
623 #define IMR_TXERR_88E BIT(11) /* Tx Err Flag Int Status, write 1 clear. */
624 #define IMR_RXERR_88E BIT(10) /* Rx Err Flag INT Status, Write 1 clear */
625 #define IMR_TXFOVW_88E BIT(9) /* Transmit FIFO Overflow */
626 #define IMR_RXFOVW_88E BIT(8) /* Receive FIFO Overflow */
628 #define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */
631 #define HWSET_MAX_SIZE 256
632 #define HWSET_MAX_SIZE_88E 512
634 /*===================================================================
635 =====================================================================
636 Here the register defines are for 92C. When the define is as same with 92C,
637 we will use the 92C's define for the consistency
638 So the following defines for 92C is not entire!!!!!!
639 =====================================================================
640 =====================================================================*/
642 Based on Datasheet V33---090401
645 0x0000h ~ 0x00FFh System Configuration (256 Bytes)
646 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
647 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
648 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
649 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
650 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
651 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
652 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
653 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
655 /* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */
657 /* The bits of stopping AC(VO/VI/BE/BK) queue in datasheet
658 * RTL8192S/RTL8192C are wrong, */
659 /* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2,
661 /* 8723 and 88E may be not correct either in the earlier version. */
662 #define StopBecon BIT(6)
663 #define StopHigh BIT(5)
664 #define StopMgt BIT(4)
665 #define StopBK BIT(3)
666 #define StopBE BIT(2)
667 #define StopVI BIT(1)
668 #define StopVO BIT(0)
670 /* 8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */
671 #define RCR_APPFCS BIT(31) /* WMAC append FCS after payload */
672 #define RCR_APP_MIC BIT(30)
673 #define RCR_APP_PHYSTS BIT(28)
674 #define RCR_APP_ICV BIT(29)
675 #define RCR_APP_PHYST_RXFF BIT(28)
676 #define RCR_APP_BA_SSN BIT(27) /* Accept BA SSN */
677 #define RCR_ENMBID BIT(24) /* Enable Multiple BssId. */
678 #define RCR_LSIGEN BIT(23)
679 #define RCR_MFBEN BIT(22)
680 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */
681 #define RCR_AMF BIT(13) /* Accept management type frame */
682 #define RCR_ACF BIT(12) /* Accept control type frame */
683 #define RCR_ADF BIT(11) /* Accept data type frame */
684 #define RCR_AICV BIT(9) /* Accept ICV error packet */
685 #define RCR_ACRC32 BIT(8) /* Accept CRC32 error packet */
686 #define RCR_CBSSID_BCN BIT(7) /* Accept BSSID match packet
687 * (Rx beacon, probe rsp) */
688 #define RCR_CBSSID_DATA BIT(6) /* Accept BSSID match (Data)*/
689 #define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match */
690 #define RCR_APWRMGT BIT(5) /* Accept power management pkt*/
691 #define RCR_ADD3 BIT(4) /* Accept address 3 match pkt */
692 #define RCR_AB BIT(3) /* Accept broadcast packet */
693 #define RCR_AM BIT(2) /* Accept multicast packet */
694 #define RCR_APM BIT(1) /* Accept physical match pkt */
695 #define RCR_AAP BIT(0) /* Accept all unicast packet */
696 #define RCR_MXDMA_OFFSET 8
697 #define RCR_FIFO_OFFSET 13
699 /* 0xFE00h ~ 0xFE55h USB Configuration */
700 #define REG_USB_INFO 0xFE17
701 #define REG_USB_SPECIAL_OPTION 0xFE55
702 #define REG_USB_DMA_AGG_TO 0xFE5B
703 #define REG_USB_AGG_TO 0xFE5C
704 #define REG_USB_AGG_TH 0xFE5D
706 #define REG_USB_HRPWM 0xFE58
707 #define REG_USB_HCPWM 0xFE57
708 /* 8192C Regsiter Bit and Content definition */
709 /* 0x0000h ~ 0x00FFh System Configuration */
712 #define ISO_MD2PP BIT(0)
713 #define ISO_UA2USB BIT(1)
714 #define ISO_UD2CORE BIT(2)
715 #define ISO_PA2PCIE BIT(3)
716 #define ISO_PD2CORE BIT(4)
717 #define ISO_IP2MAC BIT(5)
718 #define ISO_DIOP BIT(6)
719 #define ISO_DIOE BIT(7)
720 #define ISO_EB2CORE BIT(8)
721 #define ISO_DIOR BIT(9)
722 #define PWC_EV12V BIT(15)
725 #define FEN_BBRSTB BIT(0)
726 #define FEN_BB_GLB_RSTn BIT(1)
727 #define FEN_USBA BIT(2)
728 #define FEN_UPLL BIT(3)
729 #define FEN_USBD BIT(4)
730 #define FEN_DIO_PCIE BIT(5)
731 #define FEN_PCIEA BIT(6)
732 #define FEN_PPLL BIT(7)
733 #define FEN_PCIED BIT(8)
734 #define FEN_DIOE BIT(9)
735 #define FEN_CPUEN BIT(10)
736 #define FEN_DCORE BIT(11)
737 #define FEN_ELDR BIT(12)
738 #define FEN_DIO_RF BIT(13)
739 #define FEN_HWPDN BIT(14)
740 #define FEN_MREGEN BIT(15)
743 #define PFM_LDALL BIT(0)
744 #define PFM_ALDN BIT(1)
745 #define PFM_LDKP BIT(2)
746 #define PFM_WOWL BIT(3)
748 #define PDN_PL BIT(5)
749 #define APFM_ONMAC BIT(8)
750 #define APFM_OFF BIT(9)
751 #define APFM_RSM BIT(10)
752 #define AFSM_HSUS BIT(11)
753 #define AFSM_PCIE BIT(12)
754 #define APDM_MAC BIT(13)
755 #define APDM_HOST BIT(14)
756 #define APDM_HPDN BIT(15)
757 #define RDY_MACON BIT(16)
758 #define SUS_HOST BIT(17)
759 #define ROP_ALD BIT(20)
760 #define ROP_PWR BIT(21)
761 #define ROP_SPS BIT(22)
762 #define SOP_MRST BIT(25)
763 #define SOP_FUSE BIT(26)
764 #define SOP_ABG BIT(27)
765 #define SOP_AMB BIT(28)
766 #define SOP_RCK BIT(29)
767 #define SOP_A8M BIT(30)
768 #define XOP_BTCK BIT(31)
771 #define ANAD16V_EN BIT(0)
773 #define MACSLP BIT(4)
774 #define LOADER_CLK_EN BIT(5)
778 #define BOOT_FROM_EEPROM BIT(4)
779 #define EEPROM_EN BIT(5)
787 #define RF_RSTB BIT(1)
788 #define RF_SDMRSTB BIT(2)
791 #define LDV12_EN BIT(0)
792 #define LDV12_SDBY BIT(1)
793 #define LPLDO_HSM BIT(2)
794 #define LPLDO_LSM_DIS BIT(3)
795 #define _LDV12_VADJ(x) (((x) & 0xF) << 4)
798 #define ALD_EN BIT(18)
799 #define EF_PD BIT(19)
800 #define EF_FLAG BIT(31)
802 /* 2 EFUSE_TEST (For RTL8723 partially) */
803 #define EF_TRPT BIT(7)
804 /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
805 #define EF_CELL_SEL (BIT(8)|BIT(9))
806 #define LDOE25_EN BIT(31)
807 #define EFUSE_SEL(x) (((x) & 0x3) << 8)
808 #define EFUSE_SEL_MASK 0x300
809 #define EFUSE_WIFI_SEL_0 0x0
810 #define EFUSE_BT_SEL_0 0x1
811 #define EFUSE_BT_SEL_1 0x2
812 #define EFUSE_BT_SEL_2 0x3
814 #define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */
815 #define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */
819 #define MCUFWDL_EN BIT(0)
820 #define MCUFWDL_RDY BIT(1)
821 #define FWDL_ChkSum_rpt BIT(2)
822 #define MACINI_RDY BIT(3)
823 #define BBINI_RDY BIT(4)
824 #define RFINI_RDY BIT(5)
825 #define WINTINI_RDY BIT(6)
826 #define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */
827 #define ROM_DLEN BIT(19)
828 #define CPRST BIT(23)
831 #define XCLK_VLD BIT(0)
832 #define ACLK_VLD BIT(1)
833 #define UCLK_VLD BIT(2)
834 #define PCLK_VLD BIT(3)
835 #define PCIRSTB BIT(4)
836 #define V15_VLD BIT(5)
837 #define SW_OFFLOAD_EN BIT(7)
838 #define SIC_IDLE BIT(8)
839 #define BD_MAC2 BIT(9)
840 #define BD_MAC1 BIT(10)
841 #define IC_MACPHY_MODE BIT(11)
842 #define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15))
843 #define BT_FUNC BIT(16)
844 #define VENDOR_ID BIT(19)
845 #define PAD_HWPD_IDN BIT(22)
846 #define TRP_VAUX_EN BIT(23) /* RTL ID */
847 #define TRP_BT_EN BIT(24)
848 #define BD_PKG_SEL BIT(25)
849 #define BD_HCI_SEL BIT(26)
850 #define TYPE_ID BIT(27)
852 #define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */
853 #define CHIP_VER_RTL_SHIFT 12
855 /* 2REG_GPIO_OUTSTS (For RTL8723 only) */
856 #define EFS_HCI_SEL (BIT(0)|BIT(1))
857 #define PAD_HCI_SEL (BIT(2)|BIT(3))
858 #define HCI_SEL (BIT(4)|BIT(5))
859 #define PKG_SEL_HCI BIT(6)
860 #define FEN_GPS BIT(7)
861 #define FEN_BT BIT(8)
862 #define FEN_WL BIT(9)
863 #define FEN_PCI BIT(10)
864 #define FEN_USB BIT(11)
865 #define BTRF_HWPDN_N BIT(12)
866 #define WLRF_HWPDN_N BIT(13)
867 #define PDN_BT_N BIT(14)
868 #define PDN_GPS_N BIT(15)
869 #define BT_CTL_HWPDN BIT(16)
870 #define GPS_CTL_HWPDN BIT(17)
871 #define PPHY_SUSB BIT(20)
872 #define UPHY_SUSB BIT(21)
873 #define PCI_SUSEN BIT(22)
874 #define USB_SUSEN BIT(23)
875 #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
878 #define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */
880 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */
882 /* 2 Function Enable Registers */
885 #define HCI_TXDMA_EN BIT(0)
886 #define HCI_RXDMA_EN BIT(1)
887 #define TXDMA_EN BIT(2)
888 #define RXDMA_EN BIT(3)
889 #define PROTOCOL_EN BIT(4)
890 #define SCHEDULE_EN BIT(5)
891 #define MACTXEN BIT(6)
892 #define MACRXEN BIT(7)
893 #define ENSWBCN BIT(8)
895 #define CALTMR_EN BIT(10) /* 32k CAL TMR enable */
898 #define _NETTYPE(x) (((x) & 0x3) << 16)
899 #define MASK_NETTYPE 0x30000
900 #define NT_NO_LINK 0x0
901 #define NT_LINK_AD_HOC 0x1
902 #define NT_LINK_AP 0x2
905 /* 2 PBP - Page Size Register */
906 #define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
907 #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
908 #define _PSRX_MASK 0xF
909 #define _PSTX_MASK 0xF0
911 #define _PSTX(x) ((x) << 4)
920 #define RXDMA_ARBBW_EN BIT(0)
921 #define RXSHFT_EN BIT(1)
922 #define RXDMA_AGG_EN BIT(2)
923 #define QS_VO_QUEUE BIT(8)
924 #define QS_VI_QUEUE BIT(9)
925 #define QS_BE_QUEUE BIT(10)
926 #define QS_BK_QUEUE BIT(11)
927 #define QS_MANAGER_QUEUE BIT(12)
928 #define QS_HIGH_QUEUE BIT(13)
930 #define HQSEL_VOQ BIT(0)
931 #define HQSEL_VIQ BIT(1)
932 #define HQSEL_BEQ BIT(2)
933 #define HQSEL_BKQ BIT(3)
934 #define HQSEL_MGTQ BIT(4)
935 #define HQSEL_HIQ BIT(5)
937 /* For normal driver, 0x10C */
938 #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
939 #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
940 #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
941 #define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)
942 #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)
943 #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)
946 #define QUEUE_NORMAL 2
952 #define _LLT_NO_ACTIVE 0x0
953 #define _LLT_WRITE_ACCESS 0x1
954 #define _LLT_READ_ACCESS 0x2
956 #define _LLT_INIT_DATA(x) ((x) & 0xFF)
957 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
958 #define _LLT_OP(x) (((x) & 0x3) << 30)
959 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
961 /* 0x0200h ~ 0x027Fh TXDMA Configuration */
963 #define _HPQ(x) ((x) & 0xFF)
964 #define _LPQ(x) (((x) & 0xFF) << 8)
965 #define _PUBQ(x) (((x) & 0xFF) << 16)
966 /* NOTE: in RQPN_NPQ register */
967 #define _NPQ(x) ((x) & 0xFF)
969 #define HPQ_PUBLIC_DIS BIT(24)
970 #define LPQ_PUBLIC_DIS BIT(25)
971 #define LD_RQPN BIT(31)
974 #define BCN_VALID BIT(16)
975 #define BCN_HEAD(x) (((x) & 0xFF) << 8)
976 #define BCN_HEAD_MASK 0xFF00
979 #define BLK_DESC_NUM_SHIFT 4
980 #define BLK_DESC_NUM_MASK 0xF
982 /* 2 TXDMA_OFFSET_CHK */
983 #define DROP_DATA_EN BIT(9)
985 /* 0x0280h ~ 0x028Bh RX DMA Configuration */
987 /* REG_RXDMA_CONTROL, 0x0286h */
989 /* 2 REG_RXPKT_NUM, 0x0284 */
990 #define RXPKT_RELEASE_POLL BIT(16)
991 #define RXDMA_IDLE BIT(17)
992 #define RW_RELEASE_EN BIT(18)
994 /* 0x0400h ~ 0x047Fh Protocol Configuration */
995 /* 2 FWHW_TXQ_CTRL */
996 #define EN_AMPDU_RTY_NEW BIT(7)
999 #define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
1000 #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
1003 #define RETRY_LIMIT_SHORT_SHIFT 8
1004 #define RETRY_LIMIT_LONG_SHIFT 0
1006 /* 0x0500h ~ 0x05FFh EDCA Configuration */
1008 /* 2 EDCA setting */
1009 #define AC_PARAM_TXOP_LIMIT_OFFSET 16
1010 #define AC_PARAM_ECW_MAX_OFFSET 12
1011 #define AC_PARAM_ECW_MIN_OFFSET 8
1012 #define AC_PARAM_AIFS_OFFSET 0
1014 #define _LRL(x) ((x) & 0x3F)
1015 #define _SRL(x) (((x) & 0x3F) << 8)
1018 #define EN_MBSSID BIT(1)
1019 #define EN_TXBCN_RPT BIT(2)
1020 #define EN_BCN_FUNCTION BIT(3)
1021 #define DIS_TSF_UPDATE BIT(3)
1023 /* The same function but different bit field. */
1024 #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
1025 #define DIS_TSF_UDT0_TEST_CHIP BIT(5)
1026 #define STOP_BCNQ BIT(6)
1029 #define AcmHw_HwEn BIT(0)
1030 #define AcmHw_BeqEn BIT(1)
1031 #define AcmHw_ViqEn BIT(2)
1032 #define AcmHw_VoqEn BIT(3)
1033 #define AcmHw_BeqStatus BIT(4)
1034 #define AcmHw_ViqStatus BIT(5)
1035 #define AcmHw_VoqStatus BIT(6)
1037 /* 0x0600h ~ 0x07FFh WMAC Configuration */
1039 #define APSDOFF BIT(6)
1040 #define APSDOFF_STATUS BIT(7)
1042 #define RATE_BITMAP_ALL 0xFFFFF
1044 /* Only use CCK 1M rate for ACK */
1045 #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
1048 #define TSFRST BIT(0)
1049 #define DIS_GCLK BIT(1)
1050 #define PAD_SEL BIT(2)
1051 #define PWR_ST BIT(6)
1052 #define PWRBIT_OW_EN BIT(7)
1054 #define CFENDFORM BIT(9)
1063 #define APWRMGT BIT(5)
1064 #define CBSSID BIT(6)
1065 #define CBSSID_DATA BIT(6)
1066 #define CBSSID_BCN BIT(7)
1067 #define ACRC32 BIT(8)
1072 #define HTC_LOC_CTRL BIT(14)
1073 #define UC_DATA_EN BIT(16)
1074 #define BM_DATA_EN BIT(17)
1075 #define MFBEN BIT(22)
1076 #define LSIGEN BIT(23)
1077 #define EnMBID BIT(24)
1078 #define APP_BASSN BIT(27)
1079 #define APP_PHYSTS BIT(28)
1080 #define APP_ICV BIT(29)
1081 #define APP_MIC BIT(30)
1082 #define APP_FCS BIT(31)
1085 #define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */
1086 #define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */
1087 #define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */
1088 #define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */
1089 #define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */
1090 #define SCR_NoSKMC BIT(5) /* No Key Search Multicast */
1091 #define SCR_TXBCUSEDK BIT(6) /* Force Tx Bcast pkt Use Default Key */
1092 #define SCR_RXBCUSEDK BIT(7) /* Force Rx Bcast pkt Use Default Key */
1094 /* RTL8188E SDIO Configuration */
1096 /* I/O bus domain address mapping */
1097 #define SDIO_LOCAL_BASE 0x10250000
1098 #define WLAN_IOREG_BASE 0x10260000
1099 #define FIRMWARE_FIFO_BASE 0x10270000
1100 #define TX_HIQ_BASE 0x10310000
1101 #define TX_MIQ_BASE 0x10320000
1102 #define TX_LOQ_BASE 0x10330000
1103 #define RX_RX0FF_BASE 0x10340000
1105 /* SDIO host local register space mapping. */
1106 #define SDIO_LOCAL_MSK 0x0FFF
1107 #define WLAN_IOREG_MSK 0x7FFF
1108 #define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */
1109 #define WLAN_RX0FF_MSK 0x0003
1111 /* Without ref to the SDIO Device ID */
1112 #define SDIO_WITHOUT_REF_DEVICE_ID 0
1113 #define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */
1114 #define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */
1115 #define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */
1116 #define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */
1117 #define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */
1118 #define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */
1120 /* SDIO Tx Free Page Index */
1121 #define HI_QUEUE_IDX 0
1122 #define MID_QUEUE_IDX 1
1123 #define LOW_QUEUE_IDX 2
1124 #define PUBLIC_QUEUE_IDX 3
1126 #define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */
1127 #define SDIO_MAX_RX_QUEUE 1
1129 /* SDIO Tx Control */
1130 #define SDIO_REG_TX_CTRL 0x0000
1131 /* SDIO Host Interrupt Mask */
1132 #define SDIO_REG_HIMR 0x0014
1133 /* SDIO Host Interrupt Service Routine */
1134 #define SDIO_REG_HISR 0x0018
1135 /* HCI Current Power Mode */
1136 #define SDIO_REG_HCPWM 0x0019
1137 /* RXDMA Request Length */
1138 #define SDIO_REG_RX0_REQ_LEN 0x001C
1139 /* Free Tx Buffer Page */
1140 #define SDIO_REG_FREE_TXPG 0x0020
1141 /* HCI Current Power Mode 1 */
1142 #define SDIO_REG_HCPWM1 0x0024
1143 /* HCI Current Power Mode 2 */
1144 #define SDIO_REG_HCPWM2 0x0026
1145 /* HTSF Informaion */
1146 #define SDIO_REG_HTSFR_INFO 0x0030
1147 /* HCI Request Power Mode 1 */
1148 #define SDIO_REG_HRPWM1 0x0080
1149 /* HCI Request Power Mode 2 */
1150 #define SDIO_REG_HRPWM2 0x0082
1151 /* HCI Power Save Clock */
1152 #define SDIO_REG_HPS_CLKR 0x0084
1153 /* SDIO HCI Suspend Control */
1154 #define SDIO_REG_HSUS_CTRL 0x0086
1155 /* SDIO Host Extension Interrupt Mask Always */
1156 #define SDIO_REG_HIMR_ON 0x0090
1157 /* SDIO Host Extension Interrupt Status Always */
1158 #define SDIO_REG_HISR_ON 0x0091
1160 #define SDIO_HIMR_DISABLED 0
1162 /* RTL8188E SDIO Host Interrupt Mask Register */
1163 #define SDIO_HIMR_RX_REQUEST_MSK BIT(0)
1164 #define SDIO_HIMR_AVAL_MSK BIT(1)
1165 #define SDIO_HIMR_TXERR_MSK BIT(2)
1166 #define SDIO_HIMR_RXERR_MSK BIT(3)
1167 #define SDIO_HIMR_TXFOVW_MSK BIT(4)
1168 #define SDIO_HIMR_RXFOVW_MSK BIT(5)
1169 #define SDIO_HIMR_TXBCNOK_MSK BIT(6)
1170 #define SDIO_HIMR_TXBCNERR_MSK BIT(7)
1171 #define SDIO_HIMR_BCNERLY_INT_MSK BIT(16)
1172 #define SDIO_HIMR_C2HCMD_MSK BIT(17)
1173 #define SDIO_HIMR_CPWM1_MSK BIT(18)
1174 #define SDIO_HIMR_CPWM2_MSK BIT(19)
1175 #define SDIO_HIMR_HSISR_IND_MSK BIT(20)
1176 #define SDIO_HIMR_GTINT3_IND_MSK BIT(21)
1177 #define SDIO_HIMR_GTINT4_IND_MSK BIT(22)
1178 #define SDIO_HIMR_PSTIMEOUT_MSK BIT(23)
1179 #define SDIO_HIMR_OCPINT_MSK BIT(24)
1180 #define SDIO_HIMR_ATIMEND_MSK BIT(25)
1181 #define SDIO_HIMR_ATIMEND_E_MSK BIT(26)
1182 #define SDIO_HIMR_CTWEND_MSK BIT(27)
1184 /* RTL8188E SDIO Specific */
1185 #define SDIO_HIMR_MCU_ERR_MSK BIT(28)
1186 #define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT(29)
1188 /* SDIO Host Interrupt Service Routine */
1189 #define SDIO_HISR_RX_REQUEST BIT(0)
1190 #define SDIO_HISR_AVAL BIT(1)
1191 #define SDIO_HISR_TXERR BIT(2)
1192 #define SDIO_HISR_RXERR BIT(3)
1193 #define SDIO_HISR_TXFOVW BIT(4)
1194 #define SDIO_HISR_RXFOVW BIT(5)
1195 #define SDIO_HISR_TXBCNOK BIT(6)
1196 #define SDIO_HISR_TXBCNERR BIT(7)
1197 #define SDIO_HISR_BCNERLY_INT BIT(16)
1198 #define SDIO_HISR_C2HCMD BIT(17)
1199 #define SDIO_HISR_CPWM1 BIT(18)
1200 #define SDIO_HISR_CPWM2 BIT(19)
1201 #define SDIO_HISR_HSISR_IND BIT(20)
1202 #define SDIO_HISR_GTINT3_IND BIT(21)
1203 #define SDIO_HISR_GTINT4_IND BIT(22)
1204 #define SDIO_HISR_PSTIME BIT(23)
1205 #define SDIO_HISR_OCPINT BIT(24)
1206 #define SDIO_HISR_ATIMEND BIT(25)
1207 #define SDIO_HISR_ATIMEND_E BIT(26)
1208 #define SDIO_HISR_CTWEND BIT(27)
1210 /* RTL8188E SDIO Specific */
1211 #define SDIO_HISR_MCU_ERR BIT(28)
1212 #define SDIO_HISR_TSF_BIT32_TOGGLE BIT(29)
1214 #define MASK_SDIO_HISR_CLEAR \
1215 (SDIO_HISR_TXERR | SDIO_HISR_RXERR | SDIO_HISR_TXFOVW |\
1216 SDIO_HISR_RXFOVW | SDIO_HISR_TXBCNOK | SDIO_HISR_TXBCNERR |\
1217 SDIO_HISR_C2HCMD | SDIO_HISR_CPWM1 | SDIO_HISR_CPWM2 |\
1218 SDIO_HISR_HSISR_IND | SDIO_HISR_GTINT3_IND | SDIO_HISR_GTINT4_IND |\
1219 SDIO_HISR_PSTIMEOUT | SDIO_HISR_OCPINT)
1221 /* SDIO HCI Suspend Control Register */
1222 #define HCI_RESUME_PWR_RDY BIT(1)
1223 #define HCI_SUS_CTRL BIT(0)
1225 /* SDIO Tx FIFO related */
1226 /* The number of Tx FIFO free page */
1227 #define SDIO_TX_FREE_PG_QUEUE 4
1228 #define SDIO_TX_FIFO_PAGE_SZ 128
1230 /* 0xFE00h ~ 0xFE55h USB Configuration */
1232 /* 2 USB Information (0xFE17) */
1233 #define USB_IS_HIGH_SPEED 0
1234 #define USB_IS_FULL_SPEED 1
1235 #define USB_SPEED_MASK BIT(5)
1237 #define USB_NORMAL_SIE_EP_MASK 0xF
1238 #define USB_NORMAL_SIE_EP_SHIFT 4
1240 /* 2 Special Option */
1241 #define USB_AGG_EN BIT(3)
1243 /* 0; Use interrupt endpoint to upload interrupt pkt */
1244 /* 1; Use bulk endpoint to upload interrupt pkt, */
1245 #define INT_BULK_SEL BIT(4)
1247 /* 2REG_C2HEVT_CLEAR */
1248 /* Set by driver and notify FW that the driver has read
1249 * the C2H command message */
1250 #define C2H_EVT_HOST_CLOSE 0x00
1251 /* Set by FW indicating that FW had set the C2H command
1252 * message and it's not yet read by driver. */
1253 #define C2H_EVT_FW_CLOSE 0xFF
1255 /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
1256 /* Enable GPIO[9] as WiFi HW PDn source */
1257 #define WL_HWPDN_EN BIT(0)
1258 /* WiFi HW PDn polarity control */
1259 #define WL_HWPDN_SL BIT(1)
1260 /* WiFi function enable */
1261 #define WL_FUNC_EN BIT(2)
1262 /* Enable GPIO[9] as WiFi RF HW PDn source */
1263 #define WL_HWROF_EN BIT(3)
1264 /* Enable GPIO[11] as BT HW PDn source */
1265 #define BT_HWPDN_EN BIT(16)
1266 /* BT HW PDn polarity control */
1267 #define BT_HWPDN_SL BIT(17)
1268 /* BT function enable */
1269 #define BT_FUNC_EN BIT(18)
1270 /* Enable GPIO[11] as BT/GPS RF HW PDn source */
1271 #define BT_HWROF_EN BIT(19)
1272 /* Enable GPIO[10] as GPS HW PDn source */
1273 #define GPS_HWPDN_EN BIT(20)
1274 /* GPS HW PDn polarity control */
1275 #define GPS_HWPDN_SL BIT(21)
1276 /* GPS function enable */
1277 #define GPS_FUNC_EN BIT(22)
1279 /* 3 REG_LIFECTRL_CTRL */
1280 #define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3)
1281 #define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2)
1282 #define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1)
1283 #define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0)
1285 #define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us */
1287 /* General definitions */
1288 #define LAST_ENTRY_OF_TX_PKT_BUFFER 176 /* 22k 22528 bytes */
1290 #define POLLING_LLT_THRESHOLD 20
1291 #define POLLING_READY_TIMEOUT_COUNT 1000
1293 #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1295 /* 8192C EEPROM/EFUSE share register definition. */
1297 /* EEPROM/Efuse PG Offset for 88EE/88EU/88ES */
1298 #define EEPROM_TX_PWR_INX_88E 0x10
1300 #define EEPROM_ChannelPlan_88E 0xB8
1301 #define EEPROM_XTAL_88E 0xB9
1302 #define EEPROM_THERMAL_METER_88E 0xBA
1303 #define EEPROM_IQK_LCK_88E 0xBB
1305 #define EEPROM_RF_BOARD_OPTION_88E 0xC1
1306 #define EEPROM_RF_FEATURE_OPTION_88E 0xC2
1307 #define EEPROM_RF_BT_SETTING_88E 0xC3
1308 #define EEPROM_VERSION_88E 0xC4
1309 #define EEPROM_CUSTOMERID_88E 0xC5
1310 #define EEPROM_RF_ANTENNA_OPT_88E 0xC9
1313 #define EEPROM_MAC_ADDR_88EE 0xD0
1314 #define EEPROM_VID_88EE 0xD6
1315 #define EEPROM_DID_88EE 0xD8
1316 #define EEPROM_SVID_88EE 0xDA
1317 #define EEPROM_SMID_88EE 0xDC
1320 #define EEPROM_MAC_ADDR_88EU 0xD7
1321 #define EEPROM_VID_88EU 0xD0
1322 #define EEPROM_PID_88EU 0xD2
1323 #define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4
1326 #define EEPROM_MAC_ADDR_88ES 0x11A
1328 /* EEPROM/Efuse Value Type */
1329 #define EETYPE_TX_PWR 0x0
1331 /* Default Value for EEPROM or EFUSE!!! */
1332 #define EEPROM_Default_TSSI 0x0
1333 #define EEPROM_Default_TxPowerDiff 0x0
1334 #define EEPROM_Default_CrystalCap 0x5
1335 /* Default: 2X2, RTL8192CE(QFPN68) */
1336 #define EEPROM_Default_BoardType 0x02
1337 #define EEPROM_Default_TxPower 0x1010
1338 #define EEPROM_Default_HT2T_TxPwr 0x10
1340 #define EEPROM_Default_LegacyHTTxPowerDiff 0x3
1341 #define EEPROM_Default_ThermalMeter 0x12
1343 #define EEPROM_Default_AntTxPowerDiff 0x0
1344 #define EEPROM_Default_TxPwDiff_CrystalCap 0x5
1345 #define EEPROM_Default_TxPowerLevel 0x2A
1347 #define EEPROM_Default_HT40_2SDiff 0x0
1348 /* HT20<->40 default Tx Power Index Difference */
1349 #define EEPROM_Default_HT20_Diff 2
1350 #define EEPROM_Default_LegacyHTTxPowerDiff 0x3
1351 #define EEPROM_Default_HT40_PwrMaxOffset 0
1352 #define EEPROM_Default_HT20_PwrMaxOffset 0
1354 #define EEPROM_Default_CrystalCap_88E 0x20
1355 #define EEPROM_Default_ThermalMeter_88E 0x18
1357 /* New EFUSE deafult value */
1358 #define EEPROM_DEFAULT_24G_INDEX 0x2D
1359 #define EEPROM_DEFAULT_24G_HT20_DIFF 0X02
1360 #define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04
1362 #define EEPROM_DEFAULT_5G_INDEX 0X2A
1363 #define EEPROM_DEFAULT_5G_HT20_DIFF 0X00
1364 #define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04
1366 #define EEPROM_DEFAULT_DIFF 0XFE
1367 #define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F
1368 #define EEPROM_DEFAULT_BOARD_OPTION 0x00
1369 #define EEPROM_DEFAULT_FEATURE_OPTION 0x00
1370 #define EEPROM_DEFAULT_BT_OPTION 0x10
1373 #define EEPROM_Default_PID 0x1234
1374 #define EEPROM_Default_VID 0x5678
1375 #define EEPROM_Default_CustomerID 0xAB
1376 #define EEPROM_Default_CustomerID_8188E 0x00
1377 #define EEPROM_Default_SubCustomerID 0xCD
1378 #define EEPROM_Default_Version 0
1380 #define EEPROM_CHANNEL_PLAN_FCC 0x0
1381 #define EEPROM_CHANNEL_PLAN_IC 0x1
1382 #define EEPROM_CHANNEL_PLAN_ETSI 0x2
1383 #define EEPROM_CHANNEL_PLAN_SPA 0x3
1384 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4
1385 #define EEPROM_CHANNEL_PLAN_MKK 0x5
1386 #define EEPROM_CHANNEL_PLAN_MKK1 0x6
1387 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
1388 #define EEPROM_CHANNEL_PLAN_TELEC 0x8
1389 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9
1390 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
1391 #define EEPROM_CHANNEL_PLAN_NCC 0xB
1392 #define EEPROM_USB_OPTIONAL1 0xE
1393 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
1395 #define EEPROM_CID_DEFAULT 0x0
1396 #define EEPROM_CID_TOSHIBA 0x4
1397 #define EEPROM_CID_CCX 0x10 /* CCX test. */
1398 #define EEPROM_CID_QMI 0x0D
1399 #define EEPROM_CID_WHQL 0xFE
1400 #define RTL_EEPROM_ID 0x8129
1402 #endif /* __RTL8188E_SPEC_H__ */
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