kernel/drivers/staging/rtl8188eu/include/odm_HWConfig.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 #ifndef __HALHWOUTSRC_H__
  22 #define __HALHWOUTSRC_H__
  23
  24 /*  Definition */
  25 /*  CCK Rates, TxHT = 0 */
  26 #define DESC92C_RATE1M                          0x00
  27 #define DESC92C_RATE2M                          0x01
  28 #define DESC92C_RATE5_5M                        0x02
  29 #define DESC92C_RATE11M                         0x03
  30
  31 /*  OFDM Rates, TxHT = 0 */
  32 #define DESC92C_RATE6M                          0x04
  33 #define DESC92C_RATE9M                          0x05
  34 #define DESC92C_RATE12M                         0x06
  35 #define DESC92C_RATE18M                         0x07
  36 #define DESC92C_RATE24M                         0x08
  37 #define DESC92C_RATE36M                         0x09
  38 #define DESC92C_RATE48M                         0x0a
  39 #define DESC92C_RATE54M                         0x0b
  40
  41 /*  MCS Rates, TxHT = 1 */
  42 #define DESC92C_RATEMCS0                        0x0c
  43 #define DESC92C_RATEMCS1                        0x0d
  44 #define DESC92C_RATEMCS2                        0x0e
  45 #define DESC92C_RATEMCS3                        0x0f
  46 #define DESC92C_RATEMCS4                        0x10
  47 #define DESC92C_RATEMCS5                        0x11
  48 #define DESC92C_RATEMCS6                        0x12
  49 #define DESC92C_RATEMCS7                        0x13
  50 #define DESC92C_RATEMCS8                        0x14
  51 #define DESC92C_RATEMCS9                        0x15
  52 #define DESC92C_RATEMCS10                       0x16
  53 #define DESC92C_RATEMCS11                       0x17
  54 #define DESC92C_RATEMCS12                       0x18
  55 #define DESC92C_RATEMCS13                       0x19
  56 #define DESC92C_RATEMCS14                       0x1a
  57 #define DESC92C_RATEMCS15                       0x1b
  58 #define DESC92C_RATEMCS15_SG                    0x1c
  59 #define DESC92C_RATEMCS32                       0x20
  60
  61 /*  structure and define */
  62
  63 struct phy_rx_agc_info {
  64         #ifdef __LITTLE_ENDIAN
  65                 u8      gain:7, trsw:1;
  66         #else
  67                 u8      trsw:1, gain:7;
  68         #endif
  69 };
  70
  71 struct phy_status_rpt {
  72         struct phy_rx_agc_info path_agc[3];
  73         u8      ch_corr[2];
  74         u8      cck_sig_qual_ofdm_pwdb_all;
  75         u8      cck_agc_rpt_ofdm_cfosho_a;
  76         u8      cck_rpt_b_ofdm_cfosho_b;
  77         u8      rsvd_1;/* ch_corr_msb; */
  78         u8      noise_power_db_msb;
  79         u8      path_cfotail[2];
  80         u8      pcts_mask[2];
  81         s8      stream_rxevm[2];
  82         u8      path_rxsnr[3];
  83         u8      noise_power_db_lsb;
  84         u8      rsvd_2[3];
  85         u8      stream_csi[2];
  86         u8      stream_target_csi[2];
  87         s8      sig_evm;
  88         u8      rsvd_3;
  89
  90 #ifdef __LITTLE_ENDIAN
  91         u8      antsel_rx_keep_2:1;     /* ex_intf_flg:1; */
  92         u8      sgi_en:1;
  93         u8      rxsc:2;
  94         u8      idle_long:1;
  95         u8      r_ant_train_en:1;
  96         u8      ant_sel_b:1;
  97         u8      ant_sel:1;
  98 #else   /*  _BIG_ENDIAN_ */
  99         u8      ant_sel:1;
 100         u8      ant_sel_b:1;
 101         u8      r_ant_train_en:1;
 102         u8      idle_long:1;
 103         u8      rxsc:2;
 104         u8      sgi_en:1;
 105         u8      antsel_rx_keep_2:1;     /* ex_intf_flg:1; */
 106 #endif
 107 };
 108
 109 void odm_Init_RSSIForDM(struct odm_dm_struct *pDM_Odm);
 110
 111 void ODM_PhyStatusQuery(struct odm_dm_struct *pDM_Odm,
 112                         struct odm_phy_status_info *pPhyInfo,
 113                         u8 *pPhyStatus,
 114                         struct odm_per_pkt_info *pPktinfo);
 115
 116 void ODM_MacStatusQuery(struct odm_dm_struct *pDM_Odm,
 117                         u8 *pMacStatus,
 118                         u8      MacID,
 119                         bool    bPacketMatchBSSID,
 120                         bool    bPacketToSelf,
 121                         bool    bPacketBeacon);
 122
 123 enum HAL_STATUS ODM_ConfigBBWithHeaderFile(struct odm_dm_struct *pDM_Odm,
 124                                            enum odm_bb_config_type ConfigType);
 125
 126 #endif