kernel/drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __INC_HAL8188EPHYCFG_H__
  21 #define __INC_HAL8188EPHYCFG_H__
  22
  23
  24 /*--------------------------Define Parameters-------------------------------*/
  25 #define LOOP_LIMIT                      5
  26 #define MAX_STALL_TIME                  50              /* us */
  27 #define AntennaDiversityValue           0x80
  28 #define MAX_TXPWR_IDX_NMODE_92S         63
  29 #define Reset_Cnt_Limit                 3
  30
  31 #define IQK_MAC_REG_NUM                 4
  32 #define IQK_ADDA_REG_NUM                16
  33 #define IQK_BB_REG_NUM                  9
  34 #define HP_THERMAL_NUM                  8
  35
  36 #define MAX_AGGR_NUM                    0x07
  37
  38
  39 /*--------------------------Define Parameters-------------------------------*/
  40
  41
  42 /*------------------------------Define structure----------------------------*/
  43 enum sw_chnl_cmd_id {
  44         CmdID_End,
  45         CmdID_SetTxPowerLevel,
  46         CmdID_BBRegWrite10,
  47         CmdID_WritePortUlong,
  48         CmdID_WritePortUshort,
  49         CmdID_WritePortUchar,
  50         CmdID_RF_WriteReg,
  51 };
  52
  53 /* 1. Switch channel related */
  54 struct sw_chnl_cmd {
  55         enum sw_chnl_cmd_id CmdID;
  56         u32 Para1;
  57         u32 Para2;
  58         u32 msDelay;
  59 };
  60
  61 enum hw90_block {
  62         HW90_BLOCK_MAC = 0,
  63         HW90_BLOCK_PHY0 = 1,
  64         HW90_BLOCK_PHY1 = 2,
  65         HW90_BLOCK_RF = 3,
  66         HW90_BLOCK_MAXIMUM = 4, /*  Never use this */
  67 };
  68
  69 enum rf_radio_path {
  70         RF_PATH_A = 0,                  /* Radio Path A */
  71         RF_PATH_B = 1,                  /* Radio Path B */
  72         RF_PATH_C = 2,                  /* Radio Path C */
  73         RF_PATH_D = 3,                  /* Radio Path D */
  74 };
  75
  76 #define MAX_PG_GROUP 13
  77
  78 #define RF_PATH_MAX                     3
  79 #define         MAX_RF_PATH             RF_PATH_MAX
  80 #define         MAX_TX_COUNT            4 /* path numbers */
  81
  82 #define CHANNEL_MAX_NUMBER              14      /*  14 is the max chnl number */
  83 #define MAX_CHNL_GROUP_24G              6       /*  ch1~2, ch3~5, ch6~8,
  84                                                  *ch9~11, ch12~13, CH 14
  85                                                  * total three groups */
  86 #define CHANNEL_GROUP_MAX_88E           6
  87
  88 enum wireless_mode {
  89         WIRELESS_MODE_UNKNOWN = 0x00,
  90         WIRELESS_MODE_A                 = BIT2,
  91         WIRELESS_MODE_B                 = BIT0,
  92         WIRELESS_MODE_G                 = BIT1,
  93         WIRELESS_MODE_AUTO              = BIT5,
  94         WIRELESS_MODE_N_24G             = BIT3,
  95         WIRELESS_MODE_N_5G              = BIT4,
  96         WIRELESS_MODE_AC                = BIT6
  97 };
  98
  99 enum phy_rate_tx_offset_area {
 100         RA_OFFSET_LEGACY_OFDM1,
 101         RA_OFFSET_LEGACY_OFDM2,
 102         RA_OFFSET_HT_OFDM1,
 103         RA_OFFSET_HT_OFDM2,
 104         RA_OFFSET_HT_OFDM3,
 105         RA_OFFSET_HT_OFDM4,
 106         RA_OFFSET_HT_CCK,
 107 };
 108
 109 /* BB/RF related */
 110 enum RF_TYPE_8190P {
 111         RF_TYPE_MIN,            /*  0 */
 112         RF_8225 = 1,            /*  1 11b/g RF for verification only */
 113         RF_8256 = 2,            /*  2 11b/g/n */
 114         RF_8258 = 3,            /*  3 11a/b/g/n RF */
 115         RF_6052 = 4,            /*  4 11b/g/n RF */
 116         /*  TODO: We should remove this psudo PHY RF after we get new RF. */
 117         RF_PSEUDO_11N = 5,      /*  5, It is a temporality RF. */
 118 };
 119
 120 struct bb_reg_def {
 121         u32 rfintfs;            /*  set software control: */
 122                                 /*      0x870~0x877[8 bytes] */
 123         u32 rfintfi;            /*  readback data: */
 124                                 /*      0x8e0~0x8e7[8 bytes] */
 125         u32 rfintfo;            /*  output data: */
 126                                 /*      0x860~0x86f [16 bytes] */
 127         u32 rfintfe;            /*  output enable: */
 128                                 /*      0x860~0x86f [16 bytes] */
 129         u32 rf3wireOffset;      /*  LSSI data: */
 130                                 /*      0x840~0x84f [16 bytes] */
 131         u32 rfLSSI_Select;      /*  BB Band Select: */
 132                                 /*      0x878~0x87f [8 bytes] */
 133         u32 rfTxGainStage;      /*  Tx gain stage: */
 134                                 /*      0x80c~0x80f [4 bytes] */
 135         u32 rfHSSIPara1;        /*  wire parameter control1 : */
 136                                 /*      0x820~0x823,0x828~0x82b,
 137                                  *      0x830~0x833, 0x838~0x83b [16 bytes] */
 138         u32 rfHSSIPara2;        /*  wire parameter control2 : */
 139                                 /*      0x824~0x827,0x82c~0x82f, 0x834~0x837,
 140                                  *      0x83c~0x83f [16 bytes] */
 141         u32 rfSwitchControl;    /* Tx Rx antenna control : */
 142                                 /*      0x858~0x85f [16 bytes] */
 143         u32 rfAGCControl1;      /* AGC parameter control1 : */
 144                                 /*      0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
 145                                  * 0xc68~0xc6b [16 bytes] */
 146         u32 rfAGCControl2;      /* AGC parameter control2 : */
 147                                 /*      0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
 148                                  *      0xc6c~0xc6f [16 bytes] */
 149         u32 rfRxIQImbalance;    /* OFDM Rx IQ imbalance matrix : */
 150                                 /*      0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
 151                                  *      0xc2c~0xc2f [16 bytes] */
 152         u32 rfRxAFE;            /* Rx IQ DC ofset and Rx digital filter,
 153                                  * Rx DC notch filter : */
 154                                 /*      0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
 155                                  *      0xc28~0xc2b [16 bytes] */
 156         u32 rfTxIQImbalance;    /* OFDM Tx IQ imbalance matrix */
 157                                 /*      0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
 158                                  *       0xc98~0xc9b [16 bytes] */
 159         u32 rfTxAFE;            /* Tx IQ DC Offset and Tx DFIR type */
 160                                 /*      0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
 161                                  *      0xc9c~0xc9f [16 bytes] */
 162         u32 rfLSSIReadBack;     /* LSSI RF readback data SI mode */
 163                                 /*      0x8a0~0x8af [16 bytes] */
 164         u32 rfLSSIReadBackPi;   /* LSSI RF readback data PI mode 0x8b8-8bc for
 165                                  * Path A and B */
 166 };
 167
 168 struct ant_sel_ofdm {
 169         u32 r_tx_antenna:4;
 170         u32 r_ant_l:4;
 171         u32 r_ant_non_ht:4;
 172         u32 r_ant_ht1:4;
 173         u32 r_ant_ht2:4;
 174         u32 r_ant_ht_s1:4;
 175         u32 r_ant_non_ht_s1:4;
 176         u32 OFDM_TXSC:2;
 177         u32 reserved:2;
 178 };
 179
 180 struct ant_sel_cck {
 181         u8 r_cckrx_enable_2:2;
 182         u8 r_cckrx_enable:2;
 183         u8 r_ccktx_enable:4;
 184 };
 185
 186 /*------------------------------Define structure----------------------------*/
 187
 188
 189 /*------------------------Export global variable----------------------------*/
 190 /*------------------------Export global variable----------------------------*/
 191
 192
 193 /*------------------------Export Marco Definition---------------------------*/
 194 /*------------------------Export Marco Definition---------------------------*/
 195
 196
 197 /*--------------------------Exported Function prototype---------------------*/
 198 /*  */
 199 /*  BB and RF register read/write */
 200 /*  */
 201
 202 /* Read initi reg value for tx power setting. */
 203 void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter);
 204
 205 /*  BB TX Power R/W */
 206 void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel);
 207
 208 void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);
 209
 210 /*  Call after initialization */
 211 void ChkFwCmdIoDone(struct adapter *adapter);
 212
 213 /*  BB/MAC/RF other monitor API */
 214 void PHY_SetRFPathSwitch_8188E(struct adapter *adapter, bool main);
 215
 216 void PHY_SwitchEphyParameter(struct adapter *adapter);
 217
 218 void PHY_EnableHostClkReq(struct adapter *adapter);
 219
 220 bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant);
 221
 222 /*--------------------------Exported Function prototype---------------------*/
 223
 224 #define PHY_SetMacReg   PHY_SetBBReg
 225
 226 #define SIC_HW_SUPPORT                  0
 227
 228 #define SIC_MAX_POLL_CNT                5
 229
 230 #define SIC_CMD_READY                   0
 231 #define SIC_CMD_WRITE                   1
 232 #define SIC_CMD_READ                    2
 233
 234 #define SIC_CMD_REG                     0x1EB           /*  1byte */
 235 #define SIC_ADDR_REG                    0x1E8           /*  1b9~1ba, 2 bytes */
 236 #define SIC_DATA_REG                    0x1EC           /*  1bc~1bf */
 237
 238 #endif  /*  __INC_HAL8192CPHYCFG_H */