1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #define _RTL8188E_XMIT_C_
21 #include <osdep_service.h>
22 #include <drv_types.h>
24 #include <osdep_intf.h>
25 #include <usb_ops_linux.h>
26 #include <rtl8188e_hal.h>
28 s32 rtl8188eu_init_xmit_priv(struct adapter *adapt)
30 struct xmit_priv *pxmitpriv = &adapt->xmitpriv;
32 tasklet_init(&pxmitpriv->xmit_tasklet,
33 (void(*)(unsigned long))rtl8188eu_xmit_tasklet,
34 (unsigned long)adapt);
38 static u8 urb_zero_packet_chk(struct adapter *adapt, int sz)
40 u8 set_tx_desc_offset;
41 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
42 set_tx_desc_offset = (((sz + TXDESC_SIZE) % haldata->UsbBulkOutSize) == 0) ? 1 : 0;
44 return set_tx_desc_offset;
47 static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc)
49 u16 *usptr = (u16 *)ptxdesc;
50 u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */
55 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
57 for (index = 0; index < count; index++)
58 checksum = checksum ^ le16_to_cpu(*(__le16 *)(usptr + index));
59 ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff & checksum);
62 /* Description: In normal chip, we should send some packet to Hw which will be used by Fw */
63 /* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */
64 /* Fw can tell Hw to send these packet derectly. */
65 void rtl8188e_fill_fake_txdesc(struct adapter *adapt, u8 *desc, u32 BufferLen, u8 ispspoll, u8 is_btqosnull)
67 struct tx_desc *ptxdesc;
69 /* Clear all status */
70 ptxdesc = (struct tx_desc *)desc;
71 memset(desc, 0, TXDESC_SIZE);
74 ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); /* own, bFirstSeg, bLastSeg; */
76 ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000); /* 32 bytes for TX Desc */
78 ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); /* Buffer size + command header */
81 ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<<QSEL_SHT)&0x00001f00); /* Fixed queue of Mgnt queue */
83 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */
85 ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
87 ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */
88 ptxdesc->txdw3 |= cpu_to_le32((8 << 28)); /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
92 ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */
95 ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
97 /* USB interface drop packet if the checksum of descriptor isn't correct. */
98 /* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */
99 rtl8188eu_cal_txdesc_chksum(ptxdesc);
102 static void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc)
104 if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
105 switch (pattrib->encrypt) {
106 /* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */
109 ptxdesc->txdw1 |= cpu_to_le32((0x01<<SEC_TYPE_SHT)&0x00c00000);
110 ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
114 ptxdesc->txdw1 |= cpu_to_le32((0x01<<SEC_TYPE_SHT)&0x00c00000);
115 ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
118 ptxdesc->txdw1 |= cpu_to_le32((0x03<<SEC_TYPE_SHT)&0x00c00000);
119 ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
128 static void fill_txdesc_vcs(struct pkt_attrib *pattrib, __le32 *pdw)
130 switch (pattrib->vcs_mode) {
132 *pdw |= cpu_to_le32(RTS_EN);
135 *pdw |= cpu_to_le32(CTS_2_SELF);
141 if (pattrib->vcs_mode) {
142 *pdw |= cpu_to_le32(HW_RTS_EN);
144 if (pattrib->ht_en) {
145 *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(27)) : 0;
147 if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
148 *pdw |= cpu_to_le32((0x01 << 28) & 0x30000000);
149 else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
150 *pdw |= cpu_to_le32((0x02 << 28) & 0x30000000);
151 else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
154 *pdw |= cpu_to_le32((0x03 << 28) & 0x30000000);
159 static void fill_txdesc_phy(struct pkt_attrib *pattrib, __le32 *pdw)
161 if (pattrib->ht_en) {
162 *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(25)) : 0;
164 if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
165 *pdw |= cpu_to_le32((0x01 << DATA_SC_SHT) & 0x003f0000);
166 else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
167 *pdw |= cpu_to_le32((0x02 << DATA_SC_SHT) & 0x003f0000);
168 else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
171 *pdw |= cpu_to_le32((0x03 << DATA_SC_SHT) & 0x003f0000);
175 static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bagg_pkt)
179 u8 data_rate, pwr_status, offset;
180 struct adapter *adapt = pxmitframe->padapter;
181 struct pkt_attrib *pattrib = &pxmitframe->attrib;
182 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
183 struct tx_desc *ptxdesc = (struct tx_desc *)pmem;
184 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
185 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
186 int bmcst = IS_MCAST(pattrib->ra);
188 if (adapt->registrypriv.mp_mode == 0) {
189 if ((!bagg_pkt) && (urb_zero_packet_chk(adapt, sz) == 0)) {
190 ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ);
195 memset(ptxdesc, 0, sizeof(struct tx_desc));
198 ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
199 ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);/* update TXPKTSIZE */
201 offset = TXDESC_SIZE + OFFSET_SZ;
203 ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);/* 32 bytes for TX Desc */
206 ptxdesc->txdw0 |= cpu_to_le32(BMC);
208 if (adapt->registrypriv.mp_mode == 0) {
210 if ((pull) && (pxmitframe->pkt_offset > 0))
211 pxmitframe->pkt_offset = pxmitframe->pkt_offset - 1;
215 /* pkt_offset, unit:8 bytes padding */
216 if (pxmitframe->pkt_offset > 0)
217 ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000);
219 /* driver uses rate */
220 ptxdesc->txdw4 |= cpu_to_le32(USERATE);/* rate control always by driver */
222 if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {
224 ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id & 0x3F);
226 qsel = (uint)(pattrib->qsel & 0x0000001f);
227 ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
229 ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000);
231 fill_txdesc_sectype(pattrib, ptxdesc);
233 if (pattrib->ampdu_en) {
234 ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);/* AGG EN */
235 ptxdesc->txdw6 = cpu_to_le32(0x6666f800);
237 ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
243 ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0x0FFF0000);
245 /* offset 16 , offset 20 */
247 ptxdesc->txdw4 |= cpu_to_le32(QOS);/* QoS */
250 if (pxmitframe->agg_num > 1)
251 ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000);
253 if ((pattrib->ether_type != 0x888e) &&
254 (pattrib->ether_type != 0x0806) &&
255 (pattrib->ether_type != 0x88b4) &&
256 (pattrib->dhcp_pkt != 1)) {
257 /* Non EAP & ARP & DHCP type data packet */
259 fill_txdesc_vcs(pattrib, &ptxdesc->txdw4);
260 fill_txdesc_phy(pattrib, &ptxdesc->txdw4);
262 ptxdesc->txdw4 |= cpu_to_le32(0x00000008);/* RTS Rate=24M */
263 ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);/* DATA/RTS Rate FB LMT */
265 if (pattrib->ht_en) {
266 if (ODM_RA_GetShortGI_8188E(&haldata->odmpriv, pattrib->mac_id))
267 ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
269 data_rate = ODM_RA_GetDecisionRate_8188E(&haldata->odmpriv, pattrib->mac_id);
270 ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F);
271 pwr_status = ODM_RA_GetHwPwrStatus_8188E(&haldata->odmpriv, pattrib->mac_id);
272 ptxdesc->txdw4 |= cpu_to_le32((pwr_status & 0x7) << PWR_STATUS_SHT);
274 /* EAP data packet and ARP packet and DHCP. */
275 /* Use the 1M data rate to send the EAP/ARP packet. */
276 /* This will maybe make the handshake smooth. */
277 ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
278 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
279 ptxdesc->txdw4 |= cpu_to_le32(BIT(24));/* DATA_SHORT */
280 ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
282 } else if ((pxmitframe->frame_tag&0x0f) == MGNT_FRAMETAG) {
284 ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id & 0x3f);
286 qsel = (uint)(pattrib->qsel&0x0000001f);
287 ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
289 ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000f0000);
292 /* CCX-TXRPT ack for xmit mgmt frames. */
293 if (pxmitframe->ack_report)
294 ptxdesc->txdw2 |= cpu_to_le32(BIT(19));
297 ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0FFF0000);
300 ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);/* retry limit enable */
301 if (pattrib->retry_ctrl)
302 ptxdesc->txdw5 |= cpu_to_le32(0x00180000);/* retry limit = 6 */
304 ptxdesc->txdw5 |= cpu_to_le32(0x00300000);/* retry limit = 12 */
306 ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
307 } else if ((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG) {
308 DBG_88E("pxmitframe->frame_tag == TXAGG_FRAMETAG\n");
310 DBG_88E("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag);
313 ptxdesc->txdw1 |= cpu_to_le32((4) & 0x3f);/* CAM_ID(MAC_ID) */
315 ptxdesc->txdw1 |= cpu_to_le32((6 << RATE_ID_SHT) & 0x000f0000);/* raid */
320 ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0fff0000);
323 ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
326 /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
327 /* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
328 /* mgnt frame should be controlled by Hw because Fw will also send null data */
329 /* which we cannot control when Fw LPS enable. */
330 /* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
331 /* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
332 /* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
333 /* 2010.06.23. Added by tynli. */
334 if (!pattrib->qos_en) {
335 ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); /* Hw set sequence number */
336 ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); /* Hw set sequence number */
339 rtl88eu_dm_set_tx_ant_by_tx_info(&haldata->odmpriv, pmem,
342 rtl8188eu_cal_txdesc_chksum(ptxdesc);
343 _dbg_dump_tx_info(adapt, pxmitframe->frame_tag, ptxdesc);
347 /* for non-agg data frame or management frame */
348 static s32 rtw_dump_xframe(struct adapter *adapt, struct xmit_frame *pxmitframe)
351 s32 inner_ret = _SUCCESS;
352 int t, sz, w_sz, pull = 0;
355 struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
356 struct pkt_attrib *pattrib = &pxmitframe->attrib;
357 struct xmit_priv *pxmitpriv = &adapt->xmitpriv;
358 struct security_priv *psecuritypriv = &adapt->securitypriv;
359 if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
360 (pxmitframe->attrib.ether_type != 0x0806) &&
361 (pxmitframe->attrib.ether_type != 0x888e) &&
362 (pxmitframe->attrib.ether_type != 0x88b4) &&
363 (pxmitframe->attrib.dhcp_pkt != 1))
364 rtw_issue_addbareq_cmd(adapt, pxmitframe);
365 mem_addr = pxmitframe->buf_addr;
367 RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_dump_xframe()\n"));
369 for (t = 0; t < pattrib->nr_frags; t++) {
370 if (inner_ret != _SUCCESS && ret == _SUCCESS)
373 if (t != (pattrib->nr_frags - 1)) {
374 RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("pattrib->nr_frags=%d\n", pattrib->nr_frags));
376 sz = pxmitpriv->frag_len;
377 sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len);
380 sz = pattrib->last_txcmdsz;
383 pull = update_txdesc(pxmitframe, mem_addr, sz, false);
386 mem_addr += PACKET_OFFSET_SZ; /* pull txdesc head */
387 pxmitframe->buf_addr = mem_addr;
388 w_sz = sz + TXDESC_SIZE;
390 w_sz = sz + TXDESC_SIZE + PACKET_OFFSET_SZ;
392 ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
394 inner_ret = usb_write_port(adapt, ff_hwaddr, w_sz, (unsigned char *)pxmitbuf);
396 rtw_count_tx_stats(adapt, pxmitframe, sz);
398 RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_write_port, w_sz=%d\n", w_sz));
402 mem_addr = (u8 *)round_up((size_t)mem_addr, 4);
405 rtw_free_xmitframe(pxmitpriv, pxmitframe);
408 rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);
413 static u32 xmitframe_need_length(struct xmit_frame *pxmitframe)
415 struct pkt_attrib *pattrib = &pxmitframe->attrib;
419 /* no consider fragement */
420 len = pattrib->hdrlen + pattrib->iv_len +
421 SNAP_SIZE + sizeof(u16) +
423 ((pattrib->bswenc) ? pattrib->icv_len : 0);
425 if (pattrib->encrypt == _TKIP_)
431 s32 rtl8188eu_xmitframe_complete(struct adapter *adapt, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
433 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
434 struct xmit_frame *pxmitframe = NULL;
435 struct xmit_frame *pfirstframe = NULL;
437 /* aggregate variable */
438 struct hw_xmit *phwxmit;
439 struct sta_info *psta = NULL;
440 struct tx_servq *ptxservq = NULL;
442 struct list_head *xmitframe_plist = NULL, *xmitframe_phead = NULL;
444 u32 pbuf; /* next pkt address */
445 u32 pbuf_tail; /* last pkt tail */
446 u32 len; /* packet length, except TXDESC_SIZE and PKT_OFFSET */
448 u32 bulksize = haldata->UsbBulkOutSize;
452 /* dump frame variable */
455 RT_TRACE(_module_rtl8192c_xmit_c_, _drv_info_, ("+xmitframe_complete\n"));
457 /* check xmitbuffer is ok */
458 if (pxmitbuf == NULL) {
459 pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
460 if (pxmitbuf == NULL)
464 /* 3 1. pick up first frame */
466 rtw_free_xmitframe(pxmitpriv, pxmitframe);
468 pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
469 if (pxmitframe == NULL) {
470 /* no more xmit frame, release xmit buffer */
471 rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
475 pxmitframe->pxmitbuf = pxmitbuf;
476 pxmitframe->buf_addr = pxmitbuf->pbuf;
477 pxmitbuf->priv_data = pxmitframe;
479 pxmitframe->agg_num = 1; /* alloc xmitframe should assign to 1. */
480 pxmitframe->pkt_offset = 1; /* first frame of aggregation, reserve offset */
482 rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe);
484 /* always return ndis_packet after rtw_xmitframe_coalesce */
485 rtw_os_xmit_complete(adapt, pxmitframe);
490 /* 3 2. aggregate same priority and same DA(AP or STA) frames */
491 pfirstframe = pxmitframe;
492 len = xmitframe_need_length(pfirstframe) + TXDESC_SIZE + (pfirstframe->pkt_offset*PACKET_OFFSET_SZ);
494 pbuf = round_up(pbuf_tail, 8);
496 /* check pkt amount in one bulk */
499 if (pbuf < bulkptr) {
503 bulkptr = ((pbuf / bulksize) + 1) * bulksize; /* round to next bulksize */
506 /* dequeue same priority packet from station tx queue */
507 psta = pfirstframe->attrib.psta;
508 switch (pfirstframe->attrib.priority) {
511 ptxservq = &(psta->sta_xmitpriv.bk_q);
512 phwxmit = pxmitpriv->hwxmits + 3;
516 ptxservq = &(psta->sta_xmitpriv.vi_q);
517 phwxmit = pxmitpriv->hwxmits + 1;
521 ptxservq = &(psta->sta_xmitpriv.vo_q);
522 phwxmit = pxmitpriv->hwxmits;
527 ptxservq = &(psta->sta_xmitpriv.be_q);
528 phwxmit = pxmitpriv->hwxmits + 2;
531 spin_lock_bh(&pxmitpriv->lock);
533 xmitframe_phead = get_list_head(&ptxservq->sta_pending);
534 xmitframe_plist = xmitframe_phead->next;
536 while (xmitframe_phead != xmitframe_plist) {
537 pxmitframe = container_of(xmitframe_plist, struct xmit_frame, list);
538 xmitframe_plist = xmitframe_plist->next;
540 pxmitframe->agg_num = 0; /* not first frame of aggregation */
541 pxmitframe->pkt_offset = 0; /* not first frame of aggregation, no need to reserve offset */
543 len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE + (pxmitframe->pkt_offset*PACKET_OFFSET_SZ);
545 if (round_up(pbuf + len, 8) > MAX_XMITBUF_SZ) {
546 pxmitframe->agg_num = 1;
547 pxmitframe->pkt_offset = 1;
550 list_del_init(&pxmitframe->list);
554 pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf;
556 rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe);
557 /* always return ndis_packet after rtw_xmitframe_coalesce */
558 rtw_os_xmit_complete(adapt, pxmitframe);
560 /* (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz */
561 update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz, true);
563 /* don't need xmitframe any more */
564 rtw_free_xmitframe(pxmitpriv, pxmitframe);
566 /* handle pointer and stop condition */
567 pbuf_tail = pbuf + len;
568 pbuf = round_up(pbuf_tail, 8);
570 pfirstframe->agg_num++;
571 if (MAX_TX_AGG_PACKET_NUMBER == pfirstframe->agg_num)
574 if (pbuf < bulkptr) {
576 if (desc_cnt == haldata->UsbTxAggDescNum)
580 bulkptr = ((pbuf / bulksize) + 1) * bulksize;
582 } /* end while (aggregate same priority and same DA(AP or STA) frames) */
584 if (list_empty(&ptxservq->sta_pending.queue))
585 list_del_init(&ptxservq->tx_pending);
587 spin_unlock_bh(&pxmitpriv->lock);
588 if ((pfirstframe->attrib.ether_type != 0x0806) &&
589 (pfirstframe->attrib.ether_type != 0x888e) &&
590 (pfirstframe->attrib.ether_type != 0x88b4) &&
591 (pfirstframe->attrib.dhcp_pkt != 1))
592 rtw_issue_addbareq_cmd(adapt, pfirstframe);
593 /* 3 3. update first frame txdesc */
594 if ((pbuf_tail % bulksize) == 0) {
595 /* remove pkt_offset */
596 pbuf_tail -= PACKET_OFFSET_SZ;
597 pfirstframe->buf_addr += PACKET_OFFSET_SZ;
598 pfirstframe->pkt_offset--;
601 update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz, true);
603 /* 3 4. write xmit buffer to USB FIFO */
604 ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe);
605 usb_write_port(adapt, ff_hwaddr, pbuf_tail, (u8 *)pxmitbuf);
607 /* 3 5. update statisitc */
608 pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE);
609 pbuf_tail -= (pfirstframe->pkt_offset * PACKET_OFFSET_SZ);
611 rtw_count_tx_stats(adapt, pfirstframe, pbuf_tail);
613 rtw_free_xmitframe(pxmitpriv, pfirstframe);
618 static s32 xmitframe_direct(struct adapter *adapt, struct xmit_frame *pxmitframe)
622 res = rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe);
624 rtw_dump_xframe(adapt, pxmitframe);
626 DBG_88E("==> %s xmitframe_coalsece failed\n", __func__);
632 * true dump packet directly
633 * false enqueue packet
635 static s32 pre_xmitframe(struct adapter *adapt, struct xmit_frame *pxmitframe)
638 struct xmit_buf *pxmitbuf = NULL;
639 struct xmit_priv *pxmitpriv = &adapt->xmitpriv;
640 struct pkt_attrib *pattrib = &pxmitframe->attrib;
641 struct mlme_priv *pmlmepriv = &adapt->mlmepriv;
643 spin_lock_bh(&pxmitpriv->lock);
645 if (rtw_txframes_sta_ac_pending(adapt, pattrib) > 0)
648 if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == true)
651 pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
652 if (pxmitbuf == NULL)
655 spin_unlock_bh(&pxmitpriv->lock);
657 pxmitframe->pxmitbuf = pxmitbuf;
658 pxmitframe->buf_addr = pxmitbuf->pbuf;
659 pxmitbuf->priv_data = pxmitframe;
661 if (xmitframe_direct(adapt, pxmitframe) != _SUCCESS) {
662 rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
663 rtw_free_xmitframe(pxmitpriv, pxmitframe);
669 res = rtw_xmitframe_enqueue(adapt, pxmitframe);
670 spin_unlock_bh(&pxmitpriv->lock);
672 if (res != _SUCCESS) {
673 RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("pre_xmitframe: enqueue xmitframe fail\n"));
674 rtw_free_xmitframe(pxmitpriv, pxmitframe);
676 /* Trick, make the statistics correct */
677 pxmitpriv->tx_pkts--;
678 pxmitpriv->tx_drop++;
685 s32 rtl8188eu_mgnt_xmit(struct adapter *adapt, struct xmit_frame *pmgntframe)
687 return rtw_dump_xframe(adapt, pmgntframe);
692 * true dump packet directly ok
693 * false temporary can't transmit packets to hardware
695 s32 rtl8188eu_hal_xmit(struct adapter *adapt, struct xmit_frame *pxmitframe)
697 return pre_xmitframe(adapt, pxmitframe);