Add the rt linux 4.1.3-rt3 as base
[kvmfornfv.git] / kernel / drivers / staging / rtl8188eu / hal / pwrseq.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  *
19  ******************************************************************************/
20
21 #include "pwrseq.h"
22 #include <rtl8188e_hal.h>
23
24 /*
25     drivers should parse below arrays and do the corresponding actions
26 */
27 /* 3 Power on  Array */
28 struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS +
29                                          RTL8188E_TRANS_END_STEPS] = {
30         RTL8188E_TRANS_CARDEMU_TO_ACT
31         RTL8188E_TRANS_END
32 };
33
34 /* 3Radio off Array */
35 struct wl_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
36                                           RTL8188E_TRANS_END_STEPS] = {
37         RTL8188E_TRANS_ACT_TO_CARDEMU
38         RTL8188E_TRANS_END
39 };
40
41 /* 3Card Disable Array */
42 struct wl_pwr_cfg rtl8188E_card_disable_flow
43         [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
44          RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
45          RTL8188E_TRANS_END_STEPS] = {
46                 RTL8188E_TRANS_ACT_TO_CARDEMU
47                 RTL8188E_TRANS_CARDEMU_TO_CARDDIS
48                 RTL8188E_TRANS_END
49 };
50
51 /* 3 Card Enable Array */
52 struct wl_pwr_cfg rtl8188E_card_enable_flow
53         [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
54          RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
55          RTL8188E_TRANS_END_STEPS] = {
56                 RTL8188E_TRANS_CARDDIS_TO_CARDEMU
57                 RTL8188E_TRANS_CARDEMU_TO_ACT
58                 RTL8188E_TRANS_END
59 };
60
61 /* 3Suspend Array */
62 struct wl_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
63                                         RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
64                                         RTL8188E_TRANS_END_STEPS] = {
65         RTL8188E_TRANS_ACT_TO_CARDEMU
66         RTL8188E_TRANS_CARDEMU_TO_SUS
67         RTL8188E_TRANS_END
68 };
69
70 /* 3 Resume Array */
71 struct wl_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
72                                        RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
73                                        RTL8188E_TRANS_END_STEPS] = {
74         RTL8188E_TRANS_SUS_TO_CARDEMU
75         RTL8188E_TRANS_CARDEMU_TO_ACT
76         RTL8188E_TRANS_END
77 };
78
79 /* 3HWPDN Array */
80 struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
81                                       RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
82                                       RTL8188E_TRANS_END_STEPS] = {
83         RTL8188E_TRANS_ACT_TO_CARDEMU
84         RTL8188E_TRANS_CARDEMU_TO_PDN
85         RTL8188E_TRANS_END
86 };
87
88 /* 3 Enter LPS */
89 struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS +
90                                           RTL8188E_TRANS_END_STEPS] = {
91         /* FW behavior */
92         RTL8188E_TRANS_ACT_TO_LPS
93         RTL8188E_TRANS_END
94 };
95
96 /* 3 Leave LPS */
97 struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS +
98                                           RTL8188E_TRANS_END_STEPS] = {
99         /* FW behavior */
100         RTL8188E_TRANS_LPS_TO_ACT
101         RTL8188E_TRANS_END
102 };