2 * Octeon HCD hardware register definitions.
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5 * License. See the file "COPYING" in the main directory of this archive
8 * Some parts of the code were originally released under BSD license:
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47 #ifndef __OCTEON_HCD_H__
48 #define __OCTEON_HCD_H__
50 #include <asm/bitfield.h>
52 #define CVMX_USBCXBASE 0x00016F0010000000ull
53 #define CVMX_USBCXREG1(reg, bid) \
54 (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \
55 ((bid) & 1) * 0x100000000000ull)
56 #define CVMX_USBCXREG2(reg, bid, off) \
57 (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \
58 (((off) & 7) + ((bid) & 1) * 0x8000000000ull) * 32)
60 #define CVMX_USBCX_GAHBCFG(bid) CVMX_USBCXREG1(0x008, bid)
61 #define CVMX_USBCX_GHWCFG3(bid) CVMX_USBCXREG1(0x04c, bid)
62 #define CVMX_USBCX_GINTMSK(bid) CVMX_USBCXREG1(0x018, bid)
63 #define CVMX_USBCX_GINTSTS(bid) CVMX_USBCXREG1(0x014, bid)
64 #define CVMX_USBCX_GNPTXFSIZ(bid) CVMX_USBCXREG1(0x028, bid)
65 #define CVMX_USBCX_GNPTXSTS(bid) CVMX_USBCXREG1(0x02c, bid)
66 #define CVMX_USBCX_GOTGCTL(bid) CVMX_USBCXREG1(0x000, bid)
67 #define CVMX_USBCX_GRSTCTL(bid) CVMX_USBCXREG1(0x010, bid)
68 #define CVMX_USBCX_GRXFSIZ(bid) CVMX_USBCXREG1(0x024, bid)
69 #define CVMX_USBCX_GRXSTSPH(bid) CVMX_USBCXREG1(0x020, bid)
70 #define CVMX_USBCX_GUSBCFG(bid) CVMX_USBCXREG1(0x00c, bid)
71 #define CVMX_USBCX_HAINT(bid) CVMX_USBCXREG1(0x414, bid)
72 #define CVMX_USBCX_HAINTMSK(bid) CVMX_USBCXREG1(0x418, bid)
73 #define CVMX_USBCX_HCCHARX(off, bid) CVMX_USBCXREG2(0x500, bid, off)
74 #define CVMX_USBCX_HCFG(bid) CVMX_USBCXREG1(0x400, bid)
75 #define CVMX_USBCX_HCINTMSKX(off, bid) CVMX_USBCXREG2(0x50c, bid, off)
76 #define CVMX_USBCX_HCINTX(off, bid) CVMX_USBCXREG2(0x508, bid, off)
77 #define CVMX_USBCX_HCSPLTX(off, bid) CVMX_USBCXREG2(0x504, bid, off)
78 #define CVMX_USBCX_HCTSIZX(off, bid) CVMX_USBCXREG2(0x510, bid, off)
79 #define CVMX_USBCX_HFIR(bid) CVMX_USBCXREG1(0x404, bid)
80 #define CVMX_USBCX_HFNUM(bid) CVMX_USBCXREG1(0x408, bid)
81 #define CVMX_USBCX_HPRT(bid) CVMX_USBCXREG1(0x440, bid)
82 #define CVMX_USBCX_HPTXFSIZ(bid) CVMX_USBCXREG1(0x100, bid)
83 #define CVMX_USBCX_HPTXSTS(bid) CVMX_USBCXREG1(0x410, bid)
85 #define CVMX_USBNXBID1(bid) (((bid) & 1) * 0x10000000ull)
86 #define CVMX_USBNXBID2(bid) (((bid) & 1) * 0x100000000000ull)
88 #define CVMX_USBNXREG1(reg, bid) \
89 (CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid))
90 #define CVMX_USBNXREG2(reg, bid) \
91 (CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid))
93 #define CVMX_USBNX_CLK_CTL(bid) CVMX_USBNXREG1(0x10, bid)
94 #define CVMX_USBNX_DMA0_INB_CHN0(bid) CVMX_USBNXREG2(0x818, bid)
95 #define CVMX_USBNX_DMA0_OUTB_CHN0(bid) CVMX_USBNXREG2(0x858, bid)
96 #define CVMX_USBNX_USBP_CTL_STATUS(bid) CVMX_USBNXREG1(0x18, bid)
101 * Core AHB Configuration Register (GAHBCFG)
103 * This register can be used to configure the core after power-on or a change in
104 * mode of operation. This register mainly contains AHB system-related
105 * configuration parameters. The AHB is the processor interface to the O2P USB
106 * core. In general, software need not know about this interface except to
107 * program the values as specified.
109 * The application must program this register as part of the O2P USB core
110 * initialization. Do not change this register after the initial programming.
112 union cvmx_usbcx_gahbcfg {
115 * struct cvmx_usbcx_gahbcfg_s
116 * @ptxfemplvl: Periodic TxFIFO Empty Level (PTxFEmpLvl)
117 * Software should set this bit to 0x1.
118 * Indicates when the Periodic TxFIFO Empty Interrupt bit in the
119 * Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
120 * bit is used only in Slave mode.
121 * * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic
122 * TxFIFO is half empty
123 * * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic
124 * TxFIFO is completely empty
125 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
126 * Software should set this bit to 0x1.
127 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
128 * the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
129 * This bit is used only in Slave mode.
130 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
131 * Periodic TxFIFO is half empty
132 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * Periodic TxFIFO is completely empty
134 * @dmaen: DMA Enable (DMAEn)
135 * * 1'b0: Core operates in Slave mode
136 * * 1'b1: Core operates in a DMA mode
137 * @hbstlen: Burst Length/Type (HBstLen)
138 * This field has not effect and should be left as 0x0.
139 * @glblintrmsk: Global Interrupt Mask (GlblIntrMsk)
140 * Software should set this field to 0x1.
141 * The application uses this bit to mask or unmask the interrupt
142 * line assertion to itself. Irrespective of this bit's setting,
143 * the interrupt status registers are updated by the core.
144 * * 1'b0: Mask the interrupt assertion to the application.
145 * * 1'b1: Unmask the interrupt assertion to the application.
147 struct cvmx_usbcx_gahbcfg_s {
148 __BITFIELD_FIELD(uint32_t reserved_9_31 : 23,
149 __BITFIELD_FIELD(uint32_t ptxfemplvl : 1,
150 __BITFIELD_FIELD(uint32_t nptxfemplvl : 1,
151 __BITFIELD_FIELD(uint32_t reserved_6_6 : 1,
152 __BITFIELD_FIELD(uint32_t dmaen : 1,
153 __BITFIELD_FIELD(uint32_t hbstlen : 4,
154 __BITFIELD_FIELD(uint32_t glblintrmsk : 1,
162 * User HW Config3 Register (GHWCFG3)
164 * This register contains the configuration options of the O2P USB core.
166 union cvmx_usbcx_ghwcfg3 {
169 * struct cvmx_usbcx_ghwcfg3_s
170 * @dfifodepth: DFIFO Depth (DfifoDepth)
171 * This value is in terms of 32-bit words.
172 * * Minimum value is 32
173 * * Maximum value is 32768
174 * @ahbphysync: AHB and PHY Synchronous (AhbPhySync)
175 * Indicates whether AHB and PHY clocks are synchronous to
179 * This bit is tied to 1.
180 * @rsttype: Reset Style for Clocked always Blocks in RTL (RstType)
181 * * 1'b0: Asynchronous reset is used in the core
182 * * 1'b1: Synchronous reset is used in the core
183 * @optfeature: Optional Features Removed (OptFeature)
184 * Indicates whether the User ID register, GPIO interface ports,
185 * and SOF toggle and counter ports were removed for gate count
187 * @vendor_control_interface_support: Vendor Control Interface Support
188 * * 1'b0: Vendor Control Interface is not available on the core.
189 * * 1'b1: Vendor Control Interface is available.
190 * @i2c_selection: I2C Selection
191 * * 1'b0: I2C Interface is not available on the core.
192 * * 1'b1: I2C Interface is available on the core.
193 * @otgen: OTG Function Enabled (OtgEn)
194 * The application uses this bit to indicate the O2P USB core's
196 * * 1'b0: Not OTG capable
197 * * 1'b1: OTG Capable
198 * @pktsizewidth: Width of Packet Size Counters (PktSizeWidth)
207 * @xfersizewidth: Width of Transfer Size Counters (XferSizeWidth)
214 struct cvmx_usbcx_ghwcfg3_s {
215 __BITFIELD_FIELD(uint32_t dfifodepth : 16,
216 __BITFIELD_FIELD(uint32_t reserved_13_15 : 3,
217 __BITFIELD_FIELD(uint32_t ahbphysync : 1,
218 __BITFIELD_FIELD(uint32_t rsttype : 1,
219 __BITFIELD_FIELD(uint32_t optfeature : 1,
220 __BITFIELD_FIELD(uint32_t vendor_control_interface_support : 1,
221 __BITFIELD_FIELD(uint32_t i2c_selection : 1,
222 __BITFIELD_FIELD(uint32_t otgen : 1,
223 __BITFIELD_FIELD(uint32_t pktsizewidth : 3,
224 __BITFIELD_FIELD(uint32_t xfersizewidth : 4,
232 * Core Interrupt Mask Register (GINTMSK)
234 * This register works with the Core Interrupt register to interrupt the
235 * application. When an interrupt bit is masked, the interrupt associated with
236 * that bit will not be generated. However, the Core Interrupt (GINTSTS)
237 * register bit corresponding to that interrupt will still be set.
238 * Mask interrupt: 1'b0, Unmask interrupt: 1'b1
240 union cvmx_usbcx_gintmsk {
243 * struct cvmx_usbcx_gintmsk_s
244 * @wkupintmsk: Resume/Remote Wakeup Detected Interrupt Mask
246 * @sessreqintmsk: Session Request/New Session Detected Interrupt Mask
248 * @disconnintmsk: Disconnect Detected Interrupt Mask (DisconnIntMsk)
249 * @conidstschngmsk: Connector ID Status Change Mask (ConIDStsChngMsk)
250 * @ptxfempmsk: Periodic TxFIFO Empty Mask (PTxFEmpMsk)
251 * @hchintmsk: Host Channels Interrupt Mask (HChIntMsk)
252 * @prtintmsk: Host Port Interrupt Mask (PrtIntMsk)
253 * @fetsuspmsk: Data Fetch Suspended Mask (FetSuspMsk)
254 * @incomplpmsk: Incomplete Periodic Transfer Mask (incomplPMsk)
255 * Incomplete Isochronous OUT Transfer Mask
257 * @incompisoinmsk: Incomplete Isochronous IN Transfer Mask
259 * @oepintmsk: OUT Endpoints Interrupt Mask (OEPIntMsk)
260 * @inepintmsk: IN Endpoints Interrupt Mask (INEPIntMsk)
261 * @epmismsk: Endpoint Mismatch Interrupt Mask (EPMisMsk)
262 * @eopfmsk: End of Periodic Frame Interrupt Mask (EOPFMsk)
263 * @isooutdropmsk: Isochronous OUT Packet Dropped Interrupt Mask
265 * @enumdonemsk: Enumeration Done Mask (EnumDoneMsk)
266 * @usbrstmsk: USB Reset Mask (USBRstMsk)
267 * @usbsuspmsk: USB Suspend Mask (USBSuspMsk)
268 * @erlysuspmsk: Early Suspend Mask (ErlySuspMsk)
269 * @i2cint: I2C Interrupt Mask (I2CINT)
270 * @ulpickintmsk: ULPI Carkit Interrupt Mask (ULPICKINTMsk)
271 * I2C Carkit Interrupt Mask (I2CCKINTMsk)
272 * @goutnakeffmsk: Global OUT NAK Effective Mask (GOUTNakEffMsk)
273 * @ginnakeffmsk: Global Non-Periodic IN NAK Effective Mask
275 * @nptxfempmsk: Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk)
276 * @rxflvlmsk: Receive FIFO Non-Empty Mask (RxFLvlMsk)
277 * @sofmsk: Start of (micro)Frame Mask (SofMsk)
278 * @otgintmsk: OTG Interrupt Mask (OTGIntMsk)
279 * @modemismsk: Mode Mismatch Interrupt Mask (ModeMisMsk)
281 struct cvmx_usbcx_gintmsk_s {
282 __BITFIELD_FIELD(uint32_t wkupintmsk : 1,
283 __BITFIELD_FIELD(uint32_t sessreqintmsk : 1,
284 __BITFIELD_FIELD(uint32_t disconnintmsk : 1,
285 __BITFIELD_FIELD(uint32_t conidstschngmsk : 1,
286 __BITFIELD_FIELD(uint32_t reserved_27_27 : 1,
287 __BITFIELD_FIELD(uint32_t ptxfempmsk : 1,
288 __BITFIELD_FIELD(uint32_t hchintmsk : 1,
289 __BITFIELD_FIELD(uint32_t prtintmsk : 1,
290 __BITFIELD_FIELD(uint32_t reserved_23_23 : 1,
291 __BITFIELD_FIELD(uint32_t fetsuspmsk : 1,
292 __BITFIELD_FIELD(uint32_t incomplpmsk : 1,
293 __BITFIELD_FIELD(uint32_t incompisoinmsk : 1,
294 __BITFIELD_FIELD(uint32_t oepintmsk : 1,
295 __BITFIELD_FIELD(uint32_t inepintmsk : 1,
296 __BITFIELD_FIELD(uint32_t epmismsk : 1,
297 __BITFIELD_FIELD(uint32_t reserved_16_16 : 1,
298 __BITFIELD_FIELD(uint32_t eopfmsk : 1,
299 __BITFIELD_FIELD(uint32_t isooutdropmsk : 1,
300 __BITFIELD_FIELD(uint32_t enumdonemsk : 1,
301 __BITFIELD_FIELD(uint32_t usbrstmsk : 1,
302 __BITFIELD_FIELD(uint32_t usbsuspmsk : 1,
303 __BITFIELD_FIELD(uint32_t erlysuspmsk : 1,
304 __BITFIELD_FIELD(uint32_t i2cint : 1,
305 __BITFIELD_FIELD(uint32_t ulpickintmsk : 1,
306 __BITFIELD_FIELD(uint32_t goutnakeffmsk : 1,
307 __BITFIELD_FIELD(uint32_t ginnakeffmsk : 1,
308 __BITFIELD_FIELD(uint32_t nptxfempmsk : 1,
309 __BITFIELD_FIELD(uint32_t rxflvlmsk : 1,
310 __BITFIELD_FIELD(uint32_t sofmsk : 1,
311 __BITFIELD_FIELD(uint32_t otgintmsk : 1,
312 __BITFIELD_FIELD(uint32_t modemismsk : 1,
313 __BITFIELD_FIELD(uint32_t reserved_0_0 : 1,
314 ;))))))))))))))))))))))))))))))))
321 * Core Interrupt Register (GINTSTS)
323 * This register interrupts the application for system-level events in the
324 * current mode of operation (Device mode or Host mode). It is shown in
325 * Interrupt. Some of the bits in this register are valid only in Host mode,
326 * while others are valid in Device mode only. This register also indicates the
327 * current mode of operation. In order to clear the interrupt status bits of
328 * type R_SS_WC, the application must write 1'b1 into the bit. The FIFO status
329 * interrupts are read only; once software reads from or writes to the FIFO
330 * while servicing these interrupts, FIFO interrupt conditions are cleared
333 union cvmx_usbcx_gintsts {
336 * struct cvmx_usbcx_gintsts_s
337 * @wkupint: Resume/Remote Wakeup Detected Interrupt (WkUpInt)
338 * In Device mode, this interrupt is asserted when a resume is
339 * detected on the USB. In Host mode, this interrupt is asserted
340 * when a remote wakeup is detected on the USB.
341 * For more information on how to use this interrupt, see "Partial
342 * Power-Down and Clock Gating Programming Model" on
344 * @sessreqint: Session Request/New Session Detected Interrupt
346 * In Host mode, this interrupt is asserted when a session request
347 * is detected from the device. In Device mode, this interrupt is
348 * asserted when the utmiotg_bvalid signal goes high.
349 * For more information on how to use this interrupt, see "Partial
350 * Power-Down and Clock Gating Programming Model" on
352 * @disconnint: Disconnect Detected Interrupt (DisconnInt)
353 * Asserted when a device disconnect is detected.
354 * @conidstschng: Connector ID Status Change (ConIDStsChng)
355 * The core sets this bit when there is a change in connector ID
357 * @ptxfemp: Periodic TxFIFO Empty (PTxFEmp)
358 * Asserted when the Periodic Transmit FIFO is either half or
359 * completely empty and there is space for at least one entry to be
360 * written in the Periodic Request Queue. The half or completely
361 * empty status is determined by the Periodic TxFIFO Empty Level
362 * bit in the Core AHB Configuration register
363 * (GAHBCFG.PTxFEmpLvl).
364 * @hchint: Host Channels Interrupt (HChInt)
365 * The core sets this bit to indicate that an interrupt is pending
366 * on one of the channels of the core (in Host mode). The
367 * application must read the Host All Channels Interrupt (HAINT)
368 * register to determine the exact number of the channel on which
369 * the interrupt occurred, and then read the corresponding Host
370 * Channel-n Interrupt (HCINTn) register to determine the exact
371 * cause of the interrupt. The application must clear the
372 * appropriate status bit in the HCINTn register to clear this bit.
373 * @prtint: Host Port Interrupt (PrtInt)
374 * The core sets this bit to indicate a change in port status of
375 * one of the O2P USB core ports in Host mode. The application must
376 * read the Host Port Control and Status (HPRT) register to
377 * determine the exact event that caused this interrupt. The
378 * application must clear the appropriate status bit in the Host
379 * Port Control and Status register to clear this bit.
380 * @fetsusp: Data Fetch Suspended (FetSusp)
381 * This interrupt is valid only in DMA mode. This interrupt
382 * indicates that the core has stopped fetching data for IN
383 * endpoints due to the unavailability of TxFIFO space or Request
384 * Queue space. This interrupt is used by the application for an
385 * endpoint mismatch algorithm.
386 * @incomplp: Incomplete Periodic Transfer (incomplP)
387 * In Host mode, the core sets this interrupt bit when there are
388 * incomplete periodic transactions still pending which are
389 * scheduled for the current microframe.
390 * Incomplete Isochronous OUT Transfer (incompISOOUT)
391 * The Device mode, the core sets this interrupt to indicate that
392 * there is at least one isochronous OUT endpoint on which the
393 * transfer is not completed in the current microframe. This
394 * interrupt is asserted along with the End of Periodic Frame
395 * Interrupt (EOPF) bit in this register.
396 * @incompisoin: Incomplete Isochronous IN Transfer (incompISOIN)
397 * The core sets this interrupt to indicate that there is at least
398 * one isochronous IN endpoint on which the transfer is not
399 * completed in the current microframe. This interrupt is asserted
400 * along with the End of Periodic Frame Interrupt (EOPF) bit in
402 * @oepint: OUT Endpoints Interrupt (OEPInt)
403 * The core sets this bit to indicate that an interrupt is pending
404 * on one of the OUT endpoints of the core (in Device mode). The
405 * application must read the Device All Endpoints Interrupt
406 * (DAINT) register to determine the exact number of the OUT
407 * endpoint on which the interrupt occurred, and then read the
408 * corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
409 * register to determine the exact cause of the interrupt. The
410 * application must clear the appropriate status bit in the
411 * corresponding DOEPINTn register to clear this bit.
412 * @iepint: IN Endpoints Interrupt (IEPInt)
413 * The core sets this bit to indicate that an interrupt is pending
414 * on one of the IN endpoints of the core (in Device mode). The
415 * application must read the Device All Endpoints Interrupt
416 * (DAINT) register to determine the exact number of the IN
417 * endpoint on which the interrupt occurred, and then read the
418 * corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
419 * register to determine the exact cause of the interrupt. The
420 * application must clear the appropriate status bit in the
421 * corresponding DIEPINTn register to clear this bit.
422 * @epmis: Endpoint Mismatch Interrupt (EPMis)
423 * Indicates that an IN token has been received for a non-periodic
424 * endpoint, but the data for another endpoint is present in the
425 * top of the Non-Periodic Transmit FIFO and the IN endpoint
426 * mismatch count programmed by the application has expired.
427 * @eopf: End of Periodic Frame Interrupt (EOPF)
428 * Indicates that the period specified in the Periodic Frame
429 * Interval field of the Device Configuration register
430 * (DCFG.PerFrInt) has been reached in the current microframe.
431 * @isooutdrop: Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
432 * The core sets this bit when it fails to write an isochronous OUT
433 * packet into the RxFIFO because the RxFIFO doesn't have
434 * enough space to accommodate a maximum packet size packet
435 * for the isochronous OUT endpoint.
436 * @enumdone: Enumeration Done (EnumDone)
437 * The core sets this bit to indicate that speed enumeration is
438 * complete. The application must read the Device Status (DSTS)
439 * register to obtain the enumerated speed.
440 * @usbrst: USB Reset (USBRst)
441 * The core sets this bit to indicate that a reset is detected on
443 * @usbsusp: USB Suspend (USBSusp)
444 * The core sets this bit to indicate that a suspend was detected
445 * on the USB. The core enters the Suspended state when there
446 * is no activity on the phy_line_state_i signal for an extended
448 * @erlysusp: Early Suspend (ErlySusp)
449 * The core sets this bit to indicate that an Idle state has been
450 * detected on the USB for 3 ms.
451 * @i2cint: I2C Interrupt (I2CINT)
452 * This bit is always 0x0.
453 * @ulpickint: ULPI Carkit Interrupt (ULPICKINT)
454 * This bit is always 0x0.
455 * @goutnakeff: Global OUT NAK Effective (GOUTNakEff)
456 * Indicates that the Set Global OUT NAK bit in the Device Control
457 * register (DCTL.SGOUTNak), set by the application, has taken
458 * effect in the core. This bit can be cleared by writing the Clear
459 * Global OUT NAK bit in the Device Control register
461 * @ginnakeff: Global IN Non-Periodic NAK Effective (GINNakEff)
462 * Indicates that the Set Global Non-Periodic IN NAK bit in the
463 * Device Control register (DCTL.SGNPInNak), set by the
464 * application, has taken effect in the core. That is, the core has
465 * sampled the Global IN NAK bit set by the application. This bit
466 * can be cleared by clearing the Clear Global Non-Periodic IN
467 * NAK bit in the Device Control register (DCTL.CGNPInNak).
468 * This interrupt does not necessarily mean that a NAK handshake
469 * is sent out on the USB. The STALL bit takes precedence over
471 * @nptxfemp: Non-Periodic TxFIFO Empty (NPTxFEmp)
472 * This interrupt is asserted when the Non-Periodic TxFIFO is
473 * either half or completely empty, and there is space for at least
474 * one entry to be written to the Non-Periodic Transmit Request
475 * Queue. The half or completely empty status is determined by
476 * the Non-Periodic TxFIFO Empty Level bit in the Core AHB
477 * Configuration register (GAHBCFG.NPTxFEmpLvl).
478 * @rxflvl: RxFIFO Non-Empty (RxFLvl)
479 * Indicates that there is at least one packet pending to be read
481 * @sof: Start of (micro)Frame (Sof)
482 * In Host mode, the core sets this bit to indicate that an SOF
483 * (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
484 * USB. The application must write a 1 to this bit to clear the
486 * In Device mode, in the core sets this bit to indicate that an
487 * SOF token has been received on the USB. The application can read
488 * the Device Status register to get the current (micro)frame
489 * number. This interrupt is seen only when the core is operating
490 * at either HS or FS.
491 * @otgint: OTG Interrupt (OTGInt)
492 * The core sets this bit to indicate an OTG protocol event. The
493 * application must read the OTG Interrupt Status (GOTGINT)
494 * register to determine the exact event that caused this
495 * interrupt. The application must clear the appropriate status bit
496 * in the GOTGINT register to clear this bit.
497 * @modemis: Mode Mismatch Interrupt (ModeMis)
498 * The core sets this bit when the application is trying to access:
499 * * A Host mode register, when the core is operating in Device
501 * * A Device mode register, when the core is operating in Host
503 * The register access is completed on the AHB with an OKAY
504 * response, but is ignored by the core internally and doesn't
505 * affect the operation of the core.
506 * @curmod: Current Mode of Operation (CurMod)
507 * Indicates the current mode of operation.
508 * * 1'b0: Device mode
511 struct cvmx_usbcx_gintsts_s {
512 __BITFIELD_FIELD(uint32_t wkupint : 1,
513 __BITFIELD_FIELD(uint32_t sessreqint : 1,
514 __BITFIELD_FIELD(uint32_t disconnint : 1,
515 __BITFIELD_FIELD(uint32_t conidstschng : 1,
516 __BITFIELD_FIELD(uint32_t reserved_27_27 : 1,
517 __BITFIELD_FIELD(uint32_t ptxfemp : 1,
518 __BITFIELD_FIELD(uint32_t hchint : 1,
519 __BITFIELD_FIELD(uint32_t prtint : 1,
520 __BITFIELD_FIELD(uint32_t reserved_23_23 : 1,
521 __BITFIELD_FIELD(uint32_t fetsusp : 1,
522 __BITFIELD_FIELD(uint32_t incomplp : 1,
523 __BITFIELD_FIELD(uint32_t incompisoin : 1,
524 __BITFIELD_FIELD(uint32_t oepint : 1,
525 __BITFIELD_FIELD(uint32_t iepint : 1,
526 __BITFIELD_FIELD(uint32_t epmis : 1,
527 __BITFIELD_FIELD(uint32_t reserved_16_16 : 1,
528 __BITFIELD_FIELD(uint32_t eopf : 1,
529 __BITFIELD_FIELD(uint32_t isooutdrop : 1,
530 __BITFIELD_FIELD(uint32_t enumdone : 1,
531 __BITFIELD_FIELD(uint32_t usbrst : 1,
532 __BITFIELD_FIELD(uint32_t usbsusp : 1,
533 __BITFIELD_FIELD(uint32_t erlysusp : 1,
534 __BITFIELD_FIELD(uint32_t i2cint : 1,
535 __BITFIELD_FIELD(uint32_t ulpickint : 1,
536 __BITFIELD_FIELD(uint32_t goutnakeff : 1,
537 __BITFIELD_FIELD(uint32_t ginnakeff : 1,
538 __BITFIELD_FIELD(uint32_t nptxfemp : 1,
539 __BITFIELD_FIELD(uint32_t rxflvl : 1,
540 __BITFIELD_FIELD(uint32_t sof : 1,
541 __BITFIELD_FIELD(uint32_t otgint : 1,
542 __BITFIELD_FIELD(uint32_t modemis : 1,
543 __BITFIELD_FIELD(uint32_t curmod : 1,
544 ;))))))))))))))))))))))))))))))))
549 * cvmx_usbc#_gnptxfsiz
551 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
553 * The application can program the RAM size and the memory start address for the
554 * Non-Periodic TxFIFO.
556 union cvmx_usbcx_gnptxfsiz {
559 * struct cvmx_usbcx_gnptxfsiz_s
560 * @nptxfdep: Non-Periodic TxFIFO Depth (NPTxFDep)
561 * This value is in terms of 32-bit words.
562 * Minimum value is 16
563 * Maximum value is 32768
564 * @nptxfstaddr: Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
565 * This field contains the memory start address for Non-Periodic
568 struct cvmx_usbcx_gnptxfsiz_s {
569 __BITFIELD_FIELD(uint32_t nptxfdep : 16,
570 __BITFIELD_FIELD(uint32_t nptxfstaddr : 16,
576 * cvmx_usbc#_gnptxsts
578 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
580 * This read-only register contains the free space information for the
581 * Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue.
583 union cvmx_usbcx_gnptxsts {
586 * struct cvmx_usbcx_gnptxsts_s
587 * @nptxqtop: Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
588 * Entry in the Non-Periodic Tx Request Queue that is currently
589 * being processed by the MAC.
590 * * Bits [30:27]: Channel/endpoint number
592 * - 2'b00: IN/OUT token
593 * - 2'b01: Zero-length transmit packet (device IN/host OUT)
594 * - 2'b10: PING/CSPLIT token
595 * - 2'b11: Channel halt command
596 * * Bit [24]: Terminate (last entry for selected channel/endpoint)
597 * @nptxqspcavail: Non-Periodic Transmit Request Queue Space Available
599 * Indicates the amount of free space available in the Non-
600 * Periodic Transmit Request Queue. This queue holds both IN
601 * and OUT requests in Host mode. Device mode has only IN
603 * * 8'h0: Non-Periodic Transmit Request Queue is full
604 * * 8'h1: 1 location available
605 * * 8'h2: 2 locations available
606 * * n: n locations available (0..8)
608 * @nptxfspcavail: Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
609 * Indicates the amount of free space available in the Non-
611 * Values are in terms of 32-bit words.
612 * * 16'h0: Non-Periodic TxFIFO is full
613 * * 16'h1: 1 word available
614 * * 16'h2: 2 words available
615 * * 16'hn: n words available (where 0..32768)
616 * * 16'h8000: 32768 words available
619 struct cvmx_usbcx_gnptxsts_s {
620 __BITFIELD_FIELD(uint32_t reserved_31_31 : 1,
621 __BITFIELD_FIELD(uint32_t nptxqtop : 7,
622 __BITFIELD_FIELD(uint32_t nptxqspcavail : 8,
623 __BITFIELD_FIELD(uint32_t nptxfspcavail : 16,
631 * Core Reset Register (GRSTCTL)
633 * The application uses this register to reset various hardware features inside
636 union cvmx_usbcx_grstctl {
639 * struct cvmx_usbcx_grstctl_s
640 * @ahbidle: AHB Master Idle (AHBIdle)
641 * Indicates that the AHB Master State Machine is in the IDLE
643 * @dmareq: DMA Request Signal (DMAReq)
644 * Indicates that the DMA request is in progress. Used for debug.
645 * @txfnum: TxFIFO Number (TxFNum)
646 * This is the FIFO number that must be flushed using the TxFIFO
647 * Flush bit. This field must not be changed until the core clears
648 * the TxFIFO Flush bit.
649 * * 5'h0: Non-Periodic TxFIFO flush
650 * * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic
651 * TxFIFO flush in Host mode
652 * * 5'h2: Periodic TxFIFO 2 flush in Device mode
654 * * 5'hF: Periodic TxFIFO 15 flush in Device mode
655 * * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
657 * @txfflsh: TxFIFO Flush (TxFFlsh)
658 * This bit selectively flushes a single or all transmit FIFOs, but
659 * cannot do so if the core is in the midst of a transaction.
660 * The application must only write this bit after checking that the
661 * core is neither writing to the TxFIFO nor reading from the
663 * The application must wait until the core clears this bit before
664 * performing any operations. This bit takes 8 clocks (of phy_clk
665 * or hclk, whichever is slower) to clear.
666 * @rxfflsh: RxFIFO Flush (RxFFlsh)
667 * The application can flush the entire RxFIFO using this bit, but
668 * must first ensure that the core is not in the middle of a
670 * The application must only write to this bit after checking that
671 * the core is neither reading from the RxFIFO nor writing to the
673 * The application must wait until the bit is cleared before
674 * performing any other operations. This bit will take 8 clocks
675 * (slowest of PHY or AHB clock) to clear.
676 * @intknqflsh: IN Token Sequence Learning Queue Flush (INTknQFlsh)
677 * The application writes this bit to flush the IN Token Sequence
679 * @frmcntrrst: Host Frame Counter Reset (FrmCntrRst)
680 * The application writes this bit to reset the (micro)frame number
681 * counter inside the core. When the (micro)frame counter is reset,
682 * the subsequent SOF sent out by the core will have a
683 * (micro)frame number of 0.
684 * @hsftrst: HClk Soft Reset (HSftRst)
685 * The application uses this bit to flush the control logic in the
686 * AHB Clock domain. Only AHB Clock Domain pipelines are reset.
687 * * FIFOs are not flushed with this bit.
688 * * All state machines in the AHB clock domain are reset to the
689 * Idle state after terminating the transactions on the AHB,
690 * following the protocol.
691 * * CSR control bits used by the AHB clock domain state
692 * machines are cleared.
693 * * To clear this interrupt, status mask bits that control the
694 * interrupt status and are generated by the AHB clock domain
695 * state machine are cleared.
696 * * Because interrupt status bits are not cleared, the application
697 * can get the status of any core events that occurred after it set
699 * This is a self-clearing bit that the core clears after all
700 * necessary logic is reset in the core. This may take several
701 * clocks, depending on the core's current state.
702 * @csftrst: Core Soft Reset (CSftRst)
703 * Resets the hclk and phy_clock domains as follows:
704 * * Clears the interrupts and all the CSR registers except the
705 * following register bits:
706 * - PCGCCTL.RstPdwnModule
709 * - PCGCCTL.StopPPhyLPwrClkSelclk
710 * - GUSBCFG.PhyLPwrClkSel
714 * - GUSBCFG.ULPI_UTMI_Sel
718 * * All module state machines (except the AHB Slave Unit) are
719 * reset to the IDLE state, and all the transmit FIFOs and the
720 * receive FIFO are flushed.
721 * * Any transactions on the AHB Master are terminated as soon
722 * as possible, after gracefully completing the last data phase of
723 * an AHB transfer. Any transactions on the USB are terminated
725 * The application can write to this bit any time it wants to reset
726 * the core. This is a self-clearing bit and the core clears this
727 * bit after all the necessary logic is reset in the core, which
728 * may take several clocks, depending on the current state of the
729 * core. Once this bit is cleared software should wait at least 3
730 * PHY clocks before doing any access to the PHY domain
731 * (synchronization delay). Software should also should check that
732 * bit 31 of this register is 1 (AHB Master is IDLE) before
733 * starting any operation.
734 * Typically software reset is used during software development
735 * and also when you dynamically change the PHY selection bits
736 * in the USB configuration registers listed above. When you
737 * change the PHY, the corresponding clock for the PHY is
738 * selected and used in the PHY domain. Once a new clock is
739 * selected, the PHY domain has to be reset for proper operation.
741 struct cvmx_usbcx_grstctl_s {
742 __BITFIELD_FIELD(uint32_t ahbidle : 1,
743 __BITFIELD_FIELD(uint32_t dmareq : 1,
744 __BITFIELD_FIELD(uint32_t reserved_11_29 : 19,
745 __BITFIELD_FIELD(uint32_t txfnum : 5,
746 __BITFIELD_FIELD(uint32_t txfflsh : 1,
747 __BITFIELD_FIELD(uint32_t rxfflsh : 1,
748 __BITFIELD_FIELD(uint32_t intknqflsh : 1,
749 __BITFIELD_FIELD(uint32_t frmcntrrst : 1,
750 __BITFIELD_FIELD(uint32_t hsftrst : 1,
751 __BITFIELD_FIELD(uint32_t csftrst : 1,
759 * Receive FIFO Size Register (GRXFSIZ)
761 * The application can program the RAM size that must be allocated to the
764 union cvmx_usbcx_grxfsiz {
767 * struct cvmx_usbcx_grxfsiz_s
768 * @rxfdep: RxFIFO Depth (RxFDep)
769 * This value is in terms of 32-bit words.
770 * * Minimum value is 16
771 * * Maximum value is 32768
773 struct cvmx_usbcx_grxfsiz_s {
774 __BITFIELD_FIELD(uint32_t reserved_16_31 : 16,
775 __BITFIELD_FIELD(uint32_t rxfdep : 16,
781 * cvmx_usbc#_grxstsph
783 * Receive Status Read and Pop Register, Host Mode (GRXSTSPH)
785 * A read to the Receive Status Read and Pop register returns and additionally
786 * pops the top data entry out of the RxFIFO.
787 * This Description is only valid when the core is in Host Mode. For Device Mode
788 * use USBC_GRXSTSPD instead.
789 * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the
790 * same offset in the O2P USB core. The offset difference shown in this
791 * document is for software clarity and is actually ignored by the
794 union cvmx_usbcx_grxstsph {
797 * struct cvmx_usbcx_grxstsph_s
798 * @pktsts: Packet Status (PktSts)
799 * Indicates the status of the received packet
800 * * 4'b0010: IN data packet received
801 * * 4'b0011: IN transfer completed (triggers an interrupt)
802 * * 4'b0101: Data toggle error (triggers an interrupt)
803 * * 4'b0111: Channel halted (triggers an interrupt)
805 * @dpid: Data PID (DPID)
810 * @bcnt: Byte Count (BCnt)
811 * Indicates the byte count of the received IN data packet
812 * @chnum: Channel Number (ChNum)
813 * Indicates the channel number to which the current received
816 struct cvmx_usbcx_grxstsph_s {
817 __BITFIELD_FIELD(uint32_t reserved_21_31 : 11,
818 __BITFIELD_FIELD(uint32_t pktsts : 4,
819 __BITFIELD_FIELD(uint32_t dpid : 2,
820 __BITFIELD_FIELD(uint32_t bcnt : 11,
821 __BITFIELD_FIELD(uint32_t chnum : 4,
829 * Core USB Configuration Register (GUSBCFG)
831 * This register can be used to configure the core after power-on or a changing
832 * to Host mode or Device mode. It contains USB and USB-PHY related
833 * configuration parameters. The application must program this register before
834 * starting any transactions on either the AHB or the USB. Do not make changes
835 * to this register after the initial programming.
837 union cvmx_usbcx_gusbcfg {
840 * struct cvmx_usbcx_gusbcfg_s
841 * @otgi2csel: UTMIFS or I2C Interface Select (OtgI2CSel)
842 * This bit is always 0x0.
843 * @phylpwrclksel: PHY Low-Power Clock Select (PhyLPwrClkSel)
844 * Software should set this bit to 0x0.
845 * Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
846 * FS and LS modes, the PHY can usually operate on a 48-MHz
847 * clock to save power.
848 * * 1'b0: 480-MHz Internal PLL clock
849 * * 1'b1: 48-MHz External Clock
850 * In 480 MHz mode, the UTMI interface operates at either 60 or
851 * 30-MHz, depending upon whether 8- or 16-bit data width is
852 * selected. In 48-MHz mode, the UTMI interface operates at 48
853 * MHz in FS mode and at either 48 or 6 MHz in LS mode
854 * (depending on the PHY vendor).
855 * This bit drives the utmi_fsls_low_power core output signal, and
856 * is valid only for UTMI+ PHYs.
857 * @usbtrdtim: USB Turnaround Time (USBTrdTim)
858 * Sets the turnaround time in PHY clocks.
859 * Specifies the response time for a MAC request to the Packet
860 * FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
861 * This must be programmed to 0x5.
862 * @hnpcap: HNP-Capable (HNPCap)
863 * This bit is always 0x0.
864 * @srpcap: SRP-Capable (SRPCap)
865 * This bit is always 0x0.
866 * @ddrsel: ULPI DDR Select (DDRSel)
867 * Software should set this bit to 0x0.
868 * @physel: USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
869 * Software should set this bit to 0x0.
870 * @fsintf: Full-Speed Serial Interface Select (FSIntf)
871 * Software should set this bit to 0x0.
872 * @ulpi_utmi_sel: ULPI or UTMI+ Select (ULPI_UTMI_Sel)
873 * This bit is always 0x0.
874 * @phyif: PHY Interface (PHYIf)
875 * This bit is always 0x1.
876 * @toutcal: HS/FS Timeout Calibration (TOutCal)
877 * The number of PHY clocks that the application programs in this
878 * field is added to the high-speed/full-speed interpacket timeout
879 * duration in the core to account for any additional delays
880 * introduced by the PHY. This may be required, since the delay
881 * introduced by the PHY in generating the linestate condition may
882 * vary from one PHY to another.
883 * The USB standard timeout value for high-speed operation is
884 * 736 to 816 (inclusive) bit times. The USB standard timeout
885 * value for full-speed operation is 16 to 18 (inclusive) bit
886 * times. The application must program this field based on the
887 * speed of enumeration. The number of bit times added per PHY
889 * High-speed operation:
890 * * One 30-MHz PHY clock = 16 bit times
891 * * One 60-MHz PHY clock = 8 bit times
892 * Full-speed operation:
893 * * One 30-MHz PHY clock = 0.4 bit times
894 * * One 60-MHz PHY clock = 0.2 bit times
895 * * One 48-MHz PHY clock = 0.25 bit times
897 struct cvmx_usbcx_gusbcfg_s {
898 __BITFIELD_FIELD(uint32_t reserved_17_31 : 15,
899 __BITFIELD_FIELD(uint32_t otgi2csel : 1,
900 __BITFIELD_FIELD(uint32_t phylpwrclksel : 1,
901 __BITFIELD_FIELD(uint32_t reserved_14_14 : 1,
902 __BITFIELD_FIELD(uint32_t usbtrdtim : 4,
903 __BITFIELD_FIELD(uint32_t hnpcap : 1,
904 __BITFIELD_FIELD(uint32_t srpcap : 1,
905 __BITFIELD_FIELD(uint32_t ddrsel : 1,
906 __BITFIELD_FIELD(uint32_t physel : 1,
907 __BITFIELD_FIELD(uint32_t fsintf : 1,
908 __BITFIELD_FIELD(uint32_t ulpi_utmi_sel : 1,
909 __BITFIELD_FIELD(uint32_t phyif : 1,
910 __BITFIELD_FIELD(uint32_t toutcal : 3,
918 * Host All Channels Interrupt Register (HAINT)
920 * When a significant event occurs on a channel, the Host All Channels Interrupt
921 * register interrupts the application using the Host Channels Interrupt bit of
922 * the Core Interrupt register (GINTSTS.HChInt). This is shown in Interrupt.
923 * There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in
924 * this register are set and cleared when the application sets and clears bits
925 * in the corresponding Host Channel-n Interrupt register.
927 union cvmx_usbcx_haint {
930 * struct cvmx_usbcx_haint_s
931 * @haint: Channel Interrupts (HAINT)
932 * One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15
934 struct cvmx_usbcx_haint_s {
935 __BITFIELD_FIELD(uint32_t reserved_16_31 : 16,
936 __BITFIELD_FIELD(uint32_t haint : 16,
942 * cvmx_usbc#_haintmsk
944 * Host All Channels Interrupt Mask Register (HAINTMSK)
946 * The Host All Channel Interrupt Mask register works with the Host All Channel
947 * Interrupt register to interrupt the application when an event occurs on a
948 * channel. There is one interrupt mask bit per channel, up to a maximum of 16
950 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
952 union cvmx_usbcx_haintmsk {
955 * struct cvmx_usbcx_haintmsk_s
956 * @haintmsk: Channel Interrupt Mask (HAINTMsk)
957 * One bit per channel: Bit 0 for channel 0, bit 15 for channel 15
959 struct cvmx_usbcx_haintmsk_s {
960 __BITFIELD_FIELD(uint32_t reserved_16_31 : 16,
961 __BITFIELD_FIELD(uint32_t haintmsk : 16,
969 * Host Channel-n Characteristics Register (HCCHAR)
972 union cvmx_usbcx_hccharx {
975 * struct cvmx_usbcx_hccharx_s
976 * @chena: Channel Enable (ChEna)
977 * This field is set by the application and cleared by the OTG
979 * * 1'b0: Channel disabled
980 * * 1'b1: Channel enabled
981 * @chdis: Channel Disable (ChDis)
982 * The application sets this bit to stop transmitting/receiving
983 * data on a channel, even before the transfer for that channel is
984 * complete. The application must wait for the Channel Disabled
985 * interrupt before treating the channel as disabled.
986 * @oddfrm: Odd Frame (OddFrm)
987 * This field is set (reset) by the application to indicate that
988 * the OTG host must perform a transfer in an odd (micro)frame.
989 * This field is applicable for only periodic (isochronous and
990 * interrupt) transactions.
991 * * 1'b0: Even (micro)frame
992 * * 1'b1: Odd (micro)frame
993 * @devaddr: Device Address (DevAddr)
994 * This field selects the specific device serving as the data
996 * @ec: Multi Count (MC) / Error Count (EC)
997 * When the Split Enable bit of the Host Channel-n Split Control
998 * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates
999 * to the host the number of transactions that should be executed
1000 * per microframe for this endpoint.
1001 * * 2'b00: Reserved. This field yields undefined results.
1002 * * 2'b01: 1 transaction
1003 * * 2'b10: 2 transactions to be issued for this endpoint per
1005 * * 2'b11: 3 transactions to be issued for this endpoint per
1007 * When HCSPLTn.SpltEna is set (1'b1), this field indicates the
1008 * number of immediate retries to be performed for a periodic split
1009 * transactions on transaction errors. This field must be set to at
1011 * @eptype: Endpoint Type (EPType)
1012 * Indicates the transfer type selected.
1014 * * 2'b01: Isochronous
1016 * * 2'b11: Interrupt
1017 * @lspddev: Low-Speed Device (LSpdDev)
1018 * This field is set by the application to indicate that this
1019 * channel is communicating to a low-speed device.
1020 * @epdir: Endpoint Direction (EPDir)
1021 * Indicates whether the transaction is IN or OUT.
1024 * @epnum: Endpoint Number (EPNum)
1025 * Indicates the endpoint number on the device serving as the
1026 * data source or sink.
1027 * @mps: Maximum Packet Size (MPS)
1028 * Indicates the maximum packet size of the associated endpoint.
1030 struct cvmx_usbcx_hccharx_s {
1031 __BITFIELD_FIELD(uint32_t chena : 1,
1032 __BITFIELD_FIELD(uint32_t chdis : 1,
1033 __BITFIELD_FIELD(uint32_t oddfrm : 1,
1034 __BITFIELD_FIELD(uint32_t devaddr : 7,
1035 __BITFIELD_FIELD(uint32_t ec : 2,
1036 __BITFIELD_FIELD(uint32_t eptype : 2,
1037 __BITFIELD_FIELD(uint32_t lspddev : 1,
1038 __BITFIELD_FIELD(uint32_t reserved_16_16 : 1,
1039 __BITFIELD_FIELD(uint32_t epdir : 1,
1040 __BITFIELD_FIELD(uint32_t epnum : 4,
1041 __BITFIELD_FIELD(uint32_t mps : 11,
1049 * Host Configuration Register (HCFG)
1051 * This register configures the core after power-on. Do not make changes to this
1052 * register after initializing the host.
1054 union cvmx_usbcx_hcfg {
1057 * struct cvmx_usbcx_hcfg_s
1058 * @fslssupp: FS- and LS-Only Support (FSLSSupp)
1059 * The application uses this bit to control the core's enumeration
1060 * speed. Using this bit, the application can make the core
1061 * enumerate as a FS host, even if the connected device supports
1062 * HS traffic. Do not make changes to this field after initial
1064 * * 1'b0: HS/FS/LS, based on the maximum speed supported by
1065 * the connected device
1066 * * 1'b1: FS/LS-only, even if the connected device can support HS
1067 * @fslspclksel: FS/LS PHY Clock Select (FSLSPclkSel)
1068 * When the core is in FS Host mode
1069 * * 2'b00: PHY clock is running at 30/60 MHz
1070 * * 2'b01: PHY clock is running at 48 MHz
1071 * * Others: Reserved
1072 * When the core is in LS Host mode
1073 * * 2'b00: PHY clock is running at 30/60 MHz. When the
1074 * UTMI+/ULPI PHY Low Power mode is not selected, use
1076 * * 2'b01: PHY clock is running at 48 MHz. When the UTMI+
1077 * PHY Low Power mode is selected, use 48MHz if the PHY
1078 * supplies a 48 MHz clock during LS mode.
1079 * * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
1080 * use 6 MHz when the UTMI+ PHY Low Power mode is
1081 * selected and the PHY supplies a 6 MHz clock during LS
1082 * mode. If you select a 6 MHz clock during LS mode, you must
1086 struct cvmx_usbcx_hcfg_s {
1087 __BITFIELD_FIELD(uint32_t reserved_3_31 : 29,
1088 __BITFIELD_FIELD(uint32_t fslssupp : 1,
1089 __BITFIELD_FIELD(uint32_t fslspclksel : 2,
1097 * Host Channel-n Interrupt Register (HCINT)
1099 * This register indicates the status of a channel with respect to USB- and
1100 * AHB-related events. The application must read this register when the Host
1101 * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is
1102 * set. Before the application can read this register, it must first read
1103 * the Host All Channels Interrupt (HAINT) register to get the exact channel
1104 * number for the Host Channel-n Interrupt register. The application must clear
1105 * the appropriate bit in this register to clear the corresponding bits in the
1106 * HAINT and GINTSTS registers.
1108 union cvmx_usbcx_hcintx {
1111 * struct cvmx_usbcx_hcintx_s
1112 * @datatglerr: Data Toggle Error (DataTglErr)
1113 * @frmovrun: Frame Overrun (FrmOvrun)
1114 * @bblerr: Babble Error (BblErr)
1115 * @xacterr: Transaction Error (XactErr)
1116 * @nyet: NYET Response Received Interrupt (NYET)
1117 * @ack: ACK Response Received Interrupt (ACK)
1118 * @nak: NAK Response Received Interrupt (NAK)
1119 * @stall: STALL Response Received Interrupt (STALL)
1120 * @ahberr: This bit is always 0x0.
1121 * @chhltd: Channel Halted (ChHltd)
1122 * Indicates the transfer completed abnormally either because of
1123 * any USB transaction error or in response to disable request by
1125 * @xfercompl: Transfer Completed (XferCompl)
1126 * Transfer completed normally without any errors.
1128 struct cvmx_usbcx_hcintx_s {
1129 __BITFIELD_FIELD(uint32_t reserved_11_31 : 21,
1130 __BITFIELD_FIELD(uint32_t datatglerr : 1,
1131 __BITFIELD_FIELD(uint32_t frmovrun : 1,
1132 __BITFIELD_FIELD(uint32_t bblerr : 1,
1133 __BITFIELD_FIELD(uint32_t xacterr : 1,
1134 __BITFIELD_FIELD(uint32_t nyet : 1,
1135 __BITFIELD_FIELD(uint32_t ack : 1,
1136 __BITFIELD_FIELD(uint32_t nak : 1,
1137 __BITFIELD_FIELD(uint32_t stall : 1,
1138 __BITFIELD_FIELD(uint32_t ahberr : 1,
1139 __BITFIELD_FIELD(uint32_t chhltd : 1,
1140 __BITFIELD_FIELD(uint32_t xfercompl : 1,
1146 * cvmx_usbc#_hcintmsk#
1148 * Host Channel-n Interrupt Mask Register (HCINTMSKn)
1150 * This register reflects the mask for each channel status described in the
1152 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
1154 union cvmx_usbcx_hcintmskx {
1157 * struct cvmx_usbcx_hcintmskx_s
1158 * @datatglerrmsk: Data Toggle Error Mask (DataTglErrMsk)
1159 * @frmovrunmsk: Frame Overrun Mask (FrmOvrunMsk)
1160 * @bblerrmsk: Babble Error Mask (BblErrMsk)
1161 * @xacterrmsk: Transaction Error Mask (XactErrMsk)
1162 * @nyetmsk: NYET Response Received Interrupt Mask (NyetMsk)
1163 * @ackmsk: ACK Response Received Interrupt Mask (AckMsk)
1164 * @nakmsk: NAK Response Received Interrupt Mask (NakMsk)
1165 * @stallmsk: STALL Response Received Interrupt Mask (StallMsk)
1166 * @ahberrmsk: AHB Error Mask (AHBErrMsk)
1167 * @chhltdmsk: Channel Halted Mask (ChHltdMsk)
1168 * @xfercomplmsk: Transfer Completed Mask (XferComplMsk)
1170 struct cvmx_usbcx_hcintmskx_s {
1171 __BITFIELD_FIELD(uint32_t reserved_11_31 : 21,
1172 __BITFIELD_FIELD(uint32_t datatglerrmsk : 1,
1173 __BITFIELD_FIELD(uint32_t frmovrunmsk : 1,
1174 __BITFIELD_FIELD(uint32_t bblerrmsk : 1,
1175 __BITFIELD_FIELD(uint32_t xacterrmsk : 1,
1176 __BITFIELD_FIELD(uint32_t nyetmsk : 1,
1177 __BITFIELD_FIELD(uint32_t ackmsk : 1,
1178 __BITFIELD_FIELD(uint32_t nakmsk : 1,
1179 __BITFIELD_FIELD(uint32_t stallmsk : 1,
1180 __BITFIELD_FIELD(uint32_t ahberrmsk : 1,
1181 __BITFIELD_FIELD(uint32_t chhltdmsk : 1,
1182 __BITFIELD_FIELD(uint32_t xfercomplmsk : 1,
1188 * cvmx_usbc#_hcsplt#
1190 * Host Channel-n Split Control Register (HCSPLT)
1193 union cvmx_usbcx_hcspltx {
1196 * struct cvmx_usbcx_hcspltx_s
1197 * @spltena: Split Enable (SpltEna)
1198 * The application sets this field to indicate that this channel is
1199 * enabled to perform split transactions.
1200 * @compsplt: Do Complete Split (CompSplt)
1201 * The application sets this field to request the OTG host to
1202 * perform a complete split transaction.
1203 * @xactpos: Transaction Position (XactPos)
1204 * This field is used to determine whether to send all, first,
1205 * middle, or last payloads with each OUT transaction.
1206 * * 2'b11: All. This is the entire data payload is of this
1207 * transaction (which is less than or equal to 188 bytes).
1208 * * 2'b10: Begin. This is the first data payload of this
1209 * transaction (which is larger than 188 bytes).
1210 * * 2'b00: Mid. This is the middle payload of this transaction
1211 * (which is larger than 188 bytes).
1212 * * 2'b01: End. This is the last payload of this transaction
1213 * (which is larger than 188 bytes).
1214 * @hubaddr: Hub Address (HubAddr)
1215 * This field holds the device address of the transaction
1217 * @prtaddr: Port Address (PrtAddr)
1218 * This field is the port number of the recipient transaction
1221 struct cvmx_usbcx_hcspltx_s {
1222 __BITFIELD_FIELD(uint32_t spltena : 1,
1223 __BITFIELD_FIELD(uint32_t reserved_17_30 : 14,
1224 __BITFIELD_FIELD(uint32_t compsplt : 1,
1225 __BITFIELD_FIELD(uint32_t xactpos : 2,
1226 __BITFIELD_FIELD(uint32_t hubaddr : 7,
1227 __BITFIELD_FIELD(uint32_t prtaddr : 7,
1233 * cvmx_usbc#_hctsiz#
1235 * Host Channel-n Transfer Size Register (HCTSIZ)
1238 union cvmx_usbcx_hctsizx {
1241 * struct cvmx_usbcx_hctsizx_s
1242 * @dopng: Do Ping (DoPng)
1243 * Setting this field to 1 directs the host to do PING protocol.
1245 * The application programs this field with the type of PID to use
1246 * for the initial transaction. The host will maintain this field
1247 * for the rest of the transfer.
1251 * * 2'b11: MDATA (non-control)/SETUP (control)
1252 * @pktcnt: Packet Count (PktCnt)
1253 * This field is programmed by the application with the expected
1254 * number of packets to be transmitted (OUT) or received (IN).
1255 * The host decrements this count on every successful
1256 * transmission or reception of an OUT/IN packet. Once this count
1257 * reaches zero, the application is interrupted to indicate normal
1259 * @xfersize: Transfer Size (XferSize)
1260 * For an OUT, this field is the number of data bytes the host will
1261 * send during the transfer.
1262 * For an IN, this field is the buffer size that the application
1263 * has reserved for the transfer. The application is expected to
1264 * program this field as an integer multiple of the maximum packet
1265 * size for IN transactions (periodic and non-periodic).
1267 struct cvmx_usbcx_hctsizx_s {
1268 __BITFIELD_FIELD(uint32_t dopng : 1,
1269 __BITFIELD_FIELD(uint32_t pid : 2,
1270 __BITFIELD_FIELD(uint32_t pktcnt : 10,
1271 __BITFIELD_FIELD(uint32_t xfersize : 19,
1279 * Host Frame Interval Register (HFIR)
1281 * This register stores the frame interval information for the current speed to
1282 * which the O2P USB core has enumerated.
1284 union cvmx_usbcx_hfir {
1287 * struct cvmx_usbcx_hfir_s
1288 * @frint: Frame Interval (FrInt)
1289 * The value that the application programs to this field specifies
1290 * the interval between two consecutive SOFs (FS) or micro-
1291 * SOFs (HS) or Keep-Alive tokens (HS). This field contains the
1292 * number of PHY clocks that constitute the required frame
1293 * interval. The default value set in this field for a FS operation
1294 * when the PHY clock frequency is 60 MHz. The application can
1295 * write a value to this register only after the Port Enable bit of
1296 * the Host Port Control and Status register (HPRT.PrtEnaPort)
1297 * has been set. If no value is programmed, the core calculates
1298 * the value based on the PHY clock specified in the FS/LS PHY
1299 * Clock Select field of the Host Configuration register
1300 * (HCFG.FSLSPclkSel). Do not change the value of this field
1301 * after the initial configuration.
1302 * * 125 us (PHY clock frequency for HS)
1303 * * 1 ms (PHY clock frequency for FS/LS)
1305 struct cvmx_usbcx_hfir_s {
1306 __BITFIELD_FIELD(uint32_t reserved_16_31 : 16,
1307 __BITFIELD_FIELD(uint32_t frint : 16,
1315 * Host Frame Number/Frame Time Remaining Register (HFNUM)
1317 * This register indicates the current frame number.
1318 * It also indicates the time remaining (in terms of the number of PHY clocks)
1319 * in the current (micro)frame.
1321 union cvmx_usbcx_hfnum {
1324 * struct cvmx_usbcx_hfnum_s
1325 * @frrem: Frame Time Remaining (FrRem)
1326 * Indicates the amount of time remaining in the current
1327 * microframe (HS) or frame (FS/LS), in terms of PHY clocks.
1328 * This field decrements on each PHY clock. When it reaches
1329 * zero, this field is reloaded with the value in the Frame
1330 * Interval register and a new SOF is transmitted on the USB.
1331 * @frnum: Frame Number (FrNum)
1332 * This field increments when a new SOF is transmitted on the
1333 * USB, and is reset to 0 when it reaches 16'h3FFF.
1335 struct cvmx_usbcx_hfnum_s {
1336 __BITFIELD_FIELD(uint32_t frrem : 16,
1337 __BITFIELD_FIELD(uint32_t frnum : 16,
1345 * Host Port Control and Status Register (HPRT)
1347 * This register is available in both Host and Device modes.
1348 * Currently, the OTG Host supports only one port.
1349 * A single register holds USB port-related information such as USB reset,
1350 * enable, suspend, resume, connect status, and test mode for each port. The
1351 * R_SS_WC bits in this register can trigger an interrupt to the application
1352 * through the Host Port Interrupt bit of the Core Interrupt register
1353 * (GINTSTS.PrtInt). On a Port Interrupt, the application must read this
1354 * register and clear the bit that caused the interrupt. For the R_SS_WC bits,
1355 * the application must write a 1 to the bit to clear the interrupt.
1357 union cvmx_usbcx_hprt {
1360 * struct cvmx_usbcx_hprt_s
1361 * @prtspd: Port Speed (PrtSpd)
1362 * Indicates the speed of the device attached to this port.
1363 * * 2'b00: High speed
1364 * * 2'b01: Full speed
1365 * * 2'b10: Low speed
1367 * @prttstctl: Port Test Control (PrtTstCtl)
1368 * The application writes a nonzero value to this field to put
1369 * the port into a Test mode, and the corresponding pattern is
1370 * signaled on the port.
1371 * * 4'b0000: Test mode disabled
1372 * * 4'b0001: Test_J mode
1373 * * 4'b0010: Test_K mode
1374 * * 4'b0011: Test_SE0_NAK mode
1375 * * 4'b0100: Test_Packet mode
1376 * * 4'b0101: Test_Force_Enable
1377 * * Others: Reserved
1378 * PrtSpd must be zero (i.e. the interface must be in high-speed
1379 * mode) to use the PrtTstCtl test modes.
1380 * @prtpwr: Port Power (PrtPwr)
1381 * The application uses this field to control power to this port,
1382 * and the core clears this bit on an overcurrent condition.
1385 * @prtlnsts: Port Line Status (PrtLnSts)
1386 * Indicates the current logic level USB data lines
1387 * * Bit [10]: Logic level of D-
1388 * * Bit [11]: Logic level of D+
1389 * @prtrst: Port Reset (PrtRst)
1390 * When the application sets this bit, a reset sequence is
1391 * started on this port. The application must time the reset
1392 * period and clear this bit after the reset sequence is
1394 * * 1'b0: Port not in reset
1395 * * 1'b1: Port in reset
1396 * The application must leave this bit set for at least a
1397 * minimum duration mentioned below to start a reset on the
1398 * port. The application can leave it set for another 10 ms in
1399 * addition to the required minimum duration, before clearing
1400 * the bit, even though there is no maximum limit set by the
1402 * * High speed: 50 ms
1403 * * Full speed/Low speed: 10 ms
1404 * @prtsusp: Port Suspend (PrtSusp)
1405 * The application sets this bit to put this port in Suspend
1406 * mode. The core only stops sending SOFs when this is set.
1407 * To stop the PHY clock, the application must set the Port
1408 * Clock Stop bit, which will assert the suspend input pin of
1410 * The read value of this bit reflects the current suspend
1411 * status of the port. This bit is cleared by the core after a
1412 * remote wakeup signal is detected or the application sets
1413 * the Port Reset bit or Port Resume bit in this register or the
1414 * Resume/Remote Wakeup Detected Interrupt bit or
1415 * Disconnect Detected Interrupt bit in the Core Interrupt
1416 * register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
1418 * * 1'b0: Port not in Suspend mode
1419 * * 1'b1: Port in Suspend mode
1420 * @prtres: Port Resume (PrtRes)
1421 * The application sets this bit to drive resume signaling on
1422 * the port. The core continues to drive the resume signal
1423 * until the application clears this bit.
1424 * If the core detects a USB remote wakeup sequence, as
1425 * indicated by the Port Resume/Remote Wakeup Detected
1426 * Interrupt bit of the Core Interrupt register
1427 * (GINTSTS.WkUpInt), the core starts driving resume
1428 * signaling without application intervention and clears this bit
1429 * when it detects a disconnect condition. The read value of
1430 * this bit indicates whether the core is currently driving
1432 * * 1'b0: No resume driven
1433 * * 1'b1: Resume driven
1434 * @prtovrcurrchng: Port Overcurrent Change (PrtOvrCurrChng)
1435 * The core sets this bit when the status of the Port
1436 * Overcurrent Active bit (bit 4) in this register changes.
1437 * @prtovrcurract: Port Overcurrent Active (PrtOvrCurrAct)
1438 * Indicates the overcurrent condition of the port.
1439 * * 1'b0: No overcurrent condition
1440 * * 1'b1: Overcurrent condition
1441 * @prtenchng: Port Enable/Disable Change (PrtEnChng)
1442 * The core sets this bit when the status of the Port Enable bit
1443 * [2] of this register changes.
1444 * @prtena: Port Enable (PrtEna)
1445 * A port is enabled only by the core after a reset sequence,
1446 * and is disabled by an overcurrent condition, a disconnect
1447 * condition, or by the application clearing this bit. The
1448 * application cannot set this bit by a register write. It can only
1449 * clear it to disable the port. This bit does not trigger any
1450 * interrupt to the application.
1451 * * 1'b0: Port disabled
1452 * * 1'b1: Port enabled
1453 * @prtconndet: Port Connect Detected (PrtConnDet)
1454 * The core sets this bit when a device connection is detected
1455 * to trigger an interrupt to the application using the Host Port
1456 * Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).
1457 * The application must write a 1 to this bit to clear the
1459 * @prtconnsts: Port Connect Status (PrtConnSts)
1460 * * 0: No device is attached to the port.
1461 * * 1: A device is attached to the port.
1463 struct cvmx_usbcx_hprt_s {
1464 __BITFIELD_FIELD(uint32_t reserved_19_31 : 13,
1465 __BITFIELD_FIELD(uint32_t prtspd : 2,
1466 __BITFIELD_FIELD(uint32_t prttstctl : 4,
1467 __BITFIELD_FIELD(uint32_t prtpwr : 1,
1468 __BITFIELD_FIELD(uint32_t prtlnsts : 2,
1469 __BITFIELD_FIELD(uint32_t reserved_9_9 : 1,
1470 __BITFIELD_FIELD(uint32_t prtrst : 1,
1471 __BITFIELD_FIELD(uint32_t prtsusp : 1,
1472 __BITFIELD_FIELD(uint32_t prtres : 1,
1473 __BITFIELD_FIELD(uint32_t prtovrcurrchng : 1,
1474 __BITFIELD_FIELD(uint32_t prtovrcurract : 1,
1475 __BITFIELD_FIELD(uint32_t prtenchng : 1,
1476 __BITFIELD_FIELD(uint32_t prtena : 1,
1477 __BITFIELD_FIELD(uint32_t prtconndet : 1,
1478 __BITFIELD_FIELD(uint32_t prtconnsts : 1,
1484 * cvmx_usbc#_hptxfsiz
1486 * Host Periodic Transmit FIFO Size Register (HPTXFSIZ)
1488 * This register holds the size and the memory start address of the Periodic
1489 * TxFIFO, as shown in Figures 310 and 311.
1491 union cvmx_usbcx_hptxfsiz {
1494 * struct cvmx_usbcx_hptxfsiz_s
1495 * @ptxfsize: Host Periodic TxFIFO Depth (PTxFSize)
1496 * This value is in terms of 32-bit words.
1497 * * Minimum value is 16
1498 * * Maximum value is 32768
1499 * @ptxfstaddr: Host Periodic TxFIFO Start Address (PTxFStAddr)
1501 struct cvmx_usbcx_hptxfsiz_s {
1502 __BITFIELD_FIELD(uint32_t ptxfsize : 16,
1503 __BITFIELD_FIELD(uint32_t ptxfstaddr : 16,
1509 * cvmx_usbc#_hptxsts
1511 * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS)
1513 * This read-only register contains the free space information for the Periodic
1514 * TxFIFO and the Periodic Transmit Request Queue
1516 union cvmx_usbcx_hptxsts {
1519 * struct cvmx_usbcx_hptxsts_s
1520 * @ptxqtop: Top of the Periodic Transmit Request Queue (PTxQTop)
1521 * This indicates the entry in the Periodic Tx Request Queue that
1522 * is currently being processes by the MAC.
1523 * This register is used for debugging.
1524 * * Bit [31]: Odd/Even (micro)frame
1525 * - 1'b0: send in even (micro)frame
1526 * - 1'b1: send in odd (micro)frame
1527 * * Bits [30:27]: Channel/endpoint number
1528 * * Bits [26:25]: Type
1530 * - 2'b01: Zero-length packet
1532 * - 2'b11: Disable channel command
1533 * * Bit [24]: Terminate (last entry for the selected
1535 * @ptxqspcavail: Periodic Transmit Request Queue Space Available
1537 * Indicates the number of free locations available to be written
1538 * in the Periodic Transmit Request Queue. This queue holds both
1539 * IN and OUT requests.
1540 * * 8'h0: Periodic Transmit Request Queue is full
1541 * * 8'h1: 1 location available
1542 * * 8'h2: 2 locations available
1543 * * n: n locations available (0..8)
1544 * * Others: Reserved
1545 * @ptxfspcavail: Periodic Transmit Data FIFO Space Available
1547 * Indicates the number of free locations available to be written
1548 * to in the Periodic TxFIFO.
1549 * Values are in terms of 32-bit words
1550 * * 16'h0: Periodic TxFIFO is full
1551 * * 16'h1: 1 word available
1552 * * 16'h2: 2 words available
1553 * * 16'hn: n words available (where 0..32768)
1554 * * 16'h8000: 32768 words available
1555 * * Others: Reserved
1557 struct cvmx_usbcx_hptxsts_s {
1558 __BITFIELD_FIELD(uint32_t ptxqtop : 8,
1559 __BITFIELD_FIELD(uint32_t ptxqspcavail : 8,
1560 __BITFIELD_FIELD(uint32_t ptxfspcavail : 16,
1566 * cvmx_usbn#_clk_ctl
1568 * USBN_CLK_CTL = USBN's Clock Control
1570 * This register is used to control the frequency of the hclk and the
1571 * hreset and phy_rst signals.
1573 union cvmx_usbnx_clk_ctl {
1576 * struct cvmx_usbnx_clk_ctl_s
1577 * @divide2: The 'hclk' used by the USB subsystem is derived
1579 * Also see the field DIVIDE. DIVIDE2<1> must currently
1580 * be zero because it is not implemented, so the maximum
1581 * ratio of eclk/hclk is currently 16.
1582 * The actual divide number for hclk is:
1583 * (DIVIDE2 + 1) * (DIVIDE + 1)
1584 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
1585 * generate the hclk in the USB Subsystem is held
1586 * in reset. This bit must be set to '0' before
1587 * changing the value os DIVIDE in this register.
1588 * The reset to the HCLK_DIVIDERis also asserted
1589 * when core reset is asserted.
1590 * @p_x_on: Force USB-PHY on during suspend.
1591 * '1' USB-PHY XO block is powered-down during
1593 * '0' USB-PHY XO block is powered-up during
1595 * The value of this field must be set while POR is
1597 * @p_rtype: PHY reference clock type
1598 * On CN50XX/CN52XX/CN56XX the values are:
1599 * '0' The USB-PHY uses a 12MHz crystal as a clock source
1600 * at the USB_XO and USB_XI pins.
1602 * '2' The USB_PHY uses 12/24/48MHz 2.5V board clock at the
1603 * USB_XO pin. USB_XI should be tied to ground in this
1606 * On CN3xxx bits 14 and 15 are p_xenbn and p_rclk and values are:
1609 * '2' The PHY PLL uses the XO block output as a reference.
1610 * The XO block uses an external clock supplied on the
1611 * XO pin. USB_XI should be tied to ground for this
1613 * '3' The XO block uses the clock from a crystal.
1614 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
1615 * remain powered in Suspend Mode.
1616 * '1' The USB-PHY XO Bias, Bandgap and PLL are
1617 * powered down in suspend mode.
1618 * The value of this field must be set while POR is
1620 * @p_c_sel: Phy clock speed select.
1621 * Selects the reference clock / crystal frequency.
1623 * '10': 48 MHz (reserved when a crystal is used)
1624 * '01': 24 MHz (reserved when a crystal is used)
1626 * The value of this field must be set while POR is
1628 * NOTE: if a crystal is used as a reference clock,
1629 * this field must be set to 12 MHz.
1630 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV.
1631 * @sd_mode: Scaledown mode for the USBC. Control timing events
1632 * in the USBC, for normal operation this must be '0'.
1633 * @s_bist: Starts bist on the hclk memories, during the '0'
1634 * to '1' transition.
1635 * @por: Power On Reset for the PHY.
1636 * Resets all the PHYS registers and state machines.
1637 * @enable: When '1' allows the generation of the hclk. When
1638 * '0' the hclk will not be generated. SEE DIVIDE
1639 * field of this register.
1640 * @prst: When this field is '0' the reset associated with
1641 * the phy_clk functionality in the USB Subsystem is
1642 * help in reset. This bit should not be set to '1'
1643 * until the time it takes 6 clocks (hclk or phy_clk,
1644 * whichever is slower) has passed. Under normal
1645 * operation once this bit is set to '1' it should not
1647 * @hrst: When this field is '0' the reset associated with
1648 * the hclk functioanlity in the USB Subsystem is
1649 * held in reset.This bit should not be set to '1'
1650 * until 12ms after phy_clk is stable. Under normal
1651 * operation, once this bit is set to '1' it should
1652 * not be set to '0'.
1653 * @divide: The frequency of 'hclk' used by the USB subsystem
1654 * is the eclk frequency divided by the value of
1655 * (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
1656 * DIVIDE2 of this register.
1657 * The hclk frequency should be less than 125Mhz.
1658 * After writing a value to this field the SW should
1659 * read the field for the value written.
1660 * The ENABLE field of this register should not be set
1661 * until AFTER this field is set and then read.
1663 struct cvmx_usbnx_clk_ctl_s {
1664 __BITFIELD_FIELD(uint64_t reserved_20_63 : 44,
1665 __BITFIELD_FIELD(uint64_t divide2 : 2,
1666 __BITFIELD_FIELD(uint64_t hclk_rst : 1,
1667 __BITFIELD_FIELD(uint64_t p_x_on : 1,
1668 __BITFIELD_FIELD(uint64_t p_rtype : 2,
1669 __BITFIELD_FIELD(uint64_t p_com_on : 1,
1670 __BITFIELD_FIELD(uint64_t p_c_sel : 2,
1671 __BITFIELD_FIELD(uint64_t cdiv_byp : 1,
1672 __BITFIELD_FIELD(uint64_t sd_mode : 2,
1673 __BITFIELD_FIELD(uint64_t s_bist : 1,
1674 __BITFIELD_FIELD(uint64_t por : 1,
1675 __BITFIELD_FIELD(uint64_t enable : 1,
1676 __BITFIELD_FIELD(uint64_t prst : 1,
1677 __BITFIELD_FIELD(uint64_t hrst : 1,
1678 __BITFIELD_FIELD(uint64_t divide : 3,
1684 * cvmx_usbn#_usbp_ctl_status
1686 * USBN_USBP_CTL_STATUS = USBP Control And Status Register
1688 * Contains general control and status information for the USBN block.
1690 union cvmx_usbnx_usbp_ctl_status {
1693 * struct cvmx_usbnx_usbp_ctl_status_s
1694 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment
1695 * @txvreftune: HS DC Voltage Level Adjustment
1696 * @txfslstune: FS/LS Source Impedence Adjustment
1697 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
1698 * @sqrxtune: Squelch Threshold Adjustment
1699 * @compdistune: Disconnect Threshold Adjustment
1700 * @otgtune: VBUS Valid Threshold Adjustment
1701 * @otgdisable: OTG Block Disable
1702 * @portreset: Per_Port Reset
1703 * @drvvbus: Drive VBUS
1704 * @lsbist: Low-Speed BIST Enable.
1705 * @fsbist: Full-Speed BIST Enable.
1706 * @hsbist: High-Speed BIST Enable.
1707 * @bist_done: PHY Bist Done.
1708 * Asserted at the end of the PHY BIST sequence.
1709 * @bist_err: PHY Bist Error.
1710 * Indicates an internal error was detected during
1711 * the BIST sequence.
1712 * @tdata_out: PHY Test Data Out.
1713 * Presents either internaly generated signals or
1714 * test register contents, based upon the value of
1715 * test_data_out_sel.
1716 * @siddq: Drives the USBP (USB-PHY) SIDDQ input.
1717 * Normally should be set to zero.
1718 * When customers have no intent to use USB PHY
1719 * interface, they should:
1720 * - still provide 3.3V to USB_VDD33, and
1721 * - tie USB_REXT to 3.3V supply, and
1722 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
1723 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
1724 * @dma_bmode: When set to 1 the L2C DMA address will be updated
1725 * with byte-counts between packets. When set to 0
1726 * the L2C DMA address is incremented to the next
1727 * 4-byte aligned address after adding byte-count.
1728 * @usbc_end: Bigendian input to the USB Core. This should be
1729 * set to '0' for operation.
1730 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP.
1731 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP.
1732 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
1733 * This signal enables the pull-down resistance on
1734 * the D+ line. '1' pull down-resistance is connected
1735 * to D+/ '0' pull down resistance is not connected
1736 * to D+. When an A/B device is acting as a host
1737 * (downstream-facing port), dp_pulldown and
1738 * dm_pulldown are enabled. This must not toggle
1739 * during normal opeartion.
1740 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
1741 * This signal enables the pull-down resistance on
1742 * the D- line. '1' pull down-resistance is connected
1743 * to D-. '0' pull down resistance is not connected
1744 * to D-. When an A/B device is acting as a host
1745 * (downstream-facing port), dp_pulldown and
1746 * dm_pulldown are enabled. This must not toggle
1747 * during normal opeartion.
1748 * @hst_mode: When '0' the USB is acting as HOST, when '1'
1749 * USB is acting as device. This field needs to be
1750 * set while the USB is in reset.
1751 * @tuning: Transmitter Tuning for High-Speed Operation.
1752 * Tunes the current supply and rise/fall output
1753 * times for high-speed operation.
1754 * [20:19] == 11: Current supply increased
1756 * [20:19] == 10: Current supply increased
1757 * approximately 4.5%
1758 * [20:19] == 01: Design default.
1759 * [20:19] == 00: Current supply decreased
1760 * approximately 4.5%
1761 * [22:21] == 11: Rise and fall times are increased.
1762 * [22:21] == 10: Design default.
1763 * [22:21] == 01: Rise and fall times are decreased.
1764 * [22:21] == 00: Rise and fall times are decreased
1765 * further as compared to the 01 setting.
1766 * @tx_bs_enh: Transmit Bit Stuffing on [15:8].
1767 * Enables or disables bit stuffing on data[15:8]
1768 * when bit-stuffing is enabled.
1769 * @tx_bs_en: Transmit Bit Stuffing on [7:0].
1770 * Enables or disables bit stuffing on data[7:0]
1771 * when bit-stuffing is enabled.
1772 * @loop_enb: PHY Loopback Test Enable.
1773 * '1': During data transmission the receive is
1775 * '0': During data transmission the receive is
1777 * Must be '0' for normal operation.
1778 * @vtest_enb: Analog Test Pin Enable.
1779 * '1' The PHY's analog_test pin is enabled for the
1780 * input and output of applicable analog test signals.
1781 * '0' THe analog_test pin is disabled.
1782 * @bist_enb: Built-In Self Test Enable.
1783 * Used to activate BIST in the PHY.
1784 * @tdata_sel: Test Data Out Select.
1785 * '1' test_data_out[3:0] (PHY) register contents
1786 * are output. '0' internaly generated signals are
1788 * @taddr_in: Mode Address for Test Interface.
1789 * Specifies the register address for writing to or
1790 * reading from the PHY test interface register.
1791 * @tdata_in: Internal Testing Register Input Data and Select
1792 * This is a test bus. Data is present on [3:0],
1793 * and its corresponding select (enable) is present
1795 * @ate_reset: Reset input from automatic test equipment.
1796 * This is a test signal. When the USB Core is
1797 * powered up (not in Susned Mode), an automatic
1798 * tester can use this to disable phy_clock and
1799 * free_clk, then re-eanable them with an aligned
1801 * '1': The phy_clk and free_clk outputs are
1802 * disabled. "0": The phy_clock and free_clk outputs
1803 * are available within a specific period after the
1806 struct cvmx_usbnx_usbp_ctl_status_s {
1807 __BITFIELD_FIELD(uint64_t txrisetune : 1,
1808 __BITFIELD_FIELD(uint64_t txvreftune : 4,
1809 __BITFIELD_FIELD(uint64_t txfslstune : 4,
1810 __BITFIELD_FIELD(uint64_t txhsxvtune : 2,
1811 __BITFIELD_FIELD(uint64_t sqrxtune : 3,
1812 __BITFIELD_FIELD(uint64_t compdistune : 3,
1813 __BITFIELD_FIELD(uint64_t otgtune : 3,
1814 __BITFIELD_FIELD(uint64_t otgdisable : 1,
1815 __BITFIELD_FIELD(uint64_t portreset : 1,
1816 __BITFIELD_FIELD(uint64_t drvvbus : 1,
1817 __BITFIELD_FIELD(uint64_t lsbist : 1,
1818 __BITFIELD_FIELD(uint64_t fsbist : 1,
1819 __BITFIELD_FIELD(uint64_t hsbist : 1,
1820 __BITFIELD_FIELD(uint64_t bist_done : 1,
1821 __BITFIELD_FIELD(uint64_t bist_err : 1,
1822 __BITFIELD_FIELD(uint64_t tdata_out : 4,
1823 __BITFIELD_FIELD(uint64_t siddq : 1,
1824 __BITFIELD_FIELD(uint64_t txpreemphasistune : 1,
1825 __BITFIELD_FIELD(uint64_t dma_bmode : 1,
1826 __BITFIELD_FIELD(uint64_t usbc_end : 1,
1827 __BITFIELD_FIELD(uint64_t usbp_bist : 1,
1828 __BITFIELD_FIELD(uint64_t tclk : 1,
1829 __BITFIELD_FIELD(uint64_t dp_pulld : 1,
1830 __BITFIELD_FIELD(uint64_t dm_pulld : 1,
1831 __BITFIELD_FIELD(uint64_t hst_mode : 1,
1832 __BITFIELD_FIELD(uint64_t tuning : 4,
1833 __BITFIELD_FIELD(uint64_t tx_bs_enh : 1,
1834 __BITFIELD_FIELD(uint64_t tx_bs_en : 1,
1835 __BITFIELD_FIELD(uint64_t loop_enb : 1,
1836 __BITFIELD_FIELD(uint64_t vtest_enb : 1,
1837 __BITFIELD_FIELD(uint64_t bist_enb : 1,
1838 __BITFIELD_FIELD(uint64_t tdata_sel : 1,
1839 __BITFIELD_FIELD(uint64_t taddr_in : 4,
1840 __BITFIELD_FIELD(uint64_t tdata_in : 8,
1841 __BITFIELD_FIELD(uint64_t ate_reset : 1,
1842 ;)))))))))))))))))))))))))))))))))))
1846 #endif /* __OCTEON_HCD_H__ */
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