2 * Copyright (c) 2003-2012 Broadcom Corporation
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 /* #define MAC_SPLIT_MODE */
36 #define MAC_SPACING 0x400
37 #define XGMAC_SPACING 0x400
39 /* PE-MCXMAC register and bit field definitions */
40 #define R_MAC_CONFIG_1 0x00
41 #define O_MAC_CONFIG_1__srst 31
42 #define O_MAC_CONFIG_1__simr 30
43 #define O_MAC_CONFIG_1__hrrmc 18
44 #define W_MAC_CONFIG_1__hrtmc 2
45 #define O_MAC_CONFIG_1__hrrfn 16
46 #define W_MAC_CONFIG_1__hrtfn 2
47 #define O_MAC_CONFIG_1__intlb 8
48 #define O_MAC_CONFIG_1__rxfc 5
49 #define O_MAC_CONFIG_1__txfc 4
50 #define O_MAC_CONFIG_1__srxen 3
51 #define O_MAC_CONFIG_1__rxen 2
52 #define O_MAC_CONFIG_1__stxen 1
53 #define O_MAC_CONFIG_1__txen 0
54 #define R_MAC_CONFIG_2 0x01
55 #define O_MAC_CONFIG_2__prlen 12
56 #define W_MAC_CONFIG_2__prlen 4
57 #define O_MAC_CONFIG_2__speed 8
58 #define W_MAC_CONFIG_2__speed 2
59 #define O_MAC_CONFIG_2__hugen 5
60 #define O_MAC_CONFIG_2__flchk 4
61 #define O_MAC_CONFIG_2__crce 1
62 #define O_MAC_CONFIG_2__fulld 0
63 #define R_IPG_IFG 0x02
64 #define O_IPG_IFG__ipgr1 24
65 #define W_IPG_IFG__ipgr1 7
66 #define O_IPG_IFG__ipgr2 16
67 #define W_IPG_IFG__ipgr2 7
68 #define O_IPG_IFG__mifg 8
69 #define W_IPG_IFG__mifg 8
70 #define O_IPG_IFG__ipgt 0
71 #define W_IPG_IFG__ipgt 7
72 #define R_HALF_DUPLEX 0x03
73 #define O_HALF_DUPLEX__abebt 24
74 #define W_HALF_DUPLEX__abebt 4
75 #define O_HALF_DUPLEX__abebe 19
76 #define O_HALF_DUPLEX__bpnb 18
77 #define O_HALF_DUPLEX__nobo 17
78 #define O_HALF_DUPLEX__edxsdfr 16
79 #define O_HALF_DUPLEX__retry 12
80 #define W_HALF_DUPLEX__retry 4
81 #define O_HALF_DUPLEX__lcol 0
82 #define W_HALF_DUPLEX__lcol 10
83 #define R_MAXIMUM_FRAME_LENGTH 0x04
84 #define O_MAXIMUM_FRAME_LENGTH__maxf 0
85 #define W_MAXIMUM_FRAME_LENGTH__maxf 16
87 #define O_TEST__mbof 3
88 #define O_TEST__rthdf 2
89 #define O_TEST__tpause 1
90 #define O_TEST__sstct 0
91 #define R_MII_MGMT_CONFIG 0x08
92 #define O_MII_MGMT_CONFIG__scinc 5
93 #define O_MII_MGMT_CONFIG__spre 4
94 #define O_MII_MGMT_CONFIG__clks 3
95 #define W_MII_MGMT_CONFIG__clks 3
96 #define R_MII_MGMT_COMMAND 0x09
97 #define O_MII_MGMT_COMMAND__scan 1
98 #define O_MII_MGMT_COMMAND__rstat 0
99 #define R_MII_MGMT_ADDRESS 0x0A
100 #define O_MII_MGMT_ADDRESS__fiad 8
101 #define W_MII_MGMT_ADDRESS__fiad 5
102 #define O_MII_MGMT_ADDRESS__fgad 5
103 #define W_MII_MGMT_ADDRESS__fgad 0
104 #define R_MII_MGMT_WRITE_DATA 0x0B
105 #define O_MII_MGMT_WRITE_DATA__ctld 0
106 #define W_MII_MGMT_WRITE_DATA__ctld 16
107 #define R_MII_MGMT_STATUS 0x0C
108 #define R_MII_MGMT_INDICATORS 0x0D
109 #define O_MII_MGMT_INDICATORS__nvalid 2
110 #define O_MII_MGMT_INDICATORS__scan 1
111 #define O_MII_MGMT_INDICATORS__busy 0
112 #define R_INTERFACE_CONTROL 0x0E
113 #define O_INTERFACE_CONTROL__hrstint 31
114 #define O_INTERFACE_CONTROL__tbimode 27
115 #define O_INTERFACE_CONTROL__ghdmode 26
116 #define O_INTERFACE_CONTROL__lhdmode 25
117 #define O_INTERFACE_CONTROL__phymod 24
118 #define O_INTERFACE_CONTROL__hrrmi 23
119 #define O_INTERFACE_CONTROL__rspd 16
120 #define O_INTERFACE_CONTROL__hr100 15
121 #define O_INTERFACE_CONTROL__frcq 10
122 #define O_INTERFACE_CONTROL__nocfr 9
123 #define O_INTERFACE_CONTROL__dlfct 8
124 #define O_INTERFACE_CONTROL__enjab 0
125 #define R_INTERFACE_STATUS 0x0F
126 #define O_INTERFACE_STATUS__xsdfr 9
127 #define O_INTERFACE_STATUS__ssrr 8
128 #define W_INTERFACE_STATUS__ssrr 5
129 #define O_INTERFACE_STATUS__miilf 3
130 #define O_INTERFACE_STATUS__locar 2
131 #define O_INTERFACE_STATUS__sqerr 1
132 #define O_INTERFACE_STATUS__jabber 0
133 #define R_STATION_ADDRESS_LS 0x10
134 #define R_STATION_ADDRESS_MS 0x11
136 /* A-XGMAC register and bit field definitions */
137 #define R_XGMAC_CONFIG_0 0x00
138 #define O_XGMAC_CONFIG_0__hstmacrst 31
139 #define O_XGMAC_CONFIG_0__hstrstrctl 23
140 #define O_XGMAC_CONFIG_0__hstrstrfn 22
141 #define O_XGMAC_CONFIG_0__hstrsttctl 18
142 #define O_XGMAC_CONFIG_0__hstrsttfn 17
143 #define O_XGMAC_CONFIG_0__hstrstmiim 16
144 #define O_XGMAC_CONFIG_0__hstloopback 8
145 #define R_XGMAC_CONFIG_1 0x01
146 #define O_XGMAC_CONFIG_1__hsttctlen 31
147 #define O_XGMAC_CONFIG_1__hsttfen 30
148 #define O_XGMAC_CONFIG_1__hstrctlen 29
149 #define O_XGMAC_CONFIG_1__hstrfen 28
150 #define O_XGMAC_CONFIG_1__tfen 26
151 #define O_XGMAC_CONFIG_1__rfen 24
152 #define O_XGMAC_CONFIG_1__hstrctlshrtp 12
153 #define O_XGMAC_CONFIG_1__hstdlyfcstx 10
154 #define W_XGMAC_CONFIG_1__hstdlyfcstx 2
155 #define O_XGMAC_CONFIG_1__hstdlyfcsrx 8
156 #define W_XGMAC_CONFIG_1__hstdlyfcsrx 2
157 #define O_XGMAC_CONFIG_1__hstppen 7
158 #define O_XGMAC_CONFIG_1__hstbytswp 6
159 #define O_XGMAC_CONFIG_1__hstdrplt64 5
160 #define O_XGMAC_CONFIG_1__hstprmscrx 4
161 #define O_XGMAC_CONFIG_1__hstlenchk 3
162 #define O_XGMAC_CONFIG_1__hstgenfcs 2
163 #define O_XGMAC_CONFIG_1__hstpadmode 0
164 #define W_XGMAC_CONFIG_1__hstpadmode 2
165 #define R_XGMAC_CONFIG_2 0x02
166 #define O_XGMAC_CONFIG_2__hsttctlfrcp 31
167 #define O_XGMAC_CONFIG_2__hstmlnkflth 27
168 #define O_XGMAC_CONFIG_2__hstalnkflth 26
169 #define O_XGMAC_CONFIG_2__rflnkflt 24
170 #define W_XGMAC_CONFIG_2__rflnkflt 2
171 #define O_XGMAC_CONFIG_2__hstipgextmod 16
172 #define W_XGMAC_CONFIG_2__hstipgextmod 5
173 #define O_XGMAC_CONFIG_2__hstrctlfrcp 15
174 #define O_XGMAC_CONFIG_2__hstipgexten 5
175 #define O_XGMAC_CONFIG_2__hstmipgext 0
176 #define W_XGMAC_CONFIG_2__hstmipgext 5
177 #define R_XGMAC_CONFIG_3 0x03
178 #define O_XGMAC_CONFIG_3__hstfltrfrm 31
179 #define W_XGMAC_CONFIG_3__hstfltrfrm 16
180 #define O_XGMAC_CONFIG_3__hstfltrfrmdc 15
181 #define W_XGMAC_CONFIG_3__hstfltrfrmdc 16
182 #define R_XGMAC_STATION_ADDRESS_LS 0x04
183 #define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0
184 #define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32
185 #define R_XGMAC_STATION_ADDRESS_MS 0x05
186 #define R_XGMAC_MAX_FRAME_LEN 0x08
187 #define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16
188 #define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14
189 #define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0
190 #define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16
191 #define R_XGMAC_REV_LEVEL 0x0B
192 #define O_XGMAC_REV_LEVEL__revlvl 0
193 #define W_XGMAC_REV_LEVEL__revlvl 15
194 #define R_XGMAC_MIIM_COMMAND 0x10
195 #define O_XGMAC_MIIM_COMMAND__hstldcmd 3
196 #define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0
197 #define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3
198 #define R_XGMAC_MIIM_FILED 0x11
199 #define O_XGMAC_MIIM_FILED__hststfield 30
200 #define W_XGMAC_MIIM_FILED__hststfield 2
201 #define O_XGMAC_MIIM_FILED__hstopfield 28
202 #define W_XGMAC_MIIM_FILED__hstopfield 2
203 #define O_XGMAC_MIIM_FILED__hstphyadx 23
204 #define W_XGMAC_MIIM_FILED__hstphyadx 5
205 #define O_XGMAC_MIIM_FILED__hstregadx 18
206 #define W_XGMAC_MIIM_FILED__hstregadx 5
207 #define O_XGMAC_MIIM_FILED__hsttafield 16
208 #define W_XGMAC_MIIM_FILED__hsttafield 2
209 #define O_XGMAC_MIIM_FILED__miimrddat 0
210 #define W_XGMAC_MIIM_FILED__miimrddat 16
211 #define R_XGMAC_MIIM_CONFIG 0x12
212 #define O_XGMAC_MIIM_CONFIG__hstnopram 7
213 #define O_XGMAC_MIIM_CONFIG__hstclkdiv 0
214 #define W_XGMAC_MIIM_CONFIG__hstclkdiv 7
215 #define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13
216 #define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0
217 #define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32
218 #define R_XGMAC_MIIM_INDICATOR 0x14
219 #define O_XGMAC_MIIM_INDICATOR__miimphylf 4
220 #define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3
221 #define O_XGMAC_MIIM_INDICATOR__miimmonvld 2
222 #define O_XGMAC_MIIM_INDICATOR__miimmon 1
223 #define O_XGMAC_MIIM_INDICATOR__miimbusy 0
225 /* GMAC stats registers */
259 /* Glue logic register and bit field definitions */
260 #define R_MAC_ADDR0 0x50
261 #define R_MAC_ADDR1 0x52
262 #define R_MAC_ADDR2 0x54
263 #define R_MAC_ADDR3 0x56
264 #define R_MAC_ADDR_MASK2 0x58
265 #define R_MAC_ADDR_MASK3 0x5A
266 #define R_MAC_FILTER_CONFIG 0x5C
267 #define O_MAC_FILTER_CONFIG__BROADCAST_EN 10
268 #define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9
269 #define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8
270 #define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7
271 #define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6
272 #define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5
273 #define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4
274 #define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3
275 #define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2
276 #define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1
277 #define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0
278 #define R_HASH_TABLE_VECTOR 0x30
279 #define R_TX_CONTROL 0x0A0
280 #define O_TX_CONTROL__Tx15Halt 31
281 #define O_TX_CONTROL__Tx14Halt 30
282 #define O_TX_CONTROL__Tx13Halt 29
283 #define O_TX_CONTROL__Tx12Halt 28
284 #define O_TX_CONTROL__Tx11Halt 27
285 #define O_TX_CONTROL__Tx10Halt 26
286 #define O_TX_CONTROL__Tx9Halt 25
287 #define O_TX_CONTROL__Tx8Halt 24
288 #define O_TX_CONTROL__Tx7Halt 23
289 #define O_TX_CONTROL__Tx6Halt 22
290 #define O_TX_CONTROL__Tx5Halt 21
291 #define O_TX_CONTROL__Tx4Halt 20
292 #define O_TX_CONTROL__Tx3Halt 19
293 #define O_TX_CONTROL__Tx2Halt 18
294 #define O_TX_CONTROL__Tx1Halt 17
295 #define O_TX_CONTROL__Tx0Halt 16
296 #define O_TX_CONTROL__TxIdle 15
297 #define O_TX_CONTROL__TxEnable 14
298 #define O_TX_CONTROL__TxThreshold 0
299 #define W_TX_CONTROL__TxThreshold 14
300 #define R_RX_CONTROL 0x0A1
301 #define O_RX_CONTROL__RGMII 10
302 #define O_RX_CONTROL__SoftReset 2
303 #define O_RX_CONTROL__RxHalt 1
304 #define O_RX_CONTROL__RxEnable 0
305 #define R_DESC_PACK_CTRL 0x0A2
306 #define O_DESC_PACK_CTRL__ByteOffset 17
307 #define W_DESC_PACK_CTRL__ByteOffset 3
308 #define O_DESC_PACK_CTRL__PrePadEnable 16
309 #define O_DESC_PACK_CTRL__MaxEntry 14
310 #define W_DESC_PACK_CTRL__MaxEntry 2
311 #define O_DESC_PACK_CTRL__RegularSize 0
312 #define W_DESC_PACK_CTRL__RegularSize 14
313 #define R_STATCTRL 0x0A3
314 #define O_STATCTRL__OverFlowEn 4
315 #define O_STATCTRL__GIG 3
316 #define O_STATCTRL__Sten 2
317 #define O_STATCTRL__ClrCnt 1
318 #define O_STATCTRL__AutoZ 0
319 #define R_L2ALLOCCTRL 0x0A4
320 #define O_L2ALLOCCTRL__TxL2Allocate 9
321 #define W_L2ALLOCCTRL__TxL2Allocate 9
322 #define O_L2ALLOCCTRL__RxL2Allocate 0
323 #define W_L2ALLOCCTRL__RxL2Allocate 9
324 #define R_INTMASK 0x0A5
325 #define O_INTMASK__Spi4TxError 28
326 #define O_INTMASK__Spi4RxError 27
327 #define O_INTMASK__RGMIIHalfDupCollision 27
328 #define O_INTMASK__Abort 26
329 #define O_INTMASK__Underrun 25
330 #define O_INTMASK__DiscardPacket 24
331 #define O_INTMASK__AsyncFifoFull 23
332 #define O_INTMASK__TagFull 22
333 #define O_INTMASK__Class3Full 21
334 #define O_INTMASK__C3EarlyFull 20
335 #define O_INTMASK__Class2Full 19
336 #define O_INTMASK__C2EarlyFull 18
337 #define O_INTMASK__Class1Full 17
338 #define O_INTMASK__C1EarlyFull 16
339 #define O_INTMASK__Class0Full 15
340 #define O_INTMASK__C0EarlyFull 14
341 #define O_INTMASK__RxDataFull 13
342 #define O_INTMASK__RxEarlyFull 12
343 #define O_INTMASK__RFreeEmpty 9
344 #define O_INTMASK__RFEarlyEmpty 8
345 #define O_INTMASK__P2PSpillEcc 7
346 #define O_INTMASK__FreeDescFull 5
347 #define O_INTMASK__FreeEarlyFull 4
348 #define O_INTMASK__TxFetchError 3
349 #define O_INTMASK__StatCarry 2
350 #define O_INTMASK__MDInt 1
351 #define O_INTMASK__TxIllegal 0
352 #define R_INTREG 0x0A6
353 #define O_INTREG__Spi4TxError 28
354 #define O_INTREG__Spi4RxError 27
355 #define O_INTREG__RGMIIHalfDupCollision 27
356 #define O_INTREG__Abort 26
357 #define O_INTREG__Underrun 25
358 #define O_INTREG__DiscardPacket 24
359 #define O_INTREG__AsyncFifoFull 23
360 #define O_INTREG__TagFull 22
361 #define O_INTREG__Class3Full 21
362 #define O_INTREG__C3EarlyFull 20
363 #define O_INTREG__Class2Full 19
364 #define O_INTREG__C2EarlyFull 18
365 #define O_INTREG__Class1Full 17
366 #define O_INTREG__C1EarlyFull 16
367 #define O_INTREG__Class0Full 15
368 #define O_INTREG__C0EarlyFull 14
369 #define O_INTREG__RxDataFull 13
370 #define O_INTREG__RxEarlyFull 12
371 #define O_INTREG__RFreeEmpty 9
372 #define O_INTREG__RFEarlyEmpty 8
373 #define O_INTREG__P2PSpillEcc 7
374 #define O_INTREG__FreeDescFull 5
375 #define O_INTREG__FreeEarlyFull 4
376 #define O_INTREG__TxFetchError 3
377 #define O_INTREG__StatCarry 2
378 #define O_INTREG__MDInt 1
379 #define O_INTREG__TxIllegal 0
380 #define R_TXRETRY 0x0A7
381 #define O_TXRETRY__CollisionRetry 6
382 #define O_TXRETRY__BusErrorRetry 5
383 #define O_TXRETRY__UnderRunRetry 4
384 #define O_TXRETRY__Retries 0
385 #define W_TXRETRY__Retries 4
386 #define R_CORECONTROL 0x0A8
387 #define O_CORECONTROL__ErrorThread 4
388 #define W_CORECONTROL__ErrorThread 7
389 #define O_CORECONTROL__Shutdown 2
390 #define O_CORECONTROL__Speed 0
391 #define W_CORECONTROL__Speed 2
392 #define R_BYTEOFFSET0 0x0A9
393 #define R_BYTEOFFSET1 0x0AA
394 #define R_L2TYPE_0 0x0F0
395 #define O_L2TYPE__ExtraHdrProtoSize 26
396 #define W_L2TYPE__ExtraHdrProtoSize 5
397 #define O_L2TYPE__ExtraHdrProtoOffset 20
398 #define W_L2TYPE__ExtraHdrProtoOffset 6
399 #define O_L2TYPE__ExtraHeaderSize 14
400 #define W_L2TYPE__ExtraHeaderSize 6
401 #define O_L2TYPE__ProtoOffset 8
402 #define W_L2TYPE__ProtoOffset 6
403 #define O_L2TYPE__L2HdrOffset 2
404 #define W_L2TYPE__L2HdrOffset 6
405 #define O_L2TYPE__L2Proto 0
406 #define W_L2TYPE__L2Proto 2
407 #define R_L2TYPE_1 0xF0
408 #define R_L2TYPE_2 0xF0
409 #define R_L2TYPE_3 0xF0
410 #define R_PARSERCONFIGREG 0x100
411 #define O_PARSERCONFIGREG__CRCHashPoly 8
412 #define W_PARSERCONFIGREG__CRCHashPoly 7
413 #define O_PARSERCONFIGREG__PrePadOffset 4
414 #define W_PARSERCONFIGREG__PrePadOffset 4
415 #define O_PARSERCONFIGREG__UseCAM 2
416 #define O_PARSERCONFIGREG__UseHASH 1
417 #define O_PARSERCONFIGREG__UseProto 0
418 #define R_L3CTABLE 0x140
419 #define O_L3CTABLE__Offset0 25
420 #define W_L3CTABLE__Offset0 7
421 #define O_L3CTABLE__Len0 21
422 #define W_L3CTABLE__Len0 4
423 #define O_L3CTABLE__Offset1 14
424 #define W_L3CTABLE__Offset1 7
425 #define O_L3CTABLE__Len1 10
426 #define W_L3CTABLE__Len1 4
427 #define O_L3CTABLE__Offset2 4
428 #define W_L3CTABLE__Offset2 6
429 #define O_L3CTABLE__Len2 0
430 #define W_L3CTABLE__Len2 4
431 #define O_L3CTABLE__L3HdrOffset 26
432 #define W_L3CTABLE__L3HdrOffset 6
433 #define O_L3CTABLE__L4ProtoOffset 20
434 #define W_L3CTABLE__L4ProtoOffset 6
435 #define O_L3CTABLE__IPChksumCompute 19
436 #define O_L3CTABLE__L4Classify 18
437 #define O_L3CTABLE__L2Proto 16
438 #define W_L3CTABLE__L2Proto 2
439 #define O_L3CTABLE__L3ProtoKey 0
440 #define W_L3CTABLE__L3ProtoKey 16
441 #define R_L4CTABLE 0x160
442 #define O_L4CTABLE__Offset0 21
443 #define W_L4CTABLE__Offset0 6
444 #define O_L4CTABLE__Len0 17
445 #define W_L4CTABLE__Len0 4
446 #define O_L4CTABLE__Offset1 11
447 #define W_L4CTABLE__Offset1 6
448 #define O_L4CTABLE__Len1 7
449 #define W_L4CTABLE__Len1 4
450 #define O_L4CTABLE__TCPChksumEnable 0
451 #define R_CAM4X128TABLE 0x172
452 #define O_CAM4X128TABLE__ClassId 7
453 #define W_CAM4X128TABLE__ClassId 2
454 #define O_CAM4X128TABLE__BucketId 1
455 #define W_CAM4X128TABLE__BucketId 6
456 #define O_CAM4X128TABLE__UseBucket 0
457 #define R_CAM4X128KEY 0x180
458 #define R_TRANSLATETABLE 0x1A0
459 #define R_DMACR0 0x200
460 #define O_DMACR0__Data0WrMaxCr 27
461 #define W_DMACR0__Data0WrMaxCr 3
462 #define O_DMACR0__Data0RdMaxCr 24
463 #define W_DMACR0__Data0RdMaxCr 3
464 #define O_DMACR0__Data1WrMaxCr 21
465 #define W_DMACR0__Data1WrMaxCr 3
466 #define O_DMACR0__Data1RdMaxCr 18
467 #define W_DMACR0__Data1RdMaxCr 3
468 #define O_DMACR0__Data2WrMaxCr 15
469 #define W_DMACR0__Data2WrMaxCr 3
470 #define O_DMACR0__Data2RdMaxCr 12
471 #define W_DMACR0__Data2RdMaxCr 3
472 #define O_DMACR0__Data3WrMaxCr 9
473 #define W_DMACR0__Data3WrMaxCr 3
474 #define O_DMACR0__Data3RdMaxCr 6
475 #define W_DMACR0__Data3RdMaxCr 3
476 #define O_DMACR0__Data4WrMaxCr 3
477 #define W_DMACR0__Data4WrMaxCr 3
478 #define O_DMACR0__Data4RdMaxCr 0
479 #define W_DMACR0__Data4RdMaxCr 3
480 #define R_DMACR1 0x201
481 #define O_DMACR1__Data5WrMaxCr 27
482 #define W_DMACR1__Data5WrMaxCr 3
483 #define O_DMACR1__Data5RdMaxCr 24
484 #define W_DMACR1__Data5RdMaxCr 3
485 #define O_DMACR1__Data6WrMaxCr 21
486 #define W_DMACR1__Data6WrMaxCr 3
487 #define O_DMACR1__Data6RdMaxCr 18
488 #define W_DMACR1__Data6RdMaxCr 3
489 #define O_DMACR1__Data7WrMaxCr 15
490 #define W_DMACR1__Data7WrMaxCr 3
491 #define O_DMACR1__Data7RdMaxCr 12
492 #define W_DMACR1__Data7RdMaxCr 3
493 #define O_DMACR1__Data8WrMaxCr 9
494 #define W_DMACR1__Data8WrMaxCr 3
495 #define O_DMACR1__Data8RdMaxCr 6
496 #define W_DMACR1__Data8RdMaxCr 3
497 #define O_DMACR1__Data9WrMaxCr 3
498 #define W_DMACR1__Data9WrMaxCr 3
499 #define O_DMACR1__Data9RdMaxCr 0
500 #define W_DMACR1__Data9RdMaxCr 3
501 #define R_DMACR2 0x202
502 #define O_DMACR2__Data10WrMaxCr 27
503 #define W_DMACR2__Data10WrMaxCr 3
504 #define O_DMACR2__Data10RdMaxCr 24
505 #define W_DMACR2__Data10RdMaxCr 3
506 #define O_DMACR2__Data11WrMaxCr 21
507 #define W_DMACR2__Data11WrMaxCr 3
508 #define O_DMACR2__Data11RdMaxCr 18
509 #define W_DMACR2__Data11RdMaxCr 3
510 #define O_DMACR2__Data12WrMaxCr 15
511 #define W_DMACR2__Data12WrMaxCr 3
512 #define O_DMACR2__Data12RdMaxCr 12
513 #define W_DMACR2__Data12RdMaxCr 3
514 #define O_DMACR2__Data13WrMaxCr 9
515 #define W_DMACR2__Data13WrMaxCr 3
516 #define O_DMACR2__Data13RdMaxCr 6
517 #define W_DMACR2__Data13RdMaxCr 3
518 #define O_DMACR2__Data14WrMaxCr 3
519 #define W_DMACR2__Data14WrMaxCr 3
520 #define O_DMACR2__Data14RdMaxCr 0
521 #define W_DMACR2__Data14RdMaxCr 3
522 #define R_DMACR3 0x203
523 #define O_DMACR3__Data15WrMaxCr 27
524 #define W_DMACR3__Data15WrMaxCr 3
525 #define O_DMACR3__Data15RdMaxCr 24
526 #define W_DMACR3__Data15RdMaxCr 3
527 #define O_DMACR3__SpClassWrMaxCr 21
528 #define W_DMACR3__SpClassWrMaxCr 3
529 #define O_DMACR3__SpClassRdMaxCr 18
530 #define W_DMACR3__SpClassRdMaxCr 3
531 #define O_DMACR3__JumFrInWrMaxCr 15
532 #define W_DMACR3__JumFrInWrMaxCr 3
533 #define O_DMACR3__JumFrInRdMaxCr 12
534 #define W_DMACR3__JumFrInRdMaxCr 3
535 #define O_DMACR3__RegFrInWrMaxCr 9
536 #define W_DMACR3__RegFrInWrMaxCr 3
537 #define O_DMACR3__RegFrInRdMaxCr 6
538 #define W_DMACR3__RegFrInRdMaxCr 3
539 #define O_DMACR3__FrOutWrMaxCr 3
540 #define W_DMACR3__FrOutWrMaxCr 3
541 #define O_DMACR3__FrOutRdMaxCr 0
542 #define W_DMACR3__FrOutRdMaxCr 3
543 #define R_REG_FRIN_SPILL_MEM_START_0 0x204
544 #define O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 0
545 #define W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 32
546 #define R_REG_FRIN_SPILL_MEM_START_1 0x205
547 #define O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 0
548 #define W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 3
549 #define R_REG_FRIN_SPILL_MEM_SIZE 0x206
550 #define O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 0
551 #define W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 32
552 #define R_FROUT_SPILL_MEM_START_0 0x207
553 #define O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 0
554 #define W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 32
555 #define R_FROUT_SPILL_MEM_START_1 0x208
556 #define O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 0
557 #define W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 3
558 #define R_FROUT_SPILL_MEM_SIZE 0x209
559 #define O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 0
560 #define W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 32
561 #define R_CLASS0_SPILL_MEM_START_0 0x20A
562 #define O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 0
563 #define W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 32
564 #define R_CLASS0_SPILL_MEM_START_1 0x20B
565 #define O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 0
566 #define W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 3
567 #define R_CLASS0_SPILL_MEM_SIZE 0x20C
568 #define O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 0
569 #define W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 32
570 #define R_JUMFRIN_SPILL_MEM_START_0 0x20D
571 #define O_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 0
572 #define W_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 32
573 #define R_JUMFRIN_SPILL_MEM_START_1 0x20E
574 #define O_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 0
575 #define W_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 3
576 #define R_JUMFRIN_SPILL_MEM_SIZE 0x20F
577 #define O_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 0
578 #define W_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 32
579 #define R_CLASS1_SPILL_MEM_START_0 0x210
580 #define O_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 0
581 #define W_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 32
582 #define R_CLASS1_SPILL_MEM_START_1 0x211
583 #define O_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 0
584 #define W_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 3
585 #define R_CLASS1_SPILL_MEM_SIZE 0x212
586 #define O_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 0
587 #define W_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 32
588 #define R_CLASS2_SPILL_MEM_START_0 0x213
589 #define O_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 0
590 #define W_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 32
591 #define R_CLASS2_SPILL_MEM_START_1 0x214
592 #define O_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 0
593 #define W_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 3
594 #define R_CLASS2_SPILL_MEM_SIZE 0x215
595 #define O_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 0
596 #define W_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 32
597 #define R_CLASS3_SPILL_MEM_START_0 0x216
598 #define O_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 0
599 #define W_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 32
600 #define R_CLASS3_SPILL_MEM_START_1 0x217
601 #define O_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 0
602 #define W_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 3
603 #define R_CLASS3_SPILL_MEM_SIZE 0x218
604 #define O_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 0
605 #define W_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 32
606 #define R_REG_FRIN1_SPILL_MEM_START_0 0x219
607 #define R_REG_FRIN1_SPILL_MEM_START_1 0x21a
608 #define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b
609 #define R_SPIHNGY0 0x219
610 #define O_SPIHNGY0__EG_HNGY_THRESH_0 24
611 #define W_SPIHNGY0__EG_HNGY_THRESH_0 7
612 #define O_SPIHNGY0__EG_HNGY_THRESH_1 16
613 #define W_SPIHNGY0__EG_HNGY_THRESH_1 7
614 #define O_SPIHNGY0__EG_HNGY_THRESH_2 8
615 #define W_SPIHNGY0__EG_HNGY_THRESH_2 7
616 #define O_SPIHNGY0__EG_HNGY_THRESH_3 0
617 #define W_SPIHNGY0__EG_HNGY_THRESH_3 7
618 #define R_SPIHNGY1 0x21A
619 #define O_SPIHNGY1__EG_HNGY_THRESH_4 24
620 #define W_SPIHNGY1__EG_HNGY_THRESH_4 7
621 #define O_SPIHNGY1__EG_HNGY_THRESH_5 16
622 #define W_SPIHNGY1__EG_HNGY_THRESH_5 7
623 #define O_SPIHNGY1__EG_HNGY_THRESH_6 8
624 #define W_SPIHNGY1__EG_HNGY_THRESH_6 7
625 #define O_SPIHNGY1__EG_HNGY_THRESH_7 0
626 #define W_SPIHNGY1__EG_HNGY_THRESH_7 7
627 #define R_SPIHNGY2 0x21B
628 #define O_SPIHNGY2__EG_HNGY_THRESH_8 24
629 #define W_SPIHNGY2__EG_HNGY_THRESH_8 7
630 #define O_SPIHNGY2__EG_HNGY_THRESH_9 16
631 #define W_SPIHNGY2__EG_HNGY_THRESH_9 7
632 #define O_SPIHNGY2__EG_HNGY_THRESH_10 8
633 #define W_SPIHNGY2__EG_HNGY_THRESH_10 7
634 #define O_SPIHNGY2__EG_HNGY_THRESH_11 0
635 #define W_SPIHNGY2__EG_HNGY_THRESH_11 7
636 #define R_SPIHNGY3 0x21C
637 #define O_SPIHNGY3__EG_HNGY_THRESH_12 24
638 #define W_SPIHNGY3__EG_HNGY_THRESH_12 7
639 #define O_SPIHNGY3__EG_HNGY_THRESH_13 16
640 #define W_SPIHNGY3__EG_HNGY_THRESH_13 7
641 #define O_SPIHNGY3__EG_HNGY_THRESH_14 8
642 #define W_SPIHNGY3__EG_HNGY_THRESH_14 7
643 #define O_SPIHNGY3__EG_HNGY_THRESH_15 0
644 #define W_SPIHNGY3__EG_HNGY_THRESH_15 7
645 #define R_SPISTRV0 0x21D
646 #define O_SPISTRV0__EG_STRV_THRESH_0 24
647 #define W_SPISTRV0__EG_STRV_THRESH_0 7
648 #define O_SPISTRV0__EG_STRV_THRESH_1 16
649 #define W_SPISTRV0__EG_STRV_THRESH_1 7
650 #define O_SPISTRV0__EG_STRV_THRESH_2 8
651 #define W_SPISTRV0__EG_STRV_THRESH_2 7
652 #define O_SPISTRV0__EG_STRV_THRESH_3 0
653 #define W_SPISTRV0__EG_STRV_THRESH_3 7
654 #define R_SPISTRV1 0x21E
655 #define O_SPISTRV1__EG_STRV_THRESH_4 24
656 #define W_SPISTRV1__EG_STRV_THRESH_4 7
657 #define O_SPISTRV1__EG_STRV_THRESH_5 16
658 #define W_SPISTRV1__EG_STRV_THRESH_5 7
659 #define O_SPISTRV1__EG_STRV_THRESH_6 8
660 #define W_SPISTRV1__EG_STRV_THRESH_6 7
661 #define O_SPISTRV1__EG_STRV_THRESH_7 0
662 #define W_SPISTRV1__EG_STRV_THRESH_7 7
663 #define R_SPISTRV2 0x21F
664 #define O_SPISTRV2__EG_STRV_THRESH_8 24
665 #define W_SPISTRV2__EG_STRV_THRESH_8 7
666 #define O_SPISTRV2__EG_STRV_THRESH_9 16
667 #define W_SPISTRV2__EG_STRV_THRESH_9 7
668 #define O_SPISTRV2__EG_STRV_THRESH_10 8
669 #define W_SPISTRV2__EG_STRV_THRESH_10 7
670 #define O_SPISTRV2__EG_STRV_THRESH_11 0
671 #define W_SPISTRV2__EG_STRV_THRESH_11 7
672 #define R_SPISTRV3 0x220
673 #define O_SPISTRV3__EG_STRV_THRESH_12 24
674 #define W_SPISTRV3__EG_STRV_THRESH_12 7
675 #define O_SPISTRV3__EG_STRV_THRESH_13 16
676 #define W_SPISTRV3__EG_STRV_THRESH_13 7
677 #define O_SPISTRV3__EG_STRV_THRESH_14 8
678 #define W_SPISTRV3__EG_STRV_THRESH_14 7
679 #define O_SPISTRV3__EG_STRV_THRESH_15 0
680 #define W_SPISTRV3__EG_STRV_THRESH_15 7
681 #define R_TXDATAFIFO0 0x221
682 #define O_TXDATAFIFO0__Tx0DataFifoStart 24
683 #define W_TXDATAFIFO0__Tx0DataFifoStart 7
684 #define O_TXDATAFIFO0__Tx0DataFifoSize 16
685 #define W_TXDATAFIFO0__Tx0DataFifoSize 7
686 #define O_TXDATAFIFO0__Tx1DataFifoStart 8
687 #define W_TXDATAFIFO0__Tx1DataFifoStart 7
688 #define O_TXDATAFIFO0__Tx1DataFifoSize 0
689 #define W_TXDATAFIFO0__Tx1DataFifoSize 7
690 #define R_TXDATAFIFO1 0x222
691 #define O_TXDATAFIFO1__Tx2DataFifoStart 24
692 #define W_TXDATAFIFO1__Tx2DataFifoStart 7
693 #define O_TXDATAFIFO1__Tx2DataFifoSize 16
694 #define W_TXDATAFIFO1__Tx2DataFifoSize 7
695 #define O_TXDATAFIFO1__Tx3DataFifoStart 8
696 #define W_TXDATAFIFO1__Tx3DataFifoStart 7
697 #define O_TXDATAFIFO1__Tx3DataFifoSize 0
698 #define W_TXDATAFIFO1__Tx3DataFifoSize 7
699 #define R_TXDATAFIFO2 0x223
700 #define O_TXDATAFIFO2__Tx4DataFifoStart 24
701 #define W_TXDATAFIFO2__Tx4DataFifoStart 7
702 #define O_TXDATAFIFO2__Tx4DataFifoSize 16
703 #define W_TXDATAFIFO2__Tx4DataFifoSize 7
704 #define O_TXDATAFIFO2__Tx5DataFifoStart 8
705 #define W_TXDATAFIFO2__Tx5DataFifoStart 7
706 #define O_TXDATAFIFO2__Tx5DataFifoSize 0
707 #define W_TXDATAFIFO2__Tx5DataFifoSize 7
708 #define R_TXDATAFIFO3 0x224
709 #define O_TXDATAFIFO3__Tx6DataFifoStart 24
710 #define W_TXDATAFIFO3__Tx6DataFifoStart 7
711 #define O_TXDATAFIFO3__Tx6DataFifoSize 16
712 #define W_TXDATAFIFO3__Tx6DataFifoSize 7
713 #define O_TXDATAFIFO3__Tx7DataFifoStart 8
714 #define W_TXDATAFIFO3__Tx7DataFifoStart 7
715 #define O_TXDATAFIFO3__Tx7DataFifoSize 0
716 #define W_TXDATAFIFO3__Tx7DataFifoSize 7
717 #define R_TXDATAFIFO4 0x225
718 #define O_TXDATAFIFO4__Tx8DataFifoStart 24
719 #define W_TXDATAFIFO4__Tx8DataFifoStart 7
720 #define O_TXDATAFIFO4__Tx8DataFifoSize 16
721 #define W_TXDATAFIFO4__Tx8DataFifoSize 7
722 #define O_TXDATAFIFO4__Tx9DataFifoStart 8
723 #define W_TXDATAFIFO4__Tx9DataFifoStart 7
724 #define O_TXDATAFIFO4__Tx9DataFifoSize 0
725 #define W_TXDATAFIFO4__Tx9DataFifoSize 7
726 #define R_TXDATAFIFO5 0x226
727 #define O_TXDATAFIFO5__Tx10DataFifoStart 24
728 #define W_TXDATAFIFO5__Tx10DataFifoStart 7
729 #define O_TXDATAFIFO5__Tx10DataFifoSize 16
730 #define W_TXDATAFIFO5__Tx10DataFifoSize 7
731 #define O_TXDATAFIFO5__Tx11DataFifoStart 8
732 #define W_TXDATAFIFO5__Tx11DataFifoStart 7
733 #define O_TXDATAFIFO5__Tx11DataFifoSize 0
734 #define W_TXDATAFIFO5__Tx11DataFifoSize 7
735 #define R_TXDATAFIFO6 0x227
736 #define O_TXDATAFIFO6__Tx12DataFifoStart 24
737 #define W_TXDATAFIFO6__Tx12DataFifoStart 7
738 #define O_TXDATAFIFO6__Tx12DataFifoSize 16
739 #define W_TXDATAFIFO6__Tx12DataFifoSize 7
740 #define O_TXDATAFIFO6__Tx13DataFifoStart 8
741 #define W_TXDATAFIFO6__Tx13DataFifoStart 7
742 #define O_TXDATAFIFO6__Tx13DataFifoSize 0
743 #define W_TXDATAFIFO6__Tx13DataFifoSize 7
744 #define R_TXDATAFIFO7 0x228
745 #define O_TXDATAFIFO7__Tx14DataFifoStart 24
746 #define W_TXDATAFIFO7__Tx14DataFifoStart 7
747 #define O_TXDATAFIFO7__Tx14DataFifoSize 16
748 #define W_TXDATAFIFO7__Tx14DataFifoSize 7
749 #define O_TXDATAFIFO7__Tx15DataFifoStart 8
750 #define W_TXDATAFIFO7__Tx15DataFifoStart 7
751 #define O_TXDATAFIFO7__Tx15DataFifoSize 0
752 #define W_TXDATAFIFO7__Tx15DataFifoSize 7
753 #define R_RXDATAFIFO0 0x229
754 #define O_RXDATAFIFO0__Rx0DataFifoStart 24
755 #define W_RXDATAFIFO0__Rx0DataFifoStart 7
756 #define O_RXDATAFIFO0__Rx0DataFifoSize 16
757 #define W_RXDATAFIFO0__Rx0DataFifoSize 7
758 #define O_RXDATAFIFO0__Rx1DataFifoStart 8
759 #define W_RXDATAFIFO0__Rx1DataFifoStart 7
760 #define O_RXDATAFIFO0__Rx1DataFifoSize 0
761 #define W_RXDATAFIFO0__Rx1DataFifoSize 7
762 #define R_RXDATAFIFO1 0x22A
763 #define O_RXDATAFIFO1__Rx2DataFifoStart 24
764 #define W_RXDATAFIFO1__Rx2DataFifoStart 7
765 #define O_RXDATAFIFO1__Rx2DataFifoSize 16
766 #define W_RXDATAFIFO1__Rx2DataFifoSize 7
767 #define O_RXDATAFIFO1__Rx3DataFifoStart 8
768 #define W_RXDATAFIFO1__Rx3DataFifoStart 7
769 #define O_RXDATAFIFO1__Rx3DataFifoSize 0
770 #define W_RXDATAFIFO1__Rx3DataFifoSize 7
771 #define R_RXDATAFIFO2 0x22B
772 #define O_RXDATAFIFO2__Rx4DataFifoStart 24
773 #define W_RXDATAFIFO2__Rx4DataFifoStart 7
774 #define O_RXDATAFIFO2__Rx4DataFifoSize 16
775 #define W_RXDATAFIFO2__Rx4DataFifoSize 7
776 #define O_RXDATAFIFO2__Rx5DataFifoStart 8
777 #define W_RXDATAFIFO2__Rx5DataFifoStart 7
778 #define O_RXDATAFIFO2__Rx5DataFifoSize 0
779 #define W_RXDATAFIFO2__Rx5DataFifoSize 7
780 #define R_RXDATAFIFO3 0x22C
781 #define O_RXDATAFIFO3__Rx6DataFifoStart 24
782 #define W_RXDATAFIFO3__Rx6DataFifoStart 7
783 #define O_RXDATAFIFO3__Rx6DataFifoSize 16
784 #define W_RXDATAFIFO3__Rx6DataFifoSize 7
785 #define O_RXDATAFIFO3__Rx7DataFifoStart 8
786 #define W_RXDATAFIFO3__Rx7DataFifoStart 7
787 #define O_RXDATAFIFO3__Rx7DataFifoSize 0
788 #define W_RXDATAFIFO3__Rx7DataFifoSize 7
789 #define R_RXDATAFIFO4 0x22D
790 #define O_RXDATAFIFO4__Rx8DataFifoStart 24
791 #define W_RXDATAFIFO4__Rx8DataFifoStart 7
792 #define O_RXDATAFIFO4__Rx8DataFifoSize 16
793 #define W_RXDATAFIFO4__Rx8DataFifoSize 7
794 #define O_RXDATAFIFO4__Rx9DataFifoStart 8
795 #define W_RXDATAFIFO4__Rx9DataFifoStart 7
796 #define O_RXDATAFIFO4__Rx9DataFifoSize 0
797 #define W_RXDATAFIFO4__Rx9DataFifoSize 7
798 #define R_RXDATAFIFO5 0x22E
799 #define O_RXDATAFIFO5__Rx10DataFifoStart 24
800 #define W_RXDATAFIFO5__Rx10DataFifoStart 7
801 #define O_RXDATAFIFO5__Rx10DataFifoSize 16
802 #define W_RXDATAFIFO5__Rx10DataFifoSize 7
803 #define O_RXDATAFIFO5__Rx11DataFifoStart 8
804 #define W_RXDATAFIFO5__Rx11DataFifoStart 7
805 #define O_RXDATAFIFO5__Rx11DataFifoSize 0
806 #define W_RXDATAFIFO5__Rx11DataFifoSize 7
807 #define R_RXDATAFIFO6 0x22F
808 #define O_RXDATAFIFO6__Rx12DataFifoStart 24
809 #define W_RXDATAFIFO6__Rx12DataFifoStart 7
810 #define O_RXDATAFIFO6__Rx12DataFifoSize 16
811 #define W_RXDATAFIFO6__Rx12DataFifoSize 7
812 #define O_RXDATAFIFO6__Rx13DataFifoStart 8
813 #define W_RXDATAFIFO6__Rx13DataFifoStart 7
814 #define O_RXDATAFIFO6__Rx13DataFifoSize 0
815 #define W_RXDATAFIFO6__Rx13DataFifoSize 7
816 #define R_RXDATAFIFO7 0x230
817 #define O_RXDATAFIFO7__Rx14DataFifoStart 24
818 #define W_RXDATAFIFO7__Rx14DataFifoStart 7
819 #define O_RXDATAFIFO7__Rx14DataFifoSize 16
820 #define W_RXDATAFIFO7__Rx14DataFifoSize 7
821 #define O_RXDATAFIFO7__Rx15DataFifoStart 8
822 #define W_RXDATAFIFO7__Rx15DataFifoStart 7
823 #define O_RXDATAFIFO7__Rx15DataFifoSize 0
824 #define W_RXDATAFIFO7__Rx15DataFifoSize 7
825 #define R_XGMACPADCALIBRATION 0x231
826 #define R_FREEQCARVE 0x233
827 #define R_SPI4STATICDELAY0 0x240
828 #define O_SPI4STATICDELAY0__DataLine7 28
829 #define W_SPI4STATICDELAY0__DataLine7 4
830 #define O_SPI4STATICDELAY0__DataLine6 24
831 #define W_SPI4STATICDELAY0__DataLine6 4
832 #define O_SPI4STATICDELAY0__DataLine5 20
833 #define W_SPI4STATICDELAY0__DataLine5 4
834 #define O_SPI4STATICDELAY0__DataLine4 16
835 #define W_SPI4STATICDELAY0__DataLine4 4
836 #define O_SPI4STATICDELAY0__DataLine3 12
837 #define W_SPI4STATICDELAY0__DataLine3 4
838 #define O_SPI4STATICDELAY0__DataLine2 8
839 #define W_SPI4STATICDELAY0__DataLine2 4
840 #define O_SPI4STATICDELAY0__DataLine1 4
841 #define W_SPI4STATICDELAY0__DataLine1 4
842 #define O_SPI4STATICDELAY0__DataLine0 0
843 #define W_SPI4STATICDELAY0__DataLine0 4
844 #define R_SPI4STATICDELAY1 0x241
845 #define O_SPI4STATICDELAY1__DataLine15 28
846 #define W_SPI4STATICDELAY1__DataLine15 4
847 #define O_SPI4STATICDELAY1__DataLine14 24
848 #define W_SPI4STATICDELAY1__DataLine14 4
849 #define O_SPI4STATICDELAY1__DataLine13 20
850 #define W_SPI4STATICDELAY1__DataLine13 4
851 #define O_SPI4STATICDELAY1__DataLine12 16
852 #define W_SPI4STATICDELAY1__DataLine12 4
853 #define O_SPI4STATICDELAY1__DataLine11 12
854 #define W_SPI4STATICDELAY1__DataLine11 4
855 #define O_SPI4STATICDELAY1__DataLine10 8
856 #define W_SPI4STATICDELAY1__DataLine10 4
857 #define O_SPI4STATICDELAY1__DataLine9 4
858 #define W_SPI4STATICDELAY1__DataLine9 4
859 #define O_SPI4STATICDELAY1__DataLine8 0
860 #define W_SPI4STATICDELAY1__DataLine8 4
861 #define R_SPI4STATICDELAY2 0x242
862 #define O_SPI4STATICDELAY0__TxStat1 8
863 #define W_SPI4STATICDELAY0__TxStat1 4
864 #define O_SPI4STATICDELAY0__TxStat0 4
865 #define W_SPI4STATICDELAY0__TxStat0 4
866 #define O_SPI4STATICDELAY0__RxControl 0
867 #define W_SPI4STATICDELAY0__RxControl 4
868 #define R_SPI4CONTROL 0x243
869 #define O_SPI4CONTROL__StaticDelay 2
870 #define O_SPI4CONTROL__LVDS_LVTTL 1
871 #define O_SPI4CONTROL__SPI4Enable 0
872 #define R_CLASSWATERMARKS 0x244
873 #define O_CLASSWATERMARKS__Class0Watermark 24
874 #define W_CLASSWATERMARKS__Class0Watermark 5
875 #define O_CLASSWATERMARKS__Class1Watermark 16
876 #define W_CLASSWATERMARKS__Class1Watermark 5
877 #define O_CLASSWATERMARKS__Class3Watermark 0
878 #define W_CLASSWATERMARKS__Class3Watermark 5
879 #define R_RXWATERMARKS1 0x245
880 #define O_RXWATERMARKS__Rx0DataWatermark 24
881 #define W_RXWATERMARKS__Rx0DataWatermark 7
882 #define O_RXWATERMARKS__Rx1DataWatermark 16
883 #define W_RXWATERMARKS__Rx1DataWatermark 7
884 #define O_RXWATERMARKS__Rx3DataWatermark 0
885 #define W_RXWATERMARKS__Rx3DataWatermark 7
886 #define R_RXWATERMARKS2 0x246
887 #define O_RXWATERMARKS__Rx4DataWatermark 24
888 #define W_RXWATERMARKS__Rx4DataWatermark 7
889 #define O_RXWATERMARKS__Rx5DataWatermark 16
890 #define W_RXWATERMARKS__Rx5DataWatermark 7
891 #define O_RXWATERMARKS__Rx6DataWatermark 8
892 #define W_RXWATERMARKS__Rx6DataWatermark 7
893 #define O_RXWATERMARKS__Rx7DataWatermark 0
894 #define W_RXWATERMARKS__Rx7DataWatermark 7
895 #define R_RXWATERMARKS3 0x247
896 #define O_RXWATERMARKS__Rx8DataWatermark 24
897 #define W_RXWATERMARKS__Rx8DataWatermark 7
898 #define O_RXWATERMARKS__Rx9DataWatermark 16
899 #define W_RXWATERMARKS__Rx9DataWatermark 7
900 #define O_RXWATERMARKS__Rx10DataWatermark 8
901 #define W_RXWATERMARKS__Rx10DataWatermark 7
902 #define O_RXWATERMARKS__Rx11DataWatermark 0
903 #define W_RXWATERMARKS__Rx11DataWatermark 7
904 #define R_RXWATERMARKS4 0x248
905 #define O_RXWATERMARKS__Rx12DataWatermark 24
906 #define W_RXWATERMARKS__Rx12DataWatermark 7
907 #define O_RXWATERMARKS__Rx13DataWatermark 16
908 #define W_RXWATERMARKS__Rx13DataWatermark 7
909 #define O_RXWATERMARKS__Rx14DataWatermark 8
910 #define W_RXWATERMARKS__Rx14DataWatermark 7
911 #define O_RXWATERMARKS__Rx15DataWatermark 0
912 #define W_RXWATERMARKS__Rx15DataWatermark 7
913 #define R_FREEWATERMARKS 0x249
914 #define O_FREEWATERMARKS__FreeOutWatermark 16
915 #define W_FREEWATERMARKS__FreeOutWatermark 16
916 #define O_FREEWATERMARKS__JumFrWatermark 8
917 #define W_FREEWATERMARKS__JumFrWatermark 7
918 #define O_FREEWATERMARKS__RegFrWatermark 0
919 #define W_FREEWATERMARKS__RegFrWatermark 7
920 #define R_EGRESSFIFOCARVINGSLOTS 0x24a
924 #define CTRL_REG_FREE 2
925 #define CTRL_JUMBO_FREE 3
931 #define CTRL_B0_NOT_EOP 0
932 #define CTRL_B0_EOP 1
934 #define R_ROUND_ROBIN_TABLE 0
935 #define R_PDE_CLASS_0 0x300
936 #define R_PDE_CLASS_1 0x302
937 #define R_PDE_CLASS_2 0x304
938 #define R_PDE_CLASS_3 0x306
940 #define R_MSG_TX_THRESHOLD 0x308
942 #define R_GMAC_JFR0_BUCKET_SIZE 0x320
943 #define R_GMAC_RFR0_BUCKET_SIZE 0x321
944 #define R_GMAC_TX0_BUCKET_SIZE 0x322
945 #define R_GMAC_TX1_BUCKET_SIZE 0x323
946 #define R_GMAC_TX2_BUCKET_SIZE 0x324
947 #define R_GMAC_TX3_BUCKET_SIZE 0x325
948 #define R_GMAC_JFR1_BUCKET_SIZE 0x326
949 #define R_GMAC_RFR1_BUCKET_SIZE 0x327
951 #define R_XGS_TX0_BUCKET_SIZE 0x320
952 #define R_XGS_TX1_BUCKET_SIZE 0x321
953 #define R_XGS_TX2_BUCKET_SIZE 0x322
954 #define R_XGS_TX3_BUCKET_SIZE 0x323
955 #define R_XGS_TX4_BUCKET_SIZE 0x324
956 #define R_XGS_TX5_BUCKET_SIZE 0x325
957 #define R_XGS_TX6_BUCKET_SIZE 0x326
958 #define R_XGS_TX7_BUCKET_SIZE 0x327
959 #define R_XGS_TX8_BUCKET_SIZE 0x328
960 #define R_XGS_TX9_BUCKET_SIZE 0x329
961 #define R_XGS_TX10_BUCKET_SIZE 0x32A
962 #define R_XGS_TX11_BUCKET_SIZE 0x32B
963 #define R_XGS_TX12_BUCKET_SIZE 0x32C
964 #define R_XGS_TX13_BUCKET_SIZE 0x32D
965 #define R_XGS_TX14_BUCKET_SIZE 0x32E
966 #define R_XGS_TX15_BUCKET_SIZE 0x32F
967 #define R_XGS_JFR_BUCKET_SIZE 0x330
968 #define R_XGS_RFR_BUCKET_SIZE 0x331
970 #define R_CC_CPU0_0 0x380
971 #define R_CC_CPU1_0 0x388
972 #define R_CC_CPU2_0 0x390
973 #define R_CC_CPU3_0 0x398
974 #define R_CC_CPU4_0 0x3a0
975 #define R_CC_CPU5_0 0x3a8
976 #define R_CC_CPU6_0 0x3b0
977 #define R_CC_CPU7_0 0x3b8
979 #define XLR_GMAC_BLK_SZ (XLR_IO_GMAC_1_OFFSET - \
980 XLR_IO_GMAC_0_OFFSET)
982 /* Constants used for configuring the devices */
984 #define XLR_FB_STN 6 /* Bucket used for Tx freeback */
986 #define MAC_B2B_IPG 88
988 #define XLR_NET_PREPAD_LEN 32
990 /* frame sizes need to be cacheline aligned */
991 #define MAX_FRAME_SIZE (1536 + XLR_NET_PREPAD_LEN)
992 #define MAX_FRAME_SIZE_JUMBO 9216
994 #define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
996 #define BYTE_OFFSET 2
997 #define XLR_RX_BUF_SIZE (MAX_FRAME_SIZE + BYTE_OFFSET + \
998 MAC_PREPAD + MAC_SKB_BACK_PTR_SIZE + SMP_CACHE_BYTES)
999 #define MAC_CRC_LEN 4
1000 #define MAX_NUM_MSGRNG_STN_CC 128
1001 #define MAX_MSG_SND_ATTEMPTS 100 /* 13 stns x 4 entry msg/stn +
1004 #define MAC_FRIN_TO_BE_SENT_THRESHOLD 16
1006 #define MAX_NUM_DESC_SPILL 1024
1007 #define MAX_FRIN_SPILL (MAX_NUM_DESC_SPILL << 2)
1008 #define MAX_FROUT_SPILL (MAX_NUM_DESC_SPILL << 2)
1009 #define MAX_CLASS_0_SPILL (MAX_NUM_DESC_SPILL << 2)
1010 #define MAX_CLASS_1_SPILL (MAX_NUM_DESC_SPILL << 2)
1011 #define MAX_CLASS_2_SPILL (MAX_NUM_DESC_SPILL << 2)
1012 #define MAX_CLASS_3_SPILL (MAX_NUM_DESC_SPILL << 2)
1015 SGMII_SPEED_10 = 0x00000000,
1016 SGMII_SPEED_100 = 0x02000000,
1017 SGMII_SPEED_1000 = 0x04000000,
1021 TX_RX_64_BYTE_FRAME = 0x20,
1022 TX_RX_64_127_BYTE_FRAME,
1023 TX_RX_128_255_BYTE_FRAME,
1024 TX_RX_256_511_BYTE_FRAME,
1025 TX_RX_512_1023_BYTE_FRAME,
1026 TX_RX_1024_1518_BYTE_FRAME,
1027 TX_RX_1519_1522_VLAN_BYTE_FRAME,
1029 RX_BYTE_COUNTER = 0x27,
1031 RX_FCS_ERROR_COUNTER,
1032 RX_MULTICAST_PACKET_COUNTER,
1033 RX_BROADCAST_PACKET_COUNTER,
1034 RX_CONTROL_FRAME_PACKET_COUNTER,
1035 RX_PAUSE_FRAME_PACKET_COUNTER,
1036 RX_UNKNOWN_OP_CODE_COUNTER,
1037 RX_ALIGNMENT_ERROR_COUNTER,
1038 RX_FRAME_LENGTH_ERROR_COUNTER,
1039 RX_CODE_ERROR_COUNTER,
1040 RX_CARRIER_SENSE_ERROR_COUNTER,
1041 RX_UNDERSIZE_PACKET_COUNTER,
1042 RX_OVERSIZE_PACKET_COUNTER,
1043 RX_FRAGMENTS_COUNTER,
1045 RX_DROP_PACKET_COUNTER,
1047 TX_BYTE_COUNTER = 0x38,
1049 TX_MULTICAST_PACKET_COUNTER,
1050 TX_BROADCAST_PACKET_COUNTER,
1051 TX_PAUSE_CONTROL_FRAME_COUNTER,
1052 TX_DEFERRAL_PACKET_COUNTER,
1053 TX_EXCESSIVE_DEFERRAL_PACKET_COUNTER,
1054 TX_SINGLE_COLLISION_PACKET_COUNTER,
1055 TX_MULTI_COLLISION_PACKET_COUNTER,
1056 TX_LATE_COLLISION_PACKET_COUNTER,
1057 TX_EXCESSIVE_COLLISION_PACKET_COUNTER,
1058 TX_TOTAL_COLLISION_COUNTER,
1059 TX_PAUSE_FRAME_HONERED_COUNTER,
1060 TX_DROP_FRAME_COUNTER,
1061 TX_JABBER_FRAME_COUNTER,
1062 TX_FCS_ERROR_COUNTER,
1063 TX_CONTROL_FRAME_COUNTER,
1064 TX_OVERSIZE_FRAME_COUNTER,
1065 TX_UNDERSIZE_FRAME_COUNTER,
1066 TX_FRAGMENT_FRAME_COUNTER,
1072 struct xlr_adapter {
1073 struct net_device *netdev[4];
1076 struct xlr_net_priv {
1077 u32 __iomem *base_addr;
1078 struct net_device *ndev;
1079 struct xlr_adapter *adapter;
1080 struct mii_bus *mii_bus;
1082 int phy_addr; /* PHY addr on MDIO bus */
1083 int pcs_id; /* PCS id on MDIO bus */
1084 int port_id; /* Port(gmac/xgmac) number, i.e 0-7 */
1086 u32 __iomem *mii_addr;
1087 u32 __iomem *serdes_addr;
1088 u32 __iomem *pcs_addr;
1089 u32 __iomem *gpio_addr;
1092 struct timer_list queue_timer;
1094 struct platform_device *pdev;
1095 struct xlr_net_data *nd;
1105 extern void xlr_set_gmac_speed(struct xlr_net_priv *priv);
Code Review / kvmfornfv.git / blob