kernel/drivers/staging/media/omap4iss/iss_csi2.c

   1 /*
   2  * TI OMAP4 ISS V4L2 Driver - CSI PHY module
   3  *
   4  * Copyright (C) 2012 Texas Instruments, Inc.
   5  *
   6  * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <media/v4l2-common.h>
  16 #include <linux/v4l2-mediabus.h>
  17 #include <linux/mm.h>
  18
  19 #include "iss.h"
  20 #include "iss_regs.h"
  21 #include "iss_csi2.h"
  22
  23 /*
  24  * csi2_if_enable - Enable CSI2 Receiver interface.
  25  * @enable: enable flag
  26  *
  27  */
  28 static void csi2_if_enable(struct iss_csi2_device *csi2, u8 enable)
  29 {
  30         struct iss_csi2_ctrl_cfg *currctrl = &csi2->ctrl;
  31
  32         iss_reg_update(csi2->iss, csi2->regs1, CSI2_CTRL, CSI2_CTRL_IF_EN,
  33                        enable ? CSI2_CTRL_IF_EN : 0);
  34
  35         currctrl->if_enable = enable;
  36 }
  37
  38 /*
  39  * csi2_recv_config - CSI2 receiver module configuration.
  40  * @currctrl: iss_csi2_ctrl_cfg structure
  41  *
  42  */
  43 static void csi2_recv_config(struct iss_csi2_device *csi2,
  44                              struct iss_csi2_ctrl_cfg *currctrl)
  45 {
  46         u32 reg = 0;
  47
  48         if (currctrl->frame_mode)
  49                 reg |= CSI2_CTRL_FRAME;
  50         else
  51                 reg &= ~CSI2_CTRL_FRAME;
  52
  53         if (currctrl->vp_clk_enable)
  54                 reg |= CSI2_CTRL_VP_CLK_EN;
  55         else
  56                 reg &= ~CSI2_CTRL_VP_CLK_EN;
  57
  58         if (currctrl->vp_only_enable)
  59                 reg |= CSI2_CTRL_VP_ONLY_EN;
  60         else
  61                 reg &= ~CSI2_CTRL_VP_ONLY_EN;
  62
  63         reg &= ~CSI2_CTRL_VP_OUT_CTRL_MASK;
  64         reg |= currctrl->vp_out_ctrl << CSI2_CTRL_VP_OUT_CTRL_SHIFT;
  65
  66         if (currctrl->ecc_enable)
  67                 reg |= CSI2_CTRL_ECC_EN;
  68         else
  69                 reg &= ~CSI2_CTRL_ECC_EN;
  70
  71         /*
  72          * Set MFlag assertion boundaries to:
  73          * Low: 4/8 of FIFO size
  74          * High: 6/8 of FIFO size
  75          */
  76         reg &= ~(CSI2_CTRL_MFLAG_LEVH_MASK | CSI2_CTRL_MFLAG_LEVL_MASK);
  77         reg |= (2 << CSI2_CTRL_MFLAG_LEVH_SHIFT) |
  78                (4 << CSI2_CTRL_MFLAG_LEVL_SHIFT);
  79
  80         /* Generation of 16x64-bit bursts (Recommended) */
  81         reg |= CSI2_CTRL_BURST_SIZE_EXPAND;
  82
  83         /* Do Non-Posted writes (Recommended) */
  84         reg |= CSI2_CTRL_NON_POSTED_WRITE;
  85
  86         /*
  87          * Enforce Little endian for all formats, including:
  88          * YUV4:2:2 8-bit and YUV4:2:0 Legacy
  89          */
  90         reg |= CSI2_CTRL_ENDIANNESS;
  91
  92         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTRL, reg);
  93 }
  94
  95 static const unsigned int csi2_input_fmts[] = {
  96         MEDIA_BUS_FMT_SGRBG10_1X10,
  97         MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
  98         MEDIA_BUS_FMT_SRGGB10_1X10,
  99         MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8,
 100         MEDIA_BUS_FMT_SBGGR10_1X10,
 101         MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8,
 102         MEDIA_BUS_FMT_SGBRG10_1X10,
 103         MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8,
 104         MEDIA_BUS_FMT_SBGGR8_1X8,
 105         MEDIA_BUS_FMT_SGBRG8_1X8,
 106         MEDIA_BUS_FMT_SGRBG8_1X8,
 107         MEDIA_BUS_FMT_SRGGB8_1X8,
 108         MEDIA_BUS_FMT_UYVY8_1X16,
 109         MEDIA_BUS_FMT_YUYV8_1X16,
 110 };
 111
 112 /* To set the format on the CSI2 requires a mapping function that takes
 113  * the following inputs:
 114  * - 3 different formats (at this time)
 115  * - 2 destinations (mem, vp+mem) (vp only handled separately)
 116  * - 2 decompression options (on, off)
 117  * Output should be CSI2 frame format code
 118  * Array indices as follows: [format][dest][decompr]
 119  * Not all combinations are valid. 0 means invalid.
 120  */
 121 static const u16 __csi2_fmt_map[][2][2] = {
 122         /* RAW10 formats */
 123         {
 124                 /* Output to memory */
 125                 {
 126                         /* No DPCM decompression */
 127                         CSI2_PIX_FMT_RAW10_EXP16,
 128                         /* DPCM decompression */
 129                         0,
 130                 },
 131                 /* Output to both */
 132                 {
 133                         /* No DPCM decompression */
 134                         CSI2_PIX_FMT_RAW10_EXP16_VP,
 135                         /* DPCM decompression */
 136                         0,
 137                 },
 138         },
 139         /* RAW10 DPCM8 formats */
 140         {
 141                 /* Output to memory */
 142                 {
 143                         /* No DPCM decompression */
 144                         CSI2_USERDEF_8BIT_DATA1,
 145                         /* DPCM decompression */
 146                         CSI2_USERDEF_8BIT_DATA1_DPCM10,
 147                 },
 148                 /* Output to both */
 149                 {
 150                         /* No DPCM decompression */
 151                         CSI2_PIX_FMT_RAW8_VP,
 152                         /* DPCM decompression */
 153                         CSI2_USERDEF_8BIT_DATA1_DPCM10_VP,
 154                 },
 155         },
 156         /* RAW8 formats */
 157         {
 158                 /* Output to memory */
 159                 {
 160                         /* No DPCM decompression */
 161                         CSI2_PIX_FMT_RAW8,
 162                         /* DPCM decompression */
 163                         0,
 164                 },
 165                 /* Output to both */
 166                 {
 167                         /* No DPCM decompression */
 168                         CSI2_PIX_FMT_RAW8_VP,
 169                         /* DPCM decompression */
 170                         0,
 171                 },
 172         },
 173         /* YUV422 formats */
 174         {
 175                 /* Output to memory */
 176                 {
 177                         /* No DPCM decompression */
 178                         CSI2_PIX_FMT_YUV422_8BIT,
 179                         /* DPCM decompression */
 180                         0,
 181                 },
 182                 /* Output to both */
 183                 {
 184                         /* No DPCM decompression */
 185                         CSI2_PIX_FMT_YUV422_8BIT_VP16,
 186                         /* DPCM decompression */
 187                         0,
 188                 },
 189         },
 190 };
 191
 192 /*
 193  * csi2_ctx_map_format - Map CSI2 sink media bus format to CSI2 format ID
 194  * @csi2: ISS CSI2 device
 195  *
 196  * Returns CSI2 physical format id
 197  */
 198 static u16 csi2_ctx_map_format(struct iss_csi2_device *csi2)
 199 {
 200         const struct v4l2_mbus_framefmt *fmt = &csi2->formats[CSI2_PAD_SINK];
 201         int fmtidx, destidx;
 202
 203         switch (fmt->code) {
 204         case MEDIA_BUS_FMT_SGRBG10_1X10:
 205         case MEDIA_BUS_FMT_SRGGB10_1X10:
 206         case MEDIA_BUS_FMT_SBGGR10_1X10:
 207         case MEDIA_BUS_FMT_SGBRG10_1X10:
 208                 fmtidx = 0;
 209                 break;
 210         case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
 211         case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
 212         case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
 213         case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
 214                 fmtidx = 1;
 215                 break;
 216         case MEDIA_BUS_FMT_SBGGR8_1X8:
 217         case MEDIA_BUS_FMT_SGBRG8_1X8:
 218         case MEDIA_BUS_FMT_SGRBG8_1X8:
 219         case MEDIA_BUS_FMT_SRGGB8_1X8:
 220                 fmtidx = 2;
 221                 break;
 222         case MEDIA_BUS_FMT_UYVY8_1X16:
 223         case MEDIA_BUS_FMT_YUYV8_1X16:
 224                 fmtidx = 3;
 225                 break;
 226         default:
 227                 WARN(1, KERN_ERR "CSI2: pixel format %08x unsupported!\n",
 228                      fmt->code);
 229                 return 0;
 230         }
 231
 232         if (!(csi2->output & CSI2_OUTPUT_IPIPEIF) &&
 233             !(csi2->output & CSI2_OUTPUT_MEMORY)) {
 234                 /* Neither output enabled is a valid combination */
 235                 return CSI2_PIX_FMT_OTHERS;
 236         }
 237
 238         /* If we need to skip frames at the beginning of the stream disable the
 239          * video port to avoid sending the skipped frames to the IPIPEIF.
 240          */
 241         destidx = csi2->frame_skip ? 0 : !!(csi2->output & CSI2_OUTPUT_IPIPEIF);
 242
 243         return __csi2_fmt_map[fmtidx][destidx][csi2->dpcm_decompress];
 244 }
 245
 246 /*
 247  * csi2_set_outaddr - Set memory address to save output image
 248  * @csi2: Pointer to ISS CSI2a device.
 249  * @addr: 32-bit memory address aligned on 32 byte boundary.
 250  *
 251  * Sets the memory address where the output will be saved.
 252  *
 253  * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
 254  * boundary.
 255  */
 256 static void csi2_set_outaddr(struct iss_csi2_device *csi2, u32 addr)
 257 {
 258         struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[0];
 259
 260         ctx->ping_addr = addr;
 261         ctx->pong_addr = addr;
 262         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PING_ADDR(ctx->ctxnum),
 263                       ctx->ping_addr);
 264         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PONG_ADDR(ctx->ctxnum),
 265                       ctx->pong_addr);
 266 }
 267
 268 /*
 269  * is_usr_def_mapping - Checks whether USER_DEF_MAPPING should
 270  *                      be enabled by CSI2.
 271  * @format_id: mapped format id
 272  *
 273  */
 274 static inline int is_usr_def_mapping(u32 format_id)
 275 {
 276         return (format_id & 0xf0) == 0x40 ? 1 : 0;
 277 }
 278
 279 /*
 280  * csi2_ctx_enable - Enable specified CSI2 context
 281  * @ctxnum: Context number, valid between 0 and 7 values.
 282  * @enable: enable
 283  *
 284  */
 285 static void csi2_ctx_enable(struct iss_csi2_device *csi2, u8 ctxnum, u8 enable)
 286 {
 287         struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum];
 288         u32 reg;
 289
 290         reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum));
 291
 292         if (enable) {
 293                 unsigned int skip = 0;
 294
 295                 if (csi2->frame_skip)
 296                         skip = csi2->frame_skip;
 297                 else if (csi2->output & CSI2_OUTPUT_MEMORY)
 298                         skip = 1;
 299
 300                 reg &= ~CSI2_CTX_CTRL1_COUNT_MASK;
 301                 reg |= CSI2_CTX_CTRL1_COUNT_UNLOCK
 302                     |  (skip << CSI2_CTX_CTRL1_COUNT_SHIFT)
 303                     |  CSI2_CTX_CTRL1_CTX_EN;
 304         } else {
 305                 reg &= ~CSI2_CTX_CTRL1_CTX_EN;
 306         }
 307
 308         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum), reg);
 309         ctx->enabled = enable;
 310 }
 311
 312 /*
 313  * csi2_ctx_config - CSI2 context configuration.
 314  * @ctx: context configuration
 315  *
 316  */
 317 static void csi2_ctx_config(struct iss_csi2_device *csi2,
 318                             struct iss_csi2_ctx_cfg *ctx)
 319 {
 320         u32 reg = 0;
 321
 322         ctx->frame = 0;
 323
 324         /* Set up CSI2_CTx_CTRL1 */
 325         if (ctx->eof_enabled)
 326                 reg = CSI2_CTX_CTRL1_EOF_EN;
 327
 328         if (ctx->eol_enabled)
 329                 reg |= CSI2_CTX_CTRL1_EOL_EN;
 330
 331         if (ctx->checksum_enabled)
 332                 reg |= CSI2_CTX_CTRL1_CS_EN;
 333
 334         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctx->ctxnum), reg);
 335
 336         /* Set up CSI2_CTx_CTRL2 */
 337         reg = ctx->virtual_id << CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
 338         reg |= ctx->format_id << CSI2_CTX_CTRL2_FORMAT_SHIFT;
 339
 340         if (ctx->dpcm_decompress && ctx->dpcm_predictor)
 341                 reg |= CSI2_CTX_CTRL2_DPCM_PRED;
 342
 343         if (is_usr_def_mapping(ctx->format_id))
 344                 reg |= 2 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
 345
 346         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL2(ctx->ctxnum), reg);
 347
 348         /* Set up CSI2_CTx_CTRL3 */
 349         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL3(ctx->ctxnum),
 350                       ctx->alpha << CSI2_CTX_CTRL3_ALPHA_SHIFT);
 351
 352         /* Set up CSI2_CTx_DAT_OFST */
 353         iss_reg_update(csi2->iss, csi2->regs1, CSI2_CTX_DAT_OFST(ctx->ctxnum),
 354                        CSI2_CTX_DAT_OFST_MASK, ctx->data_offset);
 355
 356         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PING_ADDR(ctx->ctxnum),
 357                       ctx->ping_addr);
 358         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PONG_ADDR(ctx->ctxnum),
 359                       ctx->pong_addr);
 360 }
 361
 362 /*
 363  * csi2_timing_config - CSI2 timing configuration.
 364  * @timing: csi2_timing_cfg structure
 365  */
 366 static void csi2_timing_config(struct iss_csi2_device *csi2,
 367                                struct iss_csi2_timing_cfg *timing)
 368 {
 369         u32 reg;
 370
 371         reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_TIMING);
 372
 373         if (timing->force_rx_mode)
 374                 reg |= CSI2_TIMING_FORCE_RX_MODE_IO1;
 375         else
 376                 reg &= ~CSI2_TIMING_FORCE_RX_MODE_IO1;
 377
 378         if (timing->stop_state_16x)
 379                 reg |= CSI2_TIMING_STOP_STATE_X16_IO1;
 380         else
 381                 reg &= ~CSI2_TIMING_STOP_STATE_X16_IO1;
 382
 383         if (timing->stop_state_4x)
 384                 reg |= CSI2_TIMING_STOP_STATE_X4_IO1;
 385         else
 386                 reg &= ~CSI2_TIMING_STOP_STATE_X4_IO1;
 387
 388         reg &= ~CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK;
 389         reg |= timing->stop_state_counter <<
 390                CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT;
 391
 392         iss_reg_write(csi2->iss, csi2->regs1, CSI2_TIMING, reg);
 393 }
 394
 395 /*
 396  * csi2_irq_ctx_set - Enables CSI2 Context IRQs.
 397  * @enable: Enable/disable CSI2 Context interrupts
 398  */
 399 static void csi2_irq_ctx_set(struct iss_csi2_device *csi2, int enable)
 400 {
 401         const u32 mask = CSI2_CTX_IRQ_FE | CSI2_CTX_IRQ_FS;
 402         int i;
 403
 404         for (i = 0; i < 8; i++) {
 405                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(i),
 406                               mask);
 407                 if (enable)
 408                         iss_reg_set(csi2->iss, csi2->regs1,
 409                                     CSI2_CTX_IRQENABLE(i), mask);
 410                 else
 411                         iss_reg_clr(csi2->iss, csi2->regs1,
 412                                     CSI2_CTX_IRQENABLE(i), mask);
 413         }
 414 }
 415
 416 /*
 417  * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
 418  * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
 419  */
 420 static void csi2_irq_complexio1_set(struct iss_csi2_device *csi2, int enable)
 421 {
 422         u32 reg;
 423
 424         reg = CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT |
 425                 CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER |
 426                 CSI2_COMPLEXIO_IRQ_STATEULPM5 |
 427                 CSI2_COMPLEXIO_IRQ_ERRCONTROL5 |
 428                 CSI2_COMPLEXIO_IRQ_ERRESC5 |
 429                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5 |
 430                 CSI2_COMPLEXIO_IRQ_ERRSOTHS5 |
 431                 CSI2_COMPLEXIO_IRQ_STATEULPM4 |
 432                 CSI2_COMPLEXIO_IRQ_ERRCONTROL4 |
 433                 CSI2_COMPLEXIO_IRQ_ERRESC4 |
 434                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4 |
 435                 CSI2_COMPLEXIO_IRQ_ERRSOTHS4 |
 436                 CSI2_COMPLEXIO_IRQ_STATEULPM3 |
 437                 CSI2_COMPLEXIO_IRQ_ERRCONTROL3 |
 438                 CSI2_COMPLEXIO_IRQ_ERRESC3 |
 439                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3 |
 440                 CSI2_COMPLEXIO_IRQ_ERRSOTHS3 |
 441                 CSI2_COMPLEXIO_IRQ_STATEULPM2 |
 442                 CSI2_COMPLEXIO_IRQ_ERRCONTROL2 |
 443                 CSI2_COMPLEXIO_IRQ_ERRESC2 |
 444                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2 |
 445                 CSI2_COMPLEXIO_IRQ_ERRSOTHS2 |
 446                 CSI2_COMPLEXIO_IRQ_STATEULPM1 |
 447                 CSI2_COMPLEXIO_IRQ_ERRCONTROL1 |
 448                 CSI2_COMPLEXIO_IRQ_ERRESC1 |
 449                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1 |
 450                 CSI2_COMPLEXIO_IRQ_ERRSOTHS1;
 451         iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS, reg);
 452         if (enable)
 453                 iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE,
 454                             reg);
 455         else
 456                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE,
 457                               0);
 458 }
 459
 460 /*
 461  * csi2_irq_status_set - Enables CSI2 Status IRQs.
 462  * @enable: Enable/disable CSI2 Status interrupts
 463  */
 464 static void csi2_irq_status_set(struct iss_csi2_device *csi2, int enable)
 465 {
 466         u32 reg;
 467
 468         reg = CSI2_IRQ_OCP_ERR |
 469                 CSI2_IRQ_SHORT_PACKET |
 470                 CSI2_IRQ_ECC_CORRECTION |
 471                 CSI2_IRQ_ECC_NO_CORRECTION |
 472                 CSI2_IRQ_COMPLEXIO_ERR |
 473                 CSI2_IRQ_FIFO_OVF |
 474                 CSI2_IRQ_CONTEXT0;
 475         iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, reg);
 476         if (enable)
 477                 iss_reg_set(csi2->iss, csi2->regs1, CSI2_IRQENABLE, reg);
 478         else
 479                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQENABLE, 0);
 480 }
 481
 482 /*
 483  * omap4iss_csi2_reset - Resets the CSI2 module.
 484  *
 485  * Must be called with the phy lock held.
 486  *
 487  * Returns 0 if successful, or -EBUSY if power command didn't respond.
 488  */
 489 int omap4iss_csi2_reset(struct iss_csi2_device *csi2)
 490 {
 491         unsigned int timeout;
 492
 493         if (!csi2->available)
 494                 return -ENODEV;
 495
 496         if (csi2->phy->phy_in_use)
 497                 return -EBUSY;
 498
 499         iss_reg_set(csi2->iss, csi2->regs1, CSI2_SYSCONFIG,
 500                     CSI2_SYSCONFIG_SOFT_RESET);
 501
 502         timeout = iss_poll_condition_timeout(
 503                 iss_reg_read(csi2->iss, csi2->regs1, CSI2_SYSSTATUS) &
 504                 CSI2_SYSSTATUS_RESET_DONE, 500, 100, 200);
 505         if (timeout) {
 506                 dev_err(csi2->iss->dev, "CSI2: Soft reset timeout!\n");
 507                 return -EBUSY;
 508         }
 509
 510         iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_CFG,
 511                     CSI2_COMPLEXIO_CFG_RESET_CTRL);
 512
 513         timeout = iss_poll_condition_timeout(
 514                 iss_reg_read(csi2->iss, csi2->phy->phy_regs, REGISTER1) &
 515                 REGISTER1_RESET_DONE_CTRLCLK, 10000, 100, 500);
 516         if (timeout) {
 517                 dev_err(csi2->iss->dev, "CSI2: CSI2_96M_FCLK reset timeout!\n");
 518                 return -EBUSY;
 519         }
 520
 521         iss_reg_update(csi2->iss, csi2->regs1, CSI2_SYSCONFIG,
 522                        CSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
 523                        CSI2_SYSCONFIG_AUTO_IDLE,
 524                        CSI2_SYSCONFIG_MSTANDBY_MODE_NO);
 525
 526         return 0;
 527 }
 528
 529 static int csi2_configure(struct iss_csi2_device *csi2)
 530 {
 531         const struct iss_v4l2_subdevs_group *pdata;
 532         struct iss_csi2_timing_cfg *timing = &csi2->timing[0];
 533         struct v4l2_subdev *sensor;
 534         struct media_pad *pad;
 535
 536         /*
 537          * CSI2 fields that can be updated while the context has
 538          * been enabled or the interface has been enabled are not
 539          * updated dynamically currently. So we do not allow to
 540          * reconfigure if either has been enabled
 541          */
 542         if (csi2->contexts[0].enabled || csi2->ctrl.if_enable)
 543                 return -EBUSY;
 544
 545         pad = media_entity_remote_pad(&csi2->pads[CSI2_PAD_SINK]);
 546         sensor = media_entity_to_v4l2_subdev(pad->entity);
 547         pdata = sensor->host_priv;
 548
 549         csi2->frame_skip = 0;
 550         v4l2_subdev_call(sensor, sensor, g_skip_frames, &csi2->frame_skip);
 551
 552         csi2->ctrl.vp_out_ctrl = pdata->bus.csi2.vpclk_div;
 553         csi2->ctrl.frame_mode = ISS_CSI2_FRAME_IMMEDIATE;
 554         csi2->ctrl.ecc_enable = pdata->bus.csi2.crc;
 555
 556         timing->force_rx_mode = 1;
 557         timing->stop_state_16x = 1;
 558         timing->stop_state_4x = 1;
 559         timing->stop_state_counter = 0x1ff;
 560
 561         /*
 562          * The CSI2 receiver can't do any format conversion except DPCM
 563          * decompression, so every set_format call configures both pads
 564          * and enables DPCM decompression as a special case:
 565          */
 566         if (csi2->formats[CSI2_PAD_SINK].code !=
 567             csi2->formats[CSI2_PAD_SOURCE].code)
 568                 csi2->dpcm_decompress = true;
 569         else
 570                 csi2->dpcm_decompress = false;
 571
 572         csi2->contexts[0].format_id = csi2_ctx_map_format(csi2);
 573
 574         if (csi2->video_out.bpl_padding == 0)
 575                 csi2->contexts[0].data_offset = 0;
 576         else
 577                 csi2->contexts[0].data_offset = csi2->video_out.bpl_value;
 578
 579         /*
 580          * Enable end of frame and end of line signals generation for
 581          * context 0. These signals are generated from CSI2 receiver to
 582          * qualify the last pixel of a frame and the last pixel of a line.
 583          * Without enabling the signals CSI2 receiver writes data to memory
 584          * beyond buffer size and/or data line offset is not handled correctly.
 585          */
 586         csi2->contexts[0].eof_enabled = 1;
 587         csi2->contexts[0].eol_enabled = 1;
 588
 589         csi2_irq_complexio1_set(csi2, 1);
 590         csi2_irq_ctx_set(csi2, 1);
 591         csi2_irq_status_set(csi2, 1);
 592
 593         /* Set configuration (timings, format and links) */
 594         csi2_timing_config(csi2, timing);
 595         csi2_recv_config(csi2, &csi2->ctrl);
 596         csi2_ctx_config(csi2, &csi2->contexts[0]);
 597
 598         return 0;
 599 }
 600
 601 /*
 602  * csi2_print_status - Prints CSI2 debug information.
 603  */
 604 #define CSI2_PRINT_REGISTER(iss, regs, name)\
 605         dev_dbg(iss->dev, "###CSI2 " #name "=0x%08x\n", \
 606                 iss_reg_read(iss, regs, CSI2_##name))
 607
 608 static void csi2_print_status(struct iss_csi2_device *csi2)
 609 {
 610         struct iss_device *iss = csi2->iss;
 611
 612         if (!csi2->available)
 613                 return;
 614
 615         dev_dbg(iss->dev, "-------------CSI2 Register dump-------------\n");
 616
 617         CSI2_PRINT_REGISTER(iss, csi2->regs1, SYSCONFIG);
 618         CSI2_PRINT_REGISTER(iss, csi2->regs1, SYSSTATUS);
 619         CSI2_PRINT_REGISTER(iss, csi2->regs1, IRQENABLE);
 620         CSI2_PRINT_REGISTER(iss, csi2->regs1, IRQSTATUS);
 621         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTRL);
 622         CSI2_PRINT_REGISTER(iss, csi2->regs1, DBG_H);
 623         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_CFG);
 624         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_IRQSTATUS);
 625         CSI2_PRINT_REGISTER(iss, csi2->regs1, SHORT_PACKET);
 626         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_IRQENABLE);
 627         CSI2_PRINT_REGISTER(iss, csi2->regs1, DBG_P);
 628         CSI2_PRINT_REGISTER(iss, csi2->regs1, TIMING);
 629         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL1(0));
 630         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL2(0));
 631         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_DAT_OFST(0));
 632         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_PING_ADDR(0));
 633         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_PONG_ADDR(0));
 634         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_IRQENABLE(0));
 635         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_IRQSTATUS(0));
 636         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL3(0));
 637
 638         dev_dbg(iss->dev, "--------------------------------------------\n");
 639 }
 640
 641 /* -----------------------------------------------------------------------------
 642  * Interrupt handling
 643  */
 644
 645 /*
 646  * csi2_isr_buffer - Does buffer handling at end-of-frame
 647  * when writing to memory.
 648  */
 649 static void csi2_isr_buffer(struct iss_csi2_device *csi2)
 650 {
 651         struct iss_buffer *buffer;
 652
 653         csi2_ctx_enable(csi2, 0, 0);
 654
 655         buffer = omap4iss_video_buffer_next(&csi2->video_out);
 656
 657         /*
 658          * Let video queue operation restart engine if there is an underrun
 659          * condition.
 660          */
 661         if (buffer == NULL)
 662                 return;
 663
 664         csi2_set_outaddr(csi2, buffer->iss_addr);
 665         csi2_ctx_enable(csi2, 0, 1);
 666 }
 667
 668 static void csi2_isr_ctx(struct iss_csi2_device *csi2,
 669                          struct iss_csi2_ctx_cfg *ctx)
 670 {
 671         unsigned int n = ctx->ctxnum;
 672         u32 status;
 673
 674         status = iss_reg_read(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(n));
 675         iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(n), status);
 676
 677         /* Propagate frame number */
 678         if (status & CSI2_CTX_IRQ_FS) {
 679                 struct iss_pipeline *pipe =
 680                                      to_iss_pipeline(&csi2->subdev.entity);
 681                 u16 frame;
 682                 u16 delta;
 683
 684                 frame = iss_reg_read(csi2->iss, csi2->regs1,
 685                                      CSI2_CTX_CTRL2(ctx->ctxnum))
 686                       >> CSI2_CTX_CTRL2_FRAME_SHIFT;
 687
 688                 if (frame == 0) {
 689                         /* A zero value means that the counter isn't implemented
 690                          * by the source. Increment the frame number in software
 691                          * in that case.
 692                          */
 693                         atomic_inc(&pipe->frame_number);
 694                 } else {
 695                         /* Extend the 16 bit frame number to 32 bits by
 696                          * computing the delta between two consecutive CSI2
 697                          * frame numbers and adding it to the software frame
 698                          * number. The hardware counter starts at 1 and wraps
 699                          * from 0xffff to 1 without going through 0, so subtract
 700                          * 1 when the counter wraps.
 701                          */
 702                         delta = frame - ctx->frame;
 703                         if (frame < ctx->frame)
 704                                 delta--;
 705                         ctx->frame = frame;
 706
 707                         atomic_add(delta, &pipe->frame_number);
 708                 }
 709         }
 710
 711         if (!(status & CSI2_CTX_IRQ_FE))
 712                 return;
 713
 714         /* Skip interrupts until we reach the frame skip count. The CSI2 will be
 715          * automatically disabled, as the frame skip count has been programmed
 716          * in the CSI2_CTx_CTRL1::COUNT field, so reenable it.
 717          *
 718          * It would have been nice to rely on the FRAME_NUMBER interrupt instead
 719          * but it turned out that the interrupt is only generated when the CSI2
 720          * writes to memory (the CSI2_CTx_CTRL1::COUNT field is decreased
 721          * correctly and reaches 0 when data is forwarded to the video port only
 722          * but no interrupt arrives). Maybe a CSI2 hardware bug.
 723          */
 724         if (csi2->frame_skip) {
 725                 csi2->frame_skip--;
 726                 if (csi2->frame_skip == 0) {
 727                         ctx->format_id = csi2_ctx_map_format(csi2);
 728                         csi2_ctx_config(csi2, ctx);
 729                         csi2_ctx_enable(csi2, n, 1);
 730                 }
 731                 return;
 732         }
 733
 734         if (csi2->output & CSI2_OUTPUT_MEMORY)
 735                 csi2_isr_buffer(csi2);
 736 }
 737
 738 /*
 739  * omap4iss_csi2_isr - CSI2 interrupt handling.
 740  */
 741 void omap4iss_csi2_isr(struct iss_csi2_device *csi2)
 742 {
 743         struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
 744         u32 csi2_irqstatus, cpxio1_irqstatus;
 745         struct iss_device *iss = csi2->iss;
 746
 747         if (!csi2->available)
 748                 return;
 749
 750         csi2_irqstatus = iss_reg_read(csi2->iss, csi2->regs1, CSI2_IRQSTATUS);
 751         iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, csi2_irqstatus);
 752
 753         /* Failure Cases */
 754         if (csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR) {
 755                 cpxio1_irqstatus = iss_reg_read(csi2->iss, csi2->regs1,
 756                                                 CSI2_COMPLEXIO_IRQSTATUS);
 757                 iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS,
 758                               cpxio1_irqstatus);
 759                 dev_dbg(iss->dev, "CSI2: ComplexIO Error IRQ %x\n",
 760                         cpxio1_irqstatus);
 761                 pipe->error = true;
 762         }
 763
 764         if (csi2_irqstatus & (CSI2_IRQ_OCP_ERR |
 765                               CSI2_IRQ_SHORT_PACKET |
 766                               CSI2_IRQ_ECC_NO_CORRECTION |
 767                               CSI2_IRQ_COMPLEXIO_ERR |
 768                               CSI2_IRQ_FIFO_OVF)) {
 769                 dev_dbg(iss->dev,
 770                         "CSI2 Err: OCP:%d SHORT:%d ECC:%d CPXIO:%d OVF:%d\n",
 771                         csi2_irqstatus & CSI2_IRQ_OCP_ERR ? 1 : 0,
 772                         csi2_irqstatus & CSI2_IRQ_SHORT_PACKET ? 1 : 0,
 773                         csi2_irqstatus & CSI2_IRQ_ECC_NO_CORRECTION ? 1 : 0,
 774                         csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR ? 1 : 0,
 775                         csi2_irqstatus & CSI2_IRQ_FIFO_OVF ? 1 : 0);
 776                 pipe->error = true;
 777         }
 778
 779         if (omap4iss_module_sync_is_stopping(&csi2->wait, &csi2->stopping))
 780                 return;
 781
 782         /* Successful cases */
 783         if (csi2_irqstatus & CSI2_IRQ_CONTEXT0)
 784                 csi2_isr_ctx(csi2, &csi2->contexts[0]);
 785
 786         if (csi2_irqstatus & CSI2_IRQ_ECC_CORRECTION)
 787                 dev_dbg(iss->dev, "CSI2: ECC correction done\n");
 788 }
 789
 790 /* -----------------------------------------------------------------------------
 791  * ISS video operations
 792  */
 793
 794 /*
 795  * csi2_queue - Queues the first buffer when using memory output
 796  * @video: The video node
 797  * @buffer: buffer to queue
 798  */
 799 static int csi2_queue(struct iss_video *video, struct iss_buffer *buffer)
 800 {
 801         struct iss_csi2_device *csi2 = container_of(video,
 802                                 struct iss_csi2_device, video_out);
 803
 804         csi2_set_outaddr(csi2, buffer->iss_addr);
 805
 806         /*
 807          * If streaming was enabled before there was a buffer queued
 808          * or underrun happened in the ISR, the hardware was not enabled
 809          * and DMA queue flag ISS_VIDEO_DMAQUEUE_UNDERRUN is still set.
 810          * Enable it now.
 811          */
 812         if (csi2->video_out.dmaqueue_flags & ISS_VIDEO_DMAQUEUE_UNDERRUN) {
 813                 /* Enable / disable context 0 and IRQs */
 814                 csi2_if_enable(csi2, 1);
 815                 csi2_ctx_enable(csi2, 0, 1);
 816                 iss_video_dmaqueue_flags_clr(&csi2->video_out);
 817         }
 818
 819         return 0;
 820 }
 821
 822 static const struct iss_video_operations csi2_issvideo_ops = {
 823         .queue = csi2_queue,
 824 };
 825
 826 /* -----------------------------------------------------------------------------
 827  * V4L2 subdev operations
 828  */
 829
 830 static struct v4l2_mbus_framefmt *
 831 __csi2_get_format(struct iss_csi2_device *csi2, struct v4l2_subdev_pad_config *cfg,
 832                   unsigned int pad, enum v4l2_subdev_format_whence which)
 833 {
 834         if (which == V4L2_SUBDEV_FORMAT_TRY)
 835                 return v4l2_subdev_get_try_format(&csi2->subdev, cfg, pad);
 836
 837         return &csi2->formats[pad];
 838 }
 839
 840 static void
 841 csi2_try_format(struct iss_csi2_device *csi2, struct v4l2_subdev_pad_config *cfg,
 842                 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
 843                 enum v4l2_subdev_format_whence which)
 844 {
 845         u32 pixelcode;
 846         struct v4l2_mbus_framefmt *format;
 847         const struct iss_format_info *info;
 848         unsigned int i;
 849
 850         switch (pad) {
 851         case CSI2_PAD_SINK:
 852                 /* Clamp the width and height to valid range (1-8191). */
 853                 for (i = 0; i < ARRAY_SIZE(csi2_input_fmts); i++) {
 854                         if (fmt->code == csi2_input_fmts[i])
 855                                 break;
 856                 }
 857
 858                 /* If not found, use SGRBG10 as default */
 859                 if (i >= ARRAY_SIZE(csi2_input_fmts))
 860                         fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 861
 862                 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
 863                 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
 864                 break;
 865
 866         case CSI2_PAD_SOURCE:
 867                 /* Source format same as sink format, except for DPCM
 868                  * compression.
 869                  */
 870                 pixelcode = fmt->code;
 871                 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK, which);
 872                 memcpy(fmt, format, sizeof(*fmt));
 873
 874                 /*
 875                  * Only Allow DPCM decompression, and check that the
 876                  * pattern is preserved
 877                  */
 878                 info = omap4iss_video_format_info(fmt->code);
 879                 if (info->uncompressed == pixelcode)
 880                         fmt->code = pixelcode;
 881                 break;
 882         }
 883
 884         /* RGB, non-interlaced */
 885         fmt->colorspace = V4L2_COLORSPACE_SRGB;
 886         fmt->field = V4L2_FIELD_NONE;
 887 }
 888
 889 /*
 890  * csi2_enum_mbus_code - Handle pixel format enumeration
 891  * @sd     : pointer to v4l2 subdev structure
 892  * @cfg    : V4L2 subdev pad config
 893  * @code   : pointer to v4l2_subdev_mbus_code_enum structure
 894  * return -EINVAL or zero on success
 895  */
 896 static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
 897                                struct v4l2_subdev_pad_config *cfg,
 898                                struct v4l2_subdev_mbus_code_enum *code)
 899 {
 900         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 901         struct v4l2_mbus_framefmt *format;
 902         const struct iss_format_info *info;
 903
 904         if (code->pad == CSI2_PAD_SINK) {
 905                 if (code->index >= ARRAY_SIZE(csi2_input_fmts))
 906                         return -EINVAL;
 907
 908                 code->code = csi2_input_fmts[code->index];
 909         } else {
 910                 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK,
 911                                            code->which);
 912                 switch (code->index) {
 913                 case 0:
 914                         /* Passthrough sink pad code */
 915                         code->code = format->code;
 916                         break;
 917                 case 1:
 918                         /* Uncompressed code */
 919                         info = omap4iss_video_format_info(format->code);
 920                         if (info->uncompressed == format->code)
 921                                 return -EINVAL;
 922
 923                         code->code = info->uncompressed;
 924                         break;
 925                 default:
 926                         return -EINVAL;
 927                 }
 928         }
 929
 930         return 0;
 931 }
 932
 933 static int csi2_enum_frame_size(struct v4l2_subdev *sd,
 934                                 struct v4l2_subdev_pad_config *cfg,
 935                                 struct v4l2_subdev_frame_size_enum *fse)
 936 {
 937         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 938         struct v4l2_mbus_framefmt format;
 939
 940         if (fse->index != 0)
 941                 return -EINVAL;
 942
 943         format.code = fse->code;
 944         format.width = 1;
 945         format.height = 1;
 946         csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
 947         fse->min_width = format.width;
 948         fse->min_height = format.height;
 949
 950         if (format.code != fse->code)
 951                 return -EINVAL;
 952
 953         format.code = fse->code;
 954         format.width = -1;
 955         format.height = -1;
 956         csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
 957         fse->max_width = format.width;
 958         fse->max_height = format.height;
 959
 960         return 0;
 961 }
 962
 963 /*
 964  * csi2_get_format - Handle get format by pads subdev method
 965  * @sd : pointer to v4l2 subdev structure
 966  * @cfg: V4L2 subdev pad config
 967  * @fmt: pointer to v4l2 subdev format structure
 968  * return -EINVAL or zero on success
 969  */
 970 static int csi2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
 971                            struct v4l2_subdev_format *fmt)
 972 {
 973         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 974         struct v4l2_mbus_framefmt *format;
 975
 976         format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
 977         if (format == NULL)
 978                 return -EINVAL;
 979
 980         fmt->format = *format;
 981         return 0;
 982 }
 983
 984 /*
 985  * csi2_set_format - Handle set format by pads subdev method
 986  * @sd : pointer to v4l2 subdev structure
 987  * @cfg: V4L2 subdev pad config
 988  * @fmt: pointer to v4l2 subdev format structure
 989  * return -EINVAL or zero on success
 990  */
 991 static int csi2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
 992                            struct v4l2_subdev_format *fmt)
 993 {
 994         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 995         struct v4l2_mbus_framefmt *format;
 996
 997         format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
 998         if (format == NULL)
 999                 return -EINVAL;
1000
1001         csi2_try_format(csi2, cfg, fmt->pad, &fmt->format, fmt->which);
1002         *format = fmt->format;
1003
1004         /* Propagate the format from sink to source */
1005         if (fmt->pad == CSI2_PAD_SINK) {
1006                 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SOURCE,
1007                                            fmt->which);
1008                 *format = fmt->format;
1009                 csi2_try_format(csi2, cfg, CSI2_PAD_SOURCE, format, fmt->which);
1010         }
1011
1012         return 0;
1013 }
1014
1015 static int csi2_link_validate(struct v4l2_subdev *sd, struct media_link *link,
1016                               struct v4l2_subdev_format *source_fmt,
1017                               struct v4l2_subdev_format *sink_fmt)
1018 {
1019         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1020         struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
1021         int rval;
1022
1023         pipe->external = media_entity_to_v4l2_subdev(link->source->entity);
1024         rval = omap4iss_get_external_info(pipe, link);
1025         if (rval < 0)
1026                 return rval;
1027
1028         return v4l2_subdev_link_validate_default(sd, link, source_fmt,
1029                                                  sink_fmt);
1030 }
1031
1032 /*
1033  * csi2_init_formats - Initialize formats on all pads
1034  * @sd: ISS CSI2 V4L2 subdevice
1035  * @fh: V4L2 subdev file handle
1036  *
1037  * Initialize all pad formats with default values. If fh is not NULL, try
1038  * formats are initialized on the file handle. Otherwise active formats are
1039  * initialized on the device.
1040  */
1041 static int csi2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1042 {
1043         struct v4l2_subdev_format format;
1044
1045         memset(&format, 0, sizeof(format));
1046         format.pad = CSI2_PAD_SINK;
1047         format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
1048         format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1049         format.format.width = 4096;
1050         format.format.height = 4096;
1051         csi2_set_format(sd, fh ? fh->pad : NULL, &format);
1052
1053         return 0;
1054 }
1055
1056 /*
1057  * csi2_set_stream - Enable/Disable streaming on the CSI2 module
1058  * @sd: ISS CSI2 V4L2 subdevice
1059  * @enable: ISS pipeline stream state
1060  *
1061  * Return 0 on success or a negative error code otherwise.
1062  */
1063 static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
1064 {
1065         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1066         struct iss_device *iss = csi2->iss;
1067         struct iss_video *video_out = &csi2->video_out;
1068         int ret = 0;
1069
1070         if (csi2->state == ISS_PIPELINE_STREAM_STOPPED) {
1071                 if (enable == ISS_PIPELINE_STREAM_STOPPED)
1072                         return 0;
1073
1074                 omap4iss_subclk_enable(iss, csi2->subclk);
1075         }
1076
1077         switch (enable) {
1078         case ISS_PIPELINE_STREAM_CONTINUOUS: {
1079                 ret = omap4iss_csiphy_config(iss, sd);
1080                 if (ret < 0)
1081                         return ret;
1082
1083                 if (omap4iss_csiphy_acquire(csi2->phy) < 0)
1084                         return -ENODEV;
1085                 csi2_configure(csi2);
1086                 csi2_print_status(csi2);
1087
1088                 /*
1089                  * When outputting to memory with no buffer available, let the
1090                  * buffer queue handler start the hardware. A DMA queue flag
1091                  * ISS_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
1092                  * a buffer available.
1093                  */
1094                 if (csi2->output & CSI2_OUTPUT_MEMORY &&
1095                     !(video_out->dmaqueue_flags & ISS_VIDEO_DMAQUEUE_QUEUED))
1096                         break;
1097                 /* Enable context 0 and IRQs */
1098                 atomic_set(&csi2->stopping, 0);
1099                 csi2_ctx_enable(csi2, 0, 1);
1100                 csi2_if_enable(csi2, 1);
1101                 iss_video_dmaqueue_flags_clr(video_out);
1102                 break;
1103         }
1104         case ISS_PIPELINE_STREAM_STOPPED:
1105                 if (csi2->state == ISS_PIPELINE_STREAM_STOPPED)
1106                         return 0;
1107                 if (omap4iss_module_sync_idle(&sd->entity, &csi2->wait,
1108                                               &csi2->stopping))
1109                         ret = -ETIMEDOUT;
1110                 csi2_ctx_enable(csi2, 0, 0);
1111                 csi2_if_enable(csi2, 0);
1112                 csi2_irq_ctx_set(csi2, 0);
1113                 omap4iss_csiphy_release(csi2->phy);
1114                 omap4iss_subclk_disable(iss, csi2->subclk);
1115                 iss_video_dmaqueue_flags_clr(video_out);
1116                 break;
1117         }
1118
1119         csi2->state = enable;
1120         return ret;
1121 }
1122
1123 /* subdev video operations */
1124 static const struct v4l2_subdev_video_ops csi2_video_ops = {
1125         .s_stream = csi2_set_stream,
1126 };
1127
1128 /* subdev pad operations */
1129 static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
1130         .enum_mbus_code = csi2_enum_mbus_code,
1131         .enum_frame_size = csi2_enum_frame_size,
1132         .get_fmt = csi2_get_format,
1133         .set_fmt = csi2_set_format,
1134         .link_validate = csi2_link_validate,
1135 };
1136
1137 /* subdev operations */
1138 static const struct v4l2_subdev_ops csi2_ops = {
1139         .video = &csi2_video_ops,
1140         .pad = &csi2_pad_ops,
1141 };
1142
1143 /* subdev internal operations */
1144 static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
1145         .open = csi2_init_formats,
1146 };
1147
1148 /* -----------------------------------------------------------------------------
1149  * Media entity operations
1150  */
1151
1152 /*
1153  * csi2_link_setup - Setup CSI2 connections.
1154  * @entity : Pointer to media entity structure
1155  * @local  : Pointer to local pad array
1156  * @remote : Pointer to remote pad array
1157  * @flags  : Link flags
1158  * return -EINVAL or zero on success
1159  */
1160 static int csi2_link_setup(struct media_entity *entity,
1161                            const struct media_pad *local,
1162                            const struct media_pad *remote, u32 flags)
1163 {
1164         struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1165         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1166         struct iss_csi2_ctrl_cfg *ctrl = &csi2->ctrl;
1167
1168         /*
1169          * The ISS core doesn't support pipelines with multiple video outputs.
1170          * Revisit this when it will be implemented, and return -EBUSY for now.
1171          */
1172
1173         switch (local->index | media_entity_type(remote->entity)) {
1174         case CSI2_PAD_SOURCE | MEDIA_ENT_T_DEVNODE:
1175                 if (flags & MEDIA_LNK_FL_ENABLED) {
1176                         if (csi2->output & ~CSI2_OUTPUT_MEMORY)
1177                                 return -EBUSY;
1178                         csi2->output |= CSI2_OUTPUT_MEMORY;
1179                 } else {
1180                         csi2->output &= ~CSI2_OUTPUT_MEMORY;
1181                 }
1182                 break;
1183
1184         case CSI2_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
1185                 if (flags & MEDIA_LNK_FL_ENABLED) {
1186                         if (csi2->output & ~CSI2_OUTPUT_IPIPEIF)
1187                                 return -EBUSY;
1188                         csi2->output |= CSI2_OUTPUT_IPIPEIF;
1189                 } else {
1190                         csi2->output &= ~CSI2_OUTPUT_IPIPEIF;
1191                 }
1192                 break;
1193
1194         default:
1195                 /* Link from camera to CSI2 is fixed... */
1196                 return -EINVAL;
1197         }
1198
1199         ctrl->vp_only_enable = csi2->output & CSI2_OUTPUT_MEMORY ? false : true;
1200         ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_IPIPEIF);
1201
1202         return 0;
1203 }
1204
1205 /* media operations */
1206 static const struct media_entity_operations csi2_media_ops = {
1207         .link_setup = csi2_link_setup,
1208         .link_validate = v4l2_subdev_link_validate,
1209 };
1210
1211 void omap4iss_csi2_unregister_entities(struct iss_csi2_device *csi2)
1212 {
1213         v4l2_device_unregister_subdev(&csi2->subdev);
1214         omap4iss_video_unregister(&csi2->video_out);
1215 }
1216
1217 int omap4iss_csi2_register_entities(struct iss_csi2_device *csi2,
1218                                     struct v4l2_device *vdev)
1219 {
1220         int ret;
1221
1222         /* Register the subdev and video nodes. */
1223         ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
1224         if (ret < 0)
1225                 goto error;
1226
1227         ret = omap4iss_video_register(&csi2->video_out, vdev);
1228         if (ret < 0)
1229                 goto error;
1230
1231         return 0;
1232
1233 error:
1234         omap4iss_csi2_unregister_entities(csi2);
1235         return ret;
1236 }
1237
1238 /* -----------------------------------------------------------------------------
1239  * ISS CSI2 initialisation and cleanup
1240  */
1241
1242 /*
1243  * csi2_init_entities - Initialize subdev and media entity.
1244  * @csi2: Pointer to csi2 structure.
1245  * return -ENOMEM or zero on success
1246  */
1247 static int csi2_init_entities(struct iss_csi2_device *csi2, const char *subname)
1248 {
1249         struct v4l2_subdev *sd = &csi2->subdev;
1250         struct media_pad *pads = csi2->pads;
1251         struct media_entity *me = &sd->entity;
1252         int ret;
1253         char name[V4L2_SUBDEV_NAME_SIZE];
1254
1255         v4l2_subdev_init(sd, &csi2_ops);
1256         sd->internal_ops = &csi2_internal_ops;
1257         snprintf(name, sizeof(name), "CSI2%s", subname);
1258         snprintf(sd->name, sizeof(sd->name), "OMAP4 ISS %s", name);
1259
1260         sd->grp_id = 1 << 16;   /* group ID for iss subdevs */
1261         v4l2_set_subdevdata(sd, csi2);
1262         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1263
1264         pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1265         pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1266
1267         me->ops = &csi2_media_ops;
1268         ret = media_entity_init(me, CSI2_PADS_NUM, pads, 0);
1269         if (ret < 0)
1270                 return ret;
1271
1272         csi2_init_formats(sd, NULL);
1273
1274         /* Video device node */
1275         csi2->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1276         csi2->video_out.ops = &csi2_issvideo_ops;
1277         csi2->video_out.bpl_alignment = 32;
1278         csi2->video_out.bpl_zero_padding = 1;
1279         csi2->video_out.bpl_max = 0x1ffe0;
1280         csi2->video_out.iss = csi2->iss;
1281         csi2->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1282
1283         ret = omap4iss_video_init(&csi2->video_out, name);
1284         if (ret < 0)
1285                 goto error_video;
1286
1287         /* Connect the CSI2 subdev to the video node. */
1288         ret = media_entity_create_link(&csi2->subdev.entity, CSI2_PAD_SOURCE,
1289                                        &csi2->video_out.video.entity, 0, 0);
1290         if (ret < 0)
1291                 goto error_link;
1292
1293         return 0;
1294
1295 error_link:
1296         omap4iss_video_cleanup(&csi2->video_out);
1297 error_video:
1298         media_entity_cleanup(&csi2->subdev.entity);
1299         return ret;
1300 }
1301
1302 /*
1303  * omap4iss_csi2_init - Routine for module driver init
1304  */
1305 int omap4iss_csi2_init(struct iss_device *iss)
1306 {
1307         struct iss_csi2_device *csi2a = &iss->csi2a;
1308         struct iss_csi2_device *csi2b = &iss->csi2b;
1309         int ret;
1310
1311         csi2a->iss = iss;
1312         csi2a->available = 1;
1313         csi2a->regs1 = OMAP4_ISS_MEM_CSI2_A_REGS1;
1314         csi2a->phy = &iss->csiphy1;
1315         csi2a->subclk = OMAP4_ISS_SUBCLK_CSI2_A;
1316         csi2a->state = ISS_PIPELINE_STREAM_STOPPED;
1317         init_waitqueue_head(&csi2a->wait);
1318
1319         ret = csi2_init_entities(csi2a, "a");
1320         if (ret < 0)
1321                 return ret;
1322
1323         csi2b->iss = iss;
1324         csi2b->available = 1;
1325         csi2b->regs1 = OMAP4_ISS_MEM_CSI2_B_REGS1;
1326         csi2b->phy = &iss->csiphy2;
1327         csi2b->subclk = OMAP4_ISS_SUBCLK_CSI2_B;
1328         csi2b->state = ISS_PIPELINE_STREAM_STOPPED;
1329         init_waitqueue_head(&csi2b->wait);
1330
1331         ret = csi2_init_entities(csi2b, "b");
1332         if (ret < 0)
1333                 return ret;
1334
1335         return 0;
1336 }
1337
1338 /*
1339  * omap4iss_csi2_cleanup - Routine for module driver cleanup
1340  */
1341 void omap4iss_csi2_cleanup(struct iss_device *iss)
1342 {
1343         struct iss_csi2_device *csi2a = &iss->csi2a;
1344         struct iss_csi2_device *csi2b = &iss->csi2b;
1345
1346         omap4iss_video_cleanup(&csi2a->video_out);
1347         media_entity_cleanup(&csi2a->subdev.entity);
1348
1349         omap4iss_video_cleanup(&csi2b->video_out);
1350         media_entity_cleanup(&csi2b->subdev.entity);
1351 }