kernel/drivers/staging/media/davinci_vpfe/dm365_ipipe_hw.h

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Inc
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  16  *
  17  * Contributors:
  18  *      Manjunath Hadli <manjunath.hadli@ti.com>
  19  *      Prabhakar Lad <prabhakar.lad@ti.com>
  20  */
  21
  22 #ifndef _DAVINCI_VPFE_DM365_IPIPE_HW_H
  23 #define _DAVINCI_VPFE_DM365_IPIPE_HW_H
  24
  25 #include "vpfe_mc_capture.h"
  26
  27 #define SET_LOW_ADDR     0x0000ffff
  28 #define SET_HIGH_ADDR    0xffff0000
  29
  30 /* Below are the internal tables */
  31 #define DPC_TB0_START_ADDR      0x8000
  32 #define DPC_TB1_START_ADDR      0x8400
  33
  34 #define GAMMA_R_START_ADDR      0xa800
  35 #define GAMMA_G_START_ADDR      0xb000
  36 #define GAMMA_B_START_ADDR      0xb800
  37
  38 /* RAM table addresses for edge enhancement correction*/
  39 #define YEE_TB_START_ADDR       0x8800
  40
  41 /* RAM table address for GBC LUT */
  42 #define GBCE_TB_START_ADDR      0x9000
  43
  44 /* RAM table for 3D NF LUT */
  45 #define D3L_TB0_START_ADDR      0x9800
  46 #define D3L_TB1_START_ADDR      0x9c00
  47 #define D3L_TB2_START_ADDR      0xa000
  48 #define D3L_TB3_START_ADDR      0xa400
  49
  50 /* IPIPE Register Offsets from the base address */
  51 #define IPIPE_SRC_EN            0x0000
  52 #define IPIPE_SRC_MODE          0x0004
  53 #define IPIPE_SRC_FMT           0x0008
  54 #define IPIPE_SRC_COL           0x000c
  55 #define IPIPE_SRC_VPS           0x0010
  56 #define IPIPE_SRC_VSZ           0x0014
  57 #define IPIPE_SRC_HPS           0x0018
  58 #define IPIPE_SRC_HSZ           0x001c
  59
  60 #define IPIPE_SEL_SBU           0x0020
  61
  62 #define IPIPE_DMA_STA           0x0024
  63 #define IPIPE_GCK_MMR           0x0028
  64 #define IPIPE_GCK_PIX           0x002c
  65 #define IPIPE_RESERVED0         0x0030
  66
  67 /* Defect Correction */
  68 #define DPC_LUT_EN              0x0034
  69 #define DPC_LUT_SEL             0x0038
  70 #define DPC_LUT_ADR             0x003c
  71 #define DPC_LUT_SIZ             0x0040
  72 #define DPC_OTF_EN              0x0044
  73 #define DPC_OTF_TYP             0x0048
  74 #define DPC_OTF_2D_THR_R        0x004c
  75 #define DPC_OTF_2D_THR_GR       0x0050
  76 #define DPC_OTF_2D_THR_GB       0x0054
  77 #define DPC_OTF_2D_THR_B        0x0058
  78 #define DPC_OTF_2C_THR_R        0x005c
  79 #define DPC_OTF_2C_THR_GR       0x0060
  80 #define DPC_OTF_2C_THR_GB       0x0064
  81 #define DPC_OTF_2C_THR_B        0x0068
  82 #define DPC_OTF_3_SHF           0x006c
  83 #define DPC_OTF_3D_THR          0x0070
  84 #define DPC_OTF_3D_SLP          0x0074
  85 #define DPC_OTF_3D_MIN          0x0078
  86 #define DPC_OTF_3D_MAX          0x007c
  87 #define DPC_OTF_3C_THR          0x0080
  88 #define DPC_OTF_3C_SLP          0x0084
  89 #define DPC_OTF_3C_MIN          0x0088
  90 #define DPC_OTF_3C_MAX          0x008c
  91
  92 /* Lense Shading Correction */
  93 #define LSC_VOFT                0x90
  94 #define LSC_VA2                 0x94
  95 #define LSC_VA1                 0x98
  96 #define LSC_VS                  0x9c
  97 #define LSC_HOFT                0xa0
  98 #define LSC_HA2                 0xa4
  99 #define LSC_HA1                 0xa8
 100 #define LSC_HS                  0xac
 101 #define LSC_GAIN_R              0xb0
 102 #define LSC_GAIN_GR             0xb4
 103 #define LSC_GAIN_GB             0xb8
 104 #define LSC_GAIN_B              0xbc
 105 #define LSC_OFT_R               0xc0
 106 #define LSC_OFT_GR              0xc4
 107 #define LSC_OFT_GB              0xc8
 108 #define LSC_OFT_B               0xcc
 109 #define LSC_SHF                 0xd0
 110 #define LSC_MAX                 0xd4
 111
 112 /* Noise Filter 1. Ofsets from start address given */
 113 #define D2F_1ST                 0xd8
 114 #define D2F_EN                  0x0
 115 #define D2F_TYP                 0x4
 116 #define D2F_THR                 0x8
 117 #define D2F_STR                 0x28
 118 #define D2F_SPR                 0x48
 119 #define D2F_EDG_MIN             0x68
 120 #define D2F_EDG_MAX             0x6c
 121
 122 /* Noise Filter 2 */
 123 #define D2F_2ND                 0x148
 124
 125 /* GIC */
 126 #define GIC_EN                  0x1b8
 127 #define GIC_TYP                 0x1bc
 128 #define GIC_GAN                 0x1c0
 129 #define GIC_NFGAN               0x1c4
 130 #define GIC_THR                 0x1c8
 131 #define GIC_SLP                 0x1cc
 132
 133 /* White Balance */
 134 #define WB2_OFT_R               0x1d0
 135 #define WB2_OFT_GR              0x1d4
 136 #define WB2_OFT_GB              0x1d8
 137 #define WB2_OFT_B               0x1dc
 138 #define WB2_WGN_R               0x1e0
 139 #define WB2_WGN_GR              0x1e4
 140 #define WB2_WGN_GB              0x1e8
 141 #define WB2_WGN_B               0x1ec
 142
 143 /* CFA interpolation */
 144 #define CFA_MODE                0x1f0
 145 #define CFA_2DIR_HPF_THR        0x1f4
 146 #define CFA_2DIR_HPF_SLP        0x1f8
 147 #define CFA_2DIR_MIX_THR        0x1fc
 148 #define CFA_2DIR_MIX_SLP        0x200
 149 #define CFA_2DIR_DIR_THR        0x204
 150 #define CFA_2DIR_DIR_SLP        0x208
 151 #define CFA_2DIR_NDWT           0x20c
 152 #define CFA_MONO_HUE_FRA        0x210
 153 #define CFA_MONO_EDG_THR        0x214
 154 #define CFA_MONO_THR_MIN        0x218
 155 #define CFA_MONO_THR_SLP        0x21c
 156 #define CFA_MONO_SLP_MIN        0x220
 157 #define CFA_MONO_SLP_SLP        0x224
 158 #define CFA_MONO_LPWT           0x228
 159
 160 /* RGB to RGB conversiona - 1st */
 161 #define RGB1_MUL_BASE           0x22c
 162 /* Offsets from base */
 163 #define RGB_MUL_RR              0x0
 164 #define RGB_MUL_GR              0x4
 165 #define RGB_MUL_BR              0x8
 166 #define RGB_MUL_RG              0xc
 167 #define RGB_MUL_GG              0x10
 168 #define RGB_MUL_BG              0x14
 169 #define RGB_MUL_RB              0x18
 170 #define RGB_MUL_GB              0x1c
 171 #define RGB_MUL_BB              0x20
 172 #define RGB_OFT_OR              0x24
 173 #define RGB_OFT_OG              0x28
 174 #define RGB_OFT_OB              0x2c
 175
 176 /* Gamma */
 177 #define GMM_CFG                 0x25c
 178
 179 /* RGB to RGB conversiona - 2nd */
 180 #define RGB2_MUL_BASE           0x260
 181
 182 /* 3D LUT */
 183 #define D3LUT_EN                0x290
 184
 185 /* RGB to YUV(YCbCr) conversion */
 186 #define YUV_ADJ                 0x294
 187 #define YUV_MUL_RY              0x298
 188 #define YUV_MUL_GY              0x29c
 189 #define YUV_MUL_BY              0x2a0
 190 #define YUV_MUL_RCB             0x2a4
 191 #define YUV_MUL_GCB             0x2a8
 192 #define YUV_MUL_BCB             0x2ac
 193 #define YUV_MUL_RCR             0x2b0
 194 #define YUV_MUL_GCR             0x2b4
 195 #define YUV_MUL_BCR             0x2b8
 196 #define YUV_OFT_Y               0x2bc
 197 #define YUV_OFT_CB              0x2c0
 198 #define YUV_OFT_CR              0x2c4
 199 #define YUV_PHS                 0x2c8
 200
 201 /* Global Brightness and Contrast */
 202 #define GBCE_EN                 0x2cc
 203 #define GBCE_TYP                0x2d0
 204
 205 /* Edge Enhancer */
 206 #define YEE_EN                  0x2d4
 207 #define YEE_TYP                 0x2d8
 208 #define YEE_SHF                 0x2dc
 209 #define YEE_MUL_00              0x2e0
 210 #define YEE_MUL_01              0x2e4
 211 #define YEE_MUL_02              0x2e8
 212 #define YEE_MUL_10              0x2ec
 213 #define YEE_MUL_11              0x2f0
 214 #define YEE_MUL_12              0x2f4
 215 #define YEE_MUL_20              0x2f8
 216 #define YEE_MUL_21              0x2fc
 217 #define YEE_MUL_22              0x300
 218 #define YEE_THR                 0x304
 219 #define YEE_E_GAN               0x308
 220 #define YEE_E_THR1              0x30c
 221 #define YEE_E_THR2              0x310
 222 #define YEE_G_GAN               0x314
 223 #define YEE_G_OFT               0x318
 224
 225 /* Chroma Artifact Reduction */
 226 #define CAR_EN                  0x31c
 227 #define CAR_TYP                 0x320
 228 #define CAR_SW                  0x324
 229 #define CAR_HPF_TYP             0x328
 230 #define CAR_HPF_SHF             0x32c
 231 #define CAR_HPF_THR             0x330
 232 #define CAR_GN1_GAN             0x334
 233 #define CAR_GN1_SHF             0x338
 234 #define CAR_GN1_MIN             0x33c
 235 #define CAR_GN2_GAN             0x340
 236 #define CAR_GN2_SHF             0x344
 237 #define CAR_GN2_MIN             0x348
 238
 239 /* Chroma Gain Suppression */
 240 #define CGS_EN                  0x34c
 241 #define CGS_GN1_L_THR           0x350
 242 #define CGS_GN1_L_GAN           0x354
 243 #define CGS_GN1_L_SHF           0x358
 244 #define CGS_GN1_L_MIN           0x35c
 245 #define CGS_GN1_H_THR           0x360
 246 #define CGS_GN1_H_GAN           0x364
 247 #define CGS_GN1_H_SHF           0x368
 248 #define CGS_GN1_H_MIN           0x36c
 249 #define CGS_GN2_L_THR           0x370
 250 #define CGS_GN2_L_GAN           0x374
 251 #define CGS_GN2_L_SHF           0x378
 252 #define CGS_GN2_L_MIN           0x37c
 253
 254 /* Resizer */
 255 #define RSZ_SRC_EN              0x0
 256 #define RSZ_SRC_MODE            0x4
 257 #define RSZ_SRC_FMT0            0x8
 258 #define RSZ_SRC_FMT1            0xc
 259 #define RSZ_SRC_VPS             0x10
 260 #define RSZ_SRC_VSZ             0x14
 261 #define RSZ_SRC_HPS             0x18
 262 #define RSZ_SRC_HSZ             0x1c
 263 #define RSZ_DMA_RZA             0x20
 264 #define RSZ_DMA_RZB             0x24
 265 #define RSZ_DMA_STA             0x28
 266 #define RSZ_GCK_MMR             0x2c
 267 #define RSZ_RESERVED0           0x30
 268 #define RSZ_GCK_SDR             0x34
 269 #define RSZ_IRQ_RZA             0x38
 270 #define RSZ_IRQ_RZB             0x3c
 271 #define RSZ_YUV_Y_MIN           0x40
 272 #define RSZ_YUV_Y_MAX           0x44
 273 #define RSZ_YUV_C_MIN           0x48
 274 #define RSZ_YUV_C_MAX           0x4c
 275 #define RSZ_YUV_PHS             0x50
 276 #define RSZ_SEQ                 0x54
 277
 278 /* Resizer Rescale Parameters */
 279 #define RSZ_EN_A                0x58
 280 #define RSZ_EN_B                0xe8
 281 /* offset of the registers to be added with base register of
 282    either RSZ0 or RSZ1
 283 */
 284 #define RSZ_MODE                0x4
 285 #define RSZ_420                 0x8
 286 #define RSZ_I_VPS               0xc
 287 #define RSZ_I_HPS               0x10
 288 #define RSZ_O_VSZ               0x14
 289 #define RSZ_O_HSZ               0x18
 290 #define RSZ_V_PHS_Y             0x1c
 291 #define RSZ_V_PHS_C             0x20
 292 #define RSZ_V_DIF               0x24
 293 #define RSZ_V_TYP               0x28
 294 #define RSZ_V_LPF               0x2c
 295 #define RSZ_H_PHS               0x30
 296 #define RSZ_H_PHS_ADJ           0x34
 297 #define RSZ_H_DIF               0x38
 298 #define RSZ_H_TYP               0x3c
 299 #define RSZ_H_LPF               0x40
 300 #define RSZ_DWN_EN              0x44
 301 #define RSZ_DWN_AV              0x48
 302
 303 /* Resizer RGB Conversion Parameters */
 304 #define RSZ_RGB_EN              0x4c
 305 #define RSZ_RGB_TYP             0x50
 306 #define RSZ_RGB_BLD             0x54
 307
 308 /* Resizer External Memory Parameters */
 309 #define RSZ_SDR_Y_BAD_H         0x58
 310 #define RSZ_SDR_Y_BAD_L         0x5c
 311 #define RSZ_SDR_Y_SAD_H         0x60
 312 #define RSZ_SDR_Y_SAD_L         0x64
 313 #define RSZ_SDR_Y_OFT           0x68
 314 #define RSZ_SDR_Y_PTR_S         0x6c
 315 #define RSZ_SDR_Y_PTR_E         0x70
 316 #define RSZ_SDR_C_BAD_H         0x74
 317 #define RSZ_SDR_C_BAD_L         0x78
 318 #define RSZ_SDR_C_SAD_H         0x7c
 319 #define RSZ_SDR_C_SAD_L         0x80
 320 #define RSZ_SDR_C_OFT           0x84
 321 #define RSZ_SDR_C_PTR_S         0x88
 322 #define RSZ_SDR_C_PTR_E         0x8c
 323
 324 /* Macro for resizer */
 325 #define RSZ_YUV_Y_MIN           0x40
 326 #define RSZ_YUV_Y_MAX           0x44
 327 #define RSZ_YUV_C_MIN           0x48
 328 #define RSZ_YUV_C_MAX           0x4c
 329
 330 #define IPIPE_GCK_MMR_DEFAULT   1
 331 #define IPIPE_GCK_PIX_DEFAULT   0xe
 332 #define RSZ_GCK_MMR_DEFAULT     1
 333 #define RSZ_GCK_SDR_DEFAULT     1
 334
 335 /* LUTDPC */
 336 #define LUTDPC_TBL_256_EN       0
 337 #define LUTDPC_INF_TBL_EN       1
 338 #define LUT_DPC_START_ADDR      0
 339 #define LUT_DPC_H_POS_MASK      0x1fff
 340 #define LUT_DPC_V_POS_MASK      0x1fff
 341 #define LUT_DPC_V_POS_SHIFT     13
 342 #define LUT_DPC_CORR_METH_SHIFT 26
 343 #define LUT_DPC_MAX_SIZE        256
 344 #define LUT_DPC_SIZE_MASK       0x3ff
 345
 346 /* OTFDPC */
 347 #define OTFDPC_DPC2_THR_MASK    0xfff
 348 #define OTF_DET_METHOD_SHIFT    1
 349 #define OTF_DPC3_0_SHF_MASK     3
 350 #define OTF_DPC3_0_THR_SHIFT    6
 351 #define OTF_DPC3_0_THR_MASK     0x3f
 352 #define OTF_DPC3_0_SLP_MASK     0x3f
 353 #define OTF_DPC3_0_DET_MASK     0xfff
 354 #define OTF_DPC3_0_CORR_MASK    0xfff
 355
 356 /* NF (D2F) */
 357 #define D2F_SPR_VAL_MASK                0x1f
 358 #define D2F_SPR_VAL_SHIFT               0
 359 #define D2F_SHFT_VAL_MASK               3
 360 #define D2F_SHFT_VAL_SHIFT              5
 361 #define D2F_SAMPLE_METH_SHIFT           7
 362 #define D2F_APPLY_LSC_GAIN_SHIFT        8
 363 #define D2F_USE_SPR_REG_VAL             0
 364 #define D2F_STR_VAL_MASK                0x1f
 365 #define D2F_THR_VAL_MASK                0x3ff
 366 #define D2F_EDGE_DET_THR_MASK           0x7ff
 367
 368 /* Green Imbalance Correction */
 369 #define GIC_TYP_SHIFT                   0
 370 #define GIC_THR_SEL_SHIFT               1
 371 #define GIC_APPLY_LSC_GAIN_SHIFT        2
 372 #define GIC_GAIN_MASK                   0xff
 373 #define GIC_THR_MASK                    0xfff
 374 #define GIC_SLOPE_MASK                  0xfff
 375 #define GIC_NFGAN_INT_MASK              7
 376 #define GIC_NFGAN_DECI_MASK             0x1f
 377
 378 /* WB */
 379 #define WB_OFFSET_MASK                  0xfff
 380 #define WB_GAIN_INT_MASK                0xf
 381 #define WB_GAIN_DECI_MASK               0x1ff
 382
 383 /* CFA */
 384 #define CFA_HPF_THR_2DIR_MASK           0x1fff
 385 #define CFA_HPF_SLOPE_2DIR_MASK         0x3ff
 386 #define CFA_HPF_MIX_THR_2DIR_MASK       0x1fff
 387 #define CFA_HPF_MIX_SLP_2DIR_MASK       0x3ff
 388 #define CFA_DIR_THR_2DIR_MASK           0x3ff
 389 #define CFA_DIR_SLP_2DIR_MASK           0x7f
 390 #define CFA_ND_WT_2DIR_MASK             0x3f
 391 #define CFA_DAA_HUE_FRA_MASK            0x3f
 392 #define CFA_DAA_EDG_THR_MASK            0xff
 393 #define CFA_DAA_THR_MIN_MASK            0x3ff
 394 #define CFA_DAA_THR_SLP_MASK            0x3ff
 395 #define CFA_DAA_SLP_MIN_MASK            0x3ff
 396 #define CFA_DAA_SLP_SLP_MASK            0x3ff
 397 #define CFA_DAA_LP_WT_MASK              0x3f
 398
 399 /* RGB2RGB */
 400 #define RGB2RGB_1_OFST_MASK             0x1fff
 401 #define RGB2RGB_1_GAIN_INT_MASK         0xf
 402 #define RGB2RGB_GAIN_DECI_MASK          0xff
 403 #define RGB2RGB_2_OFST_MASK             0x7ff
 404 #define RGB2RGB_2_GAIN_INT_MASK         0x7
 405
 406 /* Gamma */
 407 #define GAMMA_BYPR_SHIFT                0
 408 #define GAMMA_BYPG_SHIFT                1
 409 #define GAMMA_BYPB_SHIFT                2
 410 #define GAMMA_TBL_SEL_SHIFT             4
 411 #define GAMMA_TBL_SIZE_SHIFT            5
 412 #define GAMMA_MASK                      0x3ff
 413 #define GAMMA_SHIFT                     10
 414
 415 /* 3D LUT */
 416 #define D3_LUT_ENTRY_MASK               0x3ff
 417 #define D3_LUT_ENTRY_R_SHIFT            20
 418 #define D3_LUT_ENTRY_G_SHIFT            10
 419 #define D3_LUT_ENTRY_B_SHIFT            0
 420
 421 /* Lumina adj */
 422 #define LUM_ADJ_CONTR_SHIFT             0
 423 #define LUM_ADJ_BRIGHT_SHIFT            8
 424
 425 /* RGB2YCbCr */
 426 #define RGB2YCBCR_OFST_MASK             0x7ff
 427 #define RGB2YCBCR_COEF_INT_MASK         0xf
 428 #define RGB2YCBCR_COEF_DECI_MASK        0xff
 429
 430 /* GBCE */
 431 #define GBCE_Y_VAL_MASK                 0xff
 432 #define GBCE_GAIN_VAL_MASK              0x3ff
 433 #define GBCE_ENTRY_SHIFT                10
 434
 435 /* Edge Enhancements */
 436 #define YEE_HALO_RED_EN_SHIFT           1
 437 #define YEE_HPF_SHIFT_MASK              0xf
 438 #define YEE_COEF_MASK                   0x3ff
 439 #define YEE_THR_MASK                    0x3f
 440 #define YEE_ES_GAIN_MASK                0xfff
 441 #define YEE_ES_THR1_MASK                0xfff
 442 #define YEE_ENTRY_SHIFT                 9
 443 #define YEE_ENTRY_MASK                  0x1ff
 444
 445 /* CAR */
 446 #define CAR_MF_THR                      0xff
 447 #define CAR_SW1_SHIFT                   8
 448 #define CAR_GAIN1_SHFT_MASK             7
 449 #define CAR_GAIN_MIN_MASK               0x1ff
 450 #define CAR_GAIN2_SHFT_MASK             0xf
 451 #define CAR_HPF_SHIFT_MASK              3
 452
 453 /* CGS */
 454 #define CAR_SHIFT_MASK                  3
 455
 456 /* Resizer */
 457 #define RSZ_BYPASS_SHIFT                1
 458 #define RSZ_SRC_IMG_FMT_SHIFT           1
 459 #define RSZ_SRC_Y_C_SEL_SHIFT           2
 460 #define IPIPE_RSZ_VPS_MASK              0xffff
 461 #define IPIPE_RSZ_HPS_MASK              0xffff
 462 #define IPIPE_RSZ_VSZ_MASK              0x1fff
 463 #define IPIPE_RSZ_HSZ_MASK              0x1fff
 464 #define RSZ_HPS_MASK                    0x1fff
 465 #define RSZ_VPS_MASK                    0x1fff
 466 #define RSZ_O_HSZ_MASK                  0x1fff
 467 #define RSZ_O_VSZ_MASK                  0x1fff
 468 #define RSZ_V_PHS_MASK                  0x3fff
 469 #define RSZ_V_DIF_MASK                  0x3fff
 470
 471 #define RSZA_H_FLIP_SHIFT               0
 472 #define RSZA_V_FLIP_SHIFT               1
 473 #define RSZB_H_FLIP_SHIFT               2
 474 #define RSZB_V_FLIP_SHIFT               3
 475 #define RSZ_A                           0
 476 #define RSZ_B                           1
 477 #define RSZ_CEN_SHIFT                   1
 478 #define RSZ_YEN_SHIFT                   0
 479 #define RSZ_TYP_Y_SHIFT                 0
 480 #define RSZ_TYP_C_SHIFT                 1
 481 #define RSZ_LPF_INT_MASK                0x3f
 482 #define RSZ_LPF_INT_C_SHIFT             6
 483 #define RSZ_H_PHS_MASK                  0x3fff
 484 #define RSZ_H_DIF_MASK                  0x3fff
 485 #define RSZ_DIFF_DOWN_THR               256
 486 #define RSZ_DWN_SCALE_AV_SZ_V_SHIFT     3
 487 #define RSZ_DWN_SCALE_AV_SZ_MASK        7
 488 #define RSZ_RGB_MSK1_SHIFT              2
 489 #define RSZ_RGB_MSK0_SHIFT              1
 490 #define RSZ_RGB_TYP_SHIFT               0
 491 #define RSZ_RGB_ALPHA_MASK              0xff
 492
 493 static inline u32 regr_ip(void __iomem *addr, u32 offset)
 494 {
 495         return readl(addr + offset);
 496 }
 497
 498 static inline void regw_ip(void __iomem *addr, u32 val, u32 offset)
 499 {
 500         writel(val, addr + offset);
 501 }
 502
 503 static inline u32 w_ip_table(void __iomem *addr, u32 val, u32 offset)
 504 {
 505         writel(val, addr + offset);
 506
 507         return val;
 508 }
 509
 510 static inline u32 regr_rsz(void __iomem *addr, u32 offset)
 511 {
 512         return readl(addr + offset);
 513 }
 514
 515 static inline u32 regw_rsz(void __iomem *addr, u32 val, u32 offset)
 516 {
 517         writel(val, addr + offset);
 518
 519         return val;
 520 }
 521
 522 int config_ipipe_hw(struct vpfe_ipipe_device *ipipe);
 523 int resizer_set_outaddr(void __iomem *rsz_base, struct resizer_params *params,
 524                         int resize_no, unsigned int address);
 525 int rsz_enable(void __iomem *rsz_base, int rsz_id, int enable);
 526 void rsz_src_enable(void __iomem *rsz_base, int enable);
 527 void rsz_set_in_pix_format(unsigned char y_c);
 528 int config_rsz_hw(struct vpfe_resizer_device *resizer,
 529                   struct resizer_params *config);
 530 void ipipe_set_d2f_regs(void __iomem *base_addr, unsigned int id,
 531         struct vpfe_ipipe_nf *noise_filter);
 532 void ipipe_set_rgb2rgb_regs(void __iomem *base_addr, unsigned int id,
 533         struct vpfe_ipipe_rgb2rgb *rgb);
 534 void ipipe_set_yuv422_conv_regs(void __iomem *base_addr,
 535         struct vpfe_ipipe_yuv422_conv *conv);
 536 void ipipe_set_lum_adj_regs(void __iomem *base_addr,
 537         struct ipipe_lum_adj *lum_adj);
 538 void ipipe_set_rgb2ycbcr_regs(void __iomem *base_addr,
 539         struct vpfe_ipipe_rgb2yuv *yuv);
 540 void ipipe_set_lutdpc_regs(void __iomem *base_addr,
 541         void __iomem *isp5_base_addr, struct vpfe_ipipe_lutdpc *lutdpc);
 542 void ipipe_set_otfdpc_regs(void __iomem *base_addr,
 543         struct vpfe_ipipe_otfdpc *otfdpc);
 544 void ipipe_set_3d_lut_regs(void __iomem *base_addr,
 545         void __iomem *isp5_base_addr, struct vpfe_ipipe_3d_lut *lut_3d);
 546 void ipipe_set_gamma_regs(void __iomem *base_addr,
 547         void __iomem *isp5_base_addr, struct vpfe_ipipe_gamma *gamma);
 548 void ipipe_set_ee_regs(void __iomem *base_addr,
 549         void __iomem *isp5_base_addr, struct vpfe_ipipe_yee *ee);
 550 void ipipe_set_gbce_regs(void __iomem *base_addr,
 551         void __iomem *isp5_base_addr, struct vpfe_ipipe_gbce *gbce);
 552 void ipipe_set_gic_regs(void __iomem *base_addr, struct vpfe_ipipe_gic *gic);
 553 void ipipe_set_cfa_regs(void __iomem *base_addr, struct vpfe_ipipe_cfa *cfa);
 554 void ipipe_set_car_regs(void __iomem *base_addr, struct vpfe_ipipe_car *car);
 555 void ipipe_set_cgs_regs(void __iomem *base_addr, struct vpfe_ipipe_cgs *cgs);
 556 void ipipe_set_wb_regs(void __iomem *base_addr, struct vpfe_ipipe_wb *wb);
 557
 558 #endif          /* _DAVINCI_VPFE_DM365_IPIPE_HW_H */