kernel/drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 #include <linux/interrupt.h>
  56 #include <linux/sched.h>
  57 #include <linux/delay.h>
  58 #include "8255.h"
  59 #include "mite.h"
  60
  61 /* A timeout count */
  62 #define NI_TIMEOUT 1000
  63 static const unsigned old_RTSI_clock_channel = 7;
  64
  65 /* Note: this table must match the ai_gain_* definitions */
  66 static const short ni_gainlkup[][16] = {
  67         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  68                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  69         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  70         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  71                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  72         [ai_gain_4] = {0, 1, 4, 7},
  73         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  74                           0x003, 0x004, 0x005, 0x006},
  75         [ai_gain_622x] = {0, 1, 4, 5},
  76         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  77         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  78 };
  79
  80 static const struct comedi_lrange range_ni_E_ai = {
  81         16, {
  82                 BIP_RANGE(10),
  83                 BIP_RANGE(5),
  84                 BIP_RANGE(2.5),
  85                 BIP_RANGE(1),
  86                 BIP_RANGE(0.5),
  87                 BIP_RANGE(0.25),
  88                 BIP_RANGE(0.1),
  89                 BIP_RANGE(0.05),
  90                 UNI_RANGE(20),
  91                 UNI_RANGE(10),
  92                 UNI_RANGE(5),
  93                 UNI_RANGE(2),
  94                 UNI_RANGE(1),
  95                 UNI_RANGE(0.5),
  96                 UNI_RANGE(0.2),
  97                 UNI_RANGE(0.1)
  98         }
  99 };
 100
 101 static const struct comedi_lrange range_ni_E_ai_limited = {
 102         8, {
 103                 BIP_RANGE(10),
 104                 BIP_RANGE(5),
 105                 BIP_RANGE(1),
 106                 BIP_RANGE(0.1),
 107                 UNI_RANGE(10),
 108                 UNI_RANGE(5),
 109                 UNI_RANGE(1),
 110                 UNI_RANGE(0.1)
 111         }
 112 };
 113
 114 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 115         14, {
 116                 BIP_RANGE(10),
 117                 BIP_RANGE(5),
 118                 BIP_RANGE(2),
 119                 BIP_RANGE(1),
 120                 BIP_RANGE(0.5),
 121                 BIP_RANGE(0.2),
 122                 BIP_RANGE(0.1),
 123                 UNI_RANGE(10),
 124                 UNI_RANGE(5),
 125                 UNI_RANGE(2),
 126                 UNI_RANGE(1),
 127                 UNI_RANGE(0.5),
 128                 UNI_RANGE(0.2),
 129                 UNI_RANGE(0.1)
 130         }
 131 };
 132
 133 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 134         4, {
 135                 BIP_RANGE(10),
 136                 BIP_RANGE(5),
 137                 BIP_RANGE(0.5),
 138                 BIP_RANGE(0.05)
 139         }
 140 };
 141
 142 static const struct comedi_lrange range_ni_E_ai_611x = {
 143         8, {
 144                 BIP_RANGE(50),
 145                 BIP_RANGE(20),
 146                 BIP_RANGE(10),
 147                 BIP_RANGE(5),
 148                 BIP_RANGE(2),
 149                 BIP_RANGE(1),
 150                 BIP_RANGE(0.5),
 151                 BIP_RANGE(0.2)
 152         }
 153 };
 154
 155 static const struct comedi_lrange range_ni_M_ai_622x = {
 156         4, {
 157                 BIP_RANGE(10),
 158                 BIP_RANGE(5),
 159                 BIP_RANGE(1),
 160                 BIP_RANGE(0.2)
 161         }
 162 };
 163
 164 static const struct comedi_lrange range_ni_M_ai_628x = {
 165         7, {
 166                 BIP_RANGE(10),
 167                 BIP_RANGE(5),
 168                 BIP_RANGE(2),
 169                 BIP_RANGE(1),
 170                 BIP_RANGE(0.5),
 171                 BIP_RANGE(0.2),
 172                 BIP_RANGE(0.1)
 173         }
 174 };
 175
 176 static const struct comedi_lrange range_ni_E_ao_ext = {
 177         4, {
 178                 BIP_RANGE(10),
 179                 UNI_RANGE(10),
 180                 RANGE_ext(-1, 1),
 181                 RANGE_ext(0, 1)
 182         }
 183 };
 184
 185 static const struct comedi_lrange *const ni_range_lkup[] = {
 186         [ai_gain_16] = &range_ni_E_ai,
 187         [ai_gain_8] = &range_ni_E_ai_limited,
 188         [ai_gain_14] = &range_ni_E_ai_limited14,
 189         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 190         [ai_gain_611x] = &range_ni_E_ai_611x,
 191         [ai_gain_622x] = &range_ni_M_ai_622x,
 192         [ai_gain_628x] = &range_ni_M_ai_628x,
 193         [ai_gain_6143] = &range_bipolar5
 194 };
 195
 196 enum aimodes {
 197         AIMODE_NONE = 0,
 198         AIMODE_HALF_FULL = 1,
 199         AIMODE_SCAN = 2,
 200         AIMODE_SAMPLE = 3,
 201 };
 202
 203 enum ni_common_subdevices {
 204         NI_AI_SUBDEV,
 205         NI_AO_SUBDEV,
 206         NI_DIO_SUBDEV,
 207         NI_8255_DIO_SUBDEV,
 208         NI_UNUSED_SUBDEV,
 209         NI_CALIBRATION_SUBDEV,
 210         NI_EEPROM_SUBDEV,
 211         NI_PFI_DIO_SUBDEV,
 212         NI_CS5529_CALIBRATION_SUBDEV,
 213         NI_SERIAL_SUBDEV,
 214         NI_RTSI_SUBDEV,
 215         NI_GPCT0_SUBDEV,
 216         NI_GPCT1_SUBDEV,
 217         NI_FREQ_OUT_SUBDEV,
 218         NI_NUM_SUBDEVICES
 219 };
 220 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 221 {
 222         switch (counter_index) {
 223         case 0:
 224                 return NI_GPCT0_SUBDEV;
 225         case 1:
 226                 return NI_GPCT1_SUBDEV;
 227         default:
 228                 break;
 229         }
 230         BUG();
 231         return NI_GPCT0_SUBDEV;
 232 }
 233
 234 enum timebase_nanoseconds {
 235         TIMEBASE_1_NS = 50,
 236         TIMEBASE_2_NS = 10000
 237 };
 238
 239 #define SERIAL_DISABLED         0
 240 #define SERIAL_600NS            600
 241 #define SERIAL_1_2US            1200
 242 #define SERIAL_10US                     10000
 243
 244 static const int num_adc_stages_611x = 3;
 245
 246 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
 247 {
 248         if (dev->mmio)
 249                 writel(data, dev->mmio + reg);
 250
 251         outl(data, dev->iobase + reg);
 252 }
 253
 254 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
 255 {
 256         if (dev->mmio)
 257                 writew(data, dev->mmio + reg);
 258
 259         outw(data, dev->iobase + reg);
 260 }
 261
 262 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
 263 {
 264         if (dev->mmio)
 265                 writeb(data, dev->mmio + reg);
 266
 267         outb(data, dev->iobase + reg);
 268 }
 269
 270 static uint32_t ni_readl(struct comedi_device *dev, int reg)
 271 {
 272         if (dev->mmio)
 273                 return readl(dev->mmio + reg);
 274
 275         return inl(dev->iobase + reg);
 276 }
 277
 278 static uint16_t ni_readw(struct comedi_device *dev, int reg)
 279 {
 280         if (dev->mmio)
 281                 return readw(dev->mmio + reg);
 282
 283         return inw(dev->iobase + reg);
 284 }
 285
 286 static uint8_t ni_readb(struct comedi_device *dev, int reg)
 287 {
 288         if (dev->mmio)
 289                 return readb(dev->mmio + reg);
 290
 291         return inb(dev->iobase + reg);
 292 }
 293
 294 /*
 295  * We automatically take advantage of STC registers that can be
 296  * read/written directly in the I/O space of the board.
 297  *
 298  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 299  * iobase+reg*2.
 300  *
 301  * Most PCIMIO devices also map the low 8 STC registers but the
 302  * 611x devices map the read registers to iobase+(addr-1)*2.
 303  * For now non-windowed STC access is disabled if a PCIMIO device
 304  * is detected (devpriv->mite has been initialized).
 305  *
 306  * The M series devices do not used windowed registers for the
 307  * STC registers. The functions below handle the mapping of the
 308  * windowed STC registers to the m series register offsets.
 309  */
 310
 311 static void m_series_stc_writel(struct comedi_device *dev,
 312                                 uint32_t data, int reg)
 313 {
 314         unsigned offset;
 315
 316         switch (reg) {
 317         case AI_SC_Load_A_Registers:
 318                 offset = M_Offset_AI_SC_Load_A;
 319                 break;
 320         case AI_SI_Load_A_Registers:
 321                 offset = M_Offset_AI_SI_Load_A;
 322                 break;
 323         case AO_BC_Load_A_Register:
 324                 offset = M_Offset_AO_BC_Load_A;
 325                 break;
 326         case AO_UC_Load_A_Register:
 327                 offset = M_Offset_AO_UC_Load_A;
 328                 break;
 329         case AO_UI_Load_A_Register:
 330                 offset = M_Offset_AO_UI_Load_A;
 331                 break;
 332         case G_Load_A_Register(0):
 333                 offset = M_Offset_G0_Load_A;
 334                 break;
 335         case G_Load_A_Register(1):
 336                 offset = M_Offset_G1_Load_A;
 337                 break;
 338         case G_Load_B_Register(0):
 339                 offset = M_Offset_G0_Load_B;
 340                 break;
 341         case G_Load_B_Register(1):
 342                 offset = M_Offset_G1_Load_B;
 343                 break;
 344         default:
 345                 dev_warn(dev->class_dev,
 346                          "%s: bug! unhandled register=0x%x in switch\n",
 347                          __func__, reg);
 348                 return;
 349         }
 350         ni_writel(dev, data, offset);
 351 }
 352
 353 static void m_series_stc_writew(struct comedi_device *dev,
 354                                 uint16_t data, int reg)
 355 {
 356         unsigned offset;
 357
 358         switch (reg) {
 359         case ADC_FIFO_Clear:
 360                 offset = M_Offset_AI_FIFO_Clear;
 361                 break;
 362         case AI_Command_1_Register:
 363                 offset = M_Offset_AI_Command_1;
 364                 break;
 365         case AI_Command_2_Register:
 366                 offset = M_Offset_AI_Command_2;
 367                 break;
 368         case AI_Mode_1_Register:
 369                 offset = M_Offset_AI_Mode_1;
 370                 break;
 371         case AI_Mode_2_Register:
 372                 offset = M_Offset_AI_Mode_2;
 373                 break;
 374         case AI_Mode_3_Register:
 375                 offset = M_Offset_AI_Mode_3;
 376                 break;
 377         case AI_Output_Control_Register:
 378                 offset = M_Offset_AI_Output_Control;
 379                 break;
 380         case AI_Personal_Register:
 381                 offset = M_Offset_AI_Personal;
 382                 break;
 383         case AI_SI2_Load_A_Register:
 384                 /* this is a 32 bit register on m series boards */
 385                 ni_writel(dev, data, M_Offset_AI_SI2_Load_A);
 386                 return;
 387         case AI_SI2_Load_B_Register:
 388                 /* this is a 32 bit register on m series boards */
 389                 ni_writel(dev, data, M_Offset_AI_SI2_Load_B);
 390                 return;
 391         case AI_START_STOP_Select_Register:
 392                 offset = M_Offset_AI_START_STOP_Select;
 393                 break;
 394         case AI_Trigger_Select_Register:
 395                 offset = M_Offset_AI_Trigger_Select;
 396                 break;
 397         case Analog_Trigger_Etc_Register:
 398                 offset = M_Offset_Analog_Trigger_Etc;
 399                 break;
 400         case AO_Command_1_Register:
 401                 offset = M_Offset_AO_Command_1;
 402                 break;
 403         case AO_Command_2_Register:
 404                 offset = M_Offset_AO_Command_2;
 405                 break;
 406         case AO_Mode_1_Register:
 407                 offset = M_Offset_AO_Mode_1;
 408                 break;
 409         case AO_Mode_2_Register:
 410                 offset = M_Offset_AO_Mode_2;
 411                 break;
 412         case AO_Mode_3_Register:
 413                 offset = M_Offset_AO_Mode_3;
 414                 break;
 415         case AO_Output_Control_Register:
 416                 offset = M_Offset_AO_Output_Control;
 417                 break;
 418         case AO_Personal_Register:
 419                 offset = M_Offset_AO_Personal;
 420                 break;
 421         case AO_Start_Select_Register:
 422                 offset = M_Offset_AO_Start_Select;
 423                 break;
 424         case AO_Trigger_Select_Register:
 425                 offset = M_Offset_AO_Trigger_Select;
 426                 break;
 427         case Clock_and_FOUT_Register:
 428                 offset = M_Offset_Clock_and_FOUT;
 429                 break;
 430         case Configuration_Memory_Clear:
 431                 offset = M_Offset_Configuration_Memory_Clear;
 432                 break;
 433         case DAC_FIFO_Clear:
 434                 offset = M_Offset_AO_FIFO_Clear;
 435                 break;
 436         case DIO_Control_Register:
 437                 dev_dbg(dev->class_dev,
 438                         "%s: FIXME: register 0x%x does not map cleanly on to m-series boards\n",
 439                         __func__, reg);
 440                 return;
 441         case G_Autoincrement_Register(0):
 442                 offset = M_Offset_G0_Autoincrement;
 443                 break;
 444         case G_Autoincrement_Register(1):
 445                 offset = M_Offset_G1_Autoincrement;
 446                 break;
 447         case G_Command_Register(0):
 448                 offset = M_Offset_G0_Command;
 449                 break;
 450         case G_Command_Register(1):
 451                 offset = M_Offset_G1_Command;
 452                 break;
 453         case G_Input_Select_Register(0):
 454                 offset = M_Offset_G0_Input_Select;
 455                 break;
 456         case G_Input_Select_Register(1):
 457                 offset = M_Offset_G1_Input_Select;
 458                 break;
 459         case G_Mode_Register(0):
 460                 offset = M_Offset_G0_Mode;
 461                 break;
 462         case G_Mode_Register(1):
 463                 offset = M_Offset_G1_Mode;
 464                 break;
 465         case Interrupt_A_Ack_Register:
 466                 offset = M_Offset_Interrupt_A_Ack;
 467                 break;
 468         case Interrupt_A_Enable_Register:
 469                 offset = M_Offset_Interrupt_A_Enable;
 470                 break;
 471         case Interrupt_B_Ack_Register:
 472                 offset = M_Offset_Interrupt_B_Ack;
 473                 break;
 474         case Interrupt_B_Enable_Register:
 475                 offset = M_Offset_Interrupt_B_Enable;
 476                 break;
 477         case Interrupt_Control_Register:
 478                 offset = M_Offset_Interrupt_Control;
 479                 break;
 480         case IO_Bidirection_Pin_Register:
 481                 offset = M_Offset_IO_Bidirection_Pin;
 482                 break;
 483         case Joint_Reset_Register:
 484                 offset = M_Offset_Joint_Reset;
 485                 break;
 486         case RTSI_Trig_A_Output_Register:
 487                 offset = M_Offset_RTSI_Trig_A_Output;
 488                 break;
 489         case RTSI_Trig_B_Output_Register:
 490                 offset = M_Offset_RTSI_Trig_B_Output;
 491                 break;
 492         case RTSI_Trig_Direction_Register:
 493                 offset = M_Offset_RTSI_Trig_Direction;
 494                 break;
 495         /*
 496          * FIXME: DIO_Output_Register (16 bit reg) is replaced by
 497          * M_Offset_Static_Digital_Output (32 bit) and
 498          * M_Offset_SCXI_Serial_Data_Out (8 bit)
 499          */
 500         default:
 501                 dev_warn(dev->class_dev,
 502                          "%s: bug! unhandled register=0x%x in switch\n",
 503                          __func__, reg);
 504                 return;
 505         }
 506         ni_writew(dev, data, offset);
 507 }
 508
 509 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
 510 {
 511         unsigned offset;
 512
 513         switch (reg) {
 514         case G_HW_Save_Register(0):
 515                 offset = M_Offset_G0_HW_Save;
 516                 break;
 517         case G_HW_Save_Register(1):
 518                 offset = M_Offset_G1_HW_Save;
 519                 break;
 520         case G_Save_Register(0):
 521                 offset = M_Offset_G0_Save;
 522                 break;
 523         case G_Save_Register(1):
 524                 offset = M_Offset_G1_Save;
 525                 break;
 526         default:
 527                 dev_warn(dev->class_dev,
 528                          "%s: bug! unhandled register=0x%x in switch\n",
 529                          __func__, reg);
 530                 return 0;
 531         }
 532         return ni_readl(dev, offset);
 533 }
 534
 535 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
 536 {
 537         unsigned offset;
 538
 539         switch (reg) {
 540         case AI_Status_1_Register:
 541                 offset = M_Offset_AI_Status_1;
 542                 break;
 543         case AO_Status_1_Register:
 544                 offset = M_Offset_AO_Status_1;
 545                 break;
 546         case AO_Status_2_Register:
 547                 offset = M_Offset_AO_Status_2;
 548                 break;
 549         case DIO_Serial_Input_Register:
 550                 return ni_readb(dev, M_Offset_SCXI_Serial_Data_In);
 551         case Joint_Status_1_Register:
 552                 offset = M_Offset_Joint_Status_1;
 553                 break;
 554         case Joint_Status_2_Register:
 555                 offset = M_Offset_Joint_Status_2;
 556                 break;
 557         case G_Status_Register:
 558                 offset = M_Offset_G01_Status;
 559                 break;
 560         default:
 561                 dev_warn(dev->class_dev,
 562                          "%s: bug! unhandled register=0x%x in switch\n",
 563                          __func__, reg);
 564                 return 0;
 565         }
 566         return ni_readw(dev, offset);
 567 }
 568
 569 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
 570 {
 571         struct ni_private *devpriv = dev->private;
 572         unsigned long flags;
 573
 574         if (devpriv->is_m_series) {
 575                 m_series_stc_writew(dev, data, reg);
 576         } else {
 577                 spin_lock_irqsave(&devpriv->window_lock, flags);
 578                 if (!devpriv->mite && reg < 8) {
 579                         ni_writew(dev, data, reg * 2);
 580                 } else {
 581                         ni_writew(dev, reg, Window_Address);
 582                         ni_writew(dev, data, Window_Data);
 583                 }
 584                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 585         }
 586 }
 587
 588 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
 589 {
 590         struct ni_private *devpriv = dev->private;
 591
 592         if (devpriv->is_m_series) {
 593                 m_series_stc_writel(dev, data, reg);
 594         } else {
 595                 ni_stc_writew(dev, data >> 16, reg);
 596                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 597         }
 598 }
 599
 600 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
 601 {
 602         struct ni_private *devpriv = dev->private;
 603         unsigned long flags;
 604         uint16_t val;
 605
 606         if (devpriv->is_m_series) {
 607                 val = m_series_stc_readw(dev, reg);
 608         } else {
 609                 spin_lock_irqsave(&devpriv->window_lock, flags);
 610                 if (!devpriv->mite && reg < 8) {
 611                         val = ni_readw(dev, reg * 2);
 612                 } else {
 613                         ni_writew(dev, reg, Window_Address);
 614                         val = ni_readw(dev, Window_Data);
 615                 }
 616                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 617         }
 618         return val;
 619 }
 620
 621 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
 622 {
 623         struct ni_private *devpriv = dev->private;
 624         uint32_t val;
 625
 626         if (devpriv->is_m_series) {
 627                 val = m_series_stc_readl(dev, reg);
 628         } else {
 629                 val = ni_stc_readw(dev, reg) << 16;
 630                 val |= ni_stc_readw(dev, reg + 1);
 631         }
 632         return val;
 633 }
 634
 635 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 636                                    unsigned bit_mask, unsigned bit_values)
 637 {
 638         struct ni_private *devpriv = dev->private;
 639         unsigned long flags;
 640
 641         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 642         switch (reg) {
 643         case Interrupt_A_Enable_Register:
 644                 devpriv->int_a_enable_reg &= ~bit_mask;
 645                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 646                 ni_stc_writew(dev, devpriv->int_a_enable_reg,
 647                               Interrupt_A_Enable_Register);
 648                 break;
 649         case Interrupt_B_Enable_Register:
 650                 devpriv->int_b_enable_reg &= ~bit_mask;
 651                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 652                 ni_stc_writew(dev, devpriv->int_b_enable_reg,
 653                               Interrupt_B_Enable_Register);
 654                 break;
 655         case IO_Bidirection_Pin_Register:
 656                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 657                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 658                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg,
 659                               IO_Bidirection_Pin_Register);
 660                 break;
 661         case AI_AO_Select:
 662                 devpriv->ai_ao_select_reg &= ~bit_mask;
 663                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 664                 ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
 665                 break;
 666         case G0_G1_Select:
 667                 devpriv->g0_g1_select_reg &= ~bit_mask;
 668                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 669                 ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
 670                 break;
 671         default:
 672                 dev_err(dev->class_dev, "called with invalid register %d\n",
 673                         reg);
 674                 break;
 675         }
 676         mmiowb();
 677         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 678 }
 679
 680 #ifdef PCIDMA
 681 /* DMA channel setup */
 682
 683 /* negative channel means no channel */
 684 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 685 {
 686         unsigned bitfield;
 687
 688         if (channel >= 0)
 689                 bitfield =
 690                     (ni_stc_dma_channel_select_bitfield(channel) <<
 691                      AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 692         else
 693                 bitfield = 0;
 694         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 695 }
 696
 697 /* negative channel means no channel */
 698 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 699 {
 700         unsigned bitfield;
 701
 702         if (channel >= 0)
 703                 bitfield =
 704                     (ni_stc_dma_channel_select_bitfield(channel) <<
 705                      AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 706         else
 707                 bitfield = 0;
 708         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 709 }
 710
 711 /* negative mite_channel means no channel */
 712 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 713                                            unsigned gpct_index,
 714                                            int mite_channel)
 715 {
 716         unsigned bitfield;
 717
 718         if (mite_channel >= 0)
 719                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 720         else
 721                 bitfield = 0;
 722         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 723                         bitfield);
 724 }
 725
 726 /* negative mite_channel means no channel */
 727 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 728                                           int mite_channel)
 729 {
 730         struct ni_private *devpriv = dev->private;
 731         unsigned long flags;
 732
 733         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 734         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 735         if (mite_channel >= 0) {
 736                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 737                    under the assumption the cdio dma selection works just like ai/ao/gpct.
 738                    Definitely works for dma channels 0 and 1. */
 739                 devpriv->cdio_dma_select_reg |=
 740                     (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 741                      CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 742         }
 743         ni_writeb(dev, devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 744         mmiowb();
 745         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 746 }
 747
 748 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 749 {
 750         struct ni_private *devpriv = dev->private;
 751         unsigned long flags;
 752
 753         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 754         BUG_ON(devpriv->ai_mite_chan);
 755         devpriv->ai_mite_chan =
 756             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 757         if (!devpriv->ai_mite_chan) {
 758                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 759                 dev_err(dev->class_dev,
 760                         "failed to reserve mite dma channel for analog input\n");
 761                 return -EBUSY;
 762         }
 763         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 764         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 765         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 766         return 0;
 767 }
 768
 769 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 770 {
 771         struct ni_private *devpriv = dev->private;
 772         unsigned long flags;
 773
 774         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 775         BUG_ON(devpriv->ao_mite_chan);
 776         devpriv->ao_mite_chan =
 777             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 778         if (!devpriv->ao_mite_chan) {
 779                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 780                 dev_err(dev->class_dev,
 781                         "failed to reserve mite dma channel for analog outut\n");
 782                 return -EBUSY;
 783         }
 784         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 785         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 786         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 787         return 0;
 788 }
 789
 790 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 791                                         unsigned gpct_index,
 792                                         enum comedi_io_direction direction)
 793 {
 794         struct ni_private *devpriv = dev->private;
 795         unsigned long flags;
 796         struct mite_channel *mite_chan;
 797
 798         BUG_ON(gpct_index >= NUM_GPCT);
 799         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 800         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 801         mite_chan =
 802             mite_request_channel(devpriv->mite,
 803                                  devpriv->gpct_mite_ring[gpct_index]);
 804         if (!mite_chan) {
 805                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 806                 dev_err(dev->class_dev,
 807                         "failed to reserve mite dma channel for counter\n");
 808                 return -EBUSY;
 809         }
 810         mite_chan->dir = direction;
 811         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 812                                 mite_chan);
 813         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 814         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 815         return 0;
 816 }
 817
 818 #endif /*  PCIDMA */
 819
 820 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 821 {
 822 #ifdef PCIDMA
 823         struct ni_private *devpriv = dev->private;
 824         unsigned long flags;
 825
 826         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 827         BUG_ON(devpriv->cdo_mite_chan);
 828         devpriv->cdo_mite_chan =
 829             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 830         if (!devpriv->cdo_mite_chan) {
 831                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 832                 dev_err(dev->class_dev,
 833                         "failed to reserve mite dma channel for correlated digital output\n");
 834                 return -EBUSY;
 835         }
 836         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 837         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 838         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 839 #endif /*  PCIDMA */
 840         return 0;
 841 }
 842
 843 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 844 {
 845 #ifdef PCIDMA
 846         struct ni_private *devpriv = dev->private;
 847         unsigned long flags;
 848
 849         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 850         if (devpriv->ai_mite_chan) {
 851                 ni_set_ai_dma_channel(dev, -1);
 852                 mite_release_channel(devpriv->ai_mite_chan);
 853                 devpriv->ai_mite_chan = NULL;
 854         }
 855         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 856 #endif /*  PCIDMA */
 857 }
 858
 859 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 860 {
 861 #ifdef PCIDMA
 862         struct ni_private *devpriv = dev->private;
 863         unsigned long flags;
 864
 865         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 866         if (devpriv->ao_mite_chan) {
 867                 ni_set_ao_dma_channel(dev, -1);
 868                 mite_release_channel(devpriv->ao_mite_chan);
 869                 devpriv->ao_mite_chan = NULL;
 870         }
 871         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 872 #endif /*  PCIDMA */
 873 }
 874
 875 #ifdef PCIDMA
 876 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 877                                          unsigned gpct_index)
 878 {
 879         struct ni_private *devpriv = dev->private;
 880         unsigned long flags;
 881
 882         BUG_ON(gpct_index >= NUM_GPCT);
 883         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 884         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 885                 struct mite_channel *mite_chan =
 886                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 887
 888                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 889                 ni_tio_set_mite_channel(&devpriv->
 890                                         counter_dev->counters[gpct_index],
 891                                         NULL);
 892                 mite_release_channel(mite_chan);
 893         }
 894         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 895 }
 896 #endif /*  PCIDMA */
 897
 898 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 899 {
 900 #ifdef PCIDMA
 901         struct ni_private *devpriv = dev->private;
 902         unsigned long flags;
 903
 904         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 905         if (devpriv->cdo_mite_chan) {
 906                 ni_set_cdo_dma_channel(dev, -1);
 907                 mite_release_channel(devpriv->cdo_mite_chan);
 908                 devpriv->cdo_mite_chan = NULL;
 909         }
 910         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 911 #endif /*  PCIDMA */
 912 }
 913
 914 #ifdef PCIDMA
 915 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 916                                           unsigned gpct_index, short enable)
 917 {
 918         struct ni_private *devpriv = dev->private;
 919         uint16_t val = 0;
 920         int reg;
 921
 922         if (devpriv->is_m_series || gpct_index > 1)
 923                 return;
 924
 925         /*
 926          * e-series boards use the second irq signals to generate
 927          * dma requests for their counters
 928          */
 929         if (gpct_index == 0) {
 930                 reg = Second_IRQ_A_Enable_Register;
 931                 if (enable)
 932                         val = G0_Gate_Second_Irq_Enable;
 933         } else {
 934                 reg = Second_IRQ_B_Enable_Register;
 935                 if (enable)
 936                         val = G1_Gate_Second_Irq_Enable;
 937         }
 938         ni_stc_writew(dev, val, reg);
 939 }
 940 #endif /*  PCIDMA */
 941
 942 static void ni_clear_ai_fifo(struct comedi_device *dev)
 943 {
 944         struct ni_private *devpriv = dev->private;
 945         static const int timeout = 10000;
 946         int i;
 947
 948         if (devpriv->is_6143) {
 949                 /*  Flush the 6143 data FIFO */
 950                 ni_writel(dev, 0x10, AIFIFO_Control_6143);
 951                 ni_writel(dev, 0x00, AIFIFO_Control_6143);
 952                 /*  Wait for complete */
 953                 for (i = 0; i < timeout; i++) {
 954                         if (!(ni_readl(dev, AIFIFO_Status_6143) & 0x10))
 955                                 break;
 956                         udelay(1);
 957                 }
 958                 if (i == timeout)
 959                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 960         } else {
 961                 ni_stc_writew(dev, 1, ADC_FIFO_Clear);
 962                 if (devpriv->is_625x) {
 963                         ni_writeb(dev, 0, M_Offset_Static_AI_Control(0));
 964                         ni_writeb(dev, 1, M_Offset_Static_AI_Control(0));
 965 #if 0
 966                         /* the NI example code does 3 convert pulses for 625x boards,
 967                            but that appears to be wrong in practice. */
 968                         ni_stc_writew(dev, AI_CONVERT_Pulse,
 969                                       AI_Command_1_Register);
 970                         ni_stc_writew(dev, AI_CONVERT_Pulse,
 971                                       AI_Command_1_Register);
 972                         ni_stc_writew(dev, AI_CONVERT_Pulse,
 973                                       AI_Command_1_Register);
 974 #endif
 975                 }
 976         }
 977 }
 978
 979 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 980                                   int addr)
 981 {
 982         struct ni_private *devpriv = dev->private;
 983         unsigned long flags;
 984
 985         spin_lock_irqsave(&devpriv->window_lock, flags);
 986         ni_writew(dev, addr, AO_Window_Address_611x);
 987         ni_writew(dev, data, AO_Window_Data_611x);
 988         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 989 }
 990
 991 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 992                                   int addr)
 993 {
 994         struct ni_private *devpriv = dev->private;
 995         unsigned long flags;
 996
 997         spin_lock_irqsave(&devpriv->window_lock, flags);
 998         ni_writew(dev, addr, AO_Window_Address_611x);
 999         ni_writel(dev, data, AO_Window_Data_611x);
1000         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1001 }
1002
1003 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
1004 {
1005         struct ni_private *devpriv = dev->private;
1006         unsigned long flags;
1007         unsigned short data;
1008
1009         spin_lock_irqsave(&devpriv->window_lock, flags);
1010         ni_writew(dev, addr, AO_Window_Address_611x);
1011         data = ni_readw(dev, AO_Window_Data_611x);
1012         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1013         return data;
1014 }
1015
1016 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
1017 * share registers (such as Interrupt_A_Register) without interfering with
1018 * each other.
1019 *
1020 * NOTE: the switch/case statements are optimized out for a constant argument
1021 * so this is actually quite fast---  If you must wrap another function around this
1022 * make it inline to avoid a large speed penalty.
1023 *
1024 * value should only be 1 or 0.
1025 */
1026 static inline void ni_set_bits(struct comedi_device *dev, int reg,
1027                                unsigned bits, unsigned value)
1028 {
1029         unsigned bit_values;
1030
1031         if (value)
1032                 bit_values = bits;
1033         else
1034                 bit_values = 0;
1035         ni_set_bitfield(dev, reg, bits, bit_values);
1036 }
1037
1038 #ifdef PCIDMA
1039 static void ni_sync_ai_dma(struct comedi_device *dev)
1040 {
1041         struct ni_private *devpriv = dev->private;
1042         struct comedi_subdevice *s = dev->read_subdev;
1043         unsigned long flags;
1044
1045         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1046         if (devpriv->ai_mite_chan)
1047                 mite_sync_input_dma(devpriv->ai_mite_chan, s);
1048         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1049 }
1050
1051 static int ni_ai_drain_dma(struct comedi_device *dev)
1052 {
1053         struct ni_private *devpriv = dev->private;
1054         int i;
1055         static const int timeout = 10000;
1056         unsigned long flags;
1057         int retval = 0;
1058
1059         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1060         if (devpriv->ai_mite_chan) {
1061                 for (i = 0; i < timeout; i++) {
1062                         if ((ni_stc_readw(dev, AI_Status_1_Register) &
1063                              AI_FIFO_Empty_St)
1064                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1065                             0)
1066                                 break;
1067                         udelay(5);
1068                 }
1069                 if (i == timeout) {
1070                         dev_err(dev->class_dev, "timed out\n");
1071                         dev_err(dev->class_dev,
1072                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1073                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
1074                                 ni_stc_readw(dev, AI_Status_1_Register));
1075                         retval = -1;
1076                 }
1077         }
1078         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1079
1080         ni_sync_ai_dma(dev);
1081
1082         return retval;
1083 }
1084
1085 static void mite_handle_b_linkc(struct mite_struct *mite,
1086                                 struct comedi_device *dev)
1087 {
1088         struct ni_private *devpriv = dev->private;
1089         struct comedi_subdevice *s = dev->write_subdev;
1090         unsigned long flags;
1091
1092         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1093         if (devpriv->ao_mite_chan)
1094                 mite_sync_output_dma(devpriv->ao_mite_chan, s);
1095         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1096 }
1097
1098 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
1099 {
1100         static const int timeout = 10000;
1101         int i;
1102
1103         for (i = 0; i < timeout; i++) {
1104                 unsigned short b_status;
1105
1106                 b_status = ni_stc_readw(dev, AO_Status_1_Register);
1107                 if (b_status & AO_FIFO_Half_Full_St)
1108                         break;
1109                 /* if we poll too often, the pci bus activity seems
1110                    to slow the dma transfer down */
1111                 udelay(10);
1112         }
1113         if (i == timeout) {
1114                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1115                 return -EPIPE;
1116         }
1117         return 0;
1118 }
1119 #endif /* PCIDMA */
1120
1121 #ifndef PCIDMA
1122
1123 static void ni_ao_fifo_load(struct comedi_device *dev,
1124                             struct comedi_subdevice *s, int n)
1125 {
1126         struct ni_private *devpriv = dev->private;
1127         int i;
1128         unsigned short d;
1129         u32 packed_data;
1130
1131         for (i = 0; i < n; i++) {
1132                 comedi_buf_read_samples(s, &d, 1);
1133
1134                 if (devpriv->is_6xxx) {
1135                         packed_data = d & 0xffff;
1136                         /* 6711 only has 16 bit wide ao fifo */
1137                         if (!devpriv->is_6711) {
1138                                 comedi_buf_read_samples(s, &d, 1);
1139                                 i++;
1140                                 packed_data |= (d << 16) & 0xffff0000;
1141                         }
1142                         ni_writel(dev, packed_data, DAC_FIFO_Data_611x);
1143                 } else {
1144                         ni_writew(dev, d, DAC_FIFO_Data);
1145                 }
1146         }
1147 }
1148
1149 /*
1150  *  There's a small problem if the FIFO gets really low and we
1151  *  don't have the data to fill it.  Basically, if after we fill
1152  *  the FIFO with all the data available, the FIFO is _still_
1153  *  less than half full, we never clear the interrupt.  If the
1154  *  IRQ is in edge mode, we never get another interrupt, because
1155  *  this one wasn't cleared.  If in level mode, we get flooded
1156  *  with interrupts that we can't fulfill, because nothing ever
1157  *  gets put into the buffer.
1158  *
1159  *  This kind of situation is recoverable, but it is easier to
1160  *  just pretend we had a FIFO underrun, since there is a good
1161  *  chance it will happen anyway.  This is _not_ the case for
1162  *  RT code, as RT code might purposely be running close to the
1163  *  metal.  Needs to be fixed eventually.
1164  */
1165 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1166                                  struct comedi_subdevice *s)
1167 {
1168         const struct ni_board_struct *board = dev->board_ptr;
1169         unsigned int nbytes;
1170         unsigned int nsamples;
1171
1172         nbytes = comedi_buf_read_n_available(s);
1173         if (nbytes == 0) {
1174                 s->async->events |= COMEDI_CB_OVERFLOW;
1175                 return 0;
1176         }
1177
1178         nsamples = comedi_bytes_to_samples(s, nbytes);
1179         if (nsamples > board->ao_fifo_depth / 2)
1180                 nsamples = board->ao_fifo_depth / 2;
1181
1182         ni_ao_fifo_load(dev, s, nsamples);
1183
1184         return 1;
1185 }
1186
1187 static int ni_ao_prep_fifo(struct comedi_device *dev,
1188                            struct comedi_subdevice *s)
1189 {
1190         const struct ni_board_struct *board = dev->board_ptr;
1191         struct ni_private *devpriv = dev->private;
1192         unsigned int nbytes;
1193         unsigned int nsamples;
1194
1195         /* reset fifo */
1196         ni_stc_writew(dev, 1, DAC_FIFO_Clear);
1197         if (devpriv->is_6xxx)
1198                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1199
1200         /* load some data */
1201         nbytes = comedi_buf_read_n_available(s);
1202         if (nbytes == 0)
1203                 return 0;
1204
1205         nsamples = comedi_bytes_to_samples(s, nbytes);
1206         if (nsamples > board->ao_fifo_depth)
1207                 nsamples = board->ao_fifo_depth;
1208
1209         ni_ao_fifo_load(dev, s, nsamples);
1210
1211         return nsamples;
1212 }
1213
1214 static void ni_ai_fifo_read(struct comedi_device *dev,
1215                             struct comedi_subdevice *s, int n)
1216 {
1217         struct ni_private *devpriv = dev->private;
1218         struct comedi_async *async = s->async;
1219         u32 dl;
1220         unsigned short data;
1221         int i;
1222
1223         if (devpriv->is_611x) {
1224                 for (i = 0; i < n / 2; i++) {
1225                         dl = ni_readl(dev, ADC_FIFO_Data_611x);
1226                         /* This may get the hi/lo data in the wrong order */
1227                         data = (dl >> 16) & 0xffff;
1228                         comedi_buf_write_samples(s, &data, 1);
1229                         data = dl & 0xffff;
1230                         comedi_buf_write_samples(s, &data, 1);
1231                 }
1232                 /* Check if there's a single sample stuck in the FIFO */
1233                 if (n % 2) {
1234                         dl = ni_readl(dev, ADC_FIFO_Data_611x);
1235                         data = dl & 0xffff;
1236                         comedi_buf_write_samples(s, &data, 1);
1237                 }
1238         } else if (devpriv->is_6143) {
1239                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1240                 for (i = 0; i < n / 2; i++) {
1241                         dl = ni_readl(dev, AIFIFO_Data_6143);
1242
1243                         data = (dl >> 16) & 0xffff;
1244                         comedi_buf_write_samples(s, &data, 1);
1245                         data = dl & 0xffff;
1246                         comedi_buf_write_samples(s, &data, 1);
1247                 }
1248                 if (n % 2) {
1249                         /* Assume there is a single sample stuck in the FIFO */
1250                         /* Get stranded sample into FIFO */
1251                         ni_writel(dev, 0x01, AIFIFO_Control_6143);
1252                         dl = ni_readl(dev, AIFIFO_Data_6143);
1253                         data = (dl >> 16) & 0xffff;
1254                         comedi_buf_write_samples(s, &data, 1);
1255                 }
1256         } else {
1257                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1258                     sizeof(devpriv->ai_fifo_buffer[0])) {
1259                         dev_err(dev->class_dev,
1260                                 "bug! ai_fifo_buffer too small\n");
1261                         async->events |= COMEDI_CB_ERROR;
1262                         return;
1263                 }
1264                 for (i = 0; i < n; i++) {
1265                         devpriv->ai_fifo_buffer[i] =
1266                             ni_readw(dev, ADC_FIFO_Data_Register);
1267                 }
1268                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1269         }
1270 }
1271
1272 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1273 {
1274         const struct ni_board_struct *board = dev->board_ptr;
1275         struct comedi_subdevice *s = dev->read_subdev;
1276         int n;
1277
1278         n = board->ai_fifo_depth / 2;
1279
1280         ni_ai_fifo_read(dev, s, n);
1281 }
1282 #endif
1283
1284 /*
1285    Empties the AI fifo
1286 */
1287 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1288 {
1289         struct ni_private *devpriv = dev->private;
1290         struct comedi_subdevice *s = dev->read_subdev;
1291         u32 dl;
1292         unsigned short data;
1293         unsigned short fifo_empty;
1294         int i;
1295
1296         if (devpriv->is_611x) {
1297                 while ((ni_stc_readw(dev, AI_Status_1_Register) &
1298                         AI_FIFO_Empty_St) == 0) {
1299                         dl = ni_readl(dev, ADC_FIFO_Data_611x);
1300
1301                         /* This may get the hi/lo data in the wrong order */
1302                         data = dl >> 16;
1303                         comedi_buf_write_samples(s, &data, 1);
1304                         data = dl & 0xffff;
1305                         comedi_buf_write_samples(s, &data, 1);
1306                 }
1307         } else if (devpriv->is_6143) {
1308                 i = 0;
1309                 while (ni_readl(dev, AIFIFO_Status_6143) & 0x04) {
1310                         dl = ni_readl(dev, AIFIFO_Data_6143);
1311
1312                         /* This may get the hi/lo data in the wrong order */
1313                         data = dl >> 16;
1314                         comedi_buf_write_samples(s, &data, 1);
1315                         data = dl & 0xffff;
1316                         comedi_buf_write_samples(s, &data, 1);
1317                         i += 2;
1318                 }
1319                 /*  Check if stranded sample is present */
1320                 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1321                         /* Get stranded sample into FIFO */
1322                         ni_writel(dev, 0x01, AIFIFO_Control_6143);
1323                         dl = ni_readl(dev, AIFIFO_Data_6143);
1324                         data = (dl >> 16) & 0xffff;
1325                         comedi_buf_write_samples(s, &data, 1);
1326                 }
1327
1328         } else {
1329                 fifo_empty = ni_stc_readw(dev, AI_Status_1_Register) &
1330                              AI_FIFO_Empty_St;
1331                 while (fifo_empty == 0) {
1332                         for (i = 0;
1333                              i <
1334                              sizeof(devpriv->ai_fifo_buffer) /
1335                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1336                                 fifo_empty = ni_stc_readw(dev,
1337                                                           AI_Status_1_Register) &
1338                                                 AI_FIFO_Empty_St;
1339                                 if (fifo_empty)
1340                                         break;
1341                                 devpriv->ai_fifo_buffer[i] =
1342                                     ni_readw(dev, ADC_FIFO_Data_Register);
1343                         }
1344                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1345                 }
1346         }
1347 }
1348
1349 static void get_last_sample_611x(struct comedi_device *dev)
1350 {
1351         struct ni_private *devpriv = dev->private;
1352         struct comedi_subdevice *s = dev->read_subdev;
1353         unsigned short data;
1354         u32 dl;
1355
1356         if (!devpriv->is_611x)
1357                 return;
1358
1359         /* Check if there's a single sample stuck in the FIFO */
1360         if (ni_readb(dev, XXX_Status) & 0x80) {
1361                 dl = ni_readl(dev, ADC_FIFO_Data_611x);
1362                 data = dl & 0xffff;
1363                 comedi_buf_write_samples(s, &data, 1);
1364         }
1365 }
1366
1367 static void get_last_sample_6143(struct comedi_device *dev)
1368 {
1369         struct ni_private *devpriv = dev->private;
1370         struct comedi_subdevice *s = dev->read_subdev;
1371         unsigned short data;
1372         u32 dl;
1373
1374         if (!devpriv->is_6143)
1375                 return;
1376
1377         /* Check if there's a single sample stuck in the FIFO */
1378         if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
1379                 /* Get stranded sample into FIFO */
1380                 ni_writel(dev, 0x01, AIFIFO_Control_6143);
1381                 dl = ni_readl(dev, AIFIFO_Data_6143);
1382
1383                 /* This may get the hi/lo data in the wrong order */
1384                 data = (dl >> 16) & 0xffff;
1385                 comedi_buf_write_samples(s, &data, 1);
1386         }
1387 }
1388
1389 static void shutdown_ai_command(struct comedi_device *dev)
1390 {
1391         struct comedi_subdevice *s = dev->read_subdev;
1392
1393 #ifdef PCIDMA
1394         ni_ai_drain_dma(dev);
1395 #endif
1396         ni_handle_fifo_dregs(dev);
1397         get_last_sample_611x(dev);
1398         get_last_sample_6143(dev);
1399
1400         s->async->events |= COMEDI_CB_EOA;
1401 }
1402
1403 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1404 {
1405         struct ni_private *devpriv = dev->private;
1406
1407         if (devpriv->aimode == AIMODE_SCAN) {
1408 #ifdef PCIDMA
1409                 static const int timeout = 10;
1410                 int i;
1411
1412                 for (i = 0; i < timeout; i++) {
1413                         ni_sync_ai_dma(dev);
1414                         if ((s->async->events & COMEDI_CB_EOS))
1415                                 break;
1416                         udelay(1);
1417                 }
1418 #else
1419                 ni_handle_fifo_dregs(dev);
1420                 s->async->events |= COMEDI_CB_EOS;
1421 #endif
1422         }
1423         /* handle special case of single scan using AI_End_On_End_Of_Scan */
1424         if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan))
1425                 shutdown_ai_command(dev);
1426 }
1427
1428 static void handle_gpct_interrupt(struct comedi_device *dev,
1429                                   unsigned short counter_index)
1430 {
1431 #ifdef PCIDMA
1432         struct ni_private *devpriv = dev->private;
1433         struct comedi_subdevice *s;
1434
1435         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1436
1437         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1438                                 s);
1439         comedi_handle_events(dev, s);
1440 #endif
1441 }
1442
1443 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1444 {
1445         unsigned short ack = 0;
1446
1447         if (a_status & AI_SC_TC_St)
1448                 ack |= AI_SC_TC_Interrupt_Ack;
1449         if (a_status & AI_START1_St)
1450                 ack |= AI_START1_Interrupt_Ack;
1451         if (a_status & AI_START_St)
1452                 ack |= AI_START_Interrupt_Ack;
1453         if (a_status & AI_STOP_St)
1454                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1455                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */;
1456         if (ack)
1457                 ni_stc_writew(dev, ack, Interrupt_A_Ack_Register);
1458 }
1459
1460 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1461                                unsigned ai_mite_status)
1462 {
1463         struct comedi_subdevice *s = dev->read_subdev;
1464         struct comedi_cmd *cmd = &s->async->cmd;
1465
1466         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1467         if (s->type == COMEDI_SUBD_UNUSED)
1468                 return;
1469
1470 #ifdef PCIDMA
1471         if (ai_mite_status & CHSR_LINKC)
1472                 ni_sync_ai_dma(dev);
1473
1474         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1475                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1476                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1477                 dev_err(dev->class_dev,
1478                         "unknown mite interrupt (ai_mite_status=%08x)\n",
1479                         ai_mite_status);
1480                 s->async->events |= COMEDI_CB_ERROR;
1481                 /* disable_irq(dev->irq); */
1482         }
1483 #endif
1484
1485         /* test for all uncommon interrupt events at the same time */
1486         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1487                       AI_SC_TC_St | AI_START1_St)) {
1488                 if (status == 0xffff) {
1489                         dev_err(dev->class_dev, "Card removed?\n");
1490                         /* we probably aren't even running a command now,
1491                          * so it's a good idea to be careful. */
1492                         if (comedi_is_subdevice_running(s)) {
1493                                 s->async->events |= COMEDI_CB_ERROR;
1494                                 comedi_handle_events(dev, s);
1495                         }
1496                         return;
1497                 }
1498                 if (status & (AI_Overrun_St | AI_Overflow_St |
1499                               AI_SC_TC_Error_St)) {
1500                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1501                                 status);
1502
1503                         shutdown_ai_command(dev);
1504
1505                         s->async->events |= COMEDI_CB_ERROR;
1506                         if (status & (AI_Overrun_St | AI_Overflow_St))
1507                                 s->async->events |= COMEDI_CB_OVERFLOW;
1508
1509                         comedi_handle_events(dev, s);
1510                         return;
1511                 }
1512                 if (status & AI_SC_TC_St) {
1513                         if (cmd->stop_src == TRIG_COUNT)
1514                                 shutdown_ai_command(dev);
1515                 }
1516         }
1517 #ifndef PCIDMA
1518         if (status & AI_FIFO_Half_Full_St) {
1519                 int i;
1520                 static const int timeout = 10;
1521                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1522                  *fail to get the fifo less than half full, so loop to be sure.*/
1523                 for (i = 0; i < timeout; ++i) {
1524                         ni_handle_fifo_half_full(dev);
1525                         if ((ni_stc_readw(dev, AI_Status_1_Register) &
1526                              AI_FIFO_Half_Full_St) == 0)
1527                                 break;
1528                 }
1529         }
1530 #endif /*  !PCIDMA */
1531
1532         if ((status & AI_STOP_St))
1533                 ni_handle_eos(dev, s);
1534
1535         comedi_handle_events(dev, s);
1536 }
1537
1538 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1539 {
1540         unsigned short ack = 0;
1541
1542         if (b_status & AO_BC_TC_St)
1543                 ack |= AO_BC_TC_Interrupt_Ack;
1544         if (b_status & AO_Overrun_St)
1545                 ack |= AO_Error_Interrupt_Ack;
1546         if (b_status & AO_START_St)
1547                 ack |= AO_START_Interrupt_Ack;
1548         if (b_status & AO_START1_St)
1549                 ack |= AO_START1_Interrupt_Ack;
1550         if (b_status & AO_UC_TC_St)
1551                 ack |= AO_UC_TC_Interrupt_Ack;
1552         if (b_status & AO_UI2_TC_St)
1553                 ack |= AO_UI2_TC_Interrupt_Ack;
1554         if (b_status & AO_UPDATE_St)
1555                 ack |= AO_UPDATE_Interrupt_Ack;
1556         if (ack)
1557                 ni_stc_writew(dev, ack, Interrupt_B_Ack_Register);
1558 }
1559
1560 static void handle_b_interrupt(struct comedi_device *dev,
1561                                unsigned short b_status, unsigned ao_mite_status)
1562 {
1563         struct comedi_subdevice *s = dev->write_subdev;
1564         /* unsigned short ack=0; */
1565
1566 #ifdef PCIDMA
1567         /* Currently, mite.c requires us to handle LINKC */
1568         if (ao_mite_status & CHSR_LINKC) {
1569                 struct ni_private *devpriv = dev->private;
1570
1571                 mite_handle_b_linkc(devpriv->mite, dev);
1572         }
1573
1574         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1575                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1576                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1577                 dev_err(dev->class_dev,
1578                         "unknown mite interrupt (ao_mite_status=%08x)\n",
1579                         ao_mite_status);
1580                 s->async->events |= COMEDI_CB_ERROR;
1581         }
1582 #endif
1583
1584         if (b_status == 0xffff)
1585                 return;
1586         if (b_status & AO_Overrun_St) {
1587                 dev_err(dev->class_dev,
1588                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1589                         b_status, ni_stc_readw(dev, AO_Status_2_Register));
1590                 s->async->events |= COMEDI_CB_OVERFLOW;
1591         }
1592
1593         if (b_status & AO_BC_TC_St)
1594                 s->async->events |= COMEDI_CB_EOA;
1595
1596 #ifndef PCIDMA
1597         if (b_status & AO_FIFO_Request_St) {
1598                 int ret;
1599
1600                 ret = ni_ao_fifo_half_empty(dev, s);
1601                 if (!ret) {
1602                         dev_err(dev->class_dev, "AO buffer underrun\n");
1603                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1604                                     AO_FIFO_Interrupt_Enable |
1605                                     AO_Error_Interrupt_Enable, 0);
1606                         s->async->events |= COMEDI_CB_OVERFLOW;
1607                 }
1608         }
1609 #endif
1610
1611         comedi_handle_events(dev, s);
1612 }
1613
1614 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1615                         void *data, unsigned int num_bytes,
1616                         unsigned int chan_index)
1617 {
1618         struct ni_private *devpriv = dev->private;
1619         struct comedi_async *async = s->async;
1620         struct comedi_cmd *cmd = &async->cmd;
1621         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1622         unsigned short *array = data;
1623         unsigned int *larray = data;
1624         unsigned int i;
1625
1626         for (i = 0; i < nsamples; i++) {
1627 #ifdef PCIDMA
1628                 if (s->subdev_flags & SDF_LSAMPL)
1629                         larray[i] = le32_to_cpu(larray[i]);
1630                 else
1631                         array[i] = le16_to_cpu(array[i]);
1632 #endif
1633                 if (s->subdev_flags & SDF_LSAMPL)
1634                         larray[i] += devpriv->ai_offset[chan_index];
1635                 else
1636                         array[i] += devpriv->ai_offset[chan_index];
1637                 chan_index++;
1638                 chan_index %= cmd->chanlist_len;
1639         }
1640 }
1641
1642 #ifdef PCIDMA
1643
1644 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1645 {
1646         struct ni_private *devpriv = dev->private;
1647         struct comedi_subdevice *s = dev->read_subdev;
1648         int retval;
1649         unsigned long flags;
1650
1651         retval = ni_request_ai_mite_channel(dev);
1652         if (retval)
1653                 return retval;
1654
1655         /* write alloc the entire buffer */
1656         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1657
1658         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1659         if (!devpriv->ai_mite_chan) {
1660                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1661                 return -EIO;
1662         }
1663
1664         if (devpriv->is_611x || devpriv->is_6143)
1665                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1666         else if (devpriv->is_628x)
1667                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1668         else
1669                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1670
1671         /*start the MITE */
1672         mite_dma_arm(devpriv->ai_mite_chan);
1673         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1674
1675         return 0;
1676 }
1677
1678 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1679 {
1680         struct ni_private *devpriv = dev->private;
1681         struct comedi_subdevice *s = dev->write_subdev;
1682         int retval;
1683         unsigned long flags;
1684
1685         retval = ni_request_ao_mite_channel(dev);
1686         if (retval)
1687                 return retval;
1688
1689         /* read alloc the entire buffer */
1690         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1691
1692         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1693         if (devpriv->ao_mite_chan) {
1694                 if (devpriv->is_611x || devpriv->is_6713) {
1695                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1696                 } else {
1697                         /* doing 32 instead of 16 bit wide transfers from memory
1698                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1699                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1700                 }
1701                 mite_dma_arm(devpriv->ao_mite_chan);
1702         } else {
1703                 retval = -EIO;
1704         }
1705         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1706
1707         return retval;
1708 }
1709
1710 #endif /*  PCIDMA */
1711
1712 /*
1713    used for both cancel ioctl and board initialization
1714
1715    this is pretty harsh for a cancel, but it works...
1716  */
1717
1718 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1719 {
1720         struct ni_private *devpriv = dev->private;
1721
1722         ni_release_ai_mite_channel(dev);
1723         /* ai configuration */
1724         ni_stc_writew(dev, AI_Configuration_Start | AI_Reset,
1725                       Joint_Reset_Register);
1726
1727         ni_set_bits(dev, Interrupt_A_Enable_Register,
1728                     AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1729                     AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1730                     AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1731                     AI_FIFO_Interrupt_Enable, 0);
1732
1733         ni_clear_ai_fifo(dev);
1734
1735         if (!devpriv->is_6143)
1736                 ni_writeb(dev, 0, Misc_Command);
1737
1738         ni_stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1739         ni_stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved
1740                             /*| AI_Trigger_Once */,
1741                       AI_Mode_1_Register);
1742         ni_stc_writew(dev, 0x0000, AI_Mode_2_Register);
1743         /* generate FIFO interrupts on non-empty */
1744         ni_stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1745         if (devpriv->is_611x) {
1746                 ni_stc_writew(dev,
1747                               AI_SHIFTIN_Pulse_Width |
1748                               AI_SOC_Polarity |
1749                               AI_LOCALMUX_CLK_Pulse_Width,
1750                               AI_Personal_Register);
1751                 ni_stc_writew(dev,
1752                               AI_SCAN_IN_PROG_Output_Select(3) |
1753                               AI_EXTMUX_CLK_Output_Select(0) |
1754                               AI_LOCALMUX_CLK_Output_Select(2) |
1755                               AI_SC_TC_Output_Select(3) |
1756                               AI_CONVERT_Output_Select
1757                               (AI_CONVERT_Output_Enable_High),
1758                               AI_Output_Control_Register);
1759         } else if (devpriv->is_6143) {
1760                 ni_stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1761                                    AI_SOC_Polarity |
1762                                    AI_LOCALMUX_CLK_Pulse_Width,
1763                               AI_Personal_Register);
1764                 ni_stc_writew(dev,
1765                               AI_SCAN_IN_PROG_Output_Select(3) |
1766                               AI_EXTMUX_CLK_Output_Select(0) |
1767                               AI_LOCALMUX_CLK_Output_Select(2) |
1768                               AI_SC_TC_Output_Select(3) |
1769                               AI_CONVERT_Output_Select
1770                               (AI_CONVERT_Output_Enable_Low),
1771                               AI_Output_Control_Register);
1772         } else {
1773                 unsigned ai_output_control_bits;
1774
1775                 ni_stc_writew(dev,
1776                               AI_SHIFTIN_Pulse_Width |
1777                               AI_SOC_Polarity |
1778                               AI_CONVERT_Pulse_Width |
1779                               AI_LOCALMUX_CLK_Pulse_Width,
1780                               AI_Personal_Register);
1781                 ai_output_control_bits =
1782                     AI_SCAN_IN_PROG_Output_Select(3) |
1783                     AI_EXTMUX_CLK_Output_Select(0) |
1784                     AI_LOCALMUX_CLK_Output_Select(2) |
1785                     AI_SC_TC_Output_Select(3);
1786                 if (devpriv->is_622x)
1787                         ai_output_control_bits |=
1788                             AI_CONVERT_Output_Select
1789                             (AI_CONVERT_Output_Enable_High);
1790                 else
1791                         ai_output_control_bits |=
1792                             AI_CONVERT_Output_Select
1793                             (AI_CONVERT_Output_Enable_Low);
1794                 ni_stc_writew(dev, ai_output_control_bits,
1795                               AI_Output_Control_Register);
1796         }
1797         /* the following registers should not be changed, because there
1798          * are no backup registers in devpriv.  If you want to change
1799          * any of these, add a backup register and other appropriate code:
1800          *      AI_Mode_1_Register
1801          *      AI_Mode_3_Register
1802          *      AI_Personal_Register
1803          *      AI_Output_Control_Register
1804          */
1805         ni_stc_writew(dev,
1806                       AI_SC_TC_Error_Confirm |
1807                       AI_START_Interrupt_Ack |
1808                       AI_START2_Interrupt_Ack |
1809                       AI_START1_Interrupt_Ack |
1810                       AI_SC_TC_Interrupt_Ack |
1811                       AI_Error_Interrupt_Ack |
1812                       AI_STOP_Interrupt_Ack,
1813                       Interrupt_A_Ack_Register);        /* clear interrupts */
1814
1815         ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1816
1817         return 0;
1818 }
1819
1820 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1821 {
1822         unsigned long flags;
1823         int count;
1824
1825         /*  lock to avoid race with interrupt handler */
1826         spin_lock_irqsave(&dev->spinlock, flags);
1827 #ifndef PCIDMA
1828         ni_handle_fifo_dregs(dev);
1829 #else
1830         ni_sync_ai_dma(dev);
1831 #endif
1832         count = comedi_buf_n_bytes_ready(s);
1833         spin_unlock_irqrestore(&dev->spinlock, flags);
1834
1835         return count;
1836 }
1837
1838 static void ni_prime_channelgain_list(struct comedi_device *dev)
1839 {
1840         int i;
1841
1842         ni_stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1843         for (i = 0; i < NI_TIMEOUT; ++i) {
1844                 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
1845                       AI_FIFO_Empty_St)) {
1846                         ni_stc_writew(dev, 1, ADC_FIFO_Clear);
1847                         return;
1848                 }
1849                 udelay(1);
1850         }
1851         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1852 }
1853
1854 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1855                                               unsigned int n_chan,
1856                                               unsigned int *list)
1857 {
1858         const struct ni_board_struct *board = dev->board_ptr;
1859         struct ni_private *devpriv = dev->private;
1860         unsigned int chan, range, aref;
1861         unsigned int i;
1862         unsigned int dither;
1863         unsigned range_code;
1864
1865         ni_stc_writew(dev, 1, Configuration_Memory_Clear);
1866
1867         if ((list[0] & CR_ALT_SOURCE)) {
1868                 unsigned bypass_bits;
1869
1870                 chan = CR_CHAN(list[0]);
1871                 range = CR_RANGE(list[0]);
1872                 range_code = ni_gainlkup[board->gainlkup][range];
1873                 dither = (list[0] & CR_ALT_FILTER) != 0;
1874                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1875                 bypass_bits |= chan;
1876                 bypass_bits |=
1877                     (devpriv->ai_calib_source) &
1878                     (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1879                      MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1880                      MSeries_AI_Bypass_Mode_Mux_Mask |
1881                      MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1882                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1883                 if (dither)
1884                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1885                 /*  don't use 2's complement encoding */
1886                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1887                 ni_writel(dev, bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1888         } else {
1889                 ni_writel(dev, 0, M_Offset_AI_Config_FIFO_Bypass);
1890         }
1891         for (i = 0; i < n_chan; i++) {
1892                 unsigned config_bits = 0;
1893
1894                 chan = CR_CHAN(list[i]);
1895                 aref = CR_AREF(list[i]);
1896                 range = CR_RANGE(list[i]);
1897                 dither = (list[i] & CR_ALT_FILTER) != 0;
1898
1899                 range_code = ni_gainlkup[board->gainlkup][range];
1900                 devpriv->ai_offset[i] = 0;
1901                 switch (aref) {
1902                 case AREF_DIFF:
1903                         config_bits |=
1904                             MSeries_AI_Config_Channel_Type_Differential_Bits;
1905                         break;
1906                 case AREF_COMMON:
1907                         config_bits |=
1908                             MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1909                         break;
1910                 case AREF_GROUND:
1911                         config_bits |=
1912                             MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1913                         break;
1914                 case AREF_OTHER:
1915                         break;
1916                 }
1917                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1918                 config_bits |=
1919                     MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
1920                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1921                 if (i == n_chan - 1)
1922                         config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1923                 if (dither)
1924                         config_bits |= MSeries_AI_Config_Dither_Bit;
1925                 /*  don't use 2's complement encoding */
1926                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1927                 ni_writew(dev, config_bits, M_Offset_AI_Config_FIFO_Data);
1928         }
1929         ni_prime_channelgain_list(dev);
1930 }
1931
1932 /*
1933  * Notes on the 6110 and 6111:
1934  * These boards a slightly different than the rest of the series, since
1935  * they have multiple A/D converters.
1936  * From the driver side, the configuration memory is a
1937  * little different.
1938  * Configuration Memory Low:
1939  *   bits 15-9: same
1940  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1941  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1942  *       1001 gain=0.1 (+/- 50)
1943  *       1010 0.2
1944  *       1011 0.1
1945  *       0001 1
1946  *       0010 2
1947  *       0011 5
1948  *       0100 10
1949  *       0101 20
1950  *       0110 50
1951  * Configuration Memory High:
1952  *   bits 12-14: Channel Type
1953  *       001 for differential
1954  *       000 for calibration
1955  *   bit 11: coupling  (this is not currently handled)
1956  *       1 AC coupling
1957  *       0 DC coupling
1958  *   bits 0-2: channel
1959  *       valid channels are 0-3
1960  */
1961 static void ni_load_channelgain_list(struct comedi_device *dev,
1962                                      struct comedi_subdevice *s,
1963                                      unsigned int n_chan, unsigned int *list)
1964 {
1965         const struct ni_board_struct *board = dev->board_ptr;
1966         struct ni_private *devpriv = dev->private;
1967         unsigned int offset = (s->maxdata + 1) >> 1;
1968         unsigned int chan, range, aref;
1969         unsigned int i;
1970         unsigned int hi, lo;
1971         unsigned int dither;
1972
1973         if (devpriv->is_m_series) {
1974                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1975                 return;
1976         }
1977         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1978                 if (devpriv->changain_state
1979                     && devpriv->changain_spec == list[0]) {
1980                         /*  ready to go. */
1981                         return;
1982                 }
1983                 devpriv->changain_state = 1;
1984                 devpriv->changain_spec = list[0];
1985         } else {
1986                 devpriv->changain_state = 0;
1987         }
1988
1989         ni_stc_writew(dev, 1, Configuration_Memory_Clear);
1990
1991         /*  Set up Calibration mode if required */
1992         if (devpriv->is_6143) {
1993                 if ((list[0] & CR_ALT_SOURCE)
1994                     && !devpriv->ai_calib_source_enabled) {
1995                         /*  Strobe Relay enable bit */
1996                         ni_writew(dev, devpriv->ai_calib_source |
1997                                        Calibration_Channel_6143_RelayOn,
1998                                   Calibration_Channel_6143);
1999                         ni_writew(dev, devpriv->ai_calib_source,
2000                                   Calibration_Channel_6143);
2001                         devpriv->ai_calib_source_enabled = 1;
2002                         msleep_interruptible(100);      /*  Allow relays to change */
2003                 } else if (!(list[0] & CR_ALT_SOURCE)
2004                            && devpriv->ai_calib_source_enabled) {
2005                         /*  Strobe Relay disable bit */
2006                         ni_writew(dev, devpriv->ai_calib_source |
2007                                        Calibration_Channel_6143_RelayOff,
2008                                   Calibration_Channel_6143);
2009                         ni_writew(dev, devpriv->ai_calib_source,
2010                                   Calibration_Channel_6143);
2011                         devpriv->ai_calib_source_enabled = 0;
2012                         msleep_interruptible(100);      /*  Allow relays to change */
2013                 }
2014         }
2015
2016         for (i = 0; i < n_chan; i++) {
2017                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
2018                         chan = devpriv->ai_calib_source;
2019                 else
2020                         chan = CR_CHAN(list[i]);
2021                 aref = CR_AREF(list[i]);
2022                 range = CR_RANGE(list[i]);
2023                 dither = (list[i] & CR_ALT_FILTER) != 0;
2024
2025                 /* fix the external/internal range differences */
2026                 range = ni_gainlkup[board->gainlkup][range];
2027                 if (devpriv->is_611x)
2028                         devpriv->ai_offset[i] = offset;
2029                 else
2030                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2031
2032                 hi = 0;
2033                 if ((list[i] & CR_ALT_SOURCE)) {
2034                         if (devpriv->is_611x)
2035                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
2036                                           Calibration_Channel_Select_611x);
2037                 } else {
2038                         if (devpriv->is_611x)
2039                                 aref = AREF_DIFF;
2040                         else if (devpriv->is_6143)
2041                                 aref = AREF_OTHER;
2042                         switch (aref) {
2043                         case AREF_DIFF:
2044                                 hi |= AI_DIFFERENTIAL;
2045                                 break;
2046                         case AREF_COMMON:
2047                                 hi |= AI_COMMON;
2048                                 break;
2049                         case AREF_GROUND:
2050                                 hi |= AI_GROUND;
2051                                 break;
2052                         case AREF_OTHER:
2053                                 break;
2054                         }
2055                 }
2056                 hi |= AI_CONFIG_CHANNEL(chan);
2057
2058                 ni_writew(dev, hi, Configuration_Memory_High);
2059
2060                 if (!devpriv->is_6143) {
2061                         lo = range;
2062                         if (i == n_chan - 1)
2063                                 lo |= AI_LAST_CHANNEL;
2064                         if (dither)
2065                                 lo |= AI_DITHER;
2066
2067                         ni_writew(dev, lo, Configuration_Memory_Low);
2068                 }
2069         }
2070
2071         /* prime the channel/gain list */
2072         if (!devpriv->is_611x && !devpriv->is_6143)
2073                 ni_prime_channelgain_list(dev);
2074 }
2075
2076 static int ni_ai_insn_read(struct comedi_device *dev,
2077                            struct comedi_subdevice *s,
2078                            struct comedi_insn *insn,
2079                            unsigned int *data)
2080 {
2081         struct ni_private *devpriv = dev->private;
2082         unsigned int mask = (s->maxdata + 1) >> 1;
2083         int i, n;
2084         unsigned signbits;
2085         unsigned int d;
2086         unsigned long dl;
2087
2088         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
2089
2090         ni_clear_ai_fifo(dev);
2091
2092         signbits = devpriv->ai_offset[0];
2093         if (devpriv->is_611x) {
2094                 for (n = 0; n < num_adc_stages_611x; n++) {
2095                         ni_stc_writew(dev, AI_CONVERT_Pulse,
2096                                       AI_Command_1_Register);
2097                         udelay(1);
2098                 }
2099                 for (n = 0; n < insn->n; n++) {
2100                         ni_stc_writew(dev, AI_CONVERT_Pulse,
2101                                       AI_Command_1_Register);
2102                         /* The 611x has screwy 32-bit FIFOs. */
2103                         d = 0;
2104                         for (i = 0; i < NI_TIMEOUT; i++) {
2105                                 if (ni_readb(dev, XXX_Status) & 0x80) {
2106                                         d = ni_readl(dev, ADC_FIFO_Data_611x);
2107                                         d >>= 16;
2108                                         d &= 0xffff;
2109                                         break;
2110                                 }
2111                                 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
2112                                       AI_FIFO_Empty_St)) {
2113                                         d = ni_readl(dev, ADC_FIFO_Data_611x);
2114                                         d &= 0xffff;
2115                                         break;
2116                                 }
2117                         }
2118                         if (i == NI_TIMEOUT) {
2119                                 dev_err(dev->class_dev, "timeout\n");
2120                                 return -ETIME;
2121                         }
2122                         d += signbits;
2123                         data[n] = d;
2124                 }
2125         } else if (devpriv->is_6143) {
2126                 for (n = 0; n < insn->n; n++) {
2127                         ni_stc_writew(dev, AI_CONVERT_Pulse,
2128                                       AI_Command_1_Register);
2129
2130                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
2131                         dl = 0;
2132                         for (i = 0; i < NI_TIMEOUT; i++) {
2133                                 if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) {
2134                                         /* Get stranded sample into FIFO */
2135                                         ni_writel(dev, 0x01,
2136                                                   AIFIFO_Control_6143);
2137                                         dl = ni_readl(dev, AIFIFO_Data_6143);
2138                                         break;
2139                                 }
2140                         }
2141                         if (i == NI_TIMEOUT) {
2142                                 dev_err(dev->class_dev, "timeout\n");
2143                                 return -ETIME;
2144                         }
2145                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2146                 }
2147         } else {
2148                 for (n = 0; n < insn->n; n++) {
2149                         ni_stc_writew(dev, AI_CONVERT_Pulse,
2150                                       AI_Command_1_Register);
2151                         for (i = 0; i < NI_TIMEOUT; i++) {
2152                                 if (!(ni_stc_readw(dev, AI_Status_1_Register) &
2153                                       AI_FIFO_Empty_St))
2154                                         break;
2155                         }
2156                         if (i == NI_TIMEOUT) {
2157                                 dev_err(dev->class_dev, "timeout\n");
2158                                 return -ETIME;
2159                         }
2160                         if (devpriv->is_m_series) {
2161                                 dl = ni_readl(dev, M_Offset_AI_FIFO_Data);
2162                                 dl &= mask;
2163                                 data[n] = dl;
2164                         } else {
2165                                 d = ni_readw(dev, ADC_FIFO_Data_Register);
2166                                 d += signbits;  /* subtle: needs to be short addition */
2167                                 data[n] = d;
2168                         }
2169                 }
2170         }
2171         return insn->n;
2172 }
2173
2174 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2175                           unsigned int flags)
2176 {
2177         struct ni_private *devpriv = dev->private;
2178         int divider;
2179
2180         switch (flags & CMDF_ROUND_MASK) {
2181         case CMDF_ROUND_NEAREST:
2182         default:
2183                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2184                 break;
2185         case CMDF_ROUND_DOWN:
2186                 divider = (nanosec) / devpriv->clock_ns;
2187                 break;
2188         case CMDF_ROUND_UP:
2189                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2190                 break;
2191         }
2192         return divider - 1;
2193 }
2194
2195 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2196 {
2197         struct ni_private *devpriv = dev->private;
2198
2199         return devpriv->clock_ns * (timer + 1);
2200 }
2201
2202 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2203                                          unsigned num_channels)
2204 {
2205         const struct ni_board_struct *board = dev->board_ptr;
2206         struct ni_private *devpriv = dev->private;
2207
2208         /* simultaneously-sampled inputs */
2209         if (devpriv->is_611x || devpriv->is_6143)
2210                 return board->ai_speed;
2211
2212         /* multiplexed inputs */
2213         return board->ai_speed * num_channels;
2214 }
2215
2216 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2217                          struct comedi_cmd *cmd)
2218 {
2219         const struct ni_board_struct *board = dev->board_ptr;
2220         struct ni_private *devpriv = dev->private;
2221         int err = 0;
2222         unsigned int tmp;
2223         unsigned int sources;
2224
2225         /* Step 1 : check if triggers are trivially valid */
2226
2227         err |= comedi_check_trigger_src(&cmd->start_src,
2228                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2229         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2230                                         TRIG_TIMER | TRIG_EXT);
2231
2232         sources = TRIG_TIMER | TRIG_EXT;
2233         if (devpriv->is_611x || devpriv->is_6143)
2234                 sources |= TRIG_NOW;
2235         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2236
2237         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2238         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2239
2240         if (err)
2241                 return 1;
2242
2243         /* Step 2a : make sure trigger sources are unique */
2244
2245         err |= comedi_check_trigger_is_unique(cmd->start_src);
2246         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2247         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2248         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2249
2250         /* Step 2b : and mutually compatible */
2251
2252         if (err)
2253                 return 2;
2254
2255         /* Step 3: check if arguments are trivially valid */
2256
2257         switch (cmd->start_src) {
2258         case TRIG_NOW:
2259         case TRIG_INT:
2260                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2261                 break;
2262         case TRIG_EXT:
2263                 tmp = CR_CHAN(cmd->start_arg);
2264
2265                 if (tmp > 16)
2266                         tmp = 16;
2267                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2268                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2269                 break;
2270         }
2271
2272         if (cmd->scan_begin_src == TRIG_TIMER) {
2273                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2274                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2275                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2276                                                     devpriv->clock_ns *
2277                                                     0xffffff);
2278         } else if (cmd->scan_begin_src == TRIG_EXT) {
2279                 /* external trigger */
2280                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2281
2282                 if (tmp > 16)
2283                         tmp = 16;
2284                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2285                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2286         } else {                /* TRIG_OTHER */
2287                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2288         }
2289
2290         if (cmd->convert_src == TRIG_TIMER) {
2291                 if (devpriv->is_611x || devpriv->is_6143) {
2292                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2293                                                            0);
2294                 } else {
2295                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2296                                                             board->ai_speed);
2297                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2298                                                             devpriv->clock_ns *
2299                                                             0xffff);
2300                 }
2301         } else if (cmd->convert_src == TRIG_EXT) {
2302                 /* external trigger */
2303                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2304
2305                 if (tmp > 16)
2306                         tmp = 16;
2307                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2308                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2309         } else if (cmd->convert_src == TRIG_NOW) {
2310                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2311         }
2312
2313         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2314                                            cmd->chanlist_len);
2315
2316         if (cmd->stop_src == TRIG_COUNT) {
2317                 unsigned int max_count = 0x01000000;
2318
2319                 if (devpriv->is_611x)
2320                         max_count -= num_adc_stages_611x;
2321                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2322                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2323         } else {
2324                 /* TRIG_NONE */
2325                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2326         }
2327
2328         if (err)
2329                 return 3;
2330
2331         /* step 4: fix up any arguments */
2332
2333         if (cmd->scan_begin_src == TRIG_TIMER) {
2334                 tmp = cmd->scan_begin_arg;
2335                 cmd->scan_begin_arg =
2336                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2337                                                        cmd->scan_begin_arg,
2338                                                        cmd->flags));
2339                 if (tmp != cmd->scan_begin_arg)
2340                         err++;
2341         }
2342         if (cmd->convert_src == TRIG_TIMER) {
2343                 if (!devpriv->is_611x && !devpriv->is_6143) {
2344                         tmp = cmd->convert_arg;
2345                         cmd->convert_arg =
2346                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2347                                                                cmd->convert_arg,
2348                                                                cmd->flags));
2349                         if (tmp != cmd->convert_arg)
2350                                 err++;
2351                         if (cmd->scan_begin_src == TRIG_TIMER &&
2352                             cmd->scan_begin_arg <
2353                             cmd->convert_arg * cmd->scan_end_arg) {
2354                                 cmd->scan_begin_arg =
2355                                     cmd->convert_arg * cmd->scan_end_arg;
2356                                 err++;
2357                         }
2358                 }
2359         }
2360
2361         if (err)
2362                 return 4;
2363
2364         return 0;
2365 }
2366
2367 static int ni_ai_inttrig(struct comedi_device *dev,
2368                          struct comedi_subdevice *s,
2369                          unsigned int trig_num)
2370 {
2371         struct ni_private *devpriv = dev->private;
2372         struct comedi_cmd *cmd = &s->async->cmd;
2373
2374         if (trig_num != cmd->start_arg)
2375                 return -EINVAL;
2376
2377         ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2378                       AI_Command_2_Register);
2379         s->async->inttrig = NULL;
2380
2381         return 1;
2382 }
2383
2384 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2385 {
2386         struct ni_private *devpriv = dev->private;
2387         const struct comedi_cmd *cmd = &s->async->cmd;
2388         int timer;
2389         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2390         int mode2 = 0;
2391         int start_stop_select = 0;
2392         unsigned int stop_count;
2393         int interrupt_a_enable = 0;
2394
2395         if (dev->irq == 0) {
2396                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2397                 return -EIO;
2398         }
2399         ni_clear_ai_fifo(dev);
2400
2401         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2402
2403         /* start configuration */
2404         ni_stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2405
2406         /* disable analog triggering for now, since it
2407          * interferes with the use of pfi0 */
2408         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2409         ni_stc_writew(dev, devpriv->an_trig_etc_reg,
2410                       Analog_Trigger_Etc_Register);
2411
2412         switch (cmd->start_src) {
2413         case TRIG_INT:
2414         case TRIG_NOW:
2415                 ni_stc_writew(dev,
2416                               AI_START2_Select(0) |
2417                               AI_START1_Sync | AI_START1_Edge |
2418                               AI_START1_Select(0),
2419                               AI_Trigger_Select_Register);
2420                 break;
2421         case TRIG_EXT:
2422                 {
2423                         int chan = CR_CHAN(cmd->start_arg);
2424                         unsigned int bits = AI_START2_Select(0) |
2425                             AI_START1_Sync | AI_START1_Select(chan + 1);
2426
2427                         if (cmd->start_arg & CR_INVERT)
2428                                 bits |= AI_START1_Polarity;
2429                         if (cmd->start_arg & CR_EDGE)
2430                                 bits |= AI_START1_Edge;
2431                         ni_stc_writew(dev, bits, AI_Trigger_Select_Register);
2432                         break;
2433                 }
2434         }
2435
2436         mode2 &= ~AI_Pre_Trigger;
2437         mode2 &= ~AI_SC_Initial_Load_Source;
2438         mode2 &= ~AI_SC_Reload_Mode;
2439         ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2440
2441         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2442                 start_stop_select |= AI_STOP_Polarity;
2443                 start_stop_select |= AI_STOP_Select(31);        /*  logic low */
2444                 start_stop_select |= AI_STOP_Sync;
2445         } else {
2446                 start_stop_select |= AI_STOP_Select(19);        /*  ai configuration memory */
2447         }
2448         ni_stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2449
2450         devpriv->ai_cmd2 = 0;
2451         switch (cmd->stop_src) {
2452         case TRIG_COUNT:
2453                 stop_count = cmd->stop_arg - 1;
2454
2455                 if (devpriv->is_611x) {
2456                         /*  have to take 3 stage adc pipeline into account */
2457                         stop_count += num_adc_stages_611x;
2458                 }
2459                 /* stage number of scans */
2460                 ni_stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2461
2462                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2463                 ni_stc_writew(dev, mode1, AI_Mode_1_Register);
2464                 /* load SC (Scan Count) */
2465                 ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2466
2467                 if (stop_count == 0) {
2468                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2469                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2470                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2471                         if (cmd->chanlist_len > 1)
2472                                 start_stop_select |=
2473                                     AI_STOP_Polarity | AI_STOP_Edge;
2474                 }
2475                 break;
2476         case TRIG_NONE:
2477                 /* stage number of scans */
2478                 ni_stc_writel(dev, 0, AI_SC_Load_A_Registers);
2479
2480                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2481                 ni_stc_writew(dev, mode1, AI_Mode_1_Register);
2482
2483                 /* load SC (Scan Count) */
2484                 ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2485                 break;
2486         }
2487
2488         switch (cmd->scan_begin_src) {
2489         case TRIG_TIMER:
2490                 /*
2491                    stop bits for non 611x boards
2492                    AI_SI_Special_Trigger_Delay=0
2493                    AI_Pre_Trigger=0
2494                    AI_START_STOP_Select_Register:
2495                    AI_START_Polarity=0 (?)      rising edge
2496                    AI_START_Edge=1              edge triggered
2497                    AI_START_Sync=1 (?)
2498                    AI_START_Select=0            SI_TC
2499                    AI_STOP_Polarity=0           rising edge
2500                    AI_STOP_Edge=0               level
2501                    AI_STOP_Sync=1
2502                    AI_STOP_Select=19            external pin (configuration mem)
2503                  */
2504                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2505                 ni_stc_writew(dev, start_stop_select,
2506                               AI_START_STOP_Select_Register);
2507
2508                 mode2 |= AI_SI_Reload_Mode(0);
2509                 /* AI_SI_Initial_Load_Source=A */
2510                 mode2 &= ~AI_SI_Initial_Load_Source;
2511                 /* mode2 |= AI_SC_Reload_Mode; */
2512                 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2513
2514                 /* load SI */
2515                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2516                                        CMDF_ROUND_NEAREST);
2517                 ni_stc_writel(dev, timer, AI_SI_Load_A_Registers);
2518                 ni_stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2519                 break;
2520         case TRIG_EXT:
2521                 if (cmd->scan_begin_arg & CR_EDGE)
2522                         start_stop_select |= AI_START_Edge;
2523                 /* AI_START_Polarity==1 is falling edge */
2524                 if (cmd->scan_begin_arg & CR_INVERT)
2525                         start_stop_select |= AI_START_Polarity;
2526                 if (cmd->scan_begin_src != cmd->convert_src ||
2527                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2528                     (cmd->convert_arg & ~CR_EDGE))
2529                         start_stop_select |= AI_START_Sync;
2530                 start_stop_select |=
2531                     AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2532                 ni_stc_writew(dev, start_stop_select,
2533                               AI_START_STOP_Select_Register);
2534                 break;
2535         }
2536
2537         switch (cmd->convert_src) {
2538         case TRIG_TIMER:
2539         case TRIG_NOW:
2540                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2541                         timer = 1;
2542                 else
2543                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2544                                                CMDF_ROUND_NEAREST);
2545                 /* 0,0 does not work */
2546                 ni_stc_writew(dev, 1, AI_SI2_Load_A_Register);
2547                 ni_stc_writew(dev, timer, AI_SI2_Load_B_Register);
2548
2549                 /* AI_SI2_Reload_Mode = alternate */
2550                 /* AI_SI2_Initial_Load_Source = A */
2551                 mode2 &= ~AI_SI2_Initial_Load_Source;
2552                 mode2 |= AI_SI2_Reload_Mode;
2553                 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2554
2555                 /* AI_SI2_Load */
2556                 ni_stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2557
2558                 mode2 |= AI_SI2_Reload_Mode;    /*  alternate */
2559                 mode2 |= AI_SI2_Initial_Load_Source;    /*  B */
2560
2561                 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2562                 break;
2563         case TRIG_EXT:
2564                 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2565                 if ((cmd->convert_arg & CR_INVERT) == 0)
2566                         mode1 |= AI_CONVERT_Source_Polarity;
2567                 ni_stc_writew(dev, mode1, AI_Mode_1_Register);
2568
2569                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2570                 ni_stc_writew(dev, mode2, AI_Mode_2_Register);
2571
2572                 break;
2573         }
2574
2575         if (dev->irq) {
2576                 /* interrupt on FIFO, errors, SC_TC */
2577                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2578                     AI_SC_TC_Interrupt_Enable;
2579
2580 #ifndef PCIDMA
2581                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2582 #endif
2583
2584                 if (cmd->flags & CMDF_WAKE_EOS
2585                     || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2586                         /* wake on end-of-scan */
2587                         devpriv->aimode = AIMODE_SCAN;
2588                 } else {
2589                         devpriv->aimode = AIMODE_HALF_FULL;
2590                 }
2591
2592                 switch (devpriv->aimode) {
2593                 case AIMODE_HALF_FULL:
2594                         /*generate FIFO interrupts and DMA requests on half-full */
2595 #ifdef PCIDMA
2596                         ni_stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2597                                       AI_Mode_3_Register);
2598 #else
2599                         ni_stc_writew(dev, AI_FIFO_Mode_HF,
2600                                       AI_Mode_3_Register);
2601 #endif
2602                         break;
2603                 case AIMODE_SAMPLE:
2604                         /*generate FIFO interrupts on non-empty */
2605                         ni_stc_writew(dev, AI_FIFO_Mode_NE,
2606                                       AI_Mode_3_Register);
2607                         break;
2608                 case AIMODE_SCAN:
2609 #ifdef PCIDMA
2610                         ni_stc_writew(dev, AI_FIFO_Mode_NE,
2611                                       AI_Mode_3_Register);
2612 #else
2613                         ni_stc_writew(dev, AI_FIFO_Mode_HF,
2614                                       AI_Mode_3_Register);
2615 #endif
2616                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2617                         break;
2618                 default:
2619                         break;
2620                 }
2621
2622                 /* clear interrupts */
2623                 ni_stc_writew(dev,
2624                               AI_Error_Interrupt_Ack |
2625                               AI_STOP_Interrupt_Ack |
2626                               AI_START_Interrupt_Ack |
2627                               AI_START2_Interrupt_Ack |
2628                               AI_START1_Interrupt_Ack |
2629                               AI_SC_TC_Interrupt_Ack |
2630                               AI_SC_TC_Error_Confirm,
2631                               Interrupt_A_Ack_Register);
2632
2633                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2634                             interrupt_a_enable, 1);
2635         } else {
2636                 /* interrupt on nothing */
2637                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2638
2639                 /* XXX start polling if necessary */
2640         }
2641
2642         /* end configuration */
2643         ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2644
2645         switch (cmd->scan_begin_src) {
2646         case TRIG_TIMER:
2647                 ni_stc_writew(dev,
2648                               AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2649                               AI_Command_1_Register);
2650                 break;
2651         case TRIG_EXT:
2652                 /* XXX AI_SI_Arm? */
2653                 ni_stc_writew(dev,
2654                               AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2655                               AI_Command_1_Register);
2656                 break;
2657         }
2658
2659 #ifdef PCIDMA
2660         {
2661                 int retval = ni_ai_setup_MITE_dma(dev);
2662
2663                 if (retval)
2664                         return retval;
2665         }
2666 #endif
2667
2668         if (cmd->start_src == TRIG_NOW) {
2669                 /* AI_START1_Pulse */
2670                 ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2671                               AI_Command_2_Register);
2672                 s->async->inttrig = NULL;
2673         } else if (cmd->start_src == TRIG_EXT) {
2674                 s->async->inttrig = NULL;
2675         } else {        /* TRIG_INT */
2676                 s->async->inttrig = ni_ai_inttrig;
2677         }
2678
2679         return 0;
2680 }
2681
2682 static int ni_ai_insn_config(struct comedi_device *dev,
2683                              struct comedi_subdevice *s,
2684                              struct comedi_insn *insn, unsigned int *data)
2685 {
2686         struct ni_private *devpriv = dev->private;
2687
2688         if (insn->n < 1)
2689                 return -EINVAL;
2690
2691         switch (data[0]) {
2692         case INSN_CONFIG_ALT_SOURCE:
2693                 if (devpriv->is_m_series) {
2694                         if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2695                                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2696                                         MSeries_AI_Bypass_Mode_Mux_Mask |
2697                                         MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2698                                 return -EINVAL;
2699                         }
2700                         devpriv->ai_calib_source = data[1];
2701                 } else if (devpriv->is_6143) {
2702                         unsigned int calib_source;
2703
2704                         calib_source = data[1] & 0xf;
2705
2706                         devpriv->ai_calib_source = calib_source;
2707                         ni_writew(dev, calib_source, Calibration_Channel_6143);
2708                 } else {
2709                         unsigned int calib_source;
2710                         unsigned int calib_source_adjust;
2711
2712                         calib_source = data[1] & 0xf;
2713                         calib_source_adjust = (data[1] >> 4) & 0xff;
2714
2715                         if (calib_source >= 8)
2716                                 return -EINVAL;
2717                         devpriv->ai_calib_source = calib_source;
2718                         if (devpriv->is_611x) {
2719                                 ni_writeb(dev, calib_source_adjust,
2720                                           Cal_Gain_Select_611x);
2721                         }
2722                 }
2723                 return 2;
2724         default:
2725                 break;
2726         }
2727
2728         return -EINVAL;
2729 }
2730
2731 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2732                         void *data, unsigned int num_bytes,
2733                         unsigned int chan_index)
2734 {
2735         struct comedi_cmd *cmd = &s->async->cmd;
2736         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2737         unsigned short *array = data;
2738         unsigned int i;
2739
2740         for (i = 0; i < nsamples; i++) {
2741                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2742                 unsigned short val = array[i];
2743
2744                 /*
2745                  * Munge data from unsigned to two's complement for
2746                  * bipolar ranges.
2747                  */
2748                 if (comedi_range_is_bipolar(s, range))
2749                         val = comedi_offset_munge(s, val);
2750 #ifdef PCIDMA
2751                 val = cpu_to_le16(val);
2752 #endif
2753                 array[i] = val;
2754
2755                 chan_index++;
2756                 chan_index %= cmd->chanlist_len;
2757         }
2758 }
2759
2760 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2761                                           struct comedi_subdevice *s,
2762                                           unsigned int chanspec[],
2763                                           unsigned int n_chans, int timed)
2764 {
2765         struct ni_private *devpriv = dev->private;
2766         unsigned int range;
2767         unsigned int chan;
2768         unsigned int conf;
2769         int i;
2770         int invert = 0;
2771
2772         if (timed) {
2773                 for (i = 0; i < s->n_chan; ++i) {
2774                         devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2775                         ni_writeb(dev, devpriv->ao_conf[i],
2776                                   M_Offset_AO_Config_Bank(i));
2777                         ni_writeb(dev, 0xf, M_Offset_AO_Waveform_Order(i));
2778                 }
2779         }
2780         for (i = 0; i < n_chans; i++) {
2781                 const struct comedi_krange *krange;
2782
2783                 chan = CR_CHAN(chanspec[i]);
2784                 range = CR_RANGE(chanspec[i]);
2785                 krange = s->range_table->range + range;
2786                 invert = 0;
2787                 conf = 0;
2788                 switch (krange->max - krange->min) {
2789                 case 20000000:
2790                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2791                         ni_writeb(dev, 0,
2792                                   M_Offset_AO_Reference_Attenuation(chan));
2793                         break;
2794                 case 10000000:
2795                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2796                         ni_writeb(dev, 0,
2797                                   M_Offset_AO_Reference_Attenuation(chan));
2798                         break;
2799                 case 4000000:
2800                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2801                         ni_writeb(dev, MSeries_Attenuate_x5_Bit,
2802                                   M_Offset_AO_Reference_Attenuation(chan));
2803                         break;
2804                 case 2000000:
2805                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2806                         ni_writeb(dev, MSeries_Attenuate_x5_Bit,
2807                                   M_Offset_AO_Reference_Attenuation(chan));
2808                         break;
2809                 default:
2810                         dev_err(dev->class_dev,
2811                                 "bug! unhandled ao reference voltage\n");
2812                         break;
2813                 }
2814                 switch (krange->max + krange->min) {
2815                 case 0:
2816                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2817                         break;
2818                 case 10000000:
2819                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2820                         break;
2821                 default:
2822                         dev_err(dev->class_dev,
2823                                 "bug! unhandled ao offset voltage\n");
2824                         break;
2825                 }
2826                 if (timed)
2827                         conf |= MSeries_AO_Update_Timed_Bit;
2828                 ni_writeb(dev, conf, M_Offset_AO_Config_Bank(chan));
2829                 devpriv->ao_conf[chan] = conf;
2830                 ni_writeb(dev, i, M_Offset_AO_Waveform_Order(chan));
2831         }
2832         return invert;
2833 }
2834
2835 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2836                                      struct comedi_subdevice *s,
2837                                      unsigned int chanspec[],
2838                                      unsigned int n_chans)
2839 {
2840         struct ni_private *devpriv = dev->private;
2841         unsigned int range;
2842         unsigned int chan;
2843         unsigned int conf;
2844         int i;
2845         int invert = 0;
2846
2847         for (i = 0; i < n_chans; i++) {
2848                 chan = CR_CHAN(chanspec[i]);
2849                 range = CR_RANGE(chanspec[i]);
2850                 conf = AO_Channel(chan);
2851
2852                 if (comedi_range_is_bipolar(s, range)) {
2853                         conf |= AO_Bipolar;
2854                         invert = (s->maxdata + 1) >> 1;
2855                 } else {
2856                         invert = 0;
2857                 }
2858                 if (comedi_range_is_external(s, range))
2859                         conf |= AO_Ext_Ref;
2860
2861                 /* not all boards can deglitch, but this shouldn't hurt */
2862                 if (chanspec[i] & CR_DEGLITCH)
2863                         conf |= AO_Deglitch;
2864
2865                 /* analog reference */
2866                 /* AREF_OTHER connects AO ground to AI ground, i think */
2867                 conf |= (CR_AREF(chanspec[i]) ==
2868                          AREF_OTHER) ? AO_Ground_Ref : 0;
2869
2870                 ni_writew(dev, conf, AO_Configuration);
2871                 devpriv->ao_conf[chan] = conf;
2872         }
2873         return invert;
2874 }
2875
2876 static int ni_ao_config_chanlist(struct comedi_device *dev,
2877                                  struct comedi_subdevice *s,
2878                                  unsigned int chanspec[], unsigned int n_chans,
2879                                  int timed)
2880 {
2881         struct ni_private *devpriv = dev->private;
2882
2883         if (devpriv->is_m_series)
2884                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2885                                                       timed);
2886         else
2887                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2888 }
2889
2890 static int ni_ao_insn_write(struct comedi_device *dev,
2891                             struct comedi_subdevice *s,
2892                             struct comedi_insn *insn,
2893                             unsigned int *data)
2894 {
2895         struct ni_private *devpriv = dev->private;
2896         unsigned int chan = CR_CHAN(insn->chanspec);
2897         unsigned int range = CR_RANGE(insn->chanspec);
2898         int reg;
2899         int i;
2900
2901         if (devpriv->is_6xxx) {
2902                 ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x);
2903
2904                 reg = DACx_Direct_Data_671x(chan);
2905         } else if (devpriv->is_m_series) {
2906                 reg = M_Offset_DAC_Direct_Data(chan);
2907         } else {
2908                 reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data;
2909         }
2910
2911         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2912
2913         for (i = 0; i < insn->n; i++) {
2914                 unsigned int val = data[i];
2915
2916                 s->readback[chan] = val;
2917
2918                 if (devpriv->is_6xxx) {
2919                         /*
2920                          * 6xxx boards have bipolar outputs, munge the
2921                          * unsigned comedi values to 2's complement
2922                          */
2923                         val = comedi_offset_munge(s, val);
2924
2925                         ni_ao_win_outw(dev, val, reg);
2926                 } else if (devpriv->is_m_series) {
2927                         /*
2928                          * M-series boards use offset binary values for
2929                          * bipolar and uinpolar outputs
2930                          */
2931                         ni_writew(dev, val, reg);
2932                 } else {
2933                         /*
2934                          * Non-M series boards need two's complement values
2935                          * for bipolar ranges.
2936                          */
2937                         if (comedi_range_is_bipolar(s, range))
2938                                 val = comedi_offset_munge(s, val);
2939
2940                         ni_writew(dev, val, reg);
2941                 }
2942         }
2943
2944         return insn->n;
2945 }
2946
2947 static int ni_ao_insn_config(struct comedi_device *dev,
2948                              struct comedi_subdevice *s,
2949                              struct comedi_insn *insn, unsigned int *data)
2950 {
2951         const struct ni_board_struct *board = dev->board_ptr;
2952         struct ni_private *devpriv = dev->private;
2953         unsigned int nbytes;
2954
2955         switch (data[0]) {
2956         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2957                 switch (data[1]) {
2958                 case COMEDI_OUTPUT:
2959                         nbytes = comedi_samples_to_bytes(s,
2960                                                          board->ao_fifo_depth);
2961                         data[2] = 1 + nbytes;
2962                         if (devpriv->mite)
2963                                 data[2] += devpriv->mite->fifo_size;
2964                         break;
2965                 case COMEDI_INPUT:
2966                         data[2] = 0;
2967                         break;
2968                 default:
2969                         return -EINVAL;
2970                 }
2971                 return 0;
2972         default:
2973                 break;
2974         }
2975
2976         return -EINVAL;
2977 }
2978
2979 static int ni_ao_inttrig(struct comedi_device *dev,
2980                          struct comedi_subdevice *s,
2981                          unsigned int trig_num)
2982 {
2983         struct ni_private *devpriv = dev->private;
2984         struct comedi_cmd *cmd = &s->async->cmd;
2985         int ret;
2986         int interrupt_b_bits;
2987         int i;
2988         static const int timeout = 1000;
2989
2990         if (trig_num != cmd->start_arg)
2991                 return -EINVAL;
2992
2993         /* Null trig at beginning prevent ao start trigger from executing more than
2994            once per command (and doing things like trying to allocate the ao dma channel
2995            multiple times) */
2996         s->async->inttrig = NULL;
2997
2998         ni_set_bits(dev, Interrupt_B_Enable_Register,
2999                     AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3000         interrupt_b_bits = AO_Error_Interrupt_Enable;
3001 #ifdef PCIDMA
3002         ni_stc_writew(dev, 1, DAC_FIFO_Clear);
3003         if (devpriv->is_6xxx)
3004                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3005         ret = ni_ao_setup_MITE_dma(dev);
3006         if (ret)
3007                 return ret;
3008         ret = ni_ao_wait_for_dma_load(dev);
3009         if (ret < 0)
3010                 return ret;
3011 #else
3012         ret = ni_ao_prep_fifo(dev, s);
3013         if (ret == 0)
3014                 return -EPIPE;
3015
3016         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3017 #endif
3018
3019         ni_stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3020                       AO_Mode_3_Register);
3021         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3022         /* wait for DACs to be loaded */
3023         for (i = 0; i < timeout; i++) {
3024                 udelay(1);
3025                 if ((ni_stc_readw(dev, Joint_Status_2_Register) &
3026                      AO_TMRDACWRs_In_Progress_St) == 0)
3027                         break;
3028         }
3029         if (i == timeout) {
3030                 dev_err(dev->class_dev,
3031                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
3032                 return -EIO;
3033         }
3034         /*
3035          * stc manual says we are need to clear error interrupt after
3036          * AO_TMRDACWRs_In_Progress_St clears
3037          */
3038         ni_stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
3039
3040         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3041
3042         ni_stc_writew(dev, devpriv->ao_cmd1 |
3043                       AO_UI_Arm | AO_UC_Arm | AO_BC_Arm |
3044                       AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3045                       AO_Command_1_Register);
3046
3047         ni_stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3048                       AO_Command_2_Register);
3049
3050         return 0;
3051 }
3052
3053 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3054 {
3055         const struct ni_board_struct *board = dev->board_ptr;
3056         struct ni_private *devpriv = dev->private;
3057         const struct comedi_cmd *cmd = &s->async->cmd;
3058         int bits;
3059         int i;
3060         unsigned trigvar;
3061
3062         if (dev->irq == 0) {
3063                 dev_err(dev->class_dev, "cannot run command without an irq\n");
3064                 return -EIO;
3065         }
3066
3067         ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3068
3069         ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3070
3071         if (devpriv->is_6xxx) {
3072                 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
3073
3074                 bits = 0;
3075                 for (i = 0; i < cmd->chanlist_len; i++) {
3076                         int chan;
3077
3078                         chan = CR_CHAN(cmd->chanlist[i]);
3079                         bits |= 1 << chan;
3080                         ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x);
3081                 }
3082                 ni_ao_win_outw(dev, bits, AO_Timed_611x);
3083         }
3084
3085         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3086
3087         if (cmd->stop_src == TRIG_NONE) {
3088                 devpriv->ao_mode1 |= AO_Continuous;
3089                 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3090         } else {
3091                 devpriv->ao_mode1 &= ~AO_Continuous;
3092                 devpriv->ao_mode1 |= AO_Trigger_Once;
3093         }
3094         ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3095         switch (cmd->start_src) {
3096         case TRIG_INT:
3097         case TRIG_NOW:
3098                 devpriv->ao_trigger_select &=
3099                     ~(AO_START1_Polarity | AO_START1_Select(-1));
3100                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3101                 ni_stc_writew(dev, devpriv->ao_trigger_select,
3102                               AO_Trigger_Select_Register);
3103                 break;
3104         case TRIG_EXT:
3105                 devpriv->ao_trigger_select =
3106                     AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3107                 if (cmd->start_arg & CR_INVERT)
3108                         devpriv->ao_trigger_select |= AO_START1_Polarity;       /*  0=active high, 1=active low. see daq-stc 3-24 (p186) */
3109                 if (cmd->start_arg & CR_EDGE)
3110                         devpriv->ao_trigger_select |= AO_START1_Edge;   /*  0=edge detection disabled, 1=enabled */
3111                 ni_stc_writew(dev, devpriv->ao_trigger_select,
3112                               AO_Trigger_Select_Register);
3113                 break;
3114         default:
3115                 BUG();
3116                 break;
3117         }
3118         devpriv->ao_mode3 &= ~AO_Trigger_Length;
3119         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3120
3121         ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3122         devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3123         ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3124         if (cmd->stop_src == TRIG_NONE)
3125                 ni_stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3126         else
3127                 ni_stc_writel(dev, 0, AO_BC_Load_A_Register);
3128         ni_stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3129         devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3130         ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3131         switch (cmd->stop_src) {
3132         case TRIG_COUNT:
3133                 if (devpriv->is_m_series) {
3134                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
3135                         ni_stc_writel(dev, cmd->stop_arg - 1,
3136                                       AO_UC_Load_A_Register);
3137                         ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3138                 } else {
3139                         ni_stc_writel(dev, cmd->stop_arg,
3140                                       AO_UC_Load_A_Register);
3141                         ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3142                         ni_stc_writel(dev, cmd->stop_arg - 1,
3143                                       AO_UC_Load_A_Register);
3144                 }
3145                 break;
3146         case TRIG_NONE:
3147                 ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3148                 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3149                 ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3150                 break;
3151         default:
3152                 ni_stc_writel(dev, 0, AO_UC_Load_A_Register);
3153                 ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3154                 ni_stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3155         }
3156
3157         devpriv->ao_mode1 &=
3158             ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3159               AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3160         switch (cmd->scan_begin_src) {
3161         case TRIG_TIMER:
3162                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3163                 trigvar =
3164                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3165                                    CMDF_ROUND_NEAREST);
3166                 ni_stc_writel(dev, 1, AO_UI_Load_A_Register);
3167                 ni_stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3168                 ni_stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3169                 break;
3170         case TRIG_EXT:
3171                 devpriv->ao_mode1 |=
3172                     AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3173                 if (cmd->scan_begin_arg & CR_INVERT)
3174                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3175                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3176                 break;
3177         default:
3178                 BUG();
3179                 break;
3180         }
3181         ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3182         ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3183         devpriv->ao_mode2 &=
3184             ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3185         ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3186
3187         if (cmd->scan_end_arg > 1) {
3188                 devpriv->ao_mode1 |= AO_Multiple_Channels;
3189                 ni_stc_writew(dev,
3190                               AO_Number_Of_Channels(cmd->scan_end_arg - 1) |
3191                               AO_UPDATE_Output_Select(AO_Update_Output_High_Z),
3192                               AO_Output_Control_Register);
3193         } else {
3194                 unsigned bits;
3195
3196                 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3197                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3198                 if (devpriv->is_m_series || devpriv->is_6xxx) {
3199                         bits |= AO_Number_Of_Channels(0);
3200                 } else {
3201                         bits |=
3202                             AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3203                 }
3204                 ni_stc_writew(dev, bits, AO_Output_Control_Register);
3205         }
3206         ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3207
3208         ni_stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3209                       AO_Command_1_Register);
3210
3211         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3212         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3213
3214         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3215 #ifdef PCIDMA
3216         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3217 #else
3218         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3219 #endif
3220         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3221         ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3222
3223         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3224             AO_TMRDACWR_Pulse_Width;
3225         if (board->ao_fifo_depth)
3226                 bits |= AO_FIFO_Enable;
3227         else
3228                 bits |= AO_DMA_PIO_Control;
3229 #if 0
3230         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3231            verified with bus analyzer. */
3232         if (devpriv->is_m_series)
3233                 bits |= AO_Number_Of_DAC_Packages;
3234 #endif
3235         ni_stc_writew(dev, bits, AO_Personal_Register);
3236         /*  enable sending of ao dma requests */
3237         ni_stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3238
3239         ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3240
3241         if (cmd->stop_src == TRIG_COUNT) {
3242                 ni_stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3243                               Interrupt_B_Ack_Register);
3244                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3245                             AO_BC_TC_Interrupt_Enable, 1);
3246         }
3247
3248         s->async->inttrig = ni_ao_inttrig;
3249
3250         return 0;
3251 }
3252
3253 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3254                          struct comedi_cmd *cmd)
3255 {
3256         const struct ni_board_struct *board = dev->board_ptr;
3257         struct ni_private *devpriv = dev->private;
3258         int err = 0;
3259         unsigned int tmp;
3260
3261         /* Step 1 : check if triggers are trivially valid */
3262
3263         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3264         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3265                                         TRIG_TIMER | TRIG_EXT);
3266         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3267         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3268         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3269
3270         if (err)
3271                 return 1;
3272
3273         /* Step 2a : make sure trigger sources are unique */
3274
3275         err |= comedi_check_trigger_is_unique(cmd->start_src);
3276         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3277         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3278
3279         /* Step 2b : and mutually compatible */
3280
3281         if (err)
3282                 return 2;
3283
3284         /* Step 3: check if arguments are trivially valid */
3285
3286         switch (cmd->start_src) {
3287         case TRIG_INT:
3288                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3289                 break;
3290         case TRIG_EXT:
3291                 tmp = CR_CHAN(cmd->start_arg);
3292
3293                 if (tmp > 18)
3294                         tmp = 18;
3295                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3296                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3297                 break;
3298         }
3299
3300         if (cmd->scan_begin_src == TRIG_TIMER) {
3301                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3302                                                     board->ao_speed);
3303                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3304                                                     devpriv->clock_ns *
3305                                                     0xffffff);
3306         }
3307
3308         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3309         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3310                                            cmd->chanlist_len);
3311
3312         if (cmd->stop_src == TRIG_COUNT)
3313                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3314         else    /* TRIG_NONE */
3315                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3316
3317         if (err)
3318                 return 3;
3319
3320         /* step 4: fix up any arguments */
3321         if (cmd->scan_begin_src == TRIG_TIMER) {
3322                 tmp = cmd->scan_begin_arg;
3323                 cmd->scan_begin_arg =
3324                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3325                                                        cmd->scan_begin_arg,
3326                                                        cmd->flags));
3327                 if (tmp != cmd->scan_begin_arg)
3328                         err++;
3329         }
3330         if (err)
3331                 return 4;
3332
3333         return 0;
3334 }
3335
3336 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3337 {
3338         struct ni_private *devpriv = dev->private;
3339
3340         ni_release_ao_mite_channel(dev);
3341
3342         ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3343         ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3344         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3345         ni_stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3346         ni_stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3347         ni_stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3348                       AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3349         ni_stc_writew(dev, 0, AO_Output_Control_Register);
3350         ni_stc_writew(dev, 0, AO_Start_Select_Register);
3351         devpriv->ao_cmd1 = 0;
3352         ni_stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3353         devpriv->ao_cmd2 = 0;
3354         ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3355         devpriv->ao_mode1 = 0;
3356         ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3357         devpriv->ao_mode2 = 0;
3358         ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3359         if (devpriv->is_m_series)
3360                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3361         else
3362                 devpriv->ao_mode3 = 0;
3363         ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3364         devpriv->ao_trigger_select = 0;
3365         ni_stc_writew(dev, devpriv->ao_trigger_select,
3366                       AO_Trigger_Select_Register);
3367         if (devpriv->is_6xxx) {
3368                 unsigned immediate_bits = 0;
3369                 unsigned i;
3370
3371                 for (i = 0; i < s->n_chan; ++i)
3372                         immediate_bits |= 1 << i;
3373                 ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x);
3374                 ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x);
3375         }
3376         ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3377
3378         return 0;
3379 }
3380
3381 /* digital io */
3382
3383 static int ni_dio_insn_config(struct comedi_device *dev,
3384                               struct comedi_subdevice *s,
3385                               struct comedi_insn *insn,
3386                               unsigned int *data)
3387 {
3388         struct ni_private *devpriv = dev->private;
3389         int ret;
3390
3391         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3392         if (ret)
3393                 return ret;
3394
3395         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3396         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3397         ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3398
3399         return insn->n;
3400 }
3401
3402 static int ni_dio_insn_bits(struct comedi_device *dev,
3403                             struct comedi_subdevice *s,
3404                             struct comedi_insn *insn,
3405                             unsigned int *data)
3406 {
3407         struct ni_private *devpriv = dev->private;
3408
3409         /* Make sure we're not using the serial part of the dio */
3410         if ((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
3411                 return -EBUSY;
3412
3413         if (comedi_dio_update_state(s, data)) {
3414                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3415                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3416                 ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3417         }
3418
3419         data[1] = ni_stc_readw(dev, DIO_Parallel_Input_Register);
3420
3421         return insn->n;
3422 }
3423
3424 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3425                                        struct comedi_subdevice *s,
3426                                        struct comedi_insn *insn,
3427                                        unsigned int *data)
3428 {
3429         int ret;
3430
3431         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3432         if (ret)
3433                 return ret;
3434
3435         ni_writel(dev, s->io_bits, M_Offset_DIO_Direction);
3436
3437         return insn->n;
3438 }
3439
3440 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3441                                      struct comedi_subdevice *s,
3442                                      struct comedi_insn *insn,
3443                                      unsigned int *data)
3444 {
3445         if (comedi_dio_update_state(s, data))
3446                 ni_writel(dev, s->state, M_Offset_Static_Digital_Output);
3447
3448         data[1] = ni_readl(dev, M_Offset_Static_Digital_Input);
3449
3450         return insn->n;
3451 }
3452
3453 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3454                                   struct comedi_subdevice *s,
3455                                   struct comedi_cmd *cmd)
3456 {
3457         int i;
3458
3459         for (i = 0; i < cmd->chanlist_len; ++i) {
3460                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3461
3462                 if (chan != i)
3463                         return -EINVAL;
3464         }
3465
3466         return 0;
3467 }
3468
3469 static int ni_cdio_cmdtest(struct comedi_device *dev,
3470                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3471 {
3472         int err = 0;
3473         int tmp;
3474
3475         /* Step 1 : check if triggers are trivially valid */
3476
3477         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3478         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3479         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3480         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3481         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3482
3483         if (err)
3484                 return 1;
3485
3486         /* Step 2a : make sure trigger sources are unique */
3487         /* Step 2b : and mutually compatible */
3488
3489         /* Step 3: check if arguments are trivially valid */
3490
3491         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3492
3493         tmp = cmd->scan_begin_arg;
3494         tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3495         if (tmp != cmd->scan_begin_arg)
3496                 err |= -EINVAL;
3497
3498         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3499         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3500                                            cmd->chanlist_len);
3501         err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3502
3503         if (err)
3504                 return 3;
3505
3506         /* Step 4: fix up any arguments */
3507
3508         /* Step 5: check channel list if it exists */
3509
3510         if (cmd->chanlist && cmd->chanlist_len > 0)
3511                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3512
3513         if (err)
3514                 return 5;
3515
3516         return 0;
3517 }
3518
3519 static int ni_cdo_inttrig(struct comedi_device *dev,
3520                           struct comedi_subdevice *s,
3521                           unsigned int trig_num)
3522 {
3523         struct comedi_cmd *cmd = &s->async->cmd;
3524         const unsigned timeout = 1000;
3525         int retval = 0;
3526         unsigned i;
3527 #ifdef PCIDMA
3528         struct ni_private *devpriv = dev->private;
3529         unsigned long flags;
3530 #endif
3531
3532         if (trig_num != cmd->start_arg)
3533                 return -EINVAL;
3534
3535         s->async->inttrig = NULL;
3536
3537         /* read alloc the entire buffer */
3538         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3539
3540 #ifdef PCIDMA
3541         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3542         if (devpriv->cdo_mite_chan) {
3543                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3544                 mite_dma_arm(devpriv->cdo_mite_chan);
3545         } else {
3546                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3547                 retval = -EIO;
3548         }
3549         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3550         if (retval < 0)
3551                 return retval;
3552 #endif
3553 /*
3554 * XXX not sure what interrupt C group does
3555 * ni_writeb(dev, Interrupt_Group_C_Enable_Bit,
3556 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3557 */
3558         for (i = 0; i < timeout; ++i) {
3559                 if (ni_readl(dev, M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3560                         break;
3561                 udelay(10);
3562         }
3563         if (i == timeout) {
3564                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3565                 s->cancel(dev, s);
3566                 return -EIO;
3567         }
3568         ni_writel(dev, CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3569                        CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3570                   M_Offset_CDIO_Command);
3571         return retval;
3572 }
3573
3574 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3575 {
3576         const struct comedi_cmd *cmd = &s->async->cmd;
3577         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3578         int retval;
3579
3580         ni_writel(dev, CDO_Reset_Bit, M_Offset_CDIO_Command);
3581         switch (cmd->scan_begin_src) {
3582         case TRIG_EXT:
3583                 cdo_mode_bits |=
3584                     CR_CHAN(cmd->scan_begin_arg) &
3585                     CDO_Sample_Source_Select_Mask;
3586                 break;
3587         default:
3588                 BUG();
3589                 break;
3590         }
3591         if (cmd->scan_begin_arg & CR_INVERT)
3592                 cdo_mode_bits |= CDO_Polarity_Bit;
3593         ni_writel(dev, cdo_mode_bits, M_Offset_CDO_Mode);
3594         if (s->io_bits) {
3595                 ni_writel(dev, s->state, M_Offset_CDO_FIFO_Data);
3596                 ni_writel(dev, CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3597                 ni_writel(dev, s->io_bits, M_Offset_CDO_Mask_Enable);
3598         } else {
3599                 dev_err(dev->class_dev,
3600                         "attempted to run digital output command with no lines configured as outputs\n");
3601                 return -EIO;
3602         }
3603         retval = ni_request_cdo_mite_channel(dev);
3604         if (retval < 0)
3605                 return retval;
3606
3607         s->async->inttrig = ni_cdo_inttrig;
3608
3609         return 0;
3610 }
3611
3612 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3613 {
3614         ni_writel(dev, CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3615                        CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3616                        CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3617                   M_Offset_CDIO_Command);
3618 /*
3619 * XXX not sure what interrupt C group does ni_writeb(dev, 0,
3620 * M_Offset_Interrupt_C_Enable);
3621 */
3622         ni_writel(dev, 0, M_Offset_CDO_Mask_Enable);
3623         ni_release_cdo_mite_channel(dev);
3624         return 0;
3625 }
3626
3627 static void handle_cdio_interrupt(struct comedi_device *dev)
3628 {
3629         struct ni_private *devpriv = dev->private;
3630         unsigned cdio_status;
3631         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3632 #ifdef PCIDMA
3633         unsigned long flags;
3634 #endif
3635
3636         if (!devpriv->is_m_series)
3637                 return;
3638 #ifdef PCIDMA
3639         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3640         if (devpriv->cdo_mite_chan) {
3641                 unsigned cdo_mite_status =
3642                     mite_get_status(devpriv->cdo_mite_chan);
3643                 if (cdo_mite_status & CHSR_LINKC) {
3644                         writel(CHOR_CLRLC,
3645                                devpriv->mite->mite_io_addr +
3646                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3647                 }
3648                 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3649         }
3650         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3651 #endif
3652
3653         cdio_status = ni_readl(dev, M_Offset_CDIO_Status);
3654         if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3655                 /* XXX just guessing this is needed and does something useful */
3656                 ni_writel(dev, CDO_Error_Interrupt_Confirm_Bit,
3657                           M_Offset_CDIO_Command);
3658                 s->async->events |= COMEDI_CB_OVERFLOW;
3659         }
3660         if (cdio_status & CDO_FIFO_Empty_Bit) {
3661                 ni_writel(dev, CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3662                           M_Offset_CDIO_Command);
3663                 /* s->async->events |= COMEDI_CB_EOA; */
3664         }
3665         comedi_handle_events(dev, s);
3666 }
3667
3668 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3669                                    struct comedi_subdevice *s,
3670                                    unsigned char data_out,
3671                                    unsigned char *data_in)
3672 {
3673         struct ni_private *devpriv = dev->private;
3674         unsigned int status1;
3675         int err = 0, count = 20;
3676
3677         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3678         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3679         ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3680
3681         status1 = ni_stc_readw(dev, Joint_Status_1_Register);
3682         if (status1 & DIO_Serial_IO_In_Progress_St) {
3683                 err = -EBUSY;
3684                 goto Error;
3685         }
3686
3687         devpriv->dio_control |= DIO_HW_Serial_Start;
3688         ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3689         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3690
3691         /* Wait until STC says we're done, but don't loop infinitely. */
3692         while ((status1 = ni_stc_readw(dev, Joint_Status_1_Register)) &
3693                DIO_Serial_IO_In_Progress_St) {
3694                 /* Delay one bit per loop */
3695                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3696                 if (--count < 0) {
3697                         dev_err(dev->class_dev,
3698                                 "SPI serial I/O didn't finish in time!\n");
3699                         err = -ETIME;
3700                         goto Error;
3701                 }
3702         }
3703
3704         /* Delay for last bit. This delay is absolutely necessary, because
3705            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3706         udelay((devpriv->serial_interval_ns + 999) / 1000);
3707
3708         if (data_in)
3709                 *data_in = ni_stc_readw(dev, DIO_Serial_Input_Register);
3710
3711 Error:
3712         ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3713
3714         return err;
3715 }
3716
3717 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3718                                    struct comedi_subdevice *s,
3719                                    unsigned char data_out,
3720                                    unsigned char *data_in)
3721 {
3722         struct ni_private *devpriv = dev->private;
3723         unsigned char mask, input = 0;
3724
3725         /* Wait for one bit before transfer */
3726         udelay((devpriv->serial_interval_ns + 999) / 1000);
3727
3728         for (mask = 0x80; mask; mask >>= 1) {
3729                 /* Output current bit; note that we cannot touch s->state
3730                    because it is a per-subdevice field, and serial is
3731                    a separate subdevice from DIO. */
3732                 devpriv->dio_output &= ~DIO_SDOUT;
3733                 if (data_out & mask)
3734                         devpriv->dio_output |= DIO_SDOUT;
3735                 ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3736
3737                 /* Assert SDCLK (active low, inverted), wait for half of
3738                    the delay, deassert SDCLK, and wait for the other half. */
3739                 devpriv->dio_control |= DIO_Software_Serial_Control;
3740                 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3741
3742                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3743
3744                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3745                 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3746
3747                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3748
3749                 /* Input current bit */
3750                 if (ni_stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN)
3751                         input |= mask;
3752         }
3753
3754         if (data_in)
3755                 *data_in = input;
3756
3757         return 0;
3758 }
3759
3760 static int ni_serial_insn_config(struct comedi_device *dev,
3761                                  struct comedi_subdevice *s,
3762                                  struct comedi_insn *insn,
3763                                  unsigned int *data)
3764 {
3765         struct ni_private *devpriv = dev->private;
3766         int err = insn->n;
3767         unsigned char byte_out, byte_in = 0;
3768
3769         if (insn->n != 2)
3770                 return -EINVAL;
3771
3772         switch (data[0]) {
3773         case INSN_CONFIG_SERIAL_CLOCK:
3774                 devpriv->serial_hw_mode = 1;
3775                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3776
3777                 if (data[1] == SERIAL_DISABLED) {
3778                         devpriv->serial_hw_mode = 0;
3779                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3780                                                   DIO_Software_Serial_Control);
3781                         data[1] = SERIAL_DISABLED;
3782                         devpriv->serial_interval_ns = data[1];
3783                 } else if (data[1] <= SERIAL_600NS) {
3784                         /* Warning: this clock speed is too fast to reliably
3785                            control SCXI. */
3786                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3787                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3788                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3789                         data[1] = SERIAL_600NS;
3790                         devpriv->serial_interval_ns = data[1];
3791                 } else if (data[1] <= SERIAL_1_2US) {
3792                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3793                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3794                             DIO_Serial_Out_Divide_By_2;
3795                         data[1] = SERIAL_1_2US;
3796                         devpriv->serial_interval_ns = data[1];
3797                 } else if (data[1] <= SERIAL_10US) {
3798                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3799                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3800                             DIO_Serial_Out_Divide_By_2;
3801                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3802                            600ns/1.2us. If you turn divide_by_2 off with the
3803                            slow clock, you will still get 10us, except then
3804                            all your delays are wrong. */
3805                         data[1] = SERIAL_10US;
3806                         devpriv->serial_interval_ns = data[1];
3807                 } else {
3808                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3809                                                   DIO_Software_Serial_Control);
3810                         devpriv->serial_hw_mode = 0;
3811                         data[1] = (data[1] / 1000) * 1000;
3812                         devpriv->serial_interval_ns = data[1];
3813                 }
3814
3815                 ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3816                 ni_stc_writew(dev, devpriv->clock_and_fout,
3817                               Clock_and_FOUT_Register);
3818                 return 1;
3819
3820         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3821
3822                 if (devpriv->serial_interval_ns == 0)
3823                         return -EINVAL;
3824
3825                 byte_out = data[1] & 0xFF;
3826
3827                 if (devpriv->serial_hw_mode) {
3828                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3829                                                       &byte_in);
3830                 } else if (devpriv->serial_interval_ns > 0) {
3831                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3832                                                       &byte_in);
3833                 } else {
3834                         dev_err(dev->class_dev, "serial disabled!\n");
3835                         return -EINVAL;
3836                 }
3837                 if (err < 0)
3838                         return err;
3839                 data[1] = byte_in & 0xFF;
3840                 return insn->n;
3841
3842                 break;
3843         default:
3844                 return -EINVAL;
3845         }
3846 }
3847
3848 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3849 {
3850         int i;
3851
3852         for (i = 0; i < s->n_chan; i++) {
3853                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
3854                                AO_Configuration_2_67xx);
3855         }
3856         ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates);
3857 }
3858
3859 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3860 {
3861         unsigned stc_register;
3862
3863         switch (reg) {
3864         case NITIO_G0_AUTO_INC:
3865                 stc_register = G_Autoincrement_Register(0);
3866                 break;
3867         case NITIO_G1_AUTO_INC:
3868                 stc_register = G_Autoincrement_Register(1);
3869                 break;
3870         case NITIO_G0_CMD:
3871                 stc_register = G_Command_Register(0);
3872                 break;
3873         case NITIO_G1_CMD:
3874                 stc_register = G_Command_Register(1);
3875                 break;
3876         case NITIO_G0_HW_SAVE:
3877                 stc_register = G_HW_Save_Register(0);
3878                 break;
3879         case NITIO_G1_HW_SAVE:
3880                 stc_register = G_HW_Save_Register(1);
3881                 break;
3882         case NITIO_G0_SW_SAVE:
3883                 stc_register = G_Save_Register(0);
3884                 break;
3885         case NITIO_G1_SW_SAVE:
3886                 stc_register = G_Save_Register(1);
3887                 break;
3888         case NITIO_G0_MODE:
3889                 stc_register = G_Mode_Register(0);
3890                 break;
3891         case NITIO_G1_MODE:
3892                 stc_register = G_Mode_Register(1);
3893                 break;
3894         case NITIO_G0_LOADA:
3895                 stc_register = G_Load_A_Register(0);
3896                 break;
3897         case NITIO_G1_LOADA:
3898                 stc_register = G_Load_A_Register(1);
3899                 break;
3900         case NITIO_G0_LOADB:
3901                 stc_register = G_Load_B_Register(0);
3902                 break;
3903         case NITIO_G1_LOADB:
3904                 stc_register = G_Load_B_Register(1);
3905                 break;
3906         case NITIO_G0_INPUT_SEL:
3907                 stc_register = G_Input_Select_Register(0);
3908                 break;
3909         case NITIO_G1_INPUT_SEL:
3910                 stc_register = G_Input_Select_Register(1);
3911                 break;
3912         case NITIO_G01_STATUS:
3913                 stc_register = G_Status_Register;
3914                 break;
3915         case NITIO_G01_RESET:
3916                 stc_register = Joint_Reset_Register;
3917                 break;
3918         case NITIO_G01_STATUS1:
3919                 stc_register = Joint_Status_1_Register;
3920                 break;
3921         case NITIO_G01_STATUS2:
3922                 stc_register = Joint_Status_2_Register;
3923                 break;
3924         case NITIO_G0_INT_ACK:
3925                 stc_register = Interrupt_A_Ack_Register;
3926                 break;
3927         case NITIO_G1_INT_ACK:
3928                 stc_register = Interrupt_B_Ack_Register;
3929                 break;
3930         case NITIO_G0_STATUS:
3931                 stc_register = AI_Status_1_Register;
3932                 break;
3933         case NITIO_G1_STATUS:
3934                 stc_register = AO_Status_1_Register;
3935                 break;
3936         case NITIO_G0_INT_ENA:
3937                 stc_register = Interrupt_A_Enable_Register;
3938                 break;
3939         case NITIO_G1_INT_ENA:
3940                 stc_register = Interrupt_B_Enable_Register;
3941                 break;
3942         default:
3943                 pr_err("%s: unhandled register 0x%x in switch.\n",
3944                        __func__, reg);
3945                 BUG();
3946                 return 0;
3947         }
3948         return stc_register;
3949 }
3950
3951 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3952                                    enum ni_gpct_register reg)
3953 {
3954         struct comedi_device *dev = counter->counter_dev->dev;
3955         unsigned stc_register;
3956         /* bits in the join reset register which are relevant to counters */
3957         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
3958         static const unsigned gpct_interrupt_a_enable_mask =
3959             G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
3960         static const unsigned gpct_interrupt_b_enable_mask =
3961             G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
3962
3963         switch (reg) {
3964                 /* m-series-only registers */
3965         case NITIO_G0_CNT_MODE:
3966                 ni_writew(dev, bits, M_Offset_G0_Counting_Mode);
3967                 break;
3968         case NITIO_G1_CNT_MODE:
3969                 ni_writew(dev, bits, M_Offset_G1_Counting_Mode);
3970                 break;
3971         case NITIO_G0_GATE2:
3972                 ni_writew(dev, bits, M_Offset_G0_Second_Gate);
3973                 break;
3974         case NITIO_G1_GATE2:
3975                 ni_writew(dev, bits, M_Offset_G1_Second_Gate);
3976                 break;
3977         case NITIO_G0_DMA_CFG:
3978                 ni_writew(dev, bits, M_Offset_G0_DMA_Config);
3979                 break;
3980         case NITIO_G1_DMA_CFG:
3981                 ni_writew(dev, bits, M_Offset_G1_DMA_Config);
3982                 break;
3983         case NITIO_G0_ABZ:
3984                 ni_writew(dev, bits, M_Offset_G0_MSeries_ABZ);
3985                 break;
3986         case NITIO_G1_ABZ:
3987                 ni_writew(dev, bits, M_Offset_G1_MSeries_ABZ);
3988                 break;
3989
3990                 /* 32 bit registers */
3991         case NITIO_G0_LOADA:
3992         case NITIO_G1_LOADA:
3993         case NITIO_G0_LOADB:
3994         case NITIO_G1_LOADB:
3995                 stc_register = ni_gpct_to_stc_register(reg);
3996                 ni_stc_writel(dev, bits, stc_register);
3997                 break;
3998
3999                 /* 16 bit registers */
4000         case NITIO_G0_INT_ENA:
4001                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4002                 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4003                                 gpct_interrupt_a_enable_mask, bits);
4004                 break;
4005         case NITIO_G1_INT_ENA:
4006                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4007                 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4008                                 gpct_interrupt_b_enable_mask, bits);
4009                 break;
4010         case NITIO_G01_RESET:
4011                 BUG_ON(bits & ~gpct_joint_reset_mask);
4012                 /* fall-through */
4013         default:
4014                 stc_register = ni_gpct_to_stc_register(reg);
4015                 ni_stc_writew(dev, bits, stc_register);
4016         }
4017 }
4018
4019 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4020                                       enum ni_gpct_register reg)
4021 {
4022         struct comedi_device *dev = counter->counter_dev->dev;
4023         unsigned stc_register;
4024
4025         switch (reg) {
4026                 /* m-series only registers */
4027         case NITIO_G0_DMA_STATUS:
4028                 return ni_readw(dev, M_Offset_G0_DMA_Status);
4029         case NITIO_G1_DMA_STATUS:
4030                 return ni_readw(dev, M_Offset_G1_DMA_Status);
4031
4032                 /* 32 bit registers */
4033         case NITIO_G0_HW_SAVE:
4034         case NITIO_G1_HW_SAVE:
4035         case NITIO_G0_SW_SAVE:
4036         case NITIO_G1_SW_SAVE:
4037                 stc_register = ni_gpct_to_stc_register(reg);
4038                 return ni_stc_readl(dev, stc_register);
4039
4040                 /* 16 bit registers */
4041         default:
4042                 stc_register = ni_gpct_to_stc_register(reg);
4043                 return ni_stc_readw(dev, stc_register);
4044         }
4045         return 0;
4046 }
4047
4048 static int ni_freq_out_insn_read(struct comedi_device *dev,
4049                                  struct comedi_subdevice *s,
4050                                  struct comedi_insn *insn,
4051                                  unsigned int *data)
4052 {
4053         struct ni_private *devpriv = dev->private;
4054         unsigned int val = devpriv->clock_and_fout & FOUT_Divider_mask;
4055         int i;
4056
4057         for (i = 0; i < insn->n; i++)
4058                 data[i] = val;
4059
4060         return insn->n;
4061 }
4062
4063 static int ni_freq_out_insn_write(struct comedi_device *dev,
4064                                   struct comedi_subdevice *s,
4065                                   struct comedi_insn *insn,
4066                                   unsigned int *data)
4067 {
4068         struct ni_private *devpriv = dev->private;
4069
4070         if (insn->n) {
4071                 devpriv->clock_and_fout &= ~FOUT_Enable;
4072                 ni_stc_writew(dev, devpriv->clock_and_fout,
4073                               Clock_and_FOUT_Register);
4074                 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4075
4076                 /* use the last data value to set the fout divider */
4077                 devpriv->clock_and_fout |= FOUT_Divider(data[insn->n - 1]);
4078
4079                 devpriv->clock_and_fout |= FOUT_Enable;
4080                 ni_stc_writew(dev, devpriv->clock_and_fout,
4081                               Clock_and_FOUT_Register);
4082         }
4083         return insn->n;
4084 }
4085
4086 static int ni_freq_out_insn_config(struct comedi_device *dev,
4087                                    struct comedi_subdevice *s,
4088                                    struct comedi_insn *insn,
4089                                    unsigned int *data)
4090 {
4091         struct ni_private *devpriv = dev->private;
4092
4093         switch (data[0]) {
4094         case INSN_CONFIG_SET_CLOCK_SRC:
4095                 switch (data[1]) {
4096                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4097                         devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4098                         break;
4099                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4100                         devpriv->clock_and_fout |= FOUT_Timebase_Select;
4101                         break;
4102                 default:
4103                         return -EINVAL;
4104                 }
4105                 ni_stc_writew(dev, devpriv->clock_and_fout,
4106                               Clock_and_FOUT_Register);
4107                 break;
4108         case INSN_CONFIG_GET_CLOCK_SRC:
4109                 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4110                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4111                         data[2] = TIMEBASE_2_NS;
4112                 } else {
4113                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4114                         data[2] = TIMEBASE_1_NS * 2;
4115                 }
4116                 break;
4117         default:
4118                 return -EINVAL;
4119         }
4120         return insn->n;
4121 }
4122
4123 static int ni_8255_callback(struct comedi_device *dev,
4124                             int dir, int port, int data, unsigned long iobase)
4125 {
4126         if (dir) {
4127                 ni_writeb(dev, data, iobase + 2 * port);
4128                 return 0;
4129         }
4130
4131         return ni_readb(dev, iobase + 2 * port);
4132 }
4133
4134 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4135 {
4136         struct ni_private *devpriv = dev->private;
4137
4138         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4139         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4140         return 3;
4141 }
4142
4143 static int ni_m_series_pwm_config(struct comedi_device *dev,
4144                                   struct comedi_subdevice *s,
4145                                   struct comedi_insn *insn,
4146                                   unsigned int *data)
4147 {
4148         struct ni_private *devpriv = dev->private;
4149         unsigned up_count, down_count;
4150
4151         switch (data[0]) {
4152         case INSN_CONFIG_PWM_OUTPUT:
4153                 switch (data[1]) {
4154                 case CMDF_ROUND_NEAREST:
4155                         up_count =
4156                             (data[2] +
4157                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4158                         break;
4159                 case CMDF_ROUND_DOWN:
4160                         up_count = data[2] / devpriv->clock_ns;
4161                         break;
4162                 case CMDF_ROUND_UP:
4163                         up_count =
4164                             (data[2] + devpriv->clock_ns -
4165                              1) / devpriv->clock_ns;
4166                         break;
4167                 default:
4168                         return -EINVAL;
4169                 }
4170                 switch (data[3]) {
4171                 case CMDF_ROUND_NEAREST:
4172                         down_count =
4173                             (data[4] +
4174                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4175                         break;
4176                 case CMDF_ROUND_DOWN:
4177                         down_count = data[4] / devpriv->clock_ns;
4178                         break;
4179                 case CMDF_ROUND_UP:
4180                         down_count =
4181                             (data[4] + devpriv->clock_ns -
4182                              1) / devpriv->clock_ns;
4183                         break;
4184                 default:
4185                         return -EINVAL;
4186                 }
4187                 if (up_count * devpriv->clock_ns != data[2] ||
4188                     down_count * devpriv->clock_ns != data[4]) {
4189                         data[2] = up_count * devpriv->clock_ns;
4190                         data[4] = down_count * devpriv->clock_ns;
4191                         return -EAGAIN;
4192                 }
4193                 ni_writel(dev, MSeries_Cal_PWM_High_Time_Bits(up_count) |
4194                                MSeries_Cal_PWM_Low_Time_Bits(down_count),
4195                           M_Offset_Cal_PWM);
4196                 devpriv->pwm_up_count = up_count;
4197                 devpriv->pwm_down_count = down_count;
4198                 return 5;
4199         case INSN_CONFIG_GET_PWM_OUTPUT:
4200                 return ni_get_pwm_config(dev, data);
4201         default:
4202                 return -EINVAL;
4203         }
4204         return 0;
4205 }
4206
4207 static int ni_6143_pwm_config(struct comedi_device *dev,
4208                               struct comedi_subdevice *s,
4209                               struct comedi_insn *insn,
4210                               unsigned int *data)
4211 {
4212         struct ni_private *devpriv = dev->private;
4213         unsigned up_count, down_count;
4214
4215         switch (data[0]) {
4216         case INSN_CONFIG_PWM_OUTPUT:
4217                 switch (data[1]) {
4218                 case CMDF_ROUND_NEAREST:
4219                         up_count =
4220                             (data[2] +
4221                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4222                         break;
4223                 case CMDF_ROUND_DOWN:
4224                         up_count = data[2] / devpriv->clock_ns;
4225                         break;
4226                 case CMDF_ROUND_UP:
4227                         up_count =
4228                             (data[2] + devpriv->clock_ns -
4229                              1) / devpriv->clock_ns;
4230                         break;
4231                 default:
4232                         return -EINVAL;
4233                 }
4234                 switch (data[3]) {
4235                 case CMDF_ROUND_NEAREST:
4236                         down_count =
4237                             (data[4] +
4238                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4239                         break;
4240                 case CMDF_ROUND_DOWN:
4241                         down_count = data[4] / devpriv->clock_ns;
4242                         break;
4243                 case CMDF_ROUND_UP:
4244                         down_count =
4245                             (data[4] + devpriv->clock_ns -
4246                              1) / devpriv->clock_ns;
4247                         break;
4248                 default:
4249                         return -EINVAL;
4250                 }
4251                 if (up_count * devpriv->clock_ns != data[2] ||
4252                     down_count * devpriv->clock_ns != data[4]) {
4253                         data[2] = up_count * devpriv->clock_ns;
4254                         data[4] = down_count * devpriv->clock_ns;
4255                         return -EAGAIN;
4256                 }
4257                 ni_writel(dev, up_count, Calibration_HighTime_6143);
4258                 devpriv->pwm_up_count = up_count;
4259                 ni_writel(dev, down_count, Calibration_LowTime_6143);
4260                 devpriv->pwm_down_count = down_count;
4261                 return 5;
4262         case INSN_CONFIG_GET_PWM_OUTPUT:
4263                 return ni_get_pwm_config(dev, data);
4264         default:
4265                 return -EINVAL;
4266         }
4267         return 0;
4268 }
4269
4270 static int pack_mb88341(int addr, int val, int *bitstring)
4271 {
4272         /*
4273            Fujitsu MB 88341
4274            Note that address bits are reversed.  Thanks to
4275            Ingo Keen for noticing this.
4276
4277            Note also that the 88341 expects address values from
4278            1-12, whereas we use channel numbers 0-11.  The NI
4279            docs use 1-12, also, so be careful here.
4280          */
4281         addr++;
4282         *bitstring = ((addr & 0x1) << 11) |
4283             ((addr & 0x2) << 9) |
4284             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4285         return 12;
4286 }
4287
4288 static int pack_dac8800(int addr, int val, int *bitstring)
4289 {
4290         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4291         return 11;
4292 }
4293
4294 static int pack_dac8043(int addr, int val, int *bitstring)
4295 {
4296         *bitstring = val & 0xfff;
4297         return 12;
4298 }
4299
4300 static int pack_ad8522(int addr, int val, int *bitstring)
4301 {
4302         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4303         return 16;
4304 }
4305
4306 static int pack_ad8804(int addr, int val, int *bitstring)
4307 {
4308         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4309         return 12;
4310 }
4311
4312 static int pack_ad8842(int addr, int val, int *bitstring)
4313 {
4314         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4315         return 12;
4316 }
4317
4318 struct caldac_struct {
4319         int n_chans;
4320         int n_bits;
4321         int (*packbits)(int, int, int *);
4322 };
4323
4324 static struct caldac_struct caldacs[] = {
4325         [mb88341] = {12, 8, pack_mb88341},
4326         [dac8800] = {8, 8, pack_dac8800},
4327         [dac8043] = {1, 12, pack_dac8043},
4328         [ad8522] = {2, 12, pack_ad8522},
4329         [ad8804] = {12, 8, pack_ad8804},
4330         [ad8842] = {8, 8, pack_ad8842},
4331         [ad8804_debug] = {16, 8, pack_ad8804},
4332 };
4333
4334 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4335 {
4336         const struct ni_board_struct *board = dev->board_ptr;
4337         struct ni_private *devpriv = dev->private;
4338         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4339         int i;
4340         int type;
4341
4342         if (devpriv->caldacs[addr] == val)
4343                 return;
4344         devpriv->caldacs[addr] = val;
4345
4346         for (i = 0; i < 3; i++) {
4347                 type = board->caldac[i];
4348                 if (type == caldac_none)
4349                         break;
4350                 if (addr < caldacs[type].n_chans) {
4351                         bits = caldacs[type].packbits(addr, val, &bitstring);
4352                         loadbit = SerDacLd(i);
4353                         break;
4354                 }
4355                 addr -= caldacs[type].n_chans;
4356         }
4357
4358         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4359                 ni_writeb(dev, ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4360                 udelay(1);
4361                 ni_writeb(dev, 1 | ((bit & bitstring) ? 0x02 : 0),
4362                           Serial_Command);
4363                 udelay(1);
4364         }
4365         ni_writeb(dev, loadbit, Serial_Command);
4366         udelay(1);
4367         ni_writeb(dev, 0, Serial_Command);
4368 }
4369
4370 static int ni_calib_insn_write(struct comedi_device *dev,
4371                                struct comedi_subdevice *s,
4372                                struct comedi_insn *insn,
4373                                unsigned int *data)
4374 {
4375         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4376
4377         return 1;
4378 }
4379
4380 static int ni_calib_insn_read(struct comedi_device *dev,
4381                               struct comedi_subdevice *s,
4382                               struct comedi_insn *insn,
4383                               unsigned int *data)
4384 {
4385         struct ni_private *devpriv = dev->private;
4386
4387         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4388
4389         return 1;
4390 }
4391
4392 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4393 {
4394         const struct ni_board_struct *board = dev->board_ptr;
4395         struct ni_private *devpriv = dev->private;
4396         int i, j;
4397         int n_dacs;
4398         int n_chans = 0;
4399         int n_bits;
4400         int diffbits = 0;
4401         int type;
4402         int chan;
4403
4404         type = board->caldac[0];
4405         if (type == caldac_none)
4406                 return;
4407         n_bits = caldacs[type].n_bits;
4408         for (i = 0; i < 3; i++) {
4409                 type = board->caldac[i];
4410                 if (type == caldac_none)
4411                         break;
4412                 if (caldacs[type].n_bits != n_bits)
4413                         diffbits = 1;
4414                 n_chans += caldacs[type].n_chans;
4415         }
4416         n_dacs = i;
4417         s->n_chan = n_chans;
4418
4419         if (diffbits) {
4420                 unsigned int *maxdata_list;
4421
4422                 if (n_chans > MAX_N_CALDACS)
4423                         dev_err(dev->class_dev,
4424                                 "BUG! MAX_N_CALDACS too small\n");
4425                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4426                 chan = 0;
4427                 for (i = 0; i < n_dacs; i++) {
4428                         type = board->caldac[i];
4429                         for (j = 0; j < caldacs[type].n_chans; j++) {
4430                                 maxdata_list[chan] =
4431                                     (1 << caldacs[type].n_bits) - 1;
4432                                 chan++;
4433                         }
4434                 }
4435
4436                 for (chan = 0; chan < s->n_chan; chan++)
4437                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4438         } else {
4439                 type = board->caldac[0];
4440                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4441
4442                 for (chan = 0; chan < s->n_chan; chan++)
4443                         ni_write_caldac(dev, i, s->maxdata / 2);
4444         }
4445 }
4446
4447 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4448 {
4449         int bit;
4450         int bitstring;
4451
4452         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4453         ni_writeb(dev, 0x04, Serial_Command);
4454         for (bit = 0x8000; bit; bit >>= 1) {
4455                 ni_writeb(dev, 0x04 | ((bit & bitstring) ? 0x02 : 0),
4456                           Serial_Command);
4457                 ni_writeb(dev, 0x05 | ((bit & bitstring) ? 0x02 : 0),
4458                           Serial_Command);
4459         }
4460         bitstring = 0;
4461         for (bit = 0x80; bit; bit >>= 1) {
4462                 ni_writeb(dev, 0x04, Serial_Command);
4463                 ni_writeb(dev, 0x05, Serial_Command);
4464                 bitstring |= ((ni_readb(dev, XXX_Status) & PROMOUT) ? bit : 0);
4465         }
4466         ni_writeb(dev, 0x00, Serial_Command);
4467
4468         return bitstring;
4469 }
4470
4471 static int ni_eeprom_insn_read(struct comedi_device *dev,
4472                                struct comedi_subdevice *s,
4473                                struct comedi_insn *insn,
4474                                unsigned int *data)
4475 {
4476         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4477
4478         return 1;
4479 }
4480
4481 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4482                                         struct comedi_subdevice *s,
4483                                         struct comedi_insn *insn,
4484                                         unsigned int *data)
4485 {
4486         struct ni_private *devpriv = dev->private;
4487
4488         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4489
4490         return 1;
4491 }
4492
4493 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4494                                        unsigned chan)
4495 {
4496         /*  pre-m-series boards have fixed signals on pfi pins */
4497         switch (chan) {
4498         case 0:
4499                 return NI_PFI_OUTPUT_AI_START1;
4500         case 1:
4501                 return NI_PFI_OUTPUT_AI_START2;
4502         case 2:
4503                 return NI_PFI_OUTPUT_AI_CONVERT;
4504         case 3:
4505                 return NI_PFI_OUTPUT_G_SRC1;
4506         case 4:
4507                 return NI_PFI_OUTPUT_G_GATE1;
4508         case 5:
4509                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4510         case 6:
4511                 return NI_PFI_OUTPUT_AO_START1;
4512         case 7:
4513                 return NI_PFI_OUTPUT_AI_START_PULSE;
4514         case 8:
4515                 return NI_PFI_OUTPUT_G_SRC0;
4516         case 9:
4517                 return NI_PFI_OUTPUT_G_GATE0;
4518         default:
4519                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4520                 break;
4521         }
4522         return 0;
4523 }
4524
4525 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4526                                   unsigned chan, unsigned source)
4527 {
4528         /*  pre-m-series boards have fixed signals on pfi pins */
4529         if (source != ni_old_get_pfi_routing(dev, chan))
4530                 return -EINVAL;
4531         return 2;
4532 }
4533
4534 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4535                                             unsigned chan)
4536 {
4537         struct ni_private *devpriv = dev->private;
4538         const unsigned array_offset = chan / 3;
4539
4540         return MSeries_PFI_Output_Select_Source(chan,
4541                                 devpriv->pfi_output_select_reg[array_offset]);
4542 }
4543
4544 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4545                                        unsigned chan, unsigned source)
4546 {
4547         struct ni_private *devpriv = dev->private;
4548         unsigned pfi_reg_index;
4549         unsigned array_offset;
4550
4551         if ((source & 0x1f) != source)
4552                 return -EINVAL;
4553         pfi_reg_index = 1 + chan / 3;
4554         array_offset = pfi_reg_index - 1;
4555         devpriv->pfi_output_select_reg[array_offset] &=
4556             ~MSeries_PFI_Output_Select_Mask(chan);
4557         devpriv->pfi_output_select_reg[array_offset] |=
4558             MSeries_PFI_Output_Select_Bits(chan, source);
4559         ni_writew(dev, devpriv->pfi_output_select_reg[array_offset],
4560                   M_Offset_PFI_Output_Select(pfi_reg_index));
4561         return 2;
4562 }
4563
4564 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4565 {
4566         struct ni_private *devpriv = dev->private;
4567
4568         return (devpriv->is_m_series)
4569                         ? ni_m_series_get_pfi_routing(dev, chan)
4570                         : ni_old_get_pfi_routing(dev, chan);
4571 }
4572
4573 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4574                               unsigned source)
4575 {
4576         struct ni_private *devpriv = dev->private;
4577
4578         return (devpriv->is_m_series)
4579                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4580                         : ni_old_set_pfi_routing(dev, chan, source);
4581 }
4582
4583 static int ni_config_filter(struct comedi_device *dev,
4584                             unsigned pfi_channel,
4585                             enum ni_pfi_filter_select filter)
4586 {
4587         struct ni_private *devpriv = dev->private;
4588         unsigned bits;
4589
4590         if (!devpriv->is_m_series)
4591                 return -ENOTSUPP;
4592
4593         bits = ni_readl(dev, M_Offset_PFI_Filter);
4594         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
4595         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
4596         ni_writel(dev, bits, M_Offset_PFI_Filter);
4597         return 0;
4598 }
4599
4600 static int ni_pfi_insn_config(struct comedi_device *dev,
4601                               struct comedi_subdevice *s,
4602                               struct comedi_insn *insn,
4603                               unsigned int *data)
4604 {
4605         struct ni_private *devpriv = dev->private;
4606         unsigned int chan;
4607
4608         if (insn->n < 1)
4609                 return -EINVAL;
4610
4611         chan = CR_CHAN(insn->chanspec);
4612
4613         switch (data[0]) {
4614         case COMEDI_OUTPUT:
4615                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
4616                 break;
4617         case COMEDI_INPUT:
4618                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
4619                 break;
4620         case INSN_CONFIG_DIO_QUERY:
4621                 data[1] =
4622                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4623                     COMEDI_OUTPUT : COMEDI_INPUT;
4624                 return 0;
4625         case INSN_CONFIG_SET_ROUTING:
4626                 return ni_set_pfi_routing(dev, chan, data[1]);
4627         case INSN_CONFIG_GET_ROUTING:
4628                 data[1] = ni_get_pfi_routing(dev, chan);
4629                 break;
4630         case INSN_CONFIG_FILTER:
4631                 return ni_config_filter(dev, chan, data[1]);
4632         default:
4633                 return -EINVAL;
4634         }
4635         return 0;
4636 }
4637
4638 static int ni_pfi_insn_bits(struct comedi_device *dev,
4639                             struct comedi_subdevice *s,
4640                             struct comedi_insn *insn,
4641                             unsigned int *data)
4642 {
4643         struct ni_private *devpriv = dev->private;
4644
4645         if (!devpriv->is_m_series)
4646                 return -ENOTSUPP;
4647
4648         if (comedi_dio_update_state(s, data))
4649                 ni_writew(dev, s->state, M_Offset_PFI_DO);
4650
4651         data[1] = ni_readw(dev, M_Offset_PFI_DI);
4652
4653         return insn->n;
4654 }
4655
4656 static int cs5529_wait_for_idle(struct comedi_device *dev)
4657 {
4658         unsigned short status;
4659         const int timeout = HZ;
4660         int i;
4661
4662         for (i = 0; i < timeout; i++) {
4663                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4664                 if ((status & CSS_ADC_BUSY) == 0)
4665                         break;
4666                 set_current_state(TASK_INTERRUPTIBLE);
4667                 if (schedule_timeout(1))
4668                         return -EIO;
4669         }
4670         if (i == timeout) {
4671                 dev_err(dev->class_dev, "timeout\n");
4672                 return -ETIME;
4673         }
4674         return 0;
4675 }
4676
4677 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4678 {
4679         static const int timeout = 100;
4680         int i;
4681
4682         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4683         /* give time for command to start being serially clocked into cs5529.
4684          * this insures that the CSS_ADC_BUSY bit will get properly
4685          * set before we exit this function.
4686          */
4687         for (i = 0; i < timeout; i++) {
4688                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4689                         break;
4690                 udelay(1);
4691         }
4692         if (i == timeout)
4693                 dev_err(dev->class_dev,
4694                         "possible problem - never saw adc go busy?\n");
4695 }
4696
4697 static int cs5529_do_conversion(struct comedi_device *dev,
4698                                 unsigned short *data)
4699 {
4700         int retval;
4701         unsigned short status;
4702
4703         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4704         retval = cs5529_wait_for_idle(dev);
4705         if (retval) {
4706                 dev_err(dev->class_dev,
4707                         "timeout or signal in cs5529_do_conversion()\n");
4708                 return -ETIME;
4709         }
4710         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4711         if (status & CSS_OSC_DETECT) {
4712                 dev_err(dev->class_dev,
4713                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4714                 return -EIO;
4715         }
4716         if (status & CSS_OVERRANGE) {
4717                 dev_err(dev->class_dev,
4718                         "cs5529 conversion error, overrange (ignoring)\n");
4719         }
4720         if (data) {
4721                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4722                 /* cs5529 returns 16 bit signed data in bipolar mode */
4723                 *data ^= (1 << 15);
4724         }
4725         return 0;
4726 }
4727
4728 static int cs5529_ai_insn_read(struct comedi_device *dev,
4729                                struct comedi_subdevice *s,
4730                                struct comedi_insn *insn,
4731                                unsigned int *data)
4732 {
4733         int n, retval;
4734         unsigned short sample;
4735         unsigned int channel_select;
4736         const unsigned int INTERNAL_REF = 0x1000;
4737
4738         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4739          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4740          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4741         if (insn->chanspec & CR_ALT_SOURCE)
4742                 channel_select = INTERNAL_REF;
4743         else
4744                 channel_select = CR_CHAN(insn->chanspec);
4745         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4746
4747         for (n = 0; n < insn->n; n++) {
4748                 retval = cs5529_do_conversion(dev, &sample);
4749                 if (retval < 0)
4750                         return retval;
4751                 data[n] = sample;
4752         }
4753         return insn->n;
4754 }
4755
4756 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4757                                 unsigned int reg_select_bits)
4758 {
4759         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
4760                        CAL_ADC_Config_Data_High_Word_67xx);
4761         ni_ao_win_outw(dev, (value & 0xffff),
4762                        CAL_ADC_Config_Data_Low_Word_67xx);
4763         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4764         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4765         if (cs5529_wait_for_idle(dev))
4766                 dev_err(dev->class_dev,
4767                         "timeout or signal in %s\n", __func__);
4768 }
4769
4770 static int init_cs5529(struct comedi_device *dev)
4771 {
4772         unsigned int config_bits =
4773             CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4774
4775 #if 1
4776         /* do self-calibration */
4777         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
4778                             CSCMD_CONFIG_REGISTER);
4779         /* need to force a conversion for calibration to run */
4780         cs5529_do_conversion(dev, NULL);
4781 #else
4782         /* force gain calibration to 1 */
4783         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4784         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
4785                             CSCMD_CONFIG_REGISTER);
4786         if (cs5529_wait_for_idle(dev))
4787                 dev_err(dev->class_dev,
4788                         "timeout or signal in %s\n", __func__);
4789 #endif
4790         return 0;
4791 }
4792
4793 /*
4794  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4795  * given an arbitrary frequency input clock.
4796  */
4797 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4798                                          unsigned *freq_divider,
4799                                          unsigned *freq_multiplier,
4800                                          unsigned *actual_period_ns)
4801 {
4802         unsigned div;
4803         unsigned best_div = 1;
4804         static const unsigned max_div = 0x10;
4805         unsigned mult;
4806         unsigned best_mult = 1;
4807         static const unsigned max_mult = 0x100;
4808         static const unsigned pico_per_nano = 1000;
4809
4810         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4811         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4812          * 20 MHz for most timing clocks */
4813         static const unsigned target_picosec = 12500;
4814         static const unsigned fudge_factor_80_to_20Mhz = 4;
4815         int best_period_picosec = 0;
4816
4817         for (div = 1; div <= max_div; ++div) {
4818                 for (mult = 1; mult <= max_mult; ++mult) {
4819                         unsigned new_period_ps =
4820                             (reference_picosec * div) / mult;
4821                         if (abs(new_period_ps - target_picosec) <
4822                             abs(best_period_picosec - target_picosec)) {
4823                                 best_period_picosec = new_period_ps;
4824                                 best_div = div;
4825                                 best_mult = mult;
4826                         }
4827                 }
4828         }
4829         if (best_period_picosec == 0)
4830                 return -EIO;
4831
4832         *freq_divider = best_div;
4833         *freq_multiplier = best_mult;
4834         *actual_period_ns =
4835             (best_period_picosec * fudge_factor_80_to_20Mhz +
4836              (pico_per_nano / 2)) / pico_per_nano;
4837         return 0;
4838 }
4839
4840 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4841                                            unsigned source, unsigned period_ns)
4842 {
4843         struct ni_private *devpriv = dev->private;
4844         static const unsigned min_period_ns = 50;
4845         static const unsigned max_period_ns = 1000;
4846         static const unsigned timeout = 1000;
4847         unsigned pll_control_bits;
4848         unsigned freq_divider;
4849         unsigned freq_multiplier;
4850         unsigned i;
4851         int retval;
4852
4853         if (source == NI_MIO_PLL_PXI10_CLOCK)
4854                 period_ns = 100;
4855         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4856         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4857                 dev_err(dev->class_dev,
4858                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4859                         __func__, min_period_ns, max_period_ns);
4860                 return -EINVAL;
4861         }
4862         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4863         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4864                       RTSI_Trig_Direction_Register);
4865         pll_control_bits =
4866             MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
4867         devpriv->clock_and_fout2 |=
4868             MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
4869         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
4870         switch (source) {
4871         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4872                 devpriv->clock_and_fout2 |=
4873                     MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
4874                 break;
4875         case NI_MIO_PLL_PXI10_CLOCK:
4876                 /* pxi clock is 10MHz */
4877                 devpriv->clock_and_fout2 |=
4878                     MSeries_PLL_In_Source_Select_PXI_Clock10;
4879                 break;
4880         default:
4881                 {
4882                         unsigned rtsi_channel;
4883                         static const unsigned max_rtsi_channel = 7;
4884
4885                         for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
4886                              ++rtsi_channel) {
4887                                 if (source ==
4888                                     NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
4889                                         devpriv->clock_and_fout2 |=
4890                                             MSeries_PLL_In_Source_Select_RTSI_Bits
4891                                             (rtsi_channel);
4892                                         break;
4893                                 }
4894                         }
4895                         if (rtsi_channel > max_rtsi_channel)
4896                                 return -EINVAL;
4897                 }
4898                 break;
4899         }
4900         retval = ni_mseries_get_pll_parameters(period_ns,
4901                                                &freq_divider,
4902                                                &freq_multiplier,
4903                                                &devpriv->clock_ns);
4904         if (retval < 0) {
4905                 dev_err(dev->class_dev,
4906                         "bug, failed to find pll parameters\n");
4907                 return retval;
4908         }
4909
4910         ni_writew(dev, devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4911         pll_control_bits |=
4912             MSeries_PLL_Divisor_Bits(freq_divider) |
4913             MSeries_PLL_Multiplier_Bits(freq_multiplier);
4914
4915         ni_writew(dev, pll_control_bits, M_Offset_PLL_Control);
4916         devpriv->clock_source = source;
4917         /* it seems to typically take a few hundred microseconds for PLL to lock */
4918         for (i = 0; i < timeout; ++i) {
4919                 if (ni_readw(dev, M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
4920                         break;
4921                 udelay(1);
4922         }
4923         if (i == timeout) {
4924                 dev_err(dev->class_dev,
4925                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4926                         __func__, source, period_ns);
4927                 return -ETIMEDOUT;
4928         }
4929         return 3;
4930 }
4931
4932 static int ni_set_master_clock(struct comedi_device *dev,
4933                                unsigned source, unsigned period_ns)
4934 {
4935         struct ni_private *devpriv = dev->private;
4936
4937         if (source == NI_MIO_INTERNAL_CLOCK) {
4938                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4939                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4940                               RTSI_Trig_Direction_Register);
4941                 devpriv->clock_ns = TIMEBASE_1_NS;
4942                 if (devpriv->is_m_series) {
4943                         devpriv->clock_and_fout2 &=
4944                             ~(MSeries_Timebase1_Select_Bit |
4945                               MSeries_Timebase3_Select_Bit);
4946                         ni_writew(dev, devpriv->clock_and_fout2,
4947                                   M_Offset_Clock_and_Fout2);
4948                         ni_writew(dev, 0, M_Offset_PLL_Control);
4949                 }
4950                 devpriv->clock_source = source;
4951         } else {
4952                 if (devpriv->is_m_series) {
4953                         return ni_mseries_set_pll_master_clock(dev, source,
4954                                                                period_ns);
4955                 } else {
4956                         if (source == NI_MIO_RTSI_CLOCK) {
4957                                 devpriv->rtsi_trig_direction_reg |=
4958                                     Use_RTSI_Clock_Bit;
4959                                 ni_stc_writew(dev,
4960                                               devpriv->rtsi_trig_direction_reg,
4961                                               RTSI_Trig_Direction_Register);
4962                                 if (period_ns == 0) {
4963                                         dev_err(dev->class_dev,
4964                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
4965                                         return -EINVAL;
4966                                 }
4967                                 devpriv->clock_ns = period_ns;
4968                                 devpriv->clock_source = source;
4969                         } else {
4970                                 return -EINVAL;
4971                         }
4972                 }
4973         }
4974         return 3;
4975 }
4976
4977 static unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
4978 {
4979         struct ni_private *devpriv = dev->private;
4980
4981         return (devpriv->is_m_series) ? 8 : 7;
4982 }
4983
4984 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4985                                        unsigned chan, unsigned source)
4986 {
4987         struct ni_private *devpriv = dev->private;
4988
4989         if (chan >= num_configurable_rtsi_channels(dev)) {
4990                 if (chan == old_RTSI_clock_channel) {
4991                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4992                                 return 1;
4993
4994                         dev_err(dev->class_dev,
4995                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4996                                 __func__, chan, old_RTSI_clock_channel);
4997                         return 0;
4998                 }
4999                 return 0;
5000         }
5001         switch (source) {
5002         case NI_RTSI_OUTPUT_ADR_START1:
5003         case NI_RTSI_OUTPUT_ADR_START2:
5004         case NI_RTSI_OUTPUT_SCLKG:
5005         case NI_RTSI_OUTPUT_DACUPDN:
5006         case NI_RTSI_OUTPUT_DA_START1:
5007         case NI_RTSI_OUTPUT_G_SRC0:
5008         case NI_RTSI_OUTPUT_G_GATE0:
5009         case NI_RTSI_OUTPUT_RGOUT0:
5010         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5011                 return 1;
5012         case NI_RTSI_OUTPUT_RTSI_OSC:
5013                 return (devpriv->is_m_series) ? 1 : 0;
5014         default:
5015                 return 0;
5016         }
5017 }
5018
5019 static int ni_set_rtsi_routing(struct comedi_device *dev,
5020                                unsigned chan, unsigned source)
5021 {
5022         struct ni_private *devpriv = dev->private;
5023
5024         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5025                 return -EINVAL;
5026         if (chan < 4) {
5027                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5028                 devpriv->rtsi_trig_a_output_reg |=
5029                     RTSI_Trig_Output_Bits(chan, source);
5030                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5031                               RTSI_Trig_A_Output_Register);
5032         } else if (chan < 8) {
5033                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5034                 devpriv->rtsi_trig_b_output_reg |=
5035                     RTSI_Trig_Output_Bits(chan, source);
5036                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5037                               RTSI_Trig_B_Output_Register);
5038         }
5039         return 2;
5040 }
5041
5042 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5043 {
5044         struct ni_private *devpriv = dev->private;
5045
5046         if (chan < 4) {
5047                 return RTSI_Trig_Output_Source(chan,
5048                                                devpriv->rtsi_trig_a_output_reg);
5049         } else if (chan < num_configurable_rtsi_channels(dev)) {
5050                 return RTSI_Trig_Output_Source(chan,
5051                                                devpriv->rtsi_trig_b_output_reg);
5052         } else {
5053                 if (chan == old_RTSI_clock_channel)
5054                         return NI_RTSI_OUTPUT_RTSI_OSC;
5055                 dev_err(dev->class_dev, "bug! should never get here?\n");
5056                 return 0;
5057         }
5058 }
5059
5060 static int ni_rtsi_insn_config(struct comedi_device *dev,
5061                                struct comedi_subdevice *s,
5062                                struct comedi_insn *insn,
5063                                unsigned int *data)
5064 {
5065         struct ni_private *devpriv = dev->private;
5066         unsigned int chan = CR_CHAN(insn->chanspec);
5067
5068         switch (data[0]) {
5069         case INSN_CONFIG_DIO_OUTPUT:
5070                 if (chan < num_configurable_rtsi_channels(dev)) {
5071                         devpriv->rtsi_trig_direction_reg |=
5072                             RTSI_Output_Bit(chan, devpriv->is_m_series);
5073                 } else if (chan == old_RTSI_clock_channel) {
5074                         devpriv->rtsi_trig_direction_reg |=
5075                             Drive_RTSI_Clock_Bit;
5076                 }
5077                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5078                               RTSI_Trig_Direction_Register);
5079                 break;
5080         case INSN_CONFIG_DIO_INPUT:
5081                 if (chan < num_configurable_rtsi_channels(dev)) {
5082                         devpriv->rtsi_trig_direction_reg &=
5083                             ~RTSI_Output_Bit(chan, devpriv->is_m_series);
5084                 } else if (chan == old_RTSI_clock_channel) {
5085                         devpriv->rtsi_trig_direction_reg &=
5086                             ~Drive_RTSI_Clock_Bit;
5087                 }
5088                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5089                               RTSI_Trig_Direction_Register);
5090                 break;
5091         case INSN_CONFIG_DIO_QUERY:
5092                 if (chan < num_configurable_rtsi_channels(dev)) {
5093                         data[1] =
5094                             (devpriv->rtsi_trig_direction_reg &
5095                              RTSI_Output_Bit(chan, devpriv->is_m_series))
5096                                 ? INSN_CONFIG_DIO_OUTPUT
5097                                 : INSN_CONFIG_DIO_INPUT;
5098                 } else if (chan == old_RTSI_clock_channel) {
5099                         data[1] =
5100                             (devpriv->rtsi_trig_direction_reg &
5101                              Drive_RTSI_Clock_Bit)
5102                             ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5103                 }
5104                 return 2;
5105         case INSN_CONFIG_SET_CLOCK_SRC:
5106                 return ni_set_master_clock(dev, data[1], data[2]);
5107         case INSN_CONFIG_GET_CLOCK_SRC:
5108                 data[1] = devpriv->clock_source;
5109                 data[2] = devpriv->clock_ns;
5110                 return 3;
5111         case INSN_CONFIG_SET_ROUTING:
5112                 return ni_set_rtsi_routing(dev, chan, data[1]);
5113         case INSN_CONFIG_GET_ROUTING:
5114                 data[1] = ni_get_rtsi_routing(dev, chan);
5115                 return 2;
5116         default:
5117                 return -EINVAL;
5118         }
5119         return 1;
5120 }
5121
5122 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5123                              struct comedi_subdevice *s,
5124                              struct comedi_insn *insn,
5125                              unsigned int *data)
5126 {
5127         data[1] = 0;
5128
5129         return insn->n;
5130 }
5131
5132 static void ni_rtsi_init(struct comedi_device *dev)
5133 {
5134         struct ni_private *devpriv = dev->private;
5135
5136         /*  Initialises the RTSI bus signal switch to a default state */
5137
5138         /*  Set clock mode to internal */
5139         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5140         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5141                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5142         /*  default internal lines routing to RTSI bus lines */
5143         devpriv->rtsi_trig_a_output_reg =
5144             RTSI_Trig_Output_Bits(0,
5145                                   NI_RTSI_OUTPUT_ADR_START1) |
5146             RTSI_Trig_Output_Bits(1,
5147                                   NI_RTSI_OUTPUT_ADR_START2) |
5148             RTSI_Trig_Output_Bits(2,
5149                                   NI_RTSI_OUTPUT_SCLKG) |
5150             RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5151         ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5152                       RTSI_Trig_A_Output_Register);
5153         devpriv->rtsi_trig_b_output_reg =
5154             RTSI_Trig_Output_Bits(4,
5155                                   NI_RTSI_OUTPUT_DA_START1) |
5156             RTSI_Trig_Output_Bits(5,
5157                                   NI_RTSI_OUTPUT_G_SRC0) |
5158             RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5159         if (devpriv->is_m_series)
5160                 devpriv->rtsi_trig_b_output_reg |=
5161                     RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5162         ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5163                       RTSI_Trig_B_Output_Register);
5164
5165 /*
5166 * Sets the source and direction of the 4 on board lines
5167 * ni_stc_writew(dev, 0x0000, RTSI_Board_Register);
5168 */
5169 }
5170
5171 #ifdef PCIDMA
5172 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5173 {
5174         struct ni_gpct *counter = s->private;
5175         int retval;
5176
5177         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5178                                               COMEDI_INPUT);
5179         if (retval) {
5180                 dev_err(dev->class_dev,
5181                         "no dma channel available for use by counter\n");
5182                 return retval;
5183         }
5184         ni_tio_acknowledge(counter);
5185         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5186
5187         return ni_tio_cmd(dev, s);
5188 }
5189
5190 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5191 {
5192         struct ni_gpct *counter = s->private;
5193         int retval;
5194
5195         retval = ni_tio_cancel(counter);
5196         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5197         ni_release_gpct_mite_channel(dev, counter->counter_index);
5198         return retval;
5199 }
5200 #endif
5201
5202 #if 0
5203 /*
5204  *      Read the GPCTs current value.
5205  */
5206 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5207 {
5208         unsigned int hi1, hi2, lo;
5209
5210         devpriv->gpct_command[chan] &= ~G_Save_Trace;
5211         ni_stc_writew(dev, devpriv->gpct_command[chan],
5212                       G_Command_Register(chan));
5213
5214         devpriv->gpct_command[chan] |= G_Save_Trace;
5215         ni_stc_writew(dev, devpriv->gpct_command[chan],
5216                       G_Command_Register(chan));
5217
5218         /* This procedure is used because the two registers cannot
5219          * be read atomically. */
5220         do {
5221                 hi1 = ni_stc_readw(dev, G_Save_Register_High(chan));
5222                 lo = ni_stc_readw(dev, G_Save_Register_Low(chan));
5223                 hi2 = ni_stc_readw(dev, G_Save_Register_High(chan));
5224         } while (hi1 != hi2);
5225
5226         return (hi1 << 16) | lo;
5227 }
5228
5229 static void GPCT_Reset(struct comedi_device *dev, int chan)
5230 {
5231         int temp_ack_reg = 0;
5232
5233         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5234
5235         switch (chan) {
5236         case 0:
5237                 ni_stc_writew(dev, G0_Reset, Joint_Reset_Register);
5238                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5239                             G0_TC_Interrupt_Enable, 0);
5240                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5241                             G0_Gate_Interrupt_Enable, 0);
5242                 temp_ack_reg |= G0_Gate_Error_Confirm;
5243                 temp_ack_reg |= G0_TC_Error_Confirm;
5244                 temp_ack_reg |= G0_TC_Interrupt_Ack;
5245                 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5246                 ni_stc_writew(dev, temp_ack_reg, Interrupt_A_Ack_Register);
5247
5248                 /* problem...this interferes with the other ctr... */
5249                 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5250                 ni_stc_writew(dev, devpriv->an_trig_etc_reg,
5251                               Analog_Trigger_Etc_Register);
5252                 break;
5253         case 1:
5254                 ni_stc_writew(dev, G1_Reset, Joint_Reset_Register);
5255                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5256                             G1_TC_Interrupt_Enable, 0);
5257                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5258                             G0_Gate_Interrupt_Enable, 0);
5259                 temp_ack_reg |= G1_Gate_Error_Confirm;
5260                 temp_ack_reg |= G1_TC_Error_Confirm;
5261                 temp_ack_reg |= G1_TC_Interrupt_Ack;
5262                 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5263                 ni_stc_writew(dev, temp_ack_reg, Interrupt_B_Ack_Register);
5264
5265                 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5266                 ni_stc_writew(dev, devpriv->an_trig_etc_reg,
5267                               Analog_Trigger_Etc_Register);
5268                 break;
5269         }
5270
5271         devpriv->gpct_mode[chan] = 0;
5272         devpriv->gpct_input_select[chan] = 0;
5273         devpriv->gpct_command[chan] = 0;
5274
5275         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5276
5277         ni_stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
5278         ni_stc_writew(dev, devpriv->gpct_input_select[chan],
5279                       G_Input_Select_Register(chan));
5280         ni_stc_writew(dev, 0, G_Autoincrement_Register(chan));
5281 }
5282 #endif
5283
5284 static irqreturn_t ni_E_interrupt(int irq, void *d)
5285 {
5286         struct comedi_device *dev = d;
5287         unsigned short a_status;
5288         unsigned short b_status;
5289         unsigned int ai_mite_status = 0;
5290         unsigned int ao_mite_status = 0;
5291         unsigned long flags;
5292 #ifdef PCIDMA
5293         struct ni_private *devpriv = dev->private;
5294         struct mite_struct *mite = devpriv->mite;
5295 #endif
5296
5297         if (!dev->attached)
5298                 return IRQ_NONE;
5299         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
5300
5301         /*  lock to avoid race with comedi_poll */
5302         spin_lock_irqsave(&dev->spinlock, flags);
5303         a_status = ni_stc_readw(dev, AI_Status_1_Register);
5304         b_status = ni_stc_readw(dev, AO_Status_1_Register);
5305 #ifdef PCIDMA
5306         if (mite) {
5307                 struct ni_private *devpriv = dev->private;
5308                 unsigned long flags_too;
5309
5310                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5311                 if (devpriv->ai_mite_chan) {
5312                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5313                         if (ai_mite_status & CHSR_LINKC)
5314                                 writel(CHOR_CLRLC,
5315                                        devpriv->mite->mite_io_addr +
5316                                        MITE_CHOR(devpriv->
5317                                                  ai_mite_chan->channel));
5318                 }
5319                 if (devpriv->ao_mite_chan) {
5320                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5321                         if (ao_mite_status & CHSR_LINKC)
5322                                 writel(CHOR_CLRLC,
5323                                        mite->mite_io_addr +
5324                                        MITE_CHOR(devpriv->
5325                                                  ao_mite_chan->channel));
5326                 }
5327                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5328         }
5329 #endif
5330         ack_a_interrupt(dev, a_status);
5331         ack_b_interrupt(dev, b_status);
5332         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
5333                 handle_a_interrupt(dev, a_status, ai_mite_status);
5334         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
5335                 handle_b_interrupt(dev, b_status, ao_mite_status);
5336         handle_gpct_interrupt(dev, 0);
5337         handle_gpct_interrupt(dev, 1);
5338         handle_cdio_interrupt(dev);
5339
5340         spin_unlock_irqrestore(&dev->spinlock, flags);
5341         return IRQ_HANDLED;
5342 }
5343
5344 static int ni_alloc_private(struct comedi_device *dev)
5345 {
5346         struct ni_private *devpriv;
5347
5348         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5349         if (!devpriv)
5350                 return -ENOMEM;
5351
5352         spin_lock_init(&devpriv->window_lock);
5353         spin_lock_init(&devpriv->soft_reg_copy_lock);
5354         spin_lock_init(&devpriv->mite_channel_lock);
5355
5356         return 0;
5357 }
5358
5359 static int ni_E_init(struct comedi_device *dev,
5360                      unsigned interrupt_pin, unsigned irq_polarity)
5361 {
5362         const struct ni_board_struct *board = dev->board_ptr;
5363         struct ni_private *devpriv = dev->private;
5364         struct comedi_subdevice *s;
5365         int ret;
5366         int i;
5367
5368         if (board->n_aochan > MAX_N_AO_CHAN) {
5369                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5370                 return -EINVAL;
5371         }
5372
5373         /* initialize clock dividers */
5374         devpriv->clock_and_fout = Slow_Internal_Time_Divide_By_2 |
5375                                   Slow_Internal_Timebase |
5376                                   Clock_To_Board_Divide_By_2 |
5377                                   Clock_To_Board;
5378         if (!devpriv->is_6xxx) {
5379                 /* BEAM is this needed for PCI-6143 ?? */
5380                 devpriv->clock_and_fout |= (AI_Output_Divide_By_2 |
5381                                             AO_Output_Divide_By_2);
5382         }
5383         ni_stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
5384
5385         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5386         if (ret)
5387                 return ret;
5388
5389         /* Analog Input subdevice */
5390         s = &dev->subdevices[NI_AI_SUBDEV];
5391         if (board->n_adchan) {
5392                 s->type         = COMEDI_SUBD_AI;
5393                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5394                 if (!devpriv->is_611x)
5395                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5396                 if (board->ai_maxdata > 0xffff)
5397                         s->subdev_flags |= SDF_LSAMPL;
5398                 if (devpriv->is_m_series)
5399                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5400                 s->n_chan       = board->n_adchan;
5401                 s->maxdata      = board->ai_maxdata;
5402                 s->range_table  = ni_range_lkup[board->gainlkup];
5403                 s->insn_read    = ni_ai_insn_read;
5404                 s->insn_config  = ni_ai_insn_config;
5405                 if (dev->irq) {
5406                         dev->read_subdev = s;
5407                         s->subdev_flags |= SDF_CMD_READ;
5408                         s->len_chanlist = 512;
5409                         s->do_cmdtest   = ni_ai_cmdtest;
5410                         s->do_cmd       = ni_ai_cmd;
5411                         s->cancel       = ni_ai_reset;
5412                         s->poll         = ni_ai_poll;
5413                         s->munge        = ni_ai_munge;
5414
5415                         if (devpriv->mite)
5416                                 s->async_dma_dir = DMA_FROM_DEVICE;
5417                 }
5418
5419                 /* reset the analog input configuration */
5420                 ni_ai_reset(dev, s);
5421         } else {
5422                 s->type         = COMEDI_SUBD_UNUSED;
5423         }
5424
5425         /* Analog Output subdevice */
5426         s = &dev->subdevices[NI_AO_SUBDEV];
5427         if (board->n_aochan) {
5428                 s->type         = COMEDI_SUBD_AO;
5429                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5430                 if (devpriv->is_m_series)
5431                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5432                 s->n_chan       = board->n_aochan;
5433                 s->maxdata      = board->ao_maxdata;
5434                 s->range_table  = board->ao_range_table;
5435                 s->insn_config  = ni_ao_insn_config;
5436                 s->insn_write   = ni_ao_insn_write;
5437
5438                 ret = comedi_alloc_subdev_readback(s);
5439                 if (ret)
5440                         return ret;
5441
5442                 /*
5443                  * Along with the IRQ we need either a FIFO or DMA for
5444                  * async command support.
5445                  */
5446                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5447                         dev->write_subdev = s;
5448                         s->subdev_flags |= SDF_CMD_WRITE;
5449                         s->len_chanlist = s->n_chan;
5450                         s->do_cmdtest   = ni_ao_cmdtest;
5451                         s->do_cmd       = ni_ao_cmd;
5452                         s->cancel       = ni_ao_reset;
5453                         if (!devpriv->is_m_series)
5454                                 s->munge        = ni_ao_munge;
5455
5456                         if (devpriv->mite)
5457                                 s->async_dma_dir = DMA_TO_DEVICE;
5458                 }
5459
5460                 if (devpriv->is_67xx)
5461                         init_ao_67xx(dev, s);
5462
5463                 /* reset the analog output configuration */
5464                 ni_ao_reset(dev, s);
5465         } else {
5466                 s->type         = COMEDI_SUBD_UNUSED;
5467         }
5468
5469         /* Digital I/O subdevice */
5470         s = &dev->subdevices[NI_DIO_SUBDEV];
5471         s->type         = COMEDI_SUBD_DIO;
5472         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5473         s->n_chan       = board->has_32dio_chan ? 32 : 8;
5474         s->maxdata      = 1;
5475         s->range_table  = &range_digital;
5476         if (devpriv->is_m_series) {
5477                 s->subdev_flags |= SDF_LSAMPL;
5478                 s->insn_bits    = ni_m_series_dio_insn_bits;
5479                 s->insn_config  = ni_m_series_dio_insn_config;
5480                 if (dev->irq) {
5481                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5482                         s->len_chanlist = s->n_chan;
5483                         s->do_cmdtest   = ni_cdio_cmdtest;
5484                         s->do_cmd       = ni_cdio_cmd;
5485                         s->cancel       = ni_cdio_cancel;
5486
5487                         /* M-series boards use DMA */
5488                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5489                 }
5490
5491                 /* reset DIO and set all channels to inputs */
5492                 ni_writel(dev, CDO_Reset_Bit | CDI_Reset_Bit,
5493                           M_Offset_CDIO_Command);
5494                 ni_writel(dev, s->io_bits, M_Offset_DIO_Direction);
5495         } else {
5496                 s->insn_bits    = ni_dio_insn_bits;
5497                 s->insn_config  = ni_dio_insn_config;
5498
5499                 /* set all channels to inputs */
5500                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
5501                 ni_writew(dev, devpriv->dio_control, DIO_Control_Register);
5502         }
5503
5504         /* 8255 device */
5505         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5506         if (board->has_8255) {
5507                 ret = subdev_8255_init(dev, s, ni_8255_callback, Port_A);
5508                 if (ret)
5509                         return ret;
5510         } else {
5511                 s->type = COMEDI_SUBD_UNUSED;
5512         }
5513
5514         /* formerly general purpose counter/timer device, but no longer used */
5515         s = &dev->subdevices[NI_UNUSED_SUBDEV];
5516         s->type = COMEDI_SUBD_UNUSED;
5517
5518         /* Calibration subdevice */
5519         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5520         s->type         = COMEDI_SUBD_CALIB;
5521         s->subdev_flags = SDF_INTERNAL;
5522         s->n_chan       = 1;
5523         s->maxdata      = 0;
5524         if (devpriv->is_m_series) {
5525                 /* internal PWM output used for AI nonlinearity calibration */
5526                 s->insn_config  = ni_m_series_pwm_config;
5527
5528                 ni_writel(dev, 0x0, M_Offset_Cal_PWM);
5529         } else if (devpriv->is_6143) {
5530                 /* internal PWM output used for AI nonlinearity calibration */
5531                 s->insn_config  = ni_6143_pwm_config;
5532         } else {
5533                 s->subdev_flags |= SDF_WRITABLE;
5534                 s->insn_read    = ni_calib_insn_read;
5535                 s->insn_write   = ni_calib_insn_write;
5536
5537                 /* setup the caldacs and find the real n_chan and maxdata */
5538                 caldac_setup(dev, s);
5539         }
5540
5541         /* EEPROM subdevice */
5542         s = &dev->subdevices[NI_EEPROM_SUBDEV];
5543         s->type         = COMEDI_SUBD_MEMORY;
5544         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5545         s->maxdata      = 0xff;
5546         if (devpriv->is_m_series) {
5547                 s->n_chan       = M_SERIES_EEPROM_SIZE;
5548                 s->insn_read    = ni_m_series_eeprom_insn_read;
5549         } else {
5550                 s->n_chan       = 512;
5551                 s->insn_read    = ni_eeprom_insn_read;
5552         }
5553
5554         /* Digital I/O (PFI) subdevice */
5555         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5556         s->type         = COMEDI_SUBD_DIO;
5557         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5558         s->maxdata      = 1;
5559         if (devpriv->is_m_series) {
5560                 s->n_chan       = 16;
5561                 s->insn_bits    = ni_pfi_insn_bits;
5562
5563                 ni_writew(dev, s->state, M_Offset_PFI_DO);
5564                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5565                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
5566                                   M_Offset_PFI_Output_Select(i + 1));
5567                 }
5568         } else {
5569                 s->n_chan       = 10;
5570         }
5571         s->insn_config  = ni_pfi_insn_config;
5572
5573         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
5574
5575         /* cs5529 calibration adc */
5576         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5577         if (devpriv->is_67xx) {
5578                 s->type = COMEDI_SUBD_AI;
5579                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5580                 /*  one channel for each analog output channel */
5581                 s->n_chan = board->n_aochan;
5582                 s->maxdata = (1 << 16) - 1;
5583                 s->range_table = &range_unknown;        /* XXX */
5584                 s->insn_read = cs5529_ai_insn_read;
5585                 s->insn_config = NULL;
5586                 init_cs5529(dev);
5587         } else {
5588                 s->type = COMEDI_SUBD_UNUSED;
5589         }
5590
5591         /* Serial */
5592         s = &dev->subdevices[NI_SERIAL_SUBDEV];
5593         s->type = COMEDI_SUBD_SERIAL;
5594         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5595         s->n_chan = 1;
5596         s->maxdata = 0xff;
5597         s->insn_config = ni_serial_insn_config;
5598         devpriv->serial_interval_ns = 0;
5599         devpriv->serial_hw_mode = 0;
5600
5601         /* RTSI */
5602         s = &dev->subdevices[NI_RTSI_SUBDEV];
5603         s->type = COMEDI_SUBD_DIO;
5604         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5605         s->n_chan = 8;
5606         s->maxdata = 1;
5607         s->insn_bits = ni_rtsi_insn_bits;
5608         s->insn_config = ni_rtsi_insn_config;
5609         ni_rtsi_init(dev);
5610
5611         /* allocate and initialize the gpct counter device */
5612         devpriv->counter_dev = ni_gpct_device_construct(dev,
5613                                         ni_gpct_write_register,
5614                                         ni_gpct_read_register,
5615                                         (devpriv->is_m_series)
5616                                                 ? ni_gpct_variant_m_series
5617                                                 : ni_gpct_variant_e_series,
5618                                         NUM_GPCT);
5619         if (!devpriv->counter_dev)
5620                 return -ENOMEM;
5621
5622         /* Counter (gpct) subdevices */
5623         for (i = 0; i < NUM_GPCT; ++i) {
5624                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5625
5626                 /* setup and initialize the counter */
5627                 gpct->chip_index = 0;
5628                 gpct->counter_index = i;
5629                 ni_tio_init_counter(gpct);
5630
5631                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5632                 s->type         = COMEDI_SUBD_COUNTER;
5633                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5634                 s->n_chan       = 3;
5635                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
5636                                                          : 0x00ffffff;
5637                 s->insn_read    = ni_tio_insn_read;
5638                 s->insn_write   = ni_tio_insn_read;
5639                 s->insn_config  = ni_tio_insn_config;
5640 #ifdef PCIDMA
5641                 if (dev->irq && devpriv->mite) {
5642                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5643                         s->len_chanlist = 1;
5644                         s->do_cmdtest   = ni_tio_cmdtest;
5645                         s->do_cmd       = ni_gpct_cmd;
5646                         s->cancel       = ni_gpct_cancel;
5647
5648                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5649                 }
5650 #endif
5651                 s->private      = gpct;
5652         }
5653
5654         /* Frequency output subdevice */
5655         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5656         s->type         = COMEDI_SUBD_COUNTER;
5657         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5658         s->n_chan       = 1;
5659         s->maxdata      = 0xf;
5660         s->insn_read    = ni_freq_out_insn_read;
5661         s->insn_write   = ni_freq_out_insn_write;
5662         s->insn_config  = ni_freq_out_insn_config;
5663
5664         if (dev->irq) {
5665                 ni_stc_writew(dev,
5666                               (irq_polarity ? Interrupt_Output_Polarity : 0) |
5667                               (Interrupt_Output_On_3_Pins & 0) |
5668                               Interrupt_A_Enable | Interrupt_B_Enable |
5669                               Interrupt_A_Output_Select(interrupt_pin) |
5670                               Interrupt_B_Output_Select(interrupt_pin),
5671                               Interrupt_Control_Register);
5672         }
5673
5674         /* DMA setup */
5675         ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select);
5676         ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select);
5677
5678         if (devpriv->is_6xxx) {
5679                 ni_writeb(dev, 0, Magic_611x);
5680         } else if (devpriv->is_m_series) {
5681                 int channel;
5682
5683                 for (channel = 0; channel < board->n_aochan; ++channel) {
5684                         ni_writeb(dev, 0xf,
5685                                   M_Offset_AO_Waveform_Order(channel));
5686                         ni_writeb(dev, 0x0,
5687                                   M_Offset_AO_Reference_Attenuation(channel));
5688                 }
5689                 ni_writeb(dev, 0x0, M_Offset_AO_Calibration);
5690         }
5691
5692         return 0;
5693 }
5694
5695 static void mio_common_detach(struct comedi_device *dev)
5696 {
5697         struct ni_private *devpriv = dev->private;
5698
5699         if (devpriv) {
5700                 if (devpriv->counter_dev)
5701                         ni_gpct_device_destroy(devpriv->counter_dev);
5702         }
5703 }