kernel/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c

   1 /*
   2  * Xilinx 'Clocking Wizard' driver
   3  *
   4  *  Copyright (C) 2013 - 2014 Xilinx
   5  *
   6  *  Sören Brinkmann <soren.brinkmann@xilinx.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License v2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/platform_device.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/slab.h>
  24 #include <linux/io.h>
  25 #include <linux/of.h>
  26 #include <linux/module.h>
  27 #include <linux/err.h>
  28
  29 #define WZRD_NUM_OUTPUTS        7
  30 #define WZRD_ACLK_MAX_FREQ      250000000UL
  31
  32 #define WZRD_CLK_CFG_REG(n)     (0x200 + 4 * (n))
  33
  34 #define WZRD_CLkOUT0_FRAC_EN    BIT(18)
  35 #define WZRD_CLkFBOUT_FRAC_EN   BIT(26)
  36
  37 #define WZRD_CLKFBOUT_MULT_SHIFT        8
  38 #define WZRD_CLKFBOUT_MULT_MASK         (0xff << WZRD_CLKFBOUT_MULT_SHIFT)
  39 #define WZRD_DIVCLK_DIVIDE_SHIFT        0
  40 #define WZRD_DIVCLK_DIVIDE_MASK         (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
  41 #define WZRD_CLKOUT_DIVIDE_SHIFT        0
  42 #define WZRD_CLKOUT_DIVIDE_MASK         (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
  43
  44 enum clk_wzrd_int_clks {
  45         wzrd_clk_mul,
  46         wzrd_clk_mul_div,
  47         wzrd_clk_int_max
  48 };
  49
  50 /**
  51  * struct clk_wzrd:
  52  * @clk_data:           Clock data
  53  * @nb:                 Notifier block
  54  * @base:               Memory base
  55  * @clk_in1:            Handle to input clock 'clk_in1'
  56  * @axi_clk:            Handle to input clock 's_axi_aclk'
  57  * @clks_internal:      Internal clocks
  58  * @clkout:             Output clocks
  59  * @speed_grade:        Speed grade of the device
  60  * @suspended:          Flag indicating power state of the device
  61  */
  62 struct clk_wzrd {
  63         struct clk_onecell_data clk_data;
  64         struct notifier_block nb;
  65         void __iomem *base;
  66         struct clk *clk_in1;
  67         struct clk *axi_clk;
  68         struct clk *clks_internal[wzrd_clk_int_max];
  69         struct clk *clkout[WZRD_NUM_OUTPUTS];
  70         int speed_grade;
  71         bool suspended;
  72 };
  73 #define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb)
  74
  75 /* maximum frequencies for input/output clocks per speed grade */
  76 static const unsigned long clk_wzrd_max_freq[] = {
  77         800000000UL,
  78         933000000UL,
  79         1066000000UL
  80 };
  81
  82 static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event,
  83                                  void *data)
  84 {
  85         unsigned long max;
  86         struct clk_notifier_data *ndata = data;
  87         struct clk_wzrd *clk_wzrd = to_clk_wzrd(nb);
  88
  89         if (clk_wzrd->suspended)
  90                 return NOTIFY_OK;
  91
  92         if (ndata->clk == clk_wzrd->clk_in1)
  93                 max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1];
  94         else if (ndata->clk == clk_wzrd->axi_clk)
  95                 max = WZRD_ACLK_MAX_FREQ;
  96         else
  97                 return NOTIFY_DONE;     /* should never happen */
  98
  99         switch (event) {
 100         case PRE_RATE_CHANGE:
 101                 if (ndata->new_rate > max)
 102                         return NOTIFY_BAD;
 103                 return NOTIFY_OK;
 104         case POST_RATE_CHANGE:
 105         case ABORT_RATE_CHANGE:
 106         default:
 107                 return NOTIFY_DONE;
 108         }
 109 }
 110
 111 static int __maybe_unused clk_wzrd_suspend(struct device *dev)
 112 {
 113         struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
 114
 115         clk_disable_unprepare(clk_wzrd->axi_clk);
 116         clk_wzrd->suspended = true;
 117
 118         return 0;
 119 }
 120
 121 static int __maybe_unused clk_wzrd_resume(struct device *dev)
 122 {
 123         int ret;
 124         struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
 125
 126         ret = clk_prepare_enable(clk_wzrd->axi_clk);
 127         if (ret) {
 128                 dev_err(dev, "unable to enable s_axi_aclk\n");
 129                 return ret;
 130         }
 131
 132         clk_wzrd->suspended = false;
 133
 134         return 0;
 135 }
 136
 137 static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend,
 138                          clk_wzrd_resume);
 139
 140 static int clk_wzrd_probe(struct platform_device *pdev)
 141 {
 142         int i, ret;
 143         u32 reg;
 144         unsigned long rate;
 145         const char *clk_name;
 146         struct clk_wzrd *clk_wzrd;
 147         struct resource *mem;
 148         struct device_node *np = pdev->dev.of_node;
 149
 150         clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
 151         if (!clk_wzrd)
 152                 return -ENOMEM;
 153         platform_set_drvdata(pdev, clk_wzrd);
 154
 155         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 156         clk_wzrd->base = devm_ioremap_resource(&pdev->dev, mem);
 157         if (IS_ERR(clk_wzrd->base))
 158                 return PTR_ERR(clk_wzrd->base);
 159
 160         ret = of_property_read_u32(np, "speed-grade", &clk_wzrd->speed_grade);
 161         if (!ret) {
 162                 if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {
 163                         dev_warn(&pdev->dev, "invalid speed grade '%d'\n",
 164                                  clk_wzrd->speed_grade);
 165                         clk_wzrd->speed_grade = 0;
 166                 }
 167         }
 168
 169         clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1");
 170         if (IS_ERR(clk_wzrd->clk_in1)) {
 171                 if (clk_wzrd->clk_in1 != ERR_PTR(-EPROBE_DEFER))
 172                         dev_err(&pdev->dev, "clk_in1 not found\n");
 173                 return PTR_ERR(clk_wzrd->clk_in1);
 174         }
 175
 176         clk_wzrd->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
 177         if (IS_ERR(clk_wzrd->axi_clk)) {
 178                 if (clk_wzrd->axi_clk != ERR_PTR(-EPROBE_DEFER))
 179                         dev_err(&pdev->dev, "s_axi_aclk not found\n");
 180                 return PTR_ERR(clk_wzrd->axi_clk);
 181         }
 182         ret = clk_prepare_enable(clk_wzrd->axi_clk);
 183         if (ret) {
 184                 dev_err(&pdev->dev, "enabling s_axi_aclk failed\n");
 185                 return ret;
 186         }
 187         rate = clk_get_rate(clk_wzrd->axi_clk);
 188         if (rate > WZRD_ACLK_MAX_FREQ) {
 189                 dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n",
 190                         rate);
 191                 ret = -EINVAL;
 192                 goto err_disable_clk;
 193         }
 194
 195         /* we don't support fractional div/mul yet */
 196         reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
 197                     WZRD_CLkFBOUT_FRAC_EN;
 198         reg |= readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2)) &
 199                      WZRD_CLkOUT0_FRAC_EN;
 200         if (reg)
 201                 dev_warn(&pdev->dev, "fractional div/mul not supported\n");
 202
 203         /* register multiplier */
 204         reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
 205                      WZRD_CLKFBOUT_MULT_MASK) >> WZRD_CLKFBOUT_MULT_SHIFT;
 206         clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev));
 207         if (!clk_name) {
 208                 ret = -ENOMEM;
 209                 goto err_disable_clk;
 210         }
 211         clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor(
 212                         &pdev->dev, clk_name,
 213                         __clk_get_name(clk_wzrd->clk_in1),
 214                         0, reg, 1);
 215         kfree(clk_name);
 216         if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) {
 217                 dev_err(&pdev->dev, "unable to register fixed-factor clock\n");
 218                 ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]);
 219                 goto err_disable_clk;
 220         }
 221
 222         /* register div */
 223         reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
 224                         WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT;
 225         clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
 226         if (!clk_name) {
 227                 ret = -ENOMEM;
 228                 goto err_rm_int_clk;
 229         }
 230
 231         clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_fixed_factor(
 232                         &pdev->dev, clk_name,
 233                         __clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
 234                         0, 1, reg);
 235         if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) {
 236                 dev_err(&pdev->dev, "unable to register divider clock\n");
 237                 ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]);
 238                 goto err_rm_int_clk;
 239         }
 240
 241         /* register div per output */
 242         for (i = WZRD_NUM_OUTPUTS - 1; i >= 0 ; i--) {
 243                 const char *clkout_name;
 244
 245                 if (of_property_read_string_index(np, "clock-output-names", i,
 246                                                   &clkout_name)) {
 247                         dev_err(&pdev->dev,
 248                                 "clock output name not specified\n");
 249                         ret = -EINVAL;
 250                         goto err_rm_int_clks;
 251                 }
 252                 reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2) + i * 12);
 253                 reg &= WZRD_CLKOUT_DIVIDE_MASK;
 254                 reg >>= WZRD_CLKOUT_DIVIDE_SHIFT;
 255                 clk_wzrd->clkout[i] = clk_register_fixed_factor(&pdev->dev,
 256                                 clkout_name, clk_name, 0, 1, reg);
 257                 if (IS_ERR(clk_wzrd->clkout[i])) {
 258                         int j;
 259
 260                         for (j = i + 1; j < WZRD_NUM_OUTPUTS; j++)
 261                                 clk_unregister(clk_wzrd->clkout[j]);
 262                         dev_err(&pdev->dev,
 263                                 "unable to register divider clock\n");
 264                         ret = PTR_ERR(clk_wzrd->clkout[i]);
 265                         goto err_rm_int_clks;
 266                 }
 267         }
 268
 269         kfree(clk_name);
 270
 271         clk_wzrd->clk_data.clks = clk_wzrd->clkout;
 272         clk_wzrd->clk_data.clk_num = ARRAY_SIZE(clk_wzrd->clkout);
 273         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_wzrd->clk_data);
 274
 275         if (clk_wzrd->speed_grade) {
 276                 clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier;
 277
 278                 ret = clk_notifier_register(clk_wzrd->clk_in1,
 279                                             &clk_wzrd->nb);
 280                 if (ret)
 281                         dev_warn(&pdev->dev,
 282                                  "unable to register clock notifier\n");
 283
 284                 ret = clk_notifier_register(clk_wzrd->axi_clk, &clk_wzrd->nb);
 285                 if (ret)
 286                         dev_warn(&pdev->dev,
 287                                  "unable to register clock notifier\n");
 288         }
 289
 290         return 0;
 291
 292 err_rm_int_clks:
 293         clk_unregister(clk_wzrd->clks_internal[1]);
 294 err_rm_int_clk:
 295         kfree(clk_name);
 296         clk_unregister(clk_wzrd->clks_internal[0]);
 297 err_disable_clk:
 298         clk_disable_unprepare(clk_wzrd->axi_clk);
 299
 300         return ret;
 301 }
 302
 303 static int clk_wzrd_remove(struct platform_device *pdev)
 304 {
 305         int i;
 306         struct clk_wzrd *clk_wzrd = platform_get_drvdata(pdev);
 307
 308         of_clk_del_provider(pdev->dev.of_node);
 309
 310         for (i = 0; i < WZRD_NUM_OUTPUTS; i++)
 311                 clk_unregister(clk_wzrd->clkout[i]);
 312         for (i = 0; i < wzrd_clk_int_max; i++)
 313                 clk_unregister(clk_wzrd->clks_internal[i]);
 314
 315         if (clk_wzrd->speed_grade) {
 316                 clk_notifier_unregister(clk_wzrd->axi_clk, &clk_wzrd->nb);
 317                 clk_notifier_unregister(clk_wzrd->clk_in1, &clk_wzrd->nb);
 318         }
 319
 320         clk_disable_unprepare(clk_wzrd->axi_clk);
 321
 322         return 0;
 323 }
 324
 325 static const struct of_device_id clk_wzrd_ids[] = {
 326         { .compatible = "xlnx,clocking-wizard" },
 327         { },
 328 };
 329 MODULE_DEVICE_TABLE(of, clk_wzrd_ids);
 330
 331 static struct platform_driver clk_wzrd_driver = {
 332         .driver = {
 333                 .name = "clk-wizard",
 334                 .of_match_table = clk_wzrd_ids,
 335                 .pm = &clk_wzrd_dev_pm_ops,
 336         },
 337         .probe = clk_wzrd_probe,
 338         .remove = clk_wzrd_remove,
 339 };
 340 module_platform_driver(clk_wzrd_driver);
 341
 342 MODULE_LICENSE("GPL");
 343 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com");
 344 MODULE_DESCRIPTION("Driver for the Xilinx Clocking Wizard IP core");