To modify Ixia port numbers and IP in pod.yaml
[kvmfornfv.git] / kernel / drivers / staging / clocking-wizard / Kconfig
1 #
2 # Xilinx Clocking Wizard Driver
3 #
4
5 config COMMON_CLK_XLNX_CLKWZRD
6         tristate "Xilinx Clocking Wizard"
7         depends on COMMON_CLK && OF
8         ---help---
9           Support for the Xilinx Clocking Wizard IP core clock generator.