kernel/drivers/spi/spi-atmel.c

   1 /*
   2  * Driver for Atmel AT32 and AT91 SPI Controllers
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/clk.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/delay.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_data/atmel.h>
  23 #include <linux/platform_data/dma-atmel.h>
  24 #include <linux/of.h>
  25
  26 #include <linux/io.h>
  27 #include <linux/gpio.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/pm_runtime.h>
  30
  31 /* SPI register offsets */
  32 #define SPI_CR                                  0x0000
  33 #define SPI_MR                                  0x0004
  34 #define SPI_RDR                                 0x0008
  35 #define SPI_TDR                                 0x000c
  36 #define SPI_SR                                  0x0010
  37 #define SPI_IER                                 0x0014
  38 #define SPI_IDR                                 0x0018
  39 #define SPI_IMR                                 0x001c
  40 #define SPI_CSR0                                0x0030
  41 #define SPI_CSR1                                0x0034
  42 #define SPI_CSR2                                0x0038
  43 #define SPI_CSR3                                0x003c
  44 #define SPI_VERSION                             0x00fc
  45 #define SPI_RPR                                 0x0100
  46 #define SPI_RCR                                 0x0104
  47 #define SPI_TPR                                 0x0108
  48 #define SPI_TCR                                 0x010c
  49 #define SPI_RNPR                                0x0110
  50 #define SPI_RNCR                                0x0114
  51 #define SPI_TNPR                                0x0118
  52 #define SPI_TNCR                                0x011c
  53 #define SPI_PTCR                                0x0120
  54 #define SPI_PTSR                                0x0124
  55
  56 /* Bitfields in CR */
  57 #define SPI_SPIEN_OFFSET                        0
  58 #define SPI_SPIEN_SIZE                          1
  59 #define SPI_SPIDIS_OFFSET                       1
  60 #define SPI_SPIDIS_SIZE                         1
  61 #define SPI_SWRST_OFFSET                        7
  62 #define SPI_SWRST_SIZE                          1
  63 #define SPI_LASTXFER_OFFSET                     24
  64 #define SPI_LASTXFER_SIZE                       1
  65
  66 /* Bitfields in MR */
  67 #define SPI_MSTR_OFFSET                         0
  68 #define SPI_MSTR_SIZE                           1
  69 #define SPI_PS_OFFSET                           1
  70 #define SPI_PS_SIZE                             1
  71 #define SPI_PCSDEC_OFFSET                       2
  72 #define SPI_PCSDEC_SIZE                         1
  73 #define SPI_FDIV_OFFSET                         3
  74 #define SPI_FDIV_SIZE                           1
  75 #define SPI_MODFDIS_OFFSET                      4
  76 #define SPI_MODFDIS_SIZE                        1
  77 #define SPI_WDRBT_OFFSET                        5
  78 #define SPI_WDRBT_SIZE                          1
  79 #define SPI_LLB_OFFSET                          7
  80 #define SPI_LLB_SIZE                            1
  81 #define SPI_PCS_OFFSET                          16
  82 #define SPI_PCS_SIZE                            4
  83 #define SPI_DLYBCS_OFFSET                       24
  84 #define SPI_DLYBCS_SIZE                         8
  85
  86 /* Bitfields in RDR */
  87 #define SPI_RD_OFFSET                           0
  88 #define SPI_RD_SIZE                             16
  89
  90 /* Bitfields in TDR */
  91 #define SPI_TD_OFFSET                           0
  92 #define SPI_TD_SIZE                             16
  93
  94 /* Bitfields in SR */
  95 #define SPI_RDRF_OFFSET                         0
  96 #define SPI_RDRF_SIZE                           1
  97 #define SPI_TDRE_OFFSET                         1
  98 #define SPI_TDRE_SIZE                           1
  99 #define SPI_MODF_OFFSET                         2
 100 #define SPI_MODF_SIZE                           1
 101 #define SPI_OVRES_OFFSET                        3
 102 #define SPI_OVRES_SIZE                          1
 103 #define SPI_ENDRX_OFFSET                        4
 104 #define SPI_ENDRX_SIZE                          1
 105 #define SPI_ENDTX_OFFSET                        5
 106 #define SPI_ENDTX_SIZE                          1
 107 #define SPI_RXBUFF_OFFSET                       6
 108 #define SPI_RXBUFF_SIZE                         1
 109 #define SPI_TXBUFE_OFFSET                       7
 110 #define SPI_TXBUFE_SIZE                         1
 111 #define SPI_NSSR_OFFSET                         8
 112 #define SPI_NSSR_SIZE                           1
 113 #define SPI_TXEMPTY_OFFSET                      9
 114 #define SPI_TXEMPTY_SIZE                        1
 115 #define SPI_SPIENS_OFFSET                       16
 116 #define SPI_SPIENS_SIZE                         1
 117
 118 /* Bitfields in CSR0 */
 119 #define SPI_CPOL_OFFSET                         0
 120 #define SPI_CPOL_SIZE                           1
 121 #define SPI_NCPHA_OFFSET                        1
 122 #define SPI_NCPHA_SIZE                          1
 123 #define SPI_CSAAT_OFFSET                        3
 124 #define SPI_CSAAT_SIZE                          1
 125 #define SPI_BITS_OFFSET                         4
 126 #define SPI_BITS_SIZE                           4
 127 #define SPI_SCBR_OFFSET                         8
 128 #define SPI_SCBR_SIZE                           8
 129 #define SPI_DLYBS_OFFSET                        16
 130 #define SPI_DLYBS_SIZE                          8
 131 #define SPI_DLYBCT_OFFSET                       24
 132 #define SPI_DLYBCT_SIZE                         8
 133
 134 /* Bitfields in RCR */
 135 #define SPI_RXCTR_OFFSET                        0
 136 #define SPI_RXCTR_SIZE                          16
 137
 138 /* Bitfields in TCR */
 139 #define SPI_TXCTR_OFFSET                        0
 140 #define SPI_TXCTR_SIZE                          16
 141
 142 /* Bitfields in RNCR */
 143 #define SPI_RXNCR_OFFSET                        0
 144 #define SPI_RXNCR_SIZE                          16
 145
 146 /* Bitfields in TNCR */
 147 #define SPI_TXNCR_OFFSET                        0
 148 #define SPI_TXNCR_SIZE                          16
 149
 150 /* Bitfields in PTCR */
 151 #define SPI_RXTEN_OFFSET                        0
 152 #define SPI_RXTEN_SIZE                          1
 153 #define SPI_RXTDIS_OFFSET                       1
 154 #define SPI_RXTDIS_SIZE                         1
 155 #define SPI_TXTEN_OFFSET                        8
 156 #define SPI_TXTEN_SIZE                          1
 157 #define SPI_TXTDIS_OFFSET                       9
 158 #define SPI_TXTDIS_SIZE                         1
 159
 160 /* Constants for BITS */
 161 #define SPI_BITS_8_BPT                          0
 162 #define SPI_BITS_9_BPT                          1
 163 #define SPI_BITS_10_BPT                         2
 164 #define SPI_BITS_11_BPT                         3
 165 #define SPI_BITS_12_BPT                         4
 166 #define SPI_BITS_13_BPT                         5
 167 #define SPI_BITS_14_BPT                         6
 168 #define SPI_BITS_15_BPT                         7
 169 #define SPI_BITS_16_BPT                         8
 170
 171 /* Bit manipulation macros */
 172 #define SPI_BIT(name) \
 173         (1 << SPI_##name##_OFFSET)
 174 #define SPI_BF(name, value) \
 175         (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
 176 #define SPI_BFEXT(name, value) \
 177         (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
 178 #define SPI_BFINS(name, value, old) \
 179         (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
 180           | SPI_BF(name, value))
 181
 182 /* Register access macros */
 183 #ifdef CONFIG_AVR32
 184 #define spi_readl(port, reg) \
 185         __raw_readl((port)->regs + SPI_##reg)
 186 #define spi_writel(port, reg, value) \
 187         __raw_writel((value), (port)->regs + SPI_##reg)
 188 #else
 189 #define spi_readl(port, reg) \
 190         readl_relaxed((port)->regs + SPI_##reg)
 191 #define spi_writel(port, reg, value) \
 192         writel_relaxed((value), (port)->regs + SPI_##reg)
 193 #endif
 194 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 195  * cache operations; better heuristics consider wordsize and bitrate.
 196  */
 197 #define DMA_MIN_BYTES   16
 198
 199 #define SPI_DMA_TIMEOUT         (msecs_to_jiffies(1000))
 200
 201 #define AUTOSUSPEND_TIMEOUT     2000
 202
 203 struct atmel_spi_dma {
 204         struct dma_chan                 *chan_rx;
 205         struct dma_chan                 *chan_tx;
 206         struct scatterlist              sgrx;
 207         struct scatterlist              sgtx;
 208         struct dma_async_tx_descriptor  *data_desc_rx;
 209         struct dma_async_tx_descriptor  *data_desc_tx;
 210
 211         struct at_dma_slave     dma_slave;
 212 };
 213
 214 struct atmel_spi_caps {
 215         bool    is_spi2;
 216         bool    has_wdrbt;
 217         bool    has_dma_support;
 218 };
 219
 220 /*
 221  * The core SPI transfer engine just talks to a register bank to set up
 222  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
 223  * framework provides the base clock, subdivided for each spi_device.
 224  */
 225 struct atmel_spi {
 226         spinlock_t              lock;
 227         unsigned long           flags;
 228
 229         phys_addr_t             phybase;
 230         void __iomem            *regs;
 231         int                     irq;
 232         struct clk              *clk;
 233         struct platform_device  *pdev;
 234
 235         struct spi_transfer     *current_transfer;
 236         int                     current_remaining_bytes;
 237         int                     done_status;
 238
 239         struct completion       xfer_completion;
 240
 241         /* scratch buffer */
 242         void                    *buffer;
 243         dma_addr_t              buffer_dma;
 244
 245         struct atmel_spi_caps   caps;
 246
 247         bool                    use_dma;
 248         bool                    use_pdc;
 249         /* dmaengine data */
 250         struct atmel_spi_dma    dma;
 251
 252         bool                    keep_cs;
 253         bool                    cs_active;
 254 };
 255
 256 /* Controller-specific per-slave state */
 257 struct atmel_spi_device {
 258         unsigned int            npcs_pin;
 259         u32                     csr;
 260 };
 261
 262 #define BUFFER_SIZE             PAGE_SIZE
 263 #define INVALID_DMA_ADDRESS     0xffffffff
 264
 265 /*
 266  * Version 2 of the SPI controller has
 267  *  - CR.LASTXFER
 268  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
 269  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
 270  *  - SPI_CSRx.CSAAT
 271  *  - SPI_CSRx.SBCR allows faster clocking
 272  */
 273 static bool atmel_spi_is_v2(struct atmel_spi *as)
 274 {
 275         return as->caps.is_spi2;
 276 }
 277
 278 /*
 279  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
 280  * they assume that spi slave device state will not change on deselect, so
 281  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
 282  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
 283  * controllers have CSAAT and friends.
 284  *
 285  * Since the CSAAT functionality is a bit weird on newer controllers as
 286  * well, we use GPIO to control nCSx pins on all controllers, updating
 287  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
 288  * support active-high chipselects despite the controller's belief that
 289  * only active-low devices/systems exists.
 290  *
 291  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
 292  * right when driven with GPIO.  ("Mode Fault does not allow more than one
 293  * Master on Chip Select 0.")  No workaround exists for that ... so for
 294  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
 295  * and (c) will trigger that first erratum in some cases.
 296  */
 297
 298 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 299 {
 300         struct atmel_spi_device *asd = spi->controller_state;
 301         unsigned active = spi->mode & SPI_CS_HIGH;
 302         u32 mr;
 303
 304         if (atmel_spi_is_v2(as)) {
 305                 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
 306                 /* For the low SPI version, there is a issue that PDC transfer
 307                  * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
 308                  */
 309                 spi_writel(as, CSR0, asd->csr);
 310                 if (as->caps.has_wdrbt) {
 311                         spi_writel(as, MR,
 312                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 313                                         | SPI_BIT(WDRBT)
 314                                         | SPI_BIT(MODFDIS)
 315                                         | SPI_BIT(MSTR));
 316                 } else {
 317                         spi_writel(as, MR,
 318                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 319                                         | SPI_BIT(MODFDIS)
 320                                         | SPI_BIT(MSTR));
 321                 }
 322
 323                 mr = spi_readl(as, MR);
 324                 gpio_set_value(asd->npcs_pin, active);
 325         } else {
 326                 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 327                 int i;
 328                 u32 csr;
 329
 330                 /* Make sure clock polarity is correct */
 331                 for (i = 0; i < spi->master->num_chipselect; i++) {
 332                         csr = spi_readl(as, CSR0 + 4 * i);
 333                         if ((csr ^ cpol) & SPI_BIT(CPOL))
 334                                 spi_writel(as, CSR0 + 4 * i,
 335                                                 csr ^ SPI_BIT(CPOL));
 336                 }
 337
 338                 mr = spi_readl(as, MR);
 339                 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
 340                 if (spi->chip_select != 0)
 341                         gpio_set_value(asd->npcs_pin, active);
 342                 spi_writel(as, MR, mr);
 343         }
 344
 345         dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
 346                         asd->npcs_pin, active ? " (high)" : "",
 347                         mr);
 348 }
 349
 350 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 351 {
 352         struct atmel_spi_device *asd = spi->controller_state;
 353         unsigned active = spi->mode & SPI_CS_HIGH;
 354         u32 mr;
 355
 356         /* only deactivate *this* device; sometimes transfers to
 357          * another device may be active when this routine is called.
 358          */
 359         mr = spi_readl(as, MR);
 360         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 361                 mr = SPI_BFINS(PCS, 0xf, mr);
 362                 spi_writel(as, MR, mr);
 363         }
 364
 365         dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
 366                         asd->npcs_pin, active ? " (low)" : "",
 367                         mr);
 368
 369         if (atmel_spi_is_v2(as) || spi->chip_select != 0)
 370                 gpio_set_value(asd->npcs_pin, !active);
 371 }
 372
 373 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
 374 {
 375         spin_lock_irqsave(&as->lock, as->flags);
 376 }
 377
 378 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
 379 {
 380         spin_unlock_irqrestore(&as->lock, as->flags);
 381 }
 382
 383 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
 384                                 struct spi_transfer *xfer)
 385 {
 386         return as->use_dma && xfer->len >= DMA_MIN_BYTES;
 387 }
 388
 389 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
 390                                 struct dma_slave_config *slave_config,
 391                                 u8 bits_per_word)
 392 {
 393         int err = 0;
 394
 395         if (bits_per_word > 8) {
 396                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 397                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 398         } else {
 399                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 400                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 401         }
 402
 403         slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
 404         slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
 405         slave_config->src_maxburst = 1;
 406         slave_config->dst_maxburst = 1;
 407         slave_config->device_fc = false;
 408
 409         slave_config->direction = DMA_MEM_TO_DEV;
 410         if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
 411                 dev_err(&as->pdev->dev,
 412                         "failed to configure tx dma channel\n");
 413                 err = -EINVAL;
 414         }
 415
 416         slave_config->direction = DMA_DEV_TO_MEM;
 417         if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
 418                 dev_err(&as->pdev->dev,
 419                         "failed to configure rx dma channel\n");
 420                 err = -EINVAL;
 421         }
 422
 423         return err;
 424 }
 425
 426 static int atmel_spi_configure_dma(struct atmel_spi *as)
 427 {
 428         struct dma_slave_config slave_config;
 429         struct device *dev = &as->pdev->dev;
 430         int err;
 431
 432         dma_cap_mask_t mask;
 433         dma_cap_zero(mask);
 434         dma_cap_set(DMA_SLAVE, mask);
 435
 436         as->dma.chan_tx = dma_request_slave_channel_reason(dev, "tx");
 437         if (IS_ERR(as->dma.chan_tx)) {
 438                 err = PTR_ERR(as->dma.chan_tx);
 439                 if (err == -EPROBE_DEFER) {
 440                         dev_warn(dev, "no DMA channel available at the moment\n");
 441                         return err;
 442                 }
 443                 dev_err(dev,
 444                         "DMA TX channel not available, SPI unable to use DMA\n");
 445                 err = -EBUSY;
 446                 goto error;
 447         }
 448
 449         /*
 450          * No reason to check EPROBE_DEFER here since we have already requested
 451          * tx channel. If it fails here, it's for another reason.
 452          */
 453         as->dma.chan_rx = dma_request_slave_channel(dev, "rx");
 454
 455         if (!as->dma.chan_rx) {
 456                 dev_err(dev,
 457                         "DMA RX channel not available, SPI unable to use DMA\n");
 458                 err = -EBUSY;
 459                 goto error;
 460         }
 461
 462         err = atmel_spi_dma_slave_config(as, &slave_config, 8);
 463         if (err)
 464                 goto error;
 465
 466         dev_info(&as->pdev->dev,
 467                         "Using %s (tx) and %s (rx) for DMA transfers\n",
 468                         dma_chan_name(as->dma.chan_tx),
 469                         dma_chan_name(as->dma.chan_rx));
 470         return 0;
 471 error:
 472         if (as->dma.chan_rx)
 473                 dma_release_channel(as->dma.chan_rx);
 474         if (!IS_ERR(as->dma.chan_tx))
 475                 dma_release_channel(as->dma.chan_tx);
 476         return err;
 477 }
 478
 479 static void atmel_spi_stop_dma(struct atmel_spi *as)
 480 {
 481         if (as->dma.chan_rx)
 482                 dmaengine_terminate_all(as->dma.chan_rx);
 483         if (as->dma.chan_tx)
 484                 dmaengine_terminate_all(as->dma.chan_tx);
 485 }
 486
 487 static void atmel_spi_release_dma(struct atmel_spi *as)
 488 {
 489         if (as->dma.chan_rx)
 490                 dma_release_channel(as->dma.chan_rx);
 491         if (as->dma.chan_tx)
 492                 dma_release_channel(as->dma.chan_tx);
 493 }
 494
 495 /* This function is called by the DMA driver from tasklet context */
 496 static void dma_callback(void *data)
 497 {
 498         struct spi_master       *master = data;
 499         struct atmel_spi        *as = spi_master_get_devdata(master);
 500
 501         complete(&as->xfer_completion);
 502 }
 503
 504 /*
 505  * Next transfer using PIO.
 506  */
 507 static void atmel_spi_next_xfer_pio(struct spi_master *master,
 508                                 struct spi_transfer *xfer)
 509 {
 510         struct atmel_spi        *as = spi_master_get_devdata(master);
 511         unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
 512
 513         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
 514
 515         /* Make sure data is not remaining in RDR */
 516         spi_readl(as, RDR);
 517         while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
 518                 spi_readl(as, RDR);
 519                 cpu_relax();
 520         }
 521
 522         if (xfer->tx_buf) {
 523                 if (xfer->bits_per_word > 8)
 524                         spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
 525                 else
 526                         spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
 527         } else {
 528                 spi_writel(as, TDR, 0);
 529         }
 530
 531         dev_dbg(master->dev.parent,
 532                 "  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
 533                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 534                 xfer->bits_per_word);
 535
 536         /* Enable relevant interrupts */
 537         spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
 538 }
 539
 540 /*
 541  * Submit next transfer for DMA.
 542  */
 543 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
 544                                 struct spi_transfer *xfer,
 545                                 u32 *plen)
 546 {
 547         struct atmel_spi        *as = spi_master_get_devdata(master);
 548         struct dma_chan         *rxchan = as->dma.chan_rx;
 549         struct dma_chan         *txchan = as->dma.chan_tx;
 550         struct dma_async_tx_descriptor *rxdesc;
 551         struct dma_async_tx_descriptor *txdesc;
 552         struct dma_slave_config slave_config;
 553         dma_cookie_t            cookie;
 554         u32     len = *plen;
 555
 556         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
 557
 558         /* Check that the channels are available */
 559         if (!rxchan || !txchan)
 560                 return -ENODEV;
 561
 562         /* release lock for DMA operations */
 563         atmel_spi_unlock(as);
 564
 565         /* prepare the RX dma transfer */
 566         sg_init_table(&as->dma.sgrx, 1);
 567         if (xfer->rx_buf) {
 568                 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
 569         } else {
 570                 as->dma.sgrx.dma_address = as->buffer_dma;
 571                 if (len > BUFFER_SIZE)
 572                         len = BUFFER_SIZE;
 573         }
 574
 575         /* prepare the TX dma transfer */
 576         sg_init_table(&as->dma.sgtx, 1);
 577         if (xfer->tx_buf) {
 578                 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
 579         } else {
 580                 as->dma.sgtx.dma_address = as->buffer_dma;
 581                 if (len > BUFFER_SIZE)
 582                         len = BUFFER_SIZE;
 583                 memset(as->buffer, 0, len);
 584         }
 585
 586         sg_dma_len(&as->dma.sgtx) = len;
 587         sg_dma_len(&as->dma.sgrx) = len;
 588
 589         *plen = len;
 590
 591         if (atmel_spi_dma_slave_config(as, &slave_config, 8))
 592                 goto err_exit;
 593
 594         /* Send both scatterlists */
 595         rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1,
 596                                          DMA_FROM_DEVICE,
 597                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 598         if (!rxdesc)
 599                 goto err_dma;
 600
 601         txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1,
 602                                          DMA_TO_DEVICE,
 603                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 604         if (!txdesc)
 605                 goto err_dma;
 606
 607         dev_dbg(master->dev.parent,
 608                 "  start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 609                 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
 610                 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
 611
 612         /* Enable relevant interrupts */
 613         spi_writel(as, IER, SPI_BIT(OVRES));
 614
 615         /* Put the callback on the RX transfer only, that should finish last */
 616         rxdesc->callback = dma_callback;
 617         rxdesc->callback_param = master;
 618
 619         /* Submit and fire RX and TX with TX last so we're ready to read! */
 620         cookie = rxdesc->tx_submit(rxdesc);
 621         if (dma_submit_error(cookie))
 622                 goto err_dma;
 623         cookie = txdesc->tx_submit(txdesc);
 624         if (dma_submit_error(cookie))
 625                 goto err_dma;
 626         rxchan->device->device_issue_pending(rxchan);
 627         txchan->device->device_issue_pending(txchan);
 628
 629         /* take back lock */
 630         atmel_spi_lock(as);
 631         return 0;
 632
 633 err_dma:
 634         spi_writel(as, IDR, SPI_BIT(OVRES));
 635         atmel_spi_stop_dma(as);
 636 err_exit:
 637         atmel_spi_lock(as);
 638         return -ENOMEM;
 639 }
 640
 641 static void atmel_spi_next_xfer_data(struct spi_master *master,
 642                                 struct spi_transfer *xfer,
 643                                 dma_addr_t *tx_dma,
 644                                 dma_addr_t *rx_dma,
 645                                 u32 *plen)
 646 {
 647         struct atmel_spi        *as = spi_master_get_devdata(master);
 648         u32                     len = *plen;
 649
 650         /* use scratch buffer only when rx or tx data is unspecified */
 651         if (xfer->rx_buf)
 652                 *rx_dma = xfer->rx_dma + xfer->len - *plen;
 653         else {
 654                 *rx_dma = as->buffer_dma;
 655                 if (len > BUFFER_SIZE)
 656                         len = BUFFER_SIZE;
 657         }
 658
 659         if (xfer->tx_buf)
 660                 *tx_dma = xfer->tx_dma + xfer->len - *plen;
 661         else {
 662                 *tx_dma = as->buffer_dma;
 663                 if (len > BUFFER_SIZE)
 664                         len = BUFFER_SIZE;
 665                 memset(as->buffer, 0, len);
 666                 dma_sync_single_for_device(&as->pdev->dev,
 667                                 as->buffer_dma, len, DMA_TO_DEVICE);
 668         }
 669
 670         *plen = len;
 671 }
 672
 673 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
 674                                     struct spi_device *spi,
 675                                     struct spi_transfer *xfer)
 676 {
 677         u32                     scbr, csr;
 678         unsigned long           bus_hz;
 679
 680         /* v1 chips start out at half the peripheral bus speed. */
 681         bus_hz = clk_get_rate(as->clk);
 682         if (!atmel_spi_is_v2(as))
 683                 bus_hz /= 2;
 684
 685         /*
 686          * Calculate the lowest divider that satisfies the
 687          * constraint, assuming div32/fdiv/mbz == 0.
 688          */
 689         if (xfer->speed_hz)
 690                 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
 691         else
 692                 /*
 693                  * This can happend if max_speed is null.
 694                  * In this case, we set the lowest possible speed
 695                  */
 696                 scbr = 0xff;
 697
 698         /*
 699          * If the resulting divider doesn't fit into the
 700          * register bitfield, we can't satisfy the constraint.
 701          */
 702         if (scbr >= (1 << SPI_SCBR_SIZE)) {
 703                 dev_err(&spi->dev,
 704                         "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 705                         xfer->speed_hz, scbr, bus_hz/255);
 706                 return -EINVAL;
 707         }
 708         if (scbr == 0) {
 709                 dev_err(&spi->dev,
 710                         "setup: %d Hz too high, scbr %u; max %ld Hz\n",
 711                         xfer->speed_hz, scbr, bus_hz);
 712                 return -EINVAL;
 713         }
 714         csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
 715         csr = SPI_BFINS(SCBR, scbr, csr);
 716         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 717
 718         return 0;
 719 }
 720
 721 /*
 722  * Submit next transfer for PDC.
 723  * lock is held, spi irq is blocked
 724  */
 725 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
 726                                         struct spi_message *msg,
 727                                         struct spi_transfer *xfer)
 728 {
 729         struct atmel_spi        *as = spi_master_get_devdata(master);
 730         u32                     len;
 731         dma_addr_t              tx_dma, rx_dma;
 732
 733         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 734
 735         len = as->current_remaining_bytes;
 736         atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 737         as->current_remaining_bytes -= len;
 738
 739         spi_writel(as, RPR, rx_dma);
 740         spi_writel(as, TPR, tx_dma);
 741
 742         if (msg->spi->bits_per_word > 8)
 743                 len >>= 1;
 744         spi_writel(as, RCR, len);
 745         spi_writel(as, TCR, len);
 746
 747         dev_dbg(&msg->spi->dev,
 748                 "  start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 749                 xfer, xfer->len, xfer->tx_buf,
 750                 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 751                 (unsigned long long)xfer->rx_dma);
 752
 753         if (as->current_remaining_bytes) {
 754                 len = as->current_remaining_bytes;
 755                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 756                 as->current_remaining_bytes -= len;
 757
 758                 spi_writel(as, RNPR, rx_dma);
 759                 spi_writel(as, TNPR, tx_dma);
 760
 761                 if (msg->spi->bits_per_word > 8)
 762                         len >>= 1;
 763                 spi_writel(as, RNCR, len);
 764                 spi_writel(as, TNCR, len);
 765
 766                 dev_dbg(&msg->spi->dev,
 767                         "  next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 768                         xfer, xfer->len, xfer->tx_buf,
 769                         (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 770                         (unsigned long long)xfer->rx_dma);
 771         }
 772
 773         /* REVISIT: We're waiting for RXBUFF before we start the next
 774          * transfer because we need to handle some difficult timing
 775          * issues otherwise. If we wait for TXBUFE in one transfer and
 776          * then starts waiting for RXBUFF in the next, it's difficult
 777          * to tell the difference between the RXBUFF interrupt we're
 778          * actually waiting for and the RXBUFF interrupt of the
 779          * previous transfer.
 780          *
 781          * It should be doable, though. Just not now...
 782          */
 783         spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
 784         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 785 }
 786
 787 /*
 788  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 789  *  - The buffer is either valid for CPU access, else NULL
 790  *  - If the buffer is valid, so is its DMA address
 791  *
 792  * This driver manages the dma address unless message->is_dma_mapped.
 793  */
 794 static int
 795 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 796 {
 797         struct device   *dev = &as->pdev->dev;
 798
 799         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 800         if (xfer->tx_buf) {
 801                 /* tx_buf is a const void* where we need a void * for the dma
 802                  * mapping */
 803                 void *nonconst_tx = (void *)xfer->tx_buf;
 804
 805                 xfer->tx_dma = dma_map_single(dev,
 806                                 nonconst_tx, xfer->len,
 807                                 DMA_TO_DEVICE);
 808                 if (dma_mapping_error(dev, xfer->tx_dma))
 809                         return -ENOMEM;
 810         }
 811         if (xfer->rx_buf) {
 812                 xfer->rx_dma = dma_map_single(dev,
 813                                 xfer->rx_buf, xfer->len,
 814                                 DMA_FROM_DEVICE);
 815                 if (dma_mapping_error(dev, xfer->rx_dma)) {
 816                         if (xfer->tx_buf)
 817                                 dma_unmap_single(dev,
 818                                                 xfer->tx_dma, xfer->len,
 819                                                 DMA_TO_DEVICE);
 820                         return -ENOMEM;
 821                 }
 822         }
 823         return 0;
 824 }
 825
 826 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 827                                      struct spi_transfer *xfer)
 828 {
 829         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 830                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
 831                                  xfer->len, DMA_TO_DEVICE);
 832         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 833                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
 834                                  xfer->len, DMA_FROM_DEVICE);
 835 }
 836
 837 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
 838 {
 839         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 840 }
 841
 842 /* Called from IRQ
 843  *
 844  * Must update "current_remaining_bytes" to keep track of data
 845  * to transfer.
 846  */
 847 static void
 848 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
 849 {
 850         u8              *rxp;
 851         u16             *rxp16;
 852         unsigned long   xfer_pos = xfer->len - as->current_remaining_bytes;
 853
 854         if (xfer->rx_buf) {
 855                 if (xfer->bits_per_word > 8) {
 856                         rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
 857                         *rxp16 = spi_readl(as, RDR);
 858                 } else {
 859                         rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
 860                         *rxp = spi_readl(as, RDR);
 861                 }
 862         } else {
 863                 spi_readl(as, RDR);
 864         }
 865         if (xfer->bits_per_word > 8) {
 866                 if (as->current_remaining_bytes > 2)
 867                         as->current_remaining_bytes -= 2;
 868                 else
 869                         as->current_remaining_bytes = 0;
 870         } else {
 871                 as->current_remaining_bytes--;
 872         }
 873 }
 874
 875 /* Interrupt
 876  *
 877  * No need for locking in this Interrupt handler: done_status is the
 878  * only information modified.
 879  */
 880 static irqreturn_t
 881 atmel_spi_pio_interrupt(int irq, void *dev_id)
 882 {
 883         struct spi_master       *master = dev_id;
 884         struct atmel_spi        *as = spi_master_get_devdata(master);
 885         u32                     status, pending, imr;
 886         struct spi_transfer     *xfer;
 887         int                     ret = IRQ_NONE;
 888
 889         imr = spi_readl(as, IMR);
 890         status = spi_readl(as, SR);
 891         pending = status & imr;
 892
 893         if (pending & SPI_BIT(OVRES)) {
 894                 ret = IRQ_HANDLED;
 895                 spi_writel(as, IDR, SPI_BIT(OVRES));
 896                 dev_warn(master->dev.parent, "overrun\n");
 897
 898                 /*
 899                  * When we get an overrun, we disregard the current
 900                  * transfer. Data will not be copied back from any
 901                  * bounce buffer and msg->actual_len will not be
 902                  * updated with the last xfer.
 903                  *
 904                  * We will also not process any remaning transfers in
 905                  * the message.
 906                  */
 907                 as->done_status = -EIO;
 908                 smp_wmb();
 909
 910                 /* Clear any overrun happening while cleaning up */
 911                 spi_readl(as, SR);
 912
 913                 complete(&as->xfer_completion);
 914
 915         } else if (pending & SPI_BIT(RDRF)) {
 916                 atmel_spi_lock(as);
 917
 918                 if (as->current_remaining_bytes) {
 919                         ret = IRQ_HANDLED;
 920                         xfer = as->current_transfer;
 921                         atmel_spi_pump_pio_data(as, xfer);
 922                         if (!as->current_remaining_bytes)
 923                                 spi_writel(as, IDR, pending);
 924
 925                         complete(&as->xfer_completion);
 926                 }
 927
 928                 atmel_spi_unlock(as);
 929         } else {
 930                 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
 931                 ret = IRQ_HANDLED;
 932                 spi_writel(as, IDR, pending);
 933         }
 934
 935         return ret;
 936 }
 937
 938 static irqreturn_t
 939 atmel_spi_pdc_interrupt(int irq, void *dev_id)
 940 {
 941         struct spi_master       *master = dev_id;
 942         struct atmel_spi        *as = spi_master_get_devdata(master);
 943         u32                     status, pending, imr;
 944         int                     ret = IRQ_NONE;
 945
 946         imr = spi_readl(as, IMR);
 947         status = spi_readl(as, SR);
 948         pending = status & imr;
 949
 950         if (pending & SPI_BIT(OVRES)) {
 951
 952                 ret = IRQ_HANDLED;
 953
 954                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
 955                                      | SPI_BIT(OVRES)));
 956
 957                 /* Clear any overrun happening while cleaning up */
 958                 spi_readl(as, SR);
 959
 960                 as->done_status = -EIO;
 961
 962                 complete(&as->xfer_completion);
 963
 964         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
 965                 ret = IRQ_HANDLED;
 966
 967                 spi_writel(as, IDR, pending);
 968
 969                 complete(&as->xfer_completion);
 970         }
 971
 972         return ret;
 973 }
 974
 975 static int atmel_spi_setup(struct spi_device *spi)
 976 {
 977         struct atmel_spi        *as;
 978         struct atmel_spi_device *asd;
 979         u32                     csr;
 980         unsigned int            bits = spi->bits_per_word;
 981         unsigned int            npcs_pin;
 982         int                     ret;
 983
 984         as = spi_master_get_devdata(spi->master);
 985
 986         /* see notes above re chipselect */
 987         if (!atmel_spi_is_v2(as)
 988                         && spi->chip_select == 0
 989                         && (spi->mode & SPI_CS_HIGH)) {
 990                 dev_dbg(&spi->dev, "setup: can't be active-high\n");
 991                 return -EINVAL;
 992         }
 993
 994         csr = SPI_BF(BITS, bits - 8);
 995         if (spi->mode & SPI_CPOL)
 996                 csr |= SPI_BIT(CPOL);
 997         if (!(spi->mode & SPI_CPHA))
 998                 csr |= SPI_BIT(NCPHA);
 999
1000         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1001          *
1002          * DLYBCT would add delays between words, slowing down transfers.
1003          * It could potentially be useful to cope with DMA bottlenecks, but
1004          * in those cases it's probably best to just use a lower bitrate.
1005          */
1006         csr |= SPI_BF(DLYBS, 0);
1007         csr |= SPI_BF(DLYBCT, 0);
1008
1009         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1010         npcs_pin = (unsigned long)spi->controller_data;
1011
1012         if (gpio_is_valid(spi->cs_gpio))
1013                 npcs_pin = spi->cs_gpio;
1014
1015         asd = spi->controller_state;
1016         if (!asd) {
1017                 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1018                 if (!asd)
1019                         return -ENOMEM;
1020
1021                 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1022                 if (ret) {
1023                         kfree(asd);
1024                         return ret;
1025                 }
1026
1027                 asd->npcs_pin = npcs_pin;
1028                 spi->controller_state = asd;
1029                 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
1030         }
1031
1032         asd->csr = csr;
1033
1034         dev_dbg(&spi->dev,
1035                 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1036                 bits, spi->mode, spi->chip_select, csr);
1037
1038         if (!atmel_spi_is_v2(as))
1039                 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1040
1041         return 0;
1042 }
1043
1044 static int atmel_spi_one_transfer(struct spi_master *master,
1045                                         struct spi_message *msg,
1046                                         struct spi_transfer *xfer)
1047 {
1048         struct atmel_spi        *as;
1049         struct spi_device       *spi = msg->spi;
1050         u8                      bits;
1051         u32                     len;
1052         struct atmel_spi_device *asd;
1053         int                     timeout;
1054         int                     ret;
1055         unsigned long           dma_timeout;
1056
1057         as = spi_master_get_devdata(master);
1058
1059         if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1060                 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1061                 return -EINVAL;
1062         }
1063
1064         if (xfer->bits_per_word) {
1065                 asd = spi->controller_state;
1066                 bits = (asd->csr >> 4) & 0xf;
1067                 if (bits != xfer->bits_per_word - 8) {
1068                         dev_dbg(&spi->dev,
1069                         "you can't yet change bits_per_word in transfers\n");
1070                         return -ENOPROTOOPT;
1071                 }
1072         }
1073
1074         /*
1075          * DMA map early, for performance (empties dcache ASAP) and
1076          * better fault reporting.
1077          */
1078         if ((!msg->is_dma_mapped)
1079                 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1080                 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1081                         return -ENOMEM;
1082         }
1083
1084         atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1085
1086         as->done_status = 0;
1087         as->current_transfer = xfer;
1088         as->current_remaining_bytes = xfer->len;
1089         while (as->current_remaining_bytes) {
1090                 reinit_completion(&as->xfer_completion);
1091
1092                 if (as->use_pdc) {
1093                         atmel_spi_pdc_next_xfer(master, msg, xfer);
1094                 } else if (atmel_spi_use_dma(as, xfer)) {
1095                         len = as->current_remaining_bytes;
1096                         ret = atmel_spi_next_xfer_dma_submit(master,
1097                                                                 xfer, &len);
1098                         if (ret) {
1099                                 dev_err(&spi->dev,
1100                                         "unable to use DMA, fallback to PIO\n");
1101                                 atmel_spi_next_xfer_pio(master, xfer);
1102                         } else {
1103                                 as->current_remaining_bytes -= len;
1104                                 if (as->current_remaining_bytes < 0)
1105                                         as->current_remaining_bytes = 0;
1106                         }
1107                 } else {
1108                         atmel_spi_next_xfer_pio(master, xfer);
1109                 }
1110
1111                 /* interrupts are disabled, so free the lock for schedule */
1112                 atmel_spi_unlock(as);
1113                 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1114                                                           SPI_DMA_TIMEOUT);
1115                 atmel_spi_lock(as);
1116                 if (WARN_ON(dma_timeout == 0)) {
1117                         dev_err(&spi->dev, "spi transfer timeout\n");
1118                         as->done_status = -EIO;
1119                 }
1120
1121                 if (as->done_status)
1122                         break;
1123         }
1124
1125         if (as->done_status) {
1126                 if (as->use_pdc) {
1127                         dev_warn(master->dev.parent,
1128                                 "overrun (%u/%u remaining)\n",
1129                                 spi_readl(as, TCR), spi_readl(as, RCR));
1130
1131                         /*
1132                          * Clean up DMA registers and make sure the data
1133                          * registers are empty.
1134                          */
1135                         spi_writel(as, RNCR, 0);
1136                         spi_writel(as, TNCR, 0);
1137                         spi_writel(as, RCR, 0);
1138                         spi_writel(as, TCR, 0);
1139                         for (timeout = 1000; timeout; timeout--)
1140                                 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1141                                         break;
1142                         if (!timeout)
1143                                 dev_warn(master->dev.parent,
1144                                          "timeout waiting for TXEMPTY");
1145                         while (spi_readl(as, SR) & SPI_BIT(RDRF))
1146                                 spi_readl(as, RDR);
1147
1148                         /* Clear any overrun happening while cleaning up */
1149                         spi_readl(as, SR);
1150
1151                 } else if (atmel_spi_use_dma(as, xfer)) {
1152                         atmel_spi_stop_dma(as);
1153                 }
1154
1155                 if (!msg->is_dma_mapped
1156                         && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1157                         atmel_spi_dma_unmap_xfer(master, xfer);
1158
1159                 return 0;
1160
1161         } else {
1162                 /* only update length if no error */
1163                 msg->actual_length += xfer->len;
1164         }
1165
1166         if (!msg->is_dma_mapped
1167                 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1168                 atmel_spi_dma_unmap_xfer(master, xfer);
1169
1170         if (xfer->delay_usecs)
1171                 udelay(xfer->delay_usecs);
1172
1173         if (xfer->cs_change) {
1174                 if (list_is_last(&xfer->transfer_list,
1175                                  &msg->transfers)) {
1176                         as->keep_cs = true;
1177                 } else {
1178                         as->cs_active = !as->cs_active;
1179                         if (as->cs_active)
1180                                 cs_activate(as, msg->spi);
1181                         else
1182                                 cs_deactivate(as, msg->spi);
1183                 }
1184         }
1185
1186         return 0;
1187 }
1188
1189 static int atmel_spi_transfer_one_message(struct spi_master *master,
1190                                                 struct spi_message *msg)
1191 {
1192         struct atmel_spi *as;
1193         struct spi_transfer *xfer;
1194         struct spi_device *spi = msg->spi;
1195         int ret = 0;
1196
1197         as = spi_master_get_devdata(master);
1198
1199         dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1200                                         msg, dev_name(&spi->dev));
1201
1202         atmel_spi_lock(as);
1203         cs_activate(as, spi);
1204
1205         as->cs_active = true;
1206         as->keep_cs = false;
1207
1208         msg->status = 0;
1209         msg->actual_length = 0;
1210
1211         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1212                 ret = atmel_spi_one_transfer(master, msg, xfer);
1213                 if (ret)
1214                         goto msg_done;
1215         }
1216
1217         if (as->use_pdc)
1218                 atmel_spi_disable_pdc_transfer(as);
1219
1220         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1221                 dev_dbg(&spi->dev,
1222                         "  xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1223                         xfer, xfer->len,
1224                         xfer->tx_buf, &xfer->tx_dma,
1225                         xfer->rx_buf, &xfer->rx_dma);
1226         }
1227
1228 msg_done:
1229         if (!as->keep_cs)
1230                 cs_deactivate(as, msg->spi);
1231
1232         atmel_spi_unlock(as);
1233
1234         msg->status = as->done_status;
1235         spi_finalize_current_message(spi->master);
1236
1237         return ret;
1238 }
1239
1240 static void atmel_spi_cleanup(struct spi_device *spi)
1241 {
1242         struct atmel_spi_device *asd = spi->controller_state;
1243         unsigned                gpio = (unsigned long) spi->controller_data;
1244
1245         if (!asd)
1246                 return;
1247
1248         spi->controller_state = NULL;
1249         gpio_free(gpio);
1250         kfree(asd);
1251 }
1252
1253 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1254 {
1255         return spi_readl(as, VERSION) & 0x00000fff;
1256 }
1257
1258 static void atmel_get_caps(struct atmel_spi *as)
1259 {
1260         unsigned int version;
1261
1262         version = atmel_get_version(as);
1263         dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1264
1265         as->caps.is_spi2 = version > 0x121;
1266         as->caps.has_wdrbt = version >= 0x210;
1267         as->caps.has_dma_support = version >= 0x212;
1268 }
1269
1270 /*-------------------------------------------------------------------------*/
1271
1272 static int atmel_spi_probe(struct platform_device *pdev)
1273 {
1274         struct resource         *regs;
1275         int                     irq;
1276         struct clk              *clk;
1277         int                     ret;
1278         struct spi_master       *master;
1279         struct atmel_spi        *as;
1280
1281         /* Select default pin state */
1282         pinctrl_pm_select_default_state(&pdev->dev);
1283
1284         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1285         if (!regs)
1286                 return -ENXIO;
1287
1288         irq = platform_get_irq(pdev, 0);
1289         if (irq < 0)
1290                 return irq;
1291
1292         clk = devm_clk_get(&pdev->dev, "spi_clk");
1293         if (IS_ERR(clk))
1294                 return PTR_ERR(clk);
1295
1296         /* setup spi core then atmel-specific driver state */
1297         ret = -ENOMEM;
1298         master = spi_alloc_master(&pdev->dev, sizeof(*as));
1299         if (!master)
1300                 goto out_free;
1301
1302         /* the spi->mode bits understood by this driver: */
1303         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1304         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1305         master->dev.of_node = pdev->dev.of_node;
1306         master->bus_num = pdev->id;
1307         master->num_chipselect = master->dev.of_node ? 0 : 4;
1308         master->setup = atmel_spi_setup;
1309         master->transfer_one_message = atmel_spi_transfer_one_message;
1310         master->cleanup = atmel_spi_cleanup;
1311         master->auto_runtime_pm = true;
1312         platform_set_drvdata(pdev, master);
1313
1314         as = spi_master_get_devdata(master);
1315
1316         /*
1317          * Scratch buffer is used for throwaway rx and tx data.
1318          * It's coherent to minimize dcache pollution.
1319          */
1320         as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1321                                         &as->buffer_dma, GFP_KERNEL);
1322         if (!as->buffer)
1323                 goto out_free;
1324
1325         spin_lock_init(&as->lock);
1326
1327         as->pdev = pdev;
1328         as->regs = devm_ioremap_resource(&pdev->dev, regs);
1329         if (IS_ERR(as->regs)) {
1330                 ret = PTR_ERR(as->regs);
1331                 goto out_free_buffer;
1332         }
1333         as->phybase = regs->start;
1334         as->irq = irq;
1335         as->clk = clk;
1336
1337         init_completion(&as->xfer_completion);
1338
1339         atmel_get_caps(as);
1340
1341         as->use_dma = false;
1342         as->use_pdc = false;
1343         if (as->caps.has_dma_support) {
1344                 ret = atmel_spi_configure_dma(as);
1345                 if (ret == 0)
1346                         as->use_dma = true;
1347                 else if (ret == -EPROBE_DEFER)
1348                         return ret;
1349         } else {
1350                 as->use_pdc = true;
1351         }
1352
1353         if (as->caps.has_dma_support && !as->use_dma)
1354                 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1355
1356         if (as->use_pdc) {
1357                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1358                                         0, dev_name(&pdev->dev), master);
1359         } else {
1360                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1361                                         0, dev_name(&pdev->dev), master);
1362         }
1363         if (ret)
1364                 goto out_unmap_regs;
1365
1366         /* Initialize the hardware */
1367         ret = clk_prepare_enable(clk);
1368         if (ret)
1369                 goto out_free_irq;
1370         spi_writel(as, CR, SPI_BIT(SWRST));
1371         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1372         if (as->caps.has_wdrbt) {
1373                 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1374                                 | SPI_BIT(MSTR));
1375         } else {
1376                 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1377         }
1378
1379         if (as->use_pdc)
1380                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1381         spi_writel(as, CR, SPI_BIT(SPIEN));
1382
1383         /* go! */
1384         dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1385                         (unsigned long)regs->start, irq);
1386
1387         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1388         pm_runtime_use_autosuspend(&pdev->dev);
1389         pm_runtime_set_active(&pdev->dev);
1390         pm_runtime_enable(&pdev->dev);
1391
1392         ret = devm_spi_register_master(&pdev->dev, master);
1393         if (ret)
1394                 goto out_free_dma;
1395
1396         return 0;
1397
1398 out_free_dma:
1399         pm_runtime_disable(&pdev->dev);
1400         pm_runtime_set_suspended(&pdev->dev);
1401
1402         if (as->use_dma)
1403                 atmel_spi_release_dma(as);
1404
1405         spi_writel(as, CR, SPI_BIT(SWRST));
1406         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1407         clk_disable_unprepare(clk);
1408 out_free_irq:
1409 out_unmap_regs:
1410 out_free_buffer:
1411         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1412                         as->buffer_dma);
1413 out_free:
1414         spi_master_put(master);
1415         return ret;
1416 }
1417
1418 static int atmel_spi_remove(struct platform_device *pdev)
1419 {
1420         struct spi_master       *master = platform_get_drvdata(pdev);
1421         struct atmel_spi        *as = spi_master_get_devdata(master);
1422
1423         pm_runtime_get_sync(&pdev->dev);
1424
1425         /* reset the hardware and block queue progress */
1426         spin_lock_irq(&as->lock);
1427         if (as->use_dma) {
1428                 atmel_spi_stop_dma(as);
1429                 atmel_spi_release_dma(as);
1430         }
1431
1432         spi_writel(as, CR, SPI_BIT(SWRST));
1433         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1434         spi_readl(as, SR);
1435         spin_unlock_irq(&as->lock);
1436
1437         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1438                         as->buffer_dma);
1439
1440         clk_disable_unprepare(as->clk);
1441
1442         pm_runtime_put_noidle(&pdev->dev);
1443         pm_runtime_disable(&pdev->dev);
1444
1445         return 0;
1446 }
1447
1448 #ifdef CONFIG_PM
1449 static int atmel_spi_runtime_suspend(struct device *dev)
1450 {
1451         struct spi_master *master = dev_get_drvdata(dev);
1452         struct atmel_spi *as = spi_master_get_devdata(master);
1453
1454         clk_disable_unprepare(as->clk);
1455         pinctrl_pm_select_sleep_state(dev);
1456
1457         return 0;
1458 }
1459
1460 static int atmel_spi_runtime_resume(struct device *dev)
1461 {
1462         struct spi_master *master = dev_get_drvdata(dev);
1463         struct atmel_spi *as = spi_master_get_devdata(master);
1464
1465         pinctrl_pm_select_default_state(dev);
1466
1467         return clk_prepare_enable(as->clk);
1468 }
1469
1470 static int atmel_spi_suspend(struct device *dev)
1471 {
1472         struct spi_master *master = dev_get_drvdata(dev);
1473         int ret;
1474
1475         /* Stop the queue running */
1476         ret = spi_master_suspend(master);
1477         if (ret) {
1478                 dev_warn(dev, "cannot suspend master\n");
1479                 return ret;
1480         }
1481
1482         if (!pm_runtime_suspended(dev))
1483                 atmel_spi_runtime_suspend(dev);
1484
1485         return 0;
1486 }
1487
1488 static int atmel_spi_resume(struct device *dev)
1489 {
1490         struct spi_master *master = dev_get_drvdata(dev);
1491         int ret;
1492
1493         if (!pm_runtime_suspended(dev)) {
1494                 ret = atmel_spi_runtime_resume(dev);
1495                 if (ret)
1496                         return ret;
1497         }
1498
1499         /* Start the queue running */
1500         ret = spi_master_resume(master);
1501         if (ret)
1502                 dev_err(dev, "problem starting queue (%d)\n", ret);
1503
1504         return ret;
1505 }
1506
1507 static const struct dev_pm_ops atmel_spi_pm_ops = {
1508         SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1509         SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1510                            atmel_spi_runtime_resume, NULL)
1511 };
1512 #define ATMEL_SPI_PM_OPS        (&atmel_spi_pm_ops)
1513 #else
1514 #define ATMEL_SPI_PM_OPS        NULL
1515 #endif
1516
1517 #if defined(CONFIG_OF)
1518 static const struct of_device_id atmel_spi_dt_ids[] = {
1519         { .compatible = "atmel,at91rm9200-spi" },
1520         { /* sentinel */ }
1521 };
1522
1523 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1524 #endif
1525
1526 static struct platform_driver atmel_spi_driver = {
1527         .driver         = {
1528                 .name   = "atmel_spi",
1529                 .pm     = ATMEL_SPI_PM_OPS,
1530                 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1531         },
1532         .probe          = atmel_spi_probe,
1533         .remove         = atmel_spi_remove,
1534 };
1535 module_platform_driver(atmel_spi_driver);
1536
1537 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1538 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1539 MODULE_LICENSE("GPL");
1540 MODULE_ALIAS("platform:atmel_spi");