kernel/drivers/scsi/ufs/ufs-qcom.c

   1 /*
   2  * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/time.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/phy/phy.h>
  19
  20 #include <linux/phy/phy-qcom-ufs.h>
  21 #include "ufshcd.h"
  22 #include "unipro.h"
  23 #include "ufs-qcom.h"
  24 #include "ufshci.h"
  25
  26 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
  27
  28 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result);
  29 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
  30                 const char *speed_mode);
  31 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
  32
  33 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
  34 {
  35         int err = 0;
  36
  37         err = ufshcd_dme_get(hba,
  38                         UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
  39         if (err)
  40                 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
  41                                 __func__, err);
  42
  43         return err;
  44 }
  45
  46 static int ufs_qcom_host_clk_get(struct device *dev,
  47                 const char *name, struct clk **clk_out)
  48 {
  49         struct clk *clk;
  50         int err = 0;
  51
  52         clk = devm_clk_get(dev, name);
  53         if (IS_ERR(clk)) {
  54                 err = PTR_ERR(clk);
  55                 dev_err(dev, "%s: failed to get %s err %d",
  56                                 __func__, name, err);
  57         } else {
  58                 *clk_out = clk;
  59         }
  60
  61         return err;
  62 }
  63
  64 static int ufs_qcom_host_clk_enable(struct device *dev,
  65                 const char *name, struct clk *clk)
  66 {
  67         int err = 0;
  68
  69         err = clk_prepare_enable(clk);
  70         if (err)
  71                 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
  72
  73         return err;
  74 }
  75
  76 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
  77 {
  78         if (!host->is_lane_clks_enabled)
  79                 return;
  80
  81         clk_disable_unprepare(host->tx_l1_sync_clk);
  82         clk_disable_unprepare(host->tx_l0_sync_clk);
  83         clk_disable_unprepare(host->rx_l1_sync_clk);
  84         clk_disable_unprepare(host->rx_l0_sync_clk);
  85
  86         host->is_lane_clks_enabled = false;
  87 }
  88
  89 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
  90 {
  91         int err = 0;
  92         struct device *dev = host->hba->dev;
  93
  94         if (host->is_lane_clks_enabled)
  95                 return 0;
  96
  97         err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
  98                 host->rx_l0_sync_clk);
  99         if (err)
 100                 goto out;
 101
 102         err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
 103                 host->tx_l0_sync_clk);
 104         if (err)
 105                 goto disable_rx_l0;
 106
 107         err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
 108                 host->rx_l1_sync_clk);
 109         if (err)
 110                 goto disable_tx_l0;
 111
 112         err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
 113                 host->tx_l1_sync_clk);
 114         if (err)
 115                 goto disable_rx_l1;
 116
 117         host->is_lane_clks_enabled = true;
 118         goto out;
 119
 120 disable_rx_l1:
 121         clk_disable_unprepare(host->rx_l1_sync_clk);
 122 disable_tx_l0:
 123         clk_disable_unprepare(host->tx_l0_sync_clk);
 124 disable_rx_l0:
 125         clk_disable_unprepare(host->rx_l0_sync_clk);
 126 out:
 127         return err;
 128 }
 129
 130 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
 131 {
 132         int err = 0;
 133         struct device *dev = host->hba->dev;
 134
 135         err = ufs_qcom_host_clk_get(dev,
 136                         "rx_lane0_sync_clk", &host->rx_l0_sync_clk);
 137         if (err)
 138                 goto out;
 139
 140         err = ufs_qcom_host_clk_get(dev,
 141                         "tx_lane0_sync_clk", &host->tx_l0_sync_clk);
 142         if (err)
 143                 goto out;
 144
 145         err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
 146                 &host->rx_l1_sync_clk);
 147         if (err)
 148                 goto out;
 149
 150         err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
 151                 &host->tx_l1_sync_clk);
 152 out:
 153         return err;
 154 }
 155
 156 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
 157 {
 158         struct ufs_qcom_host *host = hba->priv;
 159         struct phy *phy = host->generic_phy;
 160         u32 tx_lanes;
 161         int err = 0;
 162
 163         err = ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
 164         if (err)
 165                 goto out;
 166
 167         err = ufs_qcom_phy_set_tx_lane_enable(phy, tx_lanes);
 168         if (err)
 169                 dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable failed\n",
 170                         __func__);
 171
 172 out:
 173         return err;
 174 }
 175
 176 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
 177 {
 178         int err;
 179         u32 tx_fsm_val = 0;
 180         unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
 181
 182         do {
 183                 err = ufshcd_dme_get(hba,
 184                         UIC_ARG_MIB(MPHY_TX_FSM_STATE), &tx_fsm_val);
 185                 if (err || tx_fsm_val == TX_FSM_HIBERN8)
 186                         break;
 187
 188                 /* sleep for max. 200us */
 189                 usleep_range(100, 200);
 190         } while (time_before(jiffies, timeout));
 191
 192         /*
 193          * we might have scheduled out for long during polling so
 194          * check the state again.
 195          */
 196         if (time_after(jiffies, timeout))
 197                 err = ufshcd_dme_get(hba,
 198                                 UIC_ARG_MIB(MPHY_TX_FSM_STATE), &tx_fsm_val);
 199
 200         if (err) {
 201                 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
 202                                 __func__, err);
 203         } else if (tx_fsm_val != TX_FSM_HIBERN8) {
 204                 err = tx_fsm_val;
 205                 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
 206                                 __func__, err);
 207         }
 208
 209         return err;
 210 }
 211
 212 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 213 {
 214         struct ufs_qcom_host *host = hba->priv;
 215         struct phy *phy = host->generic_phy;
 216         int ret = 0;
 217         bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
 218                                                         ? true : false;
 219
 220         /* Assert PHY reset and apply PHY calibration values */
 221         ufs_qcom_assert_reset(hba);
 222         /* provide 1ms delay to let the reset pulse propagate */
 223         usleep_range(1000, 1100);
 224
 225         ret = ufs_qcom_phy_calibrate_phy(phy, is_rate_B);
 226         if (ret) {
 227                 dev_err(hba->dev, "%s: ufs_qcom_phy_calibrate_phy() failed, ret = %d\n",
 228                         __func__, ret);
 229                 goto out;
 230         }
 231
 232         /* De-assert PHY reset and start serdes */
 233         ufs_qcom_deassert_reset(hba);
 234
 235         /*
 236          * after reset deassertion, phy will need all ref clocks,
 237          * voltage, current to settle down before starting serdes.
 238          */
 239         usleep_range(1000, 1100);
 240         ret = ufs_qcom_phy_start_serdes(phy);
 241         if (ret) {
 242                 dev_err(hba->dev, "%s: ufs_qcom_phy_start_serdes() failed, ret = %d\n",
 243                         __func__, ret);
 244                 goto out;
 245         }
 246
 247         ret = ufs_qcom_phy_is_pcs_ready(phy);
 248         if (ret)
 249                 dev_err(hba->dev, "%s: is_physical_coding_sublayer_ready() failed, ret = %d\n",
 250                         __func__, ret);
 251
 252 out:
 253         return ret;
 254 }
 255
 256 /*
 257  * The UTP controller has a number of internal clock gating cells (CGCs).
 258  * Internal hardware sub-modules within the UTP controller control the CGCs.
 259  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
 260  * in a specific operation, UTP controller CGCs are by default disabled and
 261  * this function enables them (after every UFS link startup) to save some power
 262  * leakage.
 263  */
 264 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
 265 {
 266         ufshcd_writel(hba,
 267                 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
 268                 REG_UFS_CFG2);
 269
 270         /* Ensure that HW clock gating is enabled before next operations */
 271         mb();
 272 }
 273
 274 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, bool status)
 275 {
 276         struct ufs_qcom_host *host = hba->priv;
 277         int err = 0;
 278
 279         switch (status) {
 280         case PRE_CHANGE:
 281                 ufs_qcom_power_up_sequence(hba);
 282                 /*
 283                  * The PHY PLL output is the source of tx/rx lane symbol
 284                  * clocks, hence, enable the lane clocks only after PHY
 285                  * is initialized.
 286                  */
 287                 err = ufs_qcom_enable_lane_clks(host);
 288                 break;
 289         case POST_CHANGE:
 290                 /* check if UFS PHY moved from DISABLED to HIBERN8 */
 291                 err = ufs_qcom_check_hibern8(hba);
 292                 ufs_qcom_enable_hw_clk_gating(hba);
 293
 294                 break;
 295         default:
 296                 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
 297                 err = -EINVAL;
 298                 break;
 299         }
 300         return err;
 301 }
 302
 303 /**
 304  * Returns non-zero for success (which rate of core_clk) and 0
 305  * in case of a failure
 306  */
 307 static unsigned long
 308 ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate)
 309 {
 310         struct ufs_clk_info *clki;
 311         u32 core_clk_period_in_ns;
 312         u32 tx_clk_cycles_per_us = 0;
 313         unsigned long core_clk_rate = 0;
 314         u32 core_clk_cycles_per_us = 0;
 315
 316         static u32 pwm_fr_table[][2] = {
 317                 {UFS_PWM_G1, 0x1},
 318                 {UFS_PWM_G2, 0x1},
 319                 {UFS_PWM_G3, 0x1},
 320                 {UFS_PWM_G4, 0x1},
 321         };
 322
 323         static u32 hs_fr_table_rA[][2] = {
 324                 {UFS_HS_G1, 0x1F},
 325                 {UFS_HS_G2, 0x3e},
 326         };
 327
 328         static u32 hs_fr_table_rB[][2] = {
 329                 {UFS_HS_G1, 0x24},
 330                 {UFS_HS_G2, 0x49},
 331         };
 332
 333         if (gear == 0) {
 334                 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
 335                 goto out_error;
 336         }
 337
 338         list_for_each_entry(clki, &hba->clk_list_head, list) {
 339                 if (!strcmp(clki->name, "core_clk"))
 340                         core_clk_rate = clk_get_rate(clki->clk);
 341         }
 342
 343         /* If frequency is smaller than 1MHz, set to 1MHz */
 344         if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
 345                 core_clk_rate = DEFAULT_CLK_RATE_HZ;
 346
 347         core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
 348         ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
 349
 350         core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
 351         core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
 352         core_clk_period_in_ns &= MASK_CLK_NS_REG;
 353
 354         switch (hs) {
 355         case FASTAUTO_MODE:
 356         case FAST_MODE:
 357                 if (rate == PA_HS_MODE_A) {
 358                         if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
 359                                 dev_err(hba->dev,
 360                                         "%s: index %d exceeds table size %zu\n",
 361                                         __func__, gear,
 362                                         ARRAY_SIZE(hs_fr_table_rA));
 363                                 goto out_error;
 364                         }
 365                         tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
 366                 } else if (rate == PA_HS_MODE_B) {
 367                         if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
 368                                 dev_err(hba->dev,
 369                                         "%s: index %d exceeds table size %zu\n",
 370                                         __func__, gear,
 371                                         ARRAY_SIZE(hs_fr_table_rB));
 372                                 goto out_error;
 373                         }
 374                         tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
 375                 } else {
 376                         dev_err(hba->dev, "%s: invalid rate = %d\n",
 377                                 __func__, rate);
 378                         goto out_error;
 379                 }
 380                 break;
 381         case SLOWAUTO_MODE:
 382         case SLOW_MODE:
 383                 if (gear > ARRAY_SIZE(pwm_fr_table)) {
 384                         dev_err(hba->dev,
 385                                         "%s: index %d exceeds table size %zu\n",
 386                                         __func__, gear,
 387                                         ARRAY_SIZE(pwm_fr_table));
 388                         goto out_error;
 389                 }
 390                 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
 391                 break;
 392         case UNCHANGED:
 393         default:
 394                 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
 395                 goto out_error;
 396         }
 397
 398         /* this register 2 fields shall be written at once */
 399         ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
 400                                                 REG_UFS_TX_SYMBOL_CLK_NS_US);
 401         goto out;
 402
 403 out_error:
 404         core_clk_rate = 0;
 405 out:
 406         return core_clk_rate;
 407 }
 408
 409 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, bool status)
 410 {
 411         unsigned long core_clk_rate = 0;
 412         u32 core_clk_cycles_per_100ms;
 413
 414         switch (status) {
 415         case PRE_CHANGE:
 416                 core_clk_rate = ufs_qcom_cfg_timers(hba, UFS_PWM_G1,
 417                                                     SLOWAUTO_MODE, 0);
 418                 if (!core_clk_rate) {
 419                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 420                                 __func__);
 421                         return -EINVAL;
 422                 }
 423                 core_clk_cycles_per_100ms =
 424                         (core_clk_rate / MSEC_PER_SEC) * 100;
 425                 ufshcd_writel(hba, core_clk_cycles_per_100ms,
 426                                         REG_UFS_PA_LINK_STARTUP_TIMER);
 427                 break;
 428         case POST_CHANGE:
 429                 ufs_qcom_link_startup_post_change(hba);
 430                 break;
 431         default:
 432                 break;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 439 {
 440         struct ufs_qcom_host *host = hba->priv;
 441         struct phy *phy = host->generic_phy;
 442         int ret = 0;
 443
 444         if (ufs_qcom_is_link_off(hba)) {
 445                 /*
 446                  * Disable the tx/rx lane symbol clocks before PHY is
 447                  * powered down as the PLL source should be disabled
 448                  * after downstream clocks are disabled.
 449                  */
 450                 ufs_qcom_disable_lane_clks(host);
 451                 phy_power_off(phy);
 452
 453                 /* Assert PHY soft reset */
 454                 ufs_qcom_assert_reset(hba);
 455                 goto out;
 456         }
 457
 458         /*
 459          * If UniPro link is not active, PHY ref_clk, main PHY analog power
 460          * rail and low noise analog power rail for PLL can be switched off.
 461          */
 462         if (!ufs_qcom_is_link_active(hba))
 463                 phy_power_off(phy);
 464
 465 out:
 466         return ret;
 467 }
 468
 469 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 470 {
 471         struct ufs_qcom_host *host = hba->priv;
 472         struct phy *phy = host->generic_phy;
 473         int err;
 474
 475         err = phy_power_on(phy);
 476         if (err) {
 477                 dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
 478                         __func__, err);
 479                 goto out;
 480         }
 481
 482         hba->is_sys_suspended = false;
 483
 484 out:
 485         return err;
 486 }
 487
 488 struct ufs_qcom_dev_params {
 489         u32 pwm_rx_gear;        /* pwm rx gear to work in */
 490         u32 pwm_tx_gear;        /* pwm tx gear to work in */
 491         u32 hs_rx_gear;         /* hs rx gear to work in */
 492         u32 hs_tx_gear;         /* hs tx gear to work in */
 493         u32 rx_lanes;           /* number of rx lanes */
 494         u32 tx_lanes;           /* number of tx lanes */
 495         u32 rx_pwr_pwm;         /* rx pwm working pwr */
 496         u32 tx_pwr_pwm;         /* tx pwm working pwr */
 497         u32 rx_pwr_hs;          /* rx hs working pwr */
 498         u32 tx_pwr_hs;          /* tx hs working pwr */
 499         u32 hs_rate;            /* rate A/B to work in HS */
 500         u32 desired_working_mode;
 501 };
 502
 503 static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
 504                                       struct ufs_pa_layer_attr *dev_max,
 505                                       struct ufs_pa_layer_attr *agreed_pwr)
 506 {
 507         int min_qcom_gear;
 508         int min_dev_gear;
 509         bool is_dev_sup_hs = false;
 510         bool is_qcom_max_hs = false;
 511
 512         if (dev_max->pwr_rx == FAST_MODE)
 513                 is_dev_sup_hs = true;
 514
 515         if (qcom_param->desired_working_mode == FAST) {
 516                 is_qcom_max_hs = true;
 517                 min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
 518                                       qcom_param->hs_tx_gear);
 519         } else {
 520                 min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
 521                                       qcom_param->pwm_tx_gear);
 522         }
 523
 524         /*
 525          * device doesn't support HS but qcom_param->desired_working_mode is
 526          * HS, thus device and qcom_param don't agree
 527          */
 528         if (!is_dev_sup_hs && is_qcom_max_hs) {
 529                 pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
 530                         __func__);
 531                 return -ENOTSUPP;
 532         } else if (is_dev_sup_hs && is_qcom_max_hs) {
 533                 /*
 534                  * since device supports HS, it supports FAST_MODE.
 535                  * since qcom_param->desired_working_mode is also HS
 536                  * then final decision (FAST/FASTAUTO) is done according
 537                  * to qcom_params as it is the restricting factor
 538                  */
 539                 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
 540                                                 qcom_param->rx_pwr_hs;
 541         } else {
 542                 /*
 543                  * here qcom_param->desired_working_mode is PWM.
 544                  * it doesn't matter whether device supports HS or PWM,
 545                  * in both cases qcom_param->desired_working_mode will
 546                  * determine the mode
 547                  */
 548                  agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
 549                                                 qcom_param->rx_pwr_pwm;
 550         }
 551
 552         /*
 553          * we would like tx to work in the minimum number of lanes
 554          * between device capability and vendor preferences.
 555          * the same decision will be made for rx
 556          */
 557         agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
 558                                                 qcom_param->tx_lanes);
 559         agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
 560                                                 qcom_param->rx_lanes);
 561
 562         /* device maximum gear is the minimum between device rx and tx gears */
 563         min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
 564
 565         /*
 566          * if both device capabilities and vendor pre-defined preferences are
 567          * both HS or both PWM then set the minimum gear to be the chosen
 568          * working gear.
 569          * if one is PWM and one is HS then the one that is PWM get to decide
 570          * what is the gear, as it is the one that also decided previously what
 571          * pwr the device will be configured to.
 572          */
 573         if ((is_dev_sup_hs && is_qcom_max_hs) ||
 574             (!is_dev_sup_hs && !is_qcom_max_hs))
 575                 agreed_pwr->gear_rx = agreed_pwr->gear_tx =
 576                         min_t(u32, min_dev_gear, min_qcom_gear);
 577         else if (!is_dev_sup_hs)
 578                 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
 579         else
 580                 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
 581
 582         agreed_pwr->hs_rate = qcom_param->hs_rate;
 583         return 0;
 584 }
 585
 586 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 587 {
 588         int vote;
 589         int err = 0;
 590         char mode[BUS_VECTOR_NAME_LEN];
 591
 592         ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
 593
 594         vote = ufs_qcom_get_bus_vote(host, mode);
 595         if (vote >= 0)
 596                 err = ufs_qcom_set_bus_vote(host, vote);
 597         else
 598                 err = vote;
 599
 600         if (err)
 601                 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
 602         else
 603                 host->bus_vote.saved_vote = vote;
 604         return err;
 605 }
 606
 607 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 608                                 bool status,
 609                                 struct ufs_pa_layer_attr *dev_max_params,
 610                                 struct ufs_pa_layer_attr *dev_req_params)
 611 {
 612         u32 val;
 613         struct ufs_qcom_host *host = hba->priv;
 614         struct phy *phy = host->generic_phy;
 615         struct ufs_qcom_dev_params ufs_qcom_cap;
 616         int ret = 0;
 617         int res = 0;
 618
 619         if (!dev_req_params) {
 620                 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
 621                 ret = -EINVAL;
 622                 goto out;
 623         }
 624
 625         switch (status) {
 626         case PRE_CHANGE:
 627                 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
 628                 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
 629                 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
 630                 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
 631                 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
 632                 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
 633                 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
 634                 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
 635                 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
 636                 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
 637                 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
 638                 ufs_qcom_cap.desired_working_mode =
 639                                         UFS_QCOM_LIMIT_DESIRED_MODE;
 640
 641                 ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
 642                                                  dev_max_params,
 643                                                  dev_req_params);
 644                 if (ret) {
 645                         pr_err("%s: failed to determine capabilities\n",
 646                                         __func__);
 647                         goto out;
 648                 }
 649
 650                 break;
 651         case POST_CHANGE:
 652                 if (!ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
 653                                         dev_req_params->pwr_rx,
 654                                         dev_req_params->hs_rate)) {
 655                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 656                                 __func__);
 657                         /*
 658                          * we return error code at the end of the routine,
 659                          * but continue to configure UFS_PHY_TX_LANE_ENABLE
 660                          * and bus voting as usual
 661                          */
 662                         ret = -EINVAL;
 663                 }
 664
 665                 val = ~(MAX_U32 << dev_req_params->lane_tx);
 666                 res = ufs_qcom_phy_set_tx_lane_enable(phy, val);
 667                 if (res) {
 668                         dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable() failed res = %d\n",
 669                                 __func__, res);
 670                         ret = res;
 671                 }
 672
 673                 /* cache the power mode parameters to use internally */
 674                 memcpy(&host->dev_req_params,
 675                                 dev_req_params, sizeof(*dev_req_params));
 676                 ufs_qcom_update_bus_bw_vote(host);
 677                 break;
 678         default:
 679                 ret = -EINVAL;
 680                 break;
 681         }
 682 out:
 683         return ret;
 684 }
 685
 686 /**
 687  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
 688  * @hba: host controller instance
 689  *
 690  * QCOM UFS host controller might have some non standard behaviours (quirks)
 691  * than what is specified by UFSHCI specification. Advertise all such
 692  * quirks to standard UFS host controller driver so standard takes them into
 693  * account.
 694  */
 695 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
 696 {
 697         struct ufs_qcom_host *host = hba->priv;
 698
 699         if (host->hw_ver.major == 0x1)
 700                 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS;
 701
 702         if (host->hw_ver.major >= 0x2) {
 703                 if (!ufs_qcom_cap_qunipro(host))
 704                         /* Legacy UniPro mode still need following quirks */
 705                         hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS;
 706         }
 707 }
 708
 709 static void ufs_qcom_set_caps(struct ufs_hba *hba)
 710 {
 711         struct ufs_qcom_host *host = hba->priv;
 712
 713         if (host->hw_ver.major >= 0x2)
 714                 host->caps = UFS_QCOM_CAP_QUNIPRO;
 715 }
 716
 717 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
 718                 const char *speed_mode)
 719 {
 720         struct device *dev = host->hba->dev;
 721         struct device_node *np = dev->of_node;
 722         int err;
 723         const char *key = "qcom,bus-vector-names";
 724
 725         if (!speed_mode) {
 726                 err = -EINVAL;
 727                 goto out;
 728         }
 729
 730         if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
 731                 err = of_property_match_string(np, key, "MAX");
 732         else
 733                 err = of_property_match_string(np, key, speed_mode);
 734
 735 out:
 736         if (err < 0)
 737                 dev_err(dev, "%s: Invalid %s mode %d\n",
 738                                 __func__, speed_mode, err);
 739         return err;
 740 }
 741
 742 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
 743 {
 744         int err = 0;
 745
 746         if (vote != host->bus_vote.curr_vote)
 747                 host->bus_vote.curr_vote = vote;
 748
 749         return err;
 750 }
 751
 752 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
 753 {
 754         int gear = max_t(u32, p->gear_rx, p->gear_tx);
 755         int lanes = max_t(u32, p->lane_rx, p->lane_tx);
 756         int pwr;
 757
 758         /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
 759         if (!gear)
 760                 gear = 1;
 761
 762         if (!lanes)
 763                 lanes = 1;
 764
 765         if (!p->pwr_rx && !p->pwr_tx) {
 766                 pwr = SLOWAUTO_MODE;
 767                 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
 768         } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
 769                  p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
 770                 pwr = FAST_MODE;
 771                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
 772                          p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
 773         } else {
 774                 pwr = SLOW_MODE;
 775                 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
 776                          "PWM", gear, lanes);
 777         }
 778 }
 779
 780 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on)
 781 {
 782         struct ufs_qcom_host *host = hba->priv;
 783         int err = 0;
 784         int vote = 0;
 785
 786         /*
 787          * In case ufs_qcom_init() is not yet done, simply ignore.
 788          * This ufs_qcom_setup_clocks() shall be called from
 789          * ufs_qcom_init() after init is done.
 790          */
 791         if (!host)
 792                 return 0;
 793
 794         if (on) {
 795                 err = ufs_qcom_phy_enable_iface_clk(host->generic_phy);
 796                 if (err)
 797                         goto out;
 798
 799                 err = ufs_qcom_phy_enable_ref_clk(host->generic_phy);
 800                 if (err) {
 801                         dev_err(hba->dev, "%s enable phy ref clock failed, err=%d\n",
 802                                 __func__, err);
 803                         ufs_qcom_phy_disable_iface_clk(host->generic_phy);
 804                         goto out;
 805                 }
 806                 /* enable the device ref clock */
 807                 ufs_qcom_phy_enable_dev_ref_clk(host->generic_phy);
 808                 vote = host->bus_vote.saved_vote;
 809                 if (vote == host->bus_vote.min_bw_vote)
 810                         ufs_qcom_update_bus_bw_vote(host);
 811         } else {
 812                 /* M-PHY RMMI interface clocks can be turned off */
 813                 ufs_qcom_phy_disable_iface_clk(host->generic_phy);
 814                 if (!ufs_qcom_is_link_active(hba)) {
 815                         /* turn off UFS local PHY ref_clk */
 816                         ufs_qcom_phy_disable_ref_clk(host->generic_phy);
 817                         /* disable device ref_clk */
 818                         ufs_qcom_phy_disable_dev_ref_clk(host->generic_phy);
 819                 }
 820                 vote = host->bus_vote.min_bw_vote;
 821         }
 822
 823         err = ufs_qcom_set_bus_vote(host, vote);
 824         if (err)
 825                 dev_err(hba->dev, "%s: set bus vote failed %d\n",
 826                                 __func__, err);
 827
 828 out:
 829         return err;
 830 }
 831
 832 static ssize_t
 833 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 834                         char *buf)
 835 {
 836         struct ufs_hba *hba = dev_get_drvdata(dev);
 837         struct ufs_qcom_host *host = hba->priv;
 838
 839         return snprintf(buf, PAGE_SIZE, "%u\n",
 840                         host->bus_vote.is_max_bw_needed);
 841 }
 842
 843 static ssize_t
 844 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
 845                 const char *buf, size_t count)
 846 {
 847         struct ufs_hba *hba = dev_get_drvdata(dev);
 848         struct ufs_qcom_host *host = hba->priv;
 849         uint32_t value;
 850
 851         if (!kstrtou32(buf, 0, &value)) {
 852                 host->bus_vote.is_max_bw_needed = !!value;
 853                 ufs_qcom_update_bus_bw_vote(host);
 854         }
 855
 856         return count;
 857 }
 858
 859 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
 860 {
 861         int err;
 862         struct device *dev = host->hba->dev;
 863         struct device_node *np = dev->of_node;
 864
 865         err = of_property_count_strings(np, "qcom,bus-vector-names");
 866         if (err < 0 ) {
 867                 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
 868                                 __func__, err);
 869                 goto out;
 870         }
 871
 872         /* cache the vote index for minimum and maximum bandwidth */
 873         host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
 874         host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
 875
 876         host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
 877         host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
 878         sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
 879         host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
 880         host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
 881         err = device_create_file(dev, &host->bus_vote.max_bus_bw);
 882 out:
 883         return err;
 884 }
 885
 886 #define ANDROID_BOOT_DEV_MAX    30
 887 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
 888 static int get_android_boot_dev(char *str)
 889 {
 890         strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
 891         return 1;
 892 }
 893 __setup("androidboot.bootdevice=", get_android_boot_dev);
 894
 895 /**
 896  * ufs_qcom_init - bind phy with controller
 897  * @hba: host controller instance
 898  *
 899  * Binds PHY with controller and powers up PHY enabling clocks
 900  * and regulators.
 901  *
 902  * Returns -EPROBE_DEFER if binding fails, returns negative error
 903  * on phy power up failure and returns zero on success.
 904  */
 905 static int ufs_qcom_init(struct ufs_hba *hba)
 906 {
 907         int err;
 908         struct device *dev = hba->dev;
 909         struct ufs_qcom_host *host;
 910
 911         if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
 912                 return -ENODEV;
 913
 914         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
 915         if (!host) {
 916                 err = -ENOMEM;
 917                 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
 918                 goto out;
 919         }
 920
 921         host->hba = hba;
 922         hba->priv = (void *)host;
 923
 924         host->generic_phy = devm_phy_get(dev, "ufsphy");
 925
 926         if (IS_ERR(host->generic_phy)) {
 927                 err = PTR_ERR(host->generic_phy);
 928                 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
 929                 goto out;
 930         }
 931
 932         err = ufs_qcom_bus_register(host);
 933         if (err)
 934                 goto out_host_free;
 935
 936         ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
 937                 &host->hw_ver.minor, &host->hw_ver.step);
 938
 939         /* update phy revision information before calling phy_init() */
 940         ufs_qcom_phy_save_controller_version(host->generic_phy,
 941                 host->hw_ver.major, host->hw_ver.minor, host->hw_ver.step);
 942
 943         phy_init(host->generic_phy);
 944         err = phy_power_on(host->generic_phy);
 945         if (err)
 946                 goto out_unregister_bus;
 947
 948         err = ufs_qcom_init_lane_clks(host);
 949         if (err)
 950                 goto out_disable_phy;
 951
 952         ufs_qcom_set_caps(hba);
 953         ufs_qcom_advertise_quirks(hba);
 954
 955         hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_CLK_SCALING;
 956         hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
 957
 958         ufs_qcom_setup_clocks(hba, true);
 959
 960         if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
 961                 ufs_qcom_hosts[hba->dev->id] = host;
 962
 963         goto out;
 964
 965 out_disable_phy:
 966         phy_power_off(host->generic_phy);
 967 out_unregister_bus:
 968         phy_exit(host->generic_phy);
 969 out_host_free:
 970         devm_kfree(dev, host);
 971         hba->priv = NULL;
 972 out:
 973         return err;
 974 }
 975
 976 static void ufs_qcom_exit(struct ufs_hba *hba)
 977 {
 978         struct ufs_qcom_host *host = hba->priv;
 979
 980         ufs_qcom_disable_lane_clks(host);
 981         phy_power_off(host->generic_phy);
 982 }
 983
 984 static
 985 void ufs_qcom_clk_scale_notify(struct ufs_hba *hba)
 986 {
 987         struct ufs_qcom_host *host = hba->priv;
 988         struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
 989
 990         if (!dev_req_params)
 991                 return;
 992
 993         ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
 994                                 dev_req_params->pwr_rx,
 995                                 dev_req_params->hs_rate);
 996 }
 997
 998 /**
 999  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1000  *
1001  * The variant operations configure the necessary controller and PHY
1002  * handshake during initialization.
1003  */
1004 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1005         .name                   = "qcom",
1006         .init                   = ufs_qcom_init,
1007         .exit                   = ufs_qcom_exit,
1008         .clk_scale_notify       = ufs_qcom_clk_scale_notify,
1009         .setup_clocks           = ufs_qcom_setup_clocks,
1010         .hce_enable_notify      = ufs_qcom_hce_enable_notify,
1011         .link_startup_notify    = ufs_qcom_link_startup_notify,
1012         .pwr_change_notify      = ufs_qcom_pwr_change_notify,
1013         .suspend                = ufs_qcom_suspend,
1014         .resume                 = ufs_qcom_resume,
1015 };
1016 EXPORT_SYMBOL(ufs_hba_qcom_vops);