kernel/drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2014 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/slab.h>
  11 #include <linux/vmalloc.h>
  12 #include <asm/uaccess.h>
  13
  14 /*
  15  * NVRAM support routines
  16  */
  17
  18 /**
  19  * qla2x00_lock_nvram_access() -
  20  * @ha: HA context
  21  */
  22 static void
  23 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
  24 {
  25         uint16_t data;
  26         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  27
  28         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  29                 data = RD_REG_WORD(&reg->nvram);
  30                 while (data & NVR_BUSY) {
  31                         udelay(100);
  32                         data = RD_REG_WORD(&reg->nvram);
  33                 }
  34
  35                 /* Lock resource */
  36                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  37                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  38                 udelay(5);
  39                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  40                 while ((data & BIT_0) == 0) {
  41                         /* Lock failed */
  42                         udelay(100);
  43                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  44                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  45                         udelay(5);
  46                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  47                 }
  48         }
  49 }
  50
  51 /**
  52  * qla2x00_unlock_nvram_access() -
  53  * @ha: HA context
  54  */
  55 static void
  56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
  57 {
  58         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  59
  60         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  61                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  62                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  63         }
  64 }
  65
  66 /**
  67  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
  68  * @ha: HA context
  69  * @data: Serial interface selector
  70  */
  71 static void
  72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
  73 {
  74         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  75
  76         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  77         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  78         NVRAM_DELAY();
  79         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
  80             NVR_WRT_ENABLE);
  81         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  82         NVRAM_DELAY();
  83         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  84         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  85         NVRAM_DELAY();
  86 }
  87
  88 /**
  89  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
  90  *      NVRAM.
  91  * @ha: HA context
  92  * @nv_cmd: NVRAM command
  93  *
  94  * Bit definitions for NVRAM command:
  95  *
  96  *      Bit 26     = start bit
  97  *      Bit 25, 24 = opcode
  98  *      Bit 23-16  = address
  99  *      Bit 15-0   = write data
 100  *
 101  * Returns the word read from nvram @addr.
 102  */
 103 static uint16_t
 104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
 105 {
 106         uint8_t         cnt;
 107         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 108         uint16_t        data = 0;
 109         uint16_t        reg_data;
 110
 111         /* Send command to NVRAM. */
 112         nv_cmd <<= 5;
 113         for (cnt = 0; cnt < 11; cnt++) {
 114                 if (nv_cmd & BIT_31)
 115                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 116                 else
 117                         qla2x00_nv_write(ha, 0);
 118                 nv_cmd <<= 1;
 119         }
 120
 121         /* Read data from NVRAM. */
 122         for (cnt = 0; cnt < 16; cnt++) {
 123                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 124                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 125                 NVRAM_DELAY();
 126                 data <<= 1;
 127                 reg_data = RD_REG_WORD(&reg->nvram);
 128                 if (reg_data & NVR_DATA_IN)
 129                         data |= BIT_0;
 130                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 131                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 132                 NVRAM_DELAY();
 133         }
 134
 135         /* Deselect chip. */
 136         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 137         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 138         NVRAM_DELAY();
 139
 140         return data;
 141 }
 142
 143
 144 /**
 145  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
 146  *      request routine to get the word from NVRAM.
 147  * @ha: HA context
 148  * @addr: Address in NVRAM to read
 149  *
 150  * Returns the word read from nvram @addr.
 151  */
 152 static uint16_t
 153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
 154 {
 155         uint16_t        data;
 156         uint32_t        nv_cmd;
 157
 158         nv_cmd = addr << 16;
 159         nv_cmd |= NV_READ_OP;
 160         data = qla2x00_nvram_request(ha, nv_cmd);
 161
 162         return (data);
 163 }
 164
 165 /**
 166  * qla2x00_nv_deselect() - Deselect NVRAM operations.
 167  * @ha: HA context
 168  */
 169 static void
 170 qla2x00_nv_deselect(struct qla_hw_data *ha)
 171 {
 172         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 173
 174         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 175         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 176         NVRAM_DELAY();
 177 }
 178
 179 /**
 180  * qla2x00_write_nvram_word() - Write NVRAM data.
 181  * @ha: HA context
 182  * @addr: Address in NVRAM to write
 183  * @data: word to program
 184  */
 185 static void
 186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
 187 {
 188         int count;
 189         uint16_t word;
 190         uint32_t nv_cmd, wait_cnt;
 191         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 192         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 193
 194         qla2x00_nv_write(ha, NVR_DATA_OUT);
 195         qla2x00_nv_write(ha, 0);
 196         qla2x00_nv_write(ha, 0);
 197
 198         for (word = 0; word < 8; word++)
 199                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 200
 201         qla2x00_nv_deselect(ha);
 202
 203         /* Write data */
 204         nv_cmd = (addr << 16) | NV_WRITE_OP;
 205         nv_cmd |= data;
 206         nv_cmd <<= 5;
 207         for (count = 0; count < 27; count++) {
 208                 if (nv_cmd & BIT_31)
 209                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 210                 else
 211                         qla2x00_nv_write(ha, 0);
 212
 213                 nv_cmd <<= 1;
 214         }
 215
 216         qla2x00_nv_deselect(ha);
 217
 218         /* Wait for NVRAM to become ready */
 219         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 220         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 221         wait_cnt = NVR_WAIT_CNT;
 222         do {
 223                 if (!--wait_cnt) {
 224                         ql_dbg(ql_dbg_user, vha, 0x708d,
 225                             "NVRAM didn't go ready...\n");
 226                         break;
 227                 }
 228                 NVRAM_DELAY();
 229                 word = RD_REG_WORD(&reg->nvram);
 230         } while ((word & NVR_DATA_IN) == 0);
 231
 232         qla2x00_nv_deselect(ha);
 233
 234         /* Disable writes */
 235         qla2x00_nv_write(ha, NVR_DATA_OUT);
 236         for (count = 0; count < 10; count++)
 237                 qla2x00_nv_write(ha, 0);
 238
 239         qla2x00_nv_deselect(ha);
 240 }
 241
 242 static int
 243 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
 244         uint16_t data, uint32_t tmo)
 245 {
 246         int ret, count;
 247         uint16_t word;
 248         uint32_t nv_cmd;
 249         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 250
 251         ret = QLA_SUCCESS;
 252
 253         qla2x00_nv_write(ha, NVR_DATA_OUT);
 254         qla2x00_nv_write(ha, 0);
 255         qla2x00_nv_write(ha, 0);
 256
 257         for (word = 0; word < 8; word++)
 258                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 259
 260         qla2x00_nv_deselect(ha);
 261
 262         /* Write data */
 263         nv_cmd = (addr << 16) | NV_WRITE_OP;
 264         nv_cmd |= data;
 265         nv_cmd <<= 5;
 266         for (count = 0; count < 27; count++) {
 267                 if (nv_cmd & BIT_31)
 268                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 269                 else
 270                         qla2x00_nv_write(ha, 0);
 271
 272                 nv_cmd <<= 1;
 273         }
 274
 275         qla2x00_nv_deselect(ha);
 276
 277         /* Wait for NVRAM to become ready */
 278         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 279         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 280         do {
 281                 NVRAM_DELAY();
 282                 word = RD_REG_WORD(&reg->nvram);
 283                 if (!--tmo) {
 284                         ret = QLA_FUNCTION_FAILED;
 285                         break;
 286                 }
 287         } while ((word & NVR_DATA_IN) == 0);
 288
 289         qla2x00_nv_deselect(ha);
 290
 291         /* Disable writes */
 292         qla2x00_nv_write(ha, NVR_DATA_OUT);
 293         for (count = 0; count < 10; count++)
 294                 qla2x00_nv_write(ha, 0);
 295
 296         qla2x00_nv_deselect(ha);
 297
 298         return ret;
 299 }
 300
 301 /**
 302  * qla2x00_clear_nvram_protection() -
 303  * @ha: HA context
 304  */
 305 static int
 306 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
 307 {
 308         int ret, stat;
 309         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 310         uint32_t word, wait_cnt;
 311         uint16_t wprot, wprot_old;
 312         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 313
 314         /* Clear NVRAM write protection. */
 315         ret = QLA_FUNCTION_FAILED;
 316
 317         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 319             __constant_cpu_to_le16(0x1234), 100000);
 320         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 321         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 322                 /* Write enable. */
 323                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 324                 qla2x00_nv_write(ha, 0);
 325                 qla2x00_nv_write(ha, 0);
 326                 for (word = 0; word < 8; word++)
 327                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 328
 329                 qla2x00_nv_deselect(ha);
 330
 331                 /* Enable protection register. */
 332                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 333                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 334                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 335                 for (word = 0; word < 8; word++)
 336                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 337
 338                 qla2x00_nv_deselect(ha);
 339
 340                 /* Clear protection register (ffff is cleared). */
 341                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 342                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 343                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 344                 for (word = 0; word < 8; word++)
 345                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 346
 347                 qla2x00_nv_deselect(ha);
 348
 349                 /* Wait for NVRAM to become ready. */
 350                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 351                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 352                 wait_cnt = NVR_WAIT_CNT;
 353                 do {
 354                         if (!--wait_cnt) {
 355                                 ql_dbg(ql_dbg_user, vha, 0x708e,
 356                                     "NVRAM didn't go ready...\n");
 357                                 break;
 358                         }
 359                         NVRAM_DELAY();
 360                         word = RD_REG_WORD(&reg->nvram);
 361                 } while ((word & NVR_DATA_IN) == 0);
 362
 363                 if (wait_cnt)
 364                         ret = QLA_SUCCESS;
 365         } else
 366                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 367
 368         return ret;
 369 }
 370
 371 static void
 372 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
 373 {
 374         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 375         uint32_t word, wait_cnt;
 376         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 377
 378         if (stat != QLA_SUCCESS)
 379                 return;
 380
 381         /* Set NVRAM write protection. */
 382         /* Write enable. */
 383         qla2x00_nv_write(ha, NVR_DATA_OUT);
 384         qla2x00_nv_write(ha, 0);
 385         qla2x00_nv_write(ha, 0);
 386         for (word = 0; word < 8; word++)
 387                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 388
 389         qla2x00_nv_deselect(ha);
 390
 391         /* Enable protection register. */
 392         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 393         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 394         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 395         for (word = 0; word < 8; word++)
 396                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 397
 398         qla2x00_nv_deselect(ha);
 399
 400         /* Enable protection register. */
 401         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 402         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 403         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 404         for (word = 0; word < 8; word++)
 405                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 406
 407         qla2x00_nv_deselect(ha);
 408
 409         /* Wait for NVRAM to become ready. */
 410         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 411         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 412         wait_cnt = NVR_WAIT_CNT;
 413         do {
 414                 if (!--wait_cnt) {
 415                         ql_dbg(ql_dbg_user, vha, 0x708f,
 416                             "NVRAM didn't go ready...\n");
 417                         break;
 418                 }
 419                 NVRAM_DELAY();
 420                 word = RD_REG_WORD(&reg->nvram);
 421         } while ((word & NVR_DATA_IN) == 0);
 422 }
 423
 424
 425 /*****************************************************************************/
 426 /* Flash Manipulation Routines                                               */
 427 /*****************************************************************************/
 428
 429 static inline uint32_t
 430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
 431 {
 432         return ha->flash_conf_off | faddr;
 433 }
 434
 435 static inline uint32_t
 436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
 437 {
 438         return ha->flash_data_off | faddr;
 439 }
 440
 441 static inline uint32_t
 442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
 443 {
 444         return ha->nvram_conf_off | naddr;
 445 }
 446
 447 static inline uint32_t
 448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
 449 {
 450         return ha->nvram_data_off | naddr;
 451 }
 452
 453 static uint32_t
 454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
 455 {
 456         int rval;
 457         uint32_t cnt, data;
 458         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 459
 460         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 461         /* Wait for READ cycle to complete. */
 462         rval = QLA_SUCCESS;
 463         for (cnt = 3000;
 464             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 465             rval == QLA_SUCCESS; cnt--) {
 466                 if (cnt)
 467                         udelay(10);
 468                 else
 469                         rval = QLA_FUNCTION_TIMEOUT;
 470                 cond_resched();
 471         }
 472
 473         /* TODO: What happens if we time out? */
 474         data = 0xDEADDEAD;
 475         if (rval == QLA_SUCCESS)
 476                 data = RD_REG_DWORD(&reg->flash_data);
 477
 478         return data;
 479 }
 480
 481 uint32_t *
 482 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
 483     uint32_t dwords)
 484 {
 485         uint32_t i;
 486         struct qla_hw_data *ha = vha->hw;
 487
 488         /* Dword reads to flash. */
 489         for (i = 0; i < dwords; i++, faddr++)
 490                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 491                     flash_data_addr(ha, faddr)));
 492
 493         return dwptr;
 494 }
 495
 496 static int
 497 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
 498 {
 499         int rval;
 500         uint32_t cnt;
 501         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 502
 503         WRT_REG_DWORD(&reg->flash_data, data);
 504         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 505         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 506         /* Wait for Write cycle to complete. */
 507         rval = QLA_SUCCESS;
 508         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 509             rval == QLA_SUCCESS; cnt--) {
 510                 if (cnt)
 511                         udelay(10);
 512                 else
 513                         rval = QLA_FUNCTION_TIMEOUT;
 514                 cond_resched();
 515         }
 516         return rval;
 517 }
 518
 519 static void
 520 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
 521     uint8_t *flash_id)
 522 {
 523         uint32_t ids;
 524
 525         ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
 526         *man_id = LSB(ids);
 527         *flash_id = MSB(ids);
 528
 529         /* Check if man_id and flash_id are valid. */
 530         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 531                 /* Read information using 0x9f opcode
 532                  * Device ID, Mfg ID would be read in the format:
 533                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 534                  * Example: ATMEL 0x00 01 45 1F
 535                  * Extract MFG and Dev ID from last two bytes.
 536                  */
 537                 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
 538                 *man_id = LSB(ids);
 539                 *flash_id = MSB(ids);
 540         }
 541 }
 542
 543 static int
 544 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
 545 {
 546         const char *loc, *locations[] = { "DEF", "PCI" };
 547         uint32_t pcihdr, pcids;
 548         uint32_t *dcode;
 549         uint8_t *buf, *bcode, last_image;
 550         uint16_t cnt, chksum, *wptr;
 551         struct qla_flt_location *fltl;
 552         struct qla_hw_data *ha = vha->hw;
 553         struct req_que *req = ha->req_q_map[0];
 554
 555         /*
 556          * FLT-location structure resides after the last PCI region.
 557          */
 558
 559         /* Begin with sane defaults. */
 560         loc = locations[0];
 561         *start = 0;
 562         if (IS_QLA24XX_TYPE(ha))
 563                 *start = FA_FLASH_LAYOUT_ADDR_24;
 564         else if (IS_QLA25XX(ha))
 565                 *start = FA_FLASH_LAYOUT_ADDR;
 566         else if (IS_QLA81XX(ha))
 567                 *start = FA_FLASH_LAYOUT_ADDR_81;
 568         else if (IS_P3P_TYPE(ha)) {
 569                 *start = FA_FLASH_LAYOUT_ADDR_82;
 570                 goto end;
 571         } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
 572                 *start = FA_FLASH_LAYOUT_ADDR_83;
 573                 goto end;
 574         }
 575         /* Begin with first PCI expansion ROM header. */
 576         buf = (uint8_t *)req->ring;
 577         dcode = (uint32_t *)req->ring;
 578         pcihdr = 0;
 579         last_image = 1;
 580         do {
 581                 /* Verify PCI expansion ROM header. */
 582                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
 583                 bcode = buf + (pcihdr % 4);
 584                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
 585                         goto end;
 586
 587                 /* Locate PCI data structure. */
 588                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
 589                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
 590                 bcode = buf + (pcihdr % 4);
 591
 592                 /* Validate signature of PCI data structure. */
 593                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
 594                     bcode[0x2] != 'I' || bcode[0x3] != 'R')
 595                         goto end;
 596
 597                 last_image = bcode[0x15] & BIT_7;
 598
 599                 /* Locate next PCI expansion ROM. */
 600                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
 601         } while (!last_image);
 602
 603         /* Now verify FLT-location structure. */
 604         fltl = (struct qla_flt_location *)req->ring;
 605         qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
 606             sizeof(struct qla_flt_location) >> 2);
 607         if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
 608             fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
 609                 goto end;
 610
 611         wptr = (uint16_t *)req->ring;
 612         cnt = sizeof(struct qla_flt_location) >> 1;
 613         for (chksum = 0; cnt; cnt--)
 614                 chksum += le16_to_cpu(*wptr++);
 615         if (chksum) {
 616                 ql_log(ql_log_fatal, vha, 0x0045,
 617                     "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
 618                 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
 619                     buf, sizeof(struct qla_flt_location));
 620                 return QLA_FUNCTION_FAILED;
 621         }
 622
 623         /* Good data.  Use specified location. */
 624         loc = locations[1];
 625         *start = (le16_to_cpu(fltl->start_hi) << 16 |
 626             le16_to_cpu(fltl->start_lo)) >> 2;
 627 end:
 628         ql_dbg(ql_dbg_init, vha, 0x0046,
 629             "FLTL[%s] = 0x%x.\n",
 630             loc, *start);
 631         return QLA_SUCCESS;
 632 }
 633
 634 static void
 635 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
 636 {
 637         const char *loc, *locations[] = { "DEF", "FLT" };
 638         const uint32_t def_fw[] =
 639                 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
 640         const uint32_t def_boot[] =
 641                 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
 642         const uint32_t def_vpd_nvram[] =
 643                 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
 644         const uint32_t def_vpd0[] =
 645                 { 0, 0, FA_VPD0_ADDR_81 };
 646         const uint32_t def_vpd1[] =
 647                 { 0, 0, FA_VPD1_ADDR_81 };
 648         const uint32_t def_nvram0[] =
 649                 { 0, 0, FA_NVRAM0_ADDR_81 };
 650         const uint32_t def_nvram1[] =
 651                 { 0, 0, FA_NVRAM1_ADDR_81 };
 652         const uint32_t def_fdt[] =
 653                 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
 654                         FA_FLASH_DESCR_ADDR_81 };
 655         const uint32_t def_npiv_conf0[] =
 656                 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
 657                         FA_NPIV_CONF0_ADDR_81 };
 658         const uint32_t def_npiv_conf1[] =
 659                 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
 660                         FA_NPIV_CONF1_ADDR_81 };
 661         const uint32_t fcp_prio_cfg0[] =
 662                 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
 663                         0 };
 664         const uint32_t fcp_prio_cfg1[] =
 665                 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
 666                         0 };
 667         uint32_t def;
 668         uint16_t *wptr;
 669         uint16_t cnt, chksum;
 670         uint32_t start;
 671         struct qla_flt_header *flt;
 672         struct qla_flt_region *region;
 673         struct qla_hw_data *ha = vha->hw;
 674         struct req_que *req = ha->req_q_map[0];
 675
 676         def = 0;
 677         if (IS_QLA25XX(ha))
 678                 def = 1;
 679         else if (IS_QLA81XX(ha))
 680                 def = 2;
 681
 682         /* Assign FCP prio region since older adapters may not have FLT, or
 683            FCP prio region in it's FLT.
 684          */
 685         ha->flt_region_fcp_prio = (ha->port_no == 0) ?
 686             fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
 687
 688         ha->flt_region_flt = flt_addr;
 689         wptr = (uint16_t *)req->ring;
 690         flt = (struct qla_flt_header *)req->ring;
 691         region = (struct qla_flt_region *)&flt[1];
 692         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 693             flt_addr << 2, OPTROM_BURST_SIZE);
 694         if (*wptr == __constant_cpu_to_le16(0xffff))
 695                 goto no_flash_data;
 696         if (flt->version != __constant_cpu_to_le16(1)) {
 697                 ql_log(ql_log_warn, vha, 0x0047,
 698                     "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
 699                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 700                     le16_to_cpu(flt->checksum));
 701                 goto no_flash_data;
 702         }
 703
 704         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
 705         for (chksum = 0; cnt; cnt--)
 706                 chksum += le16_to_cpu(*wptr++);
 707         if (chksum) {
 708                 ql_log(ql_log_fatal, vha, 0x0048,
 709                     "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
 710                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 711                     le16_to_cpu(flt->checksum));
 712                 goto no_flash_data;
 713         }
 714
 715         loc = locations[1];
 716         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
 717         for ( ; cnt; cnt--, region++) {
 718                 /* Store addresses as DWORD offsets. */
 719                 start = le32_to_cpu(region->start) >> 2;
 720                 ql_dbg(ql_dbg_init, vha, 0x0049,
 721                     "FLT[%02x]: start=0x%x "
 722                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code) & 0xff,
 723                     start, le32_to_cpu(region->end) >> 2,
 724                     le32_to_cpu(region->size));
 725
 726                 switch (le32_to_cpu(region->code) & 0xff) {
 727                 case FLT_REG_FCOE_FW:
 728                         if (!IS_QLA8031(ha))
 729                                 break;
 730                         ha->flt_region_fw = start;
 731                         break;
 732                 case FLT_REG_FW:
 733                         if (IS_QLA8031(ha))
 734                                 break;
 735                         ha->flt_region_fw = start;
 736                         break;
 737                 case FLT_REG_BOOT_CODE:
 738                         ha->flt_region_boot = start;
 739                         break;
 740                 case FLT_REG_VPD_0:
 741                         if (IS_QLA8031(ha))
 742                                 break;
 743                         ha->flt_region_vpd_nvram = start;
 744                         if (IS_P3P_TYPE(ha))
 745                                 break;
 746                         if (ha->port_no == 0)
 747                                 ha->flt_region_vpd = start;
 748                         break;
 749                 case FLT_REG_VPD_1:
 750                         if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
 751                                 break;
 752                         if (ha->port_no == 1)
 753                                 ha->flt_region_vpd = start;
 754                         break;
 755                 case FLT_REG_VPD_2:
 756                         if (!IS_QLA27XX(ha))
 757                                 break;
 758                         if (ha->port_no == 2)
 759                                 ha->flt_region_vpd = start;
 760                         break;
 761                 case FLT_REG_VPD_3:
 762                         if (!IS_QLA27XX(ha))
 763                                 break;
 764                         if (ha->port_no == 3)
 765                                 ha->flt_region_vpd = start;
 766                         break;
 767                 case FLT_REG_NVRAM_0:
 768                         if (IS_QLA8031(ha))
 769                                 break;
 770                         if (ha->port_no == 0)
 771                                 ha->flt_region_nvram = start;
 772                         break;
 773                 case FLT_REG_NVRAM_1:
 774                         if (IS_QLA8031(ha))
 775                                 break;
 776                         if (ha->port_no == 1)
 777                                 ha->flt_region_nvram = start;
 778                         break;
 779                 case FLT_REG_NVRAM_2:
 780                         if (!IS_QLA27XX(ha))
 781                                 break;
 782                         if (ha->port_no == 2)
 783                                 ha->flt_region_nvram = start;
 784                         break;
 785                 case FLT_REG_NVRAM_3:
 786                         if (!IS_QLA27XX(ha))
 787                                 break;
 788                         if (ha->port_no == 3)
 789                                 ha->flt_region_nvram = start;
 790                         break;
 791                 case FLT_REG_FDT:
 792                         ha->flt_region_fdt = start;
 793                         break;
 794                 case FLT_REG_NPIV_CONF_0:
 795                         if (ha->port_no == 0)
 796                                 ha->flt_region_npiv_conf = start;
 797                         break;
 798                 case FLT_REG_NPIV_CONF_1:
 799                         if (ha->port_no == 1)
 800                                 ha->flt_region_npiv_conf = start;
 801                         break;
 802                 case FLT_REG_GOLD_FW:
 803                         ha->flt_region_gold_fw = start;
 804                         break;
 805                 case FLT_REG_FCP_PRIO_0:
 806                         if (ha->port_no == 0)
 807                                 ha->flt_region_fcp_prio = start;
 808                         break;
 809                 case FLT_REG_FCP_PRIO_1:
 810                         if (ha->port_no == 1)
 811                                 ha->flt_region_fcp_prio = start;
 812                         break;
 813                 case FLT_REG_BOOT_CODE_82XX:
 814                         ha->flt_region_boot = start;
 815                         break;
 816                 case FLT_REG_BOOT_CODE_8044:
 817                         if (IS_QLA8044(ha))
 818                                 ha->flt_region_boot = start;
 819                         break;
 820                 case FLT_REG_FW_82XX:
 821                         ha->flt_region_fw = start;
 822                         break;
 823                 case FLT_REG_CNA_FW:
 824                         if (IS_CNA_CAPABLE(ha))
 825                                 ha->flt_region_fw = start;
 826                         break;
 827                 case FLT_REG_GOLD_FW_82XX:
 828                         ha->flt_region_gold_fw = start;
 829                         break;
 830                 case FLT_REG_BOOTLOAD_82XX:
 831                         ha->flt_region_bootload = start;
 832                         break;
 833                 case FLT_REG_VPD_8XXX:
 834                         if (IS_CNA_CAPABLE(ha))
 835                                 ha->flt_region_vpd = start;
 836                         break;
 837                 case FLT_REG_FCOE_NVRAM_0:
 838                         if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
 839                                 break;
 840                         if (ha->port_no == 0)
 841                                 ha->flt_region_nvram = start;
 842                         break;
 843                 case FLT_REG_FCOE_NVRAM_1:
 844                         if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
 845                                 break;
 846                         if (ha->port_no == 1)
 847                                 ha->flt_region_nvram = start;
 848                         break;
 849                 }
 850         }
 851         goto done;
 852
 853 no_flash_data:
 854         /* Use hardcoded defaults. */
 855         loc = locations[0];
 856         ha->flt_region_fw = def_fw[def];
 857         ha->flt_region_boot = def_boot[def];
 858         ha->flt_region_vpd_nvram = def_vpd_nvram[def];
 859         ha->flt_region_vpd = (ha->port_no == 0) ?
 860             def_vpd0[def] : def_vpd1[def];
 861         ha->flt_region_nvram = (ha->port_no == 0) ?
 862             def_nvram0[def] : def_nvram1[def];
 863         ha->flt_region_fdt = def_fdt[def];
 864         ha->flt_region_npiv_conf = (ha->port_no == 0) ?
 865             def_npiv_conf0[def] : def_npiv_conf1[def];
 866 done:
 867         ql_dbg(ql_dbg_init, vha, 0x004a,
 868             "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x "
 869             "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
 870             loc, ha->flt_region_boot, ha->flt_region_fw,
 871             ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
 872             ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf,
 873             ha->flt_region_fcp_prio);
 874 }
 875
 876 static void
 877 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
 878 {
 879 #define FLASH_BLK_SIZE_4K       0x1000
 880 #define FLASH_BLK_SIZE_32K      0x8000
 881 #define FLASH_BLK_SIZE_64K      0x10000
 882         const char *loc, *locations[] = { "MID", "FDT" };
 883         uint16_t cnt, chksum;
 884         uint16_t *wptr;
 885         struct qla_fdt_layout *fdt;
 886         uint8_t man_id, flash_id;
 887         uint16_t mid = 0, fid = 0;
 888         struct qla_hw_data *ha = vha->hw;
 889         struct req_que *req = ha->req_q_map[0];
 890
 891         wptr = (uint16_t *)req->ring;
 892         fdt = (struct qla_fdt_layout *)req->ring;
 893         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 894             ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
 895         if (*wptr == __constant_cpu_to_le16(0xffff))
 896                 goto no_flash_data;
 897         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
 898             fdt->sig[3] != 'D')
 899                 goto no_flash_data;
 900
 901         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
 902             cnt++)
 903                 chksum += le16_to_cpu(*wptr++);
 904         if (chksum) {
 905                 ql_dbg(ql_dbg_init, vha, 0x004c,
 906                     "Inconsistent FDT detected:"
 907                     " checksum=0x%x id=%c version0x%x.\n", chksum,
 908                     fdt->sig[0], le16_to_cpu(fdt->version));
 909                 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
 910                     (uint8_t *)fdt, sizeof(*fdt));
 911                 goto no_flash_data;
 912         }
 913
 914         loc = locations[1];
 915         mid = le16_to_cpu(fdt->man_id);
 916         fid = le16_to_cpu(fdt->id);
 917         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
 918         ha->fdt_wrt_enable = fdt->wrt_enable_bits;
 919         ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd;
 920         if (IS_QLA8044(ha))
 921                 ha->fdt_erase_cmd = fdt->erase_cmd;
 922         else
 923                 ha->fdt_erase_cmd =
 924                     flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
 925         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
 926         if (fdt->unprotect_sec_cmd) {
 927                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
 928                     fdt->unprotect_sec_cmd);
 929                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
 930                     flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
 931                     flash_conf_addr(ha, 0x0336);
 932         }
 933         goto done;
 934 no_flash_data:
 935         loc = locations[0];
 936         if (IS_P3P_TYPE(ha)) {
 937                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 938                 goto done;
 939         }
 940         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 941         mid = man_id;
 942         fid = flash_id;
 943         ha->fdt_wrt_disable = 0x9c;
 944         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
 945         switch (man_id) {
 946         case 0xbf: /* STT flash. */
 947                 if (flash_id == 0x8e)
 948                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 949                 else
 950                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
 951
 952                 if (flash_id == 0x80)
 953                         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
 954                 break;
 955         case 0x13: /* ST M25P80. */
 956                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 957                 break;
 958         case 0x1f: /* Atmel 26DF081A. */
 959                 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
 960                 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
 961                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
 962                 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
 963                 break;
 964         default:
 965                 /* Default to 64 kb sector size. */
 966                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 967                 break;
 968         }
 969 done:
 970         ql_dbg(ql_dbg_init, vha, 0x004d,
 971             "FDT[%s]: (0x%x/0x%x) erase=0x%x "
 972             "pr=%x wrtd=0x%x blk=0x%x.\n",
 973             loc, mid, fid,
 974             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
 975             ha->fdt_wrt_disable, ha->fdt_block_size);
 976
 977 }
 978
 979 static void
 980 qla2xxx_get_idc_param(scsi_qla_host_t *vha)
 981 {
 982 #define QLA82XX_IDC_PARAM_ADDR       0x003e885c
 983         uint32_t *wptr;
 984         struct qla_hw_data *ha = vha->hw;
 985         struct req_que *req = ha->req_q_map[0];
 986
 987         if (!(IS_P3P_TYPE(ha)))
 988                 return;
 989
 990         wptr = (uint32_t *)req->ring;
 991         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 992                 QLA82XX_IDC_PARAM_ADDR , 8);
 993
 994         if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
 995                 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
 996                 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
 997         } else {
 998                 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr++);
 999                 ha->fcoe_reset_timeout = le32_to_cpu(*wptr);
1000         }
1001         ql_dbg(ql_dbg_init, vha, 0x004e,
1002             "fcoe_dev_init_timeout=%d "
1003             "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout,
1004             ha->fcoe_reset_timeout);
1005         return;
1006 }
1007
1008 int
1009 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
1010 {
1011         int ret;
1012         uint32_t flt_addr;
1013         struct qla_hw_data *ha = vha->hw;
1014
1015         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1016             !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLA27XX(ha))
1017                 return QLA_SUCCESS;
1018
1019         ret = qla2xxx_find_flt_start(vha, &flt_addr);
1020         if (ret != QLA_SUCCESS)
1021                 return ret;
1022
1023         qla2xxx_get_flt_info(vha, flt_addr);
1024         qla2xxx_get_fdt_info(vha);
1025         qla2xxx_get_idc_param(vha);
1026
1027         return QLA_SUCCESS;
1028 }
1029
1030 void
1031 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
1032 {
1033 #define NPIV_CONFIG_SIZE        (16*1024)
1034         void *data;
1035         uint16_t *wptr;
1036         uint16_t cnt, chksum;
1037         int i;
1038         struct qla_npiv_header hdr;
1039         struct qla_npiv_entry *entry;
1040         struct qla_hw_data *ha = vha->hw;
1041
1042         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1043             !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
1044                 return;
1045
1046         if (ha->flags.nic_core_reset_hdlr_active)
1047                 return;
1048
1049         if (IS_QLA8044(ha))
1050                 return;
1051
1052         ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
1053             ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
1054         if (hdr.version == __constant_cpu_to_le16(0xffff))
1055                 return;
1056         if (hdr.version != __constant_cpu_to_le16(1)) {
1057                 ql_dbg(ql_dbg_user, vha, 0x7090,
1058                     "Unsupported NPIV-Config "
1059                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1060                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1061                     le16_to_cpu(hdr.checksum));
1062                 return;
1063         }
1064
1065         data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
1066         if (!data) {
1067                 ql_log(ql_log_warn, vha, 0x7091,
1068                     "Unable to allocate memory for data.\n");
1069                 return;
1070         }
1071
1072         ha->isp_ops->read_optrom(vha, (uint8_t *)data,
1073             ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
1074
1075         cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
1076             sizeof(struct qla_npiv_entry)) >> 1;
1077         for (wptr = data, chksum = 0; cnt; cnt--)
1078                 chksum += le16_to_cpu(*wptr++);
1079         if (chksum) {
1080                 ql_dbg(ql_dbg_user, vha, 0x7092,
1081                     "Inconsistent NPIV-Config "
1082                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1083                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1084                     le16_to_cpu(hdr.checksum));
1085                 goto done;
1086         }
1087
1088         entry = data + sizeof(struct qla_npiv_header);
1089         cnt = le16_to_cpu(hdr.entries);
1090         for (i = 0; cnt; cnt--, entry++, i++) {
1091                 uint16_t flags;
1092                 struct fc_vport_identifiers vid;
1093                 struct fc_vport *vport;
1094
1095                 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1096
1097                 flags = le16_to_cpu(entry->flags);
1098                 if (flags == 0xffff)
1099                         continue;
1100                 if ((flags & BIT_0) == 0)
1101                         continue;
1102
1103                 memset(&vid, 0, sizeof(vid));
1104                 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1105                 vid.vport_type = FC_PORTTYPE_NPIV;
1106                 vid.disable = false;
1107                 vid.port_name = wwn_to_u64(entry->port_name);
1108                 vid.node_name = wwn_to_u64(entry->node_name);
1109
1110                 ql_dbg(ql_dbg_user, vha, 0x7093,
1111                     "NPIV[%02x]: wwpn=%llx "
1112                     "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1113                     (unsigned long long)vid.port_name,
1114                     (unsigned long long)vid.node_name,
1115                     le16_to_cpu(entry->vf_id),
1116                     entry->q_qos, entry->f_qos);
1117
1118                 if (i < QLA_PRECONFIG_VPORTS) {
1119                         vport = fc_vport_create(vha->host, 0, &vid);
1120                         if (!vport)
1121                                 ql_log(ql_log_warn, vha, 0x7094,
1122                                     "NPIV-Config Failed to create vport [%02x]: "
1123                                     "wwpn=%llx wwnn=%llx.\n", cnt,
1124                                     (unsigned long long)vid.port_name,
1125                                     (unsigned long long)vid.node_name);
1126                 }
1127         }
1128 done:
1129         kfree(data);
1130 }
1131
1132 static int
1133 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
1134 {
1135         struct qla_hw_data *ha = vha->hw;
1136         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1137
1138         if (ha->flags.fac_supported)
1139                 return qla81xx_fac_do_write_enable(vha, 1);
1140
1141         /* Enable flash write. */
1142         WRT_REG_DWORD(&reg->ctrl_status,
1143             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1144         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1145
1146         if (!ha->fdt_wrt_disable)
1147                 goto done;
1148
1149         /* Disable flash write-protection, first clear SR protection bit */
1150         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1151         /* Then write zero again to clear remaining SR bits.*/
1152         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1153 done:
1154         return QLA_SUCCESS;
1155 }
1156
1157 static int
1158 qla24xx_protect_flash(scsi_qla_host_t *vha)
1159 {
1160         uint32_t cnt;
1161         struct qla_hw_data *ha = vha->hw;
1162         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1163
1164         if (ha->flags.fac_supported)
1165                 return qla81xx_fac_do_write_enable(vha, 0);
1166
1167         if (!ha->fdt_wrt_disable)
1168                 goto skip_wrt_protect;
1169
1170         /* Enable flash write-protection and wait for completion. */
1171         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1172             ha->fdt_wrt_disable);
1173         for (cnt = 300; cnt &&
1174             qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1175             cnt--) {
1176                 udelay(10);
1177         }
1178
1179 skip_wrt_protect:
1180         /* Disable flash write. */
1181         WRT_REG_DWORD(&reg->ctrl_status,
1182             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1183         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1184
1185         return QLA_SUCCESS;
1186 }
1187
1188 static int
1189 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1190 {
1191         struct qla_hw_data *ha = vha->hw;
1192         uint32_t start, finish;
1193
1194         if (ha->flags.fac_supported) {
1195                 start = fdata >> 2;
1196                 finish = start + (ha->fdt_block_size >> 2) - 1;
1197                 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1198                     start), flash_data_addr(ha, finish));
1199         }
1200
1201         return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1202             (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1203             ((fdata >> 16) & 0xff));
1204 }
1205
1206 static int
1207 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1208     uint32_t dwords)
1209 {
1210         int ret;
1211         uint32_t liter;
1212         uint32_t sec_mask, rest_addr;
1213         uint32_t fdata;
1214         dma_addr_t optrom_dma;
1215         void *optrom = NULL;
1216         struct qla_hw_data *ha = vha->hw;
1217
1218         /* Prepare burst-capable write on supported ISPs. */
1219         if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
1220             IS_QLA27XX(ha)) &&
1221             !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) {
1222                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1223                     &optrom_dma, GFP_KERNEL);
1224                 if (!optrom) {
1225                         ql_log(ql_log_warn, vha, 0x7095,
1226                             "Unable to allocate "
1227                             "memory for optrom burst write (%x KB).\n",
1228                             OPTROM_BURST_SIZE / 1024);
1229                 }
1230         }
1231
1232         rest_addr = (ha->fdt_block_size >> 2) - 1;
1233         sec_mask = ~rest_addr;
1234
1235         ret = qla24xx_unprotect_flash(vha);
1236         if (ret != QLA_SUCCESS) {
1237                 ql_log(ql_log_warn, vha, 0x7096,
1238                     "Unable to unprotect flash for update.\n");
1239                 goto done;
1240         }
1241
1242         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1243                 fdata = (faddr & sec_mask) << 2;
1244
1245                 /* Are we at the beginning of a sector? */
1246                 if ((faddr & rest_addr) == 0) {
1247                         /* Do sector unprotect. */
1248                         if (ha->fdt_unprotect_sec_cmd)
1249                                 qla24xx_write_flash_dword(ha,
1250                                     ha->fdt_unprotect_sec_cmd,
1251                                     (fdata & 0xff00) | ((fdata << 16) &
1252                                     0xff0000) | ((fdata >> 16) & 0xff));
1253                         ret = qla24xx_erase_sector(vha, fdata);
1254                         if (ret != QLA_SUCCESS) {
1255                                 ql_dbg(ql_dbg_user, vha, 0x7007,
1256                                     "Unable to erase erase sector: address=%x.\n",
1257                                     faddr);
1258                                 break;
1259                         }
1260                 }
1261
1262                 /* Go with burst-write. */
1263                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1264                         /* Copy data to DMA'ble buffer. */
1265                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1266
1267                         ret = qla2x00_load_ram(vha, optrom_dma,
1268                             flash_data_addr(ha, faddr),
1269                             OPTROM_BURST_DWORDS);
1270                         if (ret != QLA_SUCCESS) {
1271                                 ql_log(ql_log_warn, vha, 0x7097,
1272                                     "Unable to burst-write optrom segment "
1273                                     "(%x/%x/%llx).\n", ret,
1274                                     flash_data_addr(ha, faddr),
1275                                     (unsigned long long)optrom_dma);
1276                                 ql_log(ql_log_warn, vha, 0x7098,
1277                                     "Reverting to slow-write.\n");
1278
1279                                 dma_free_coherent(&ha->pdev->dev,
1280                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1281                                 optrom = NULL;
1282                         } else {
1283                                 liter += OPTROM_BURST_DWORDS - 1;
1284                                 faddr += OPTROM_BURST_DWORDS - 1;
1285                                 dwptr += OPTROM_BURST_DWORDS - 1;
1286                                 continue;
1287                         }
1288                 }
1289
1290                 ret = qla24xx_write_flash_dword(ha,
1291                     flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1292                 if (ret != QLA_SUCCESS) {
1293                         ql_dbg(ql_dbg_user, vha, 0x7006,
1294                             "Unable to program flash address=%x data=%x.\n",
1295                             faddr, *dwptr);
1296                         break;
1297                 }
1298
1299                 /* Do sector protect. */
1300                 if (ha->fdt_unprotect_sec_cmd &&
1301                     ((faddr & rest_addr) == rest_addr))
1302                         qla24xx_write_flash_dword(ha,
1303                             ha->fdt_protect_sec_cmd,
1304                             (fdata & 0xff00) | ((fdata << 16) &
1305                             0xff0000) | ((fdata >> 16) & 0xff));
1306         }
1307
1308         ret = qla24xx_protect_flash(vha);
1309         if (ret != QLA_SUCCESS)
1310                 ql_log(ql_log_warn, vha, 0x7099,
1311                     "Unable to protect flash after update.\n");
1312 done:
1313         if (optrom)
1314                 dma_free_coherent(&ha->pdev->dev,
1315                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1316
1317         return ret;
1318 }
1319
1320 uint8_t *
1321 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1322     uint32_t bytes)
1323 {
1324         uint32_t i;
1325         uint16_t *wptr;
1326         struct qla_hw_data *ha = vha->hw;
1327
1328         /* Word reads to NVRAM via registers. */
1329         wptr = (uint16_t *)buf;
1330         qla2x00_lock_nvram_access(ha);
1331         for (i = 0; i < bytes >> 1; i++, naddr++)
1332                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1333                     naddr));
1334         qla2x00_unlock_nvram_access(ha);
1335
1336         return buf;
1337 }
1338
1339 uint8_t *
1340 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1341     uint32_t bytes)
1342 {
1343         uint32_t i;
1344         uint32_t *dwptr;
1345         struct qla_hw_data *ha = vha->hw;
1346
1347         if (IS_P3P_TYPE(ha))
1348                 return  buf;
1349
1350         /* Dword reads to flash. */
1351         dwptr = (uint32_t *)buf;
1352         for (i = 0; i < bytes >> 2; i++, naddr++)
1353                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1354                     nvram_data_addr(ha, naddr)));
1355
1356         return buf;
1357 }
1358
1359 int
1360 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1361     uint32_t bytes)
1362 {
1363         int ret, stat;
1364         uint32_t i;
1365         uint16_t *wptr;
1366         unsigned long flags;
1367         struct qla_hw_data *ha = vha->hw;
1368
1369         ret = QLA_SUCCESS;
1370
1371         spin_lock_irqsave(&ha->hardware_lock, flags);
1372         qla2x00_lock_nvram_access(ha);
1373
1374         /* Disable NVRAM write-protection. */
1375         stat = qla2x00_clear_nvram_protection(ha);
1376
1377         wptr = (uint16_t *)buf;
1378         for (i = 0; i < bytes >> 1; i++, naddr++) {
1379                 qla2x00_write_nvram_word(ha, naddr,
1380                     cpu_to_le16(*wptr));
1381                 wptr++;
1382         }
1383
1384         /* Enable NVRAM write-protection. */
1385         qla2x00_set_nvram_protection(ha, stat);
1386
1387         qla2x00_unlock_nvram_access(ha);
1388         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1389
1390         return ret;
1391 }
1392
1393 int
1394 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1395     uint32_t bytes)
1396 {
1397         int ret;
1398         uint32_t i;
1399         uint32_t *dwptr;
1400         struct qla_hw_data *ha = vha->hw;
1401         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1402
1403         ret = QLA_SUCCESS;
1404
1405         if (IS_P3P_TYPE(ha))
1406                 return ret;
1407
1408         /* Enable flash write. */
1409         WRT_REG_DWORD(&reg->ctrl_status,
1410             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1411         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1412
1413         /* Disable NVRAM write-protection. */
1414         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1415         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1416
1417         /* Dword writes to flash. */
1418         dwptr = (uint32_t *)buf;
1419         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1420                 ret = qla24xx_write_flash_dword(ha,
1421                     nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1422                 if (ret != QLA_SUCCESS) {
1423                         ql_dbg(ql_dbg_user, vha, 0x709a,
1424                             "Unable to program nvram address=%x data=%x.\n",
1425                             naddr, *dwptr);
1426                         break;
1427                 }
1428         }
1429
1430         /* Enable NVRAM write-protection. */
1431         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1432
1433         /* Disable flash write. */
1434         WRT_REG_DWORD(&reg->ctrl_status,
1435             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1436         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1437
1438         return ret;
1439 }
1440
1441 uint8_t *
1442 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1443     uint32_t bytes)
1444 {
1445         uint32_t i;
1446         uint32_t *dwptr;
1447         struct qla_hw_data *ha = vha->hw;
1448
1449         /* Dword reads to flash. */
1450         dwptr = (uint32_t *)buf;
1451         for (i = 0; i < bytes >> 2; i++, naddr++)
1452                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1453                     flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1454
1455         return buf;
1456 }
1457
1458 int
1459 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1460     uint32_t bytes)
1461 {
1462         struct qla_hw_data *ha = vha->hw;
1463 #define RMW_BUFFER_SIZE (64 * 1024)
1464         uint8_t *dbuf;
1465
1466         dbuf = vmalloc(RMW_BUFFER_SIZE);
1467         if (!dbuf)
1468                 return QLA_MEMORY_ALLOC_FAILED;
1469         ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1470             RMW_BUFFER_SIZE);
1471         memcpy(dbuf + (naddr << 2), buf, bytes);
1472         ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1473             RMW_BUFFER_SIZE);
1474         vfree(dbuf);
1475
1476         return QLA_SUCCESS;
1477 }
1478
1479 static inline void
1480 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1481 {
1482         if (IS_QLA2322(ha)) {
1483                 /* Flip all colors. */
1484                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1485                         /* Turn off. */
1486                         ha->beacon_color_state = 0;
1487                         *pflags = GPIO_LED_ALL_OFF;
1488                 } else {
1489                         /* Turn on. */
1490                         ha->beacon_color_state = QLA_LED_ALL_ON;
1491                         *pflags = GPIO_LED_RGA_ON;
1492                 }
1493         } else {
1494                 /* Flip green led only. */
1495                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1496                         /* Turn off. */
1497                         ha->beacon_color_state = 0;
1498                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1499                 } else {
1500                         /* Turn on. */
1501                         ha->beacon_color_state = QLA_LED_GRN_ON;
1502                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1503                 }
1504         }
1505 }
1506
1507 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1508
1509 void
1510 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1511 {
1512         uint16_t gpio_enable;
1513         uint16_t gpio_data;
1514         uint16_t led_color = 0;
1515         unsigned long flags;
1516         struct qla_hw_data *ha = vha->hw;
1517         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1518
1519         if (IS_P3P_TYPE(ha))
1520                 return;
1521
1522         spin_lock_irqsave(&ha->hardware_lock, flags);
1523
1524         /* Save the Original GPIOE. */
1525         if (ha->pio_address) {
1526                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1527                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1528         } else {
1529                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1530                 gpio_data = RD_REG_WORD(&reg->gpiod);
1531         }
1532
1533         /* Set the modified gpio_enable values */
1534         gpio_enable |= GPIO_LED_MASK;
1535
1536         if (ha->pio_address) {
1537                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1538         } else {
1539                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1540                 RD_REG_WORD(&reg->gpioe);
1541         }
1542
1543         qla2x00_flip_colors(ha, &led_color);
1544
1545         /* Clear out any previously set LED color. */
1546         gpio_data &= ~GPIO_LED_MASK;
1547
1548         /* Set the new input LED color to GPIOD. */
1549         gpio_data |= led_color;
1550
1551         /* Set the modified gpio_data values */
1552         if (ha->pio_address) {
1553                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1554         } else {
1555                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1556                 RD_REG_WORD(&reg->gpiod);
1557         }
1558
1559         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1560 }
1561
1562 int
1563 qla2x00_beacon_on(struct scsi_qla_host *vha)
1564 {
1565         uint16_t gpio_enable;
1566         uint16_t gpio_data;
1567         unsigned long flags;
1568         struct qla_hw_data *ha = vha->hw;
1569         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1570
1571         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1572         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1573
1574         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1575                 ql_log(ql_log_warn, vha, 0x709b,
1576                     "Unable to update fw options (beacon on).\n");
1577                 return QLA_FUNCTION_FAILED;
1578         }
1579
1580         /* Turn off LEDs. */
1581         spin_lock_irqsave(&ha->hardware_lock, flags);
1582         if (ha->pio_address) {
1583                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1584                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1585         } else {
1586                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1587                 gpio_data = RD_REG_WORD(&reg->gpiod);
1588         }
1589         gpio_enable |= GPIO_LED_MASK;
1590
1591         /* Set the modified gpio_enable values. */
1592         if (ha->pio_address) {
1593                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1594         } else {
1595                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1596                 RD_REG_WORD(&reg->gpioe);
1597         }
1598
1599         /* Clear out previously set LED colour. */
1600         gpio_data &= ~GPIO_LED_MASK;
1601         if (ha->pio_address) {
1602                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1603         } else {
1604                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1605                 RD_REG_WORD(&reg->gpiod);
1606         }
1607         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1608
1609         /*
1610          * Let the per HBA timer kick off the blinking process based on
1611          * the following flags. No need to do anything else now.
1612          */
1613         ha->beacon_blink_led = 1;
1614         ha->beacon_color_state = 0;
1615
1616         return QLA_SUCCESS;
1617 }
1618
1619 int
1620 qla2x00_beacon_off(struct scsi_qla_host *vha)
1621 {
1622         int rval = QLA_SUCCESS;
1623         struct qla_hw_data *ha = vha->hw;
1624
1625         ha->beacon_blink_led = 0;
1626
1627         /* Set the on flag so when it gets flipped it will be off. */
1628         if (IS_QLA2322(ha))
1629                 ha->beacon_color_state = QLA_LED_ALL_ON;
1630         else
1631                 ha->beacon_color_state = QLA_LED_GRN_ON;
1632
1633         ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1634
1635         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1636         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1637
1638         rval = qla2x00_set_fw_options(vha, ha->fw_options);
1639         if (rval != QLA_SUCCESS)
1640                 ql_log(ql_log_warn, vha, 0x709c,
1641                     "Unable to update fw options (beacon off).\n");
1642         return rval;
1643 }
1644
1645
1646 static inline void
1647 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1648 {
1649         /* Flip all colors. */
1650         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1651                 /* Turn off. */
1652                 ha->beacon_color_state = 0;
1653                 *pflags = 0;
1654         } else {
1655                 /* Turn on. */
1656                 ha->beacon_color_state = QLA_LED_ALL_ON;
1657                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1658         }
1659 }
1660
1661 void
1662 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1663 {
1664         uint16_t led_color = 0;
1665         uint32_t gpio_data;
1666         unsigned long flags;
1667         struct qla_hw_data *ha = vha->hw;
1668         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1669
1670         /* Save the Original GPIOD. */
1671         spin_lock_irqsave(&ha->hardware_lock, flags);
1672         gpio_data = RD_REG_DWORD(&reg->gpiod);
1673
1674         /* Enable the gpio_data reg for update. */
1675         gpio_data |= GPDX_LED_UPDATE_MASK;
1676
1677         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1678         gpio_data = RD_REG_DWORD(&reg->gpiod);
1679
1680         /* Set the color bits. */
1681         qla24xx_flip_colors(ha, &led_color);
1682
1683         /* Clear out any previously set LED color. */
1684         gpio_data &= ~GPDX_LED_COLOR_MASK;
1685
1686         /* Set the new input LED color to GPIOD. */
1687         gpio_data |= led_color;
1688
1689         /* Set the modified gpio_data values. */
1690         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1691         gpio_data = RD_REG_DWORD(&reg->gpiod);
1692         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1693 }
1694
1695 static uint32_t
1696 qla83xx_select_led_port(struct qla_hw_data *ha)
1697 {
1698         uint32_t led_select_value = 0;
1699
1700         if (!IS_QLA83XX(ha))
1701                 goto out;
1702
1703         if (ha->port_no == 0)
1704                 led_select_value = QLA83XX_LED_PORT0;
1705         else
1706                 led_select_value = QLA83XX_LED_PORT1;
1707
1708 out:
1709         return led_select_value;
1710 }
1711
1712 void
1713 qla83xx_beacon_blink(struct scsi_qla_host *vha)
1714 {
1715         uint32_t led_select_value;
1716         struct qla_hw_data *ha = vha->hw;
1717         uint16_t led_cfg[6];
1718         uint16_t orig_led_cfg[6];
1719         uint32_t led_10_value, led_43_value;
1720
1721         if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha))
1722                 return;
1723
1724         if (!ha->beacon_blink_led)
1725                 return;
1726
1727         if (IS_QLA27XX(ha)) {
1728                 qla2x00_write_ram_word(vha, 0x1003, 0x40000230);
1729                 qla2x00_write_ram_word(vha, 0x1004, 0x40000230);
1730         } else if (IS_QLA2031(ha)) {
1731                 led_select_value = qla83xx_select_led_port(ha);
1732
1733                 qla83xx_wr_reg(vha, led_select_value, 0x40000230);
1734                 qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230);
1735         } else if (IS_QLA8031(ha)) {
1736                 led_select_value = qla83xx_select_led_port(ha);
1737
1738                 qla83xx_rd_reg(vha, led_select_value, &led_10_value);
1739                 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value);
1740                 qla83xx_wr_reg(vha, led_select_value, 0x01f44000);
1741                 msleep(500);
1742                 qla83xx_wr_reg(vha, led_select_value, 0x400001f4);
1743                 msleep(1000);
1744                 qla83xx_wr_reg(vha, led_select_value, led_10_value);
1745                 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value);
1746         } else if (IS_QLA81XX(ha)) {
1747                 int rval;
1748
1749                 /* Save Current */
1750                 rval = qla81xx_get_led_config(vha, orig_led_cfg);
1751                 /* Do the blink */
1752                 if (rval == QLA_SUCCESS) {
1753                         if (IS_QLA81XX(ha)) {
1754                                 led_cfg[0] = 0x4000;
1755                                 led_cfg[1] = 0x2000;
1756                                 led_cfg[2] = 0;
1757                                 led_cfg[3] = 0;
1758                                 led_cfg[4] = 0;
1759                                 led_cfg[5] = 0;
1760                         } else {
1761                                 led_cfg[0] = 0x4000;
1762                                 led_cfg[1] = 0x4000;
1763                                 led_cfg[2] = 0x4000;
1764                                 led_cfg[3] = 0x2000;
1765                                 led_cfg[4] = 0;
1766                                 led_cfg[5] = 0x2000;
1767                         }
1768                         rval = qla81xx_set_led_config(vha, led_cfg);
1769                         msleep(1000);
1770                         if (IS_QLA81XX(ha)) {
1771                                 led_cfg[0] = 0x4000;
1772                                 led_cfg[1] = 0x2000;
1773                                 led_cfg[2] = 0;
1774                         } else {
1775                                 led_cfg[0] = 0x4000;
1776                                 led_cfg[1] = 0x2000;
1777                                 led_cfg[2] = 0x4000;
1778                                 led_cfg[3] = 0x4000;
1779                                 led_cfg[4] = 0;
1780                                 led_cfg[5] = 0x2000;
1781                         }
1782                         rval = qla81xx_set_led_config(vha, led_cfg);
1783                 }
1784                 /* On exit, restore original (presumes no status change) */
1785                 qla81xx_set_led_config(vha, orig_led_cfg);
1786         }
1787 }
1788
1789 int
1790 qla24xx_beacon_on(struct scsi_qla_host *vha)
1791 {
1792         uint32_t gpio_data;
1793         unsigned long flags;
1794         struct qla_hw_data *ha = vha->hw;
1795         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1796
1797         if (IS_P3P_TYPE(ha))
1798                 return QLA_SUCCESS;
1799
1800         if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1801                 goto skip_gpio; /* let blink handle it */
1802
1803         if (ha->beacon_blink_led == 0) {
1804                 /* Enable firmware for update */
1805                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1806
1807                 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1808                         return QLA_FUNCTION_FAILED;
1809
1810                 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1811                     QLA_SUCCESS) {
1812                         ql_log(ql_log_warn, vha, 0x7009,
1813                             "Unable to update fw options (beacon on).\n");
1814                         return QLA_FUNCTION_FAILED;
1815                 }
1816
1817                 if (IS_QLA2031(ha) || IS_QLA27XX(ha))
1818                         goto skip_gpio;
1819
1820                 spin_lock_irqsave(&ha->hardware_lock, flags);
1821                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1822
1823                 /* Enable the gpio_data reg for update. */
1824                 gpio_data |= GPDX_LED_UPDATE_MASK;
1825                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1826                 RD_REG_DWORD(&reg->gpiod);
1827
1828                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1829         }
1830
1831         /* So all colors blink together. */
1832         ha->beacon_color_state = 0;
1833
1834 skip_gpio:
1835         /* Let the per HBA timer kick off the blinking process. */
1836         ha->beacon_blink_led = 1;
1837
1838         return QLA_SUCCESS;
1839 }
1840
1841 int
1842 qla24xx_beacon_off(struct scsi_qla_host *vha)
1843 {
1844         uint32_t gpio_data;
1845         unsigned long flags;
1846         struct qla_hw_data *ha = vha->hw;
1847         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1848
1849         if (IS_P3P_TYPE(ha))
1850                 return QLA_SUCCESS;
1851
1852         ha->beacon_blink_led = 0;
1853
1854         if (IS_QLA2031(ha) || IS_QLA27XX(ha))
1855                 goto set_fw_options;
1856
1857         if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1858                 return QLA_SUCCESS;
1859
1860         ha->beacon_color_state = QLA_LED_ALL_ON;
1861
1862         ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1863
1864         /* Give control back to firmware. */
1865         spin_lock_irqsave(&ha->hardware_lock, flags);
1866         gpio_data = RD_REG_DWORD(&reg->gpiod);
1867
1868         /* Disable the gpio_data reg for update. */
1869         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1870         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1871         RD_REG_DWORD(&reg->gpiod);
1872         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1873
1874 set_fw_options:
1875         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1876
1877         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1878                 ql_log(ql_log_warn, vha, 0x704d,
1879                     "Unable to update fw options (beacon on).\n");
1880                 return QLA_FUNCTION_FAILED;
1881         }
1882
1883         if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1884                 ql_log(ql_log_warn, vha, 0x704e,
1885                     "Unable to update fw options (beacon on).\n");
1886                 return QLA_FUNCTION_FAILED;
1887         }
1888
1889         return QLA_SUCCESS;
1890 }
1891
1892
1893 /*
1894  * Flash support routines
1895  */
1896
1897 /**
1898  * qla2x00_flash_enable() - Setup flash for reading and writing.
1899  * @ha: HA context
1900  */
1901 static void
1902 qla2x00_flash_enable(struct qla_hw_data *ha)
1903 {
1904         uint16_t data;
1905         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1906
1907         data = RD_REG_WORD(&reg->ctrl_status);
1908         data |= CSR_FLASH_ENABLE;
1909         WRT_REG_WORD(&reg->ctrl_status, data);
1910         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1911 }
1912
1913 /**
1914  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1915  * @ha: HA context
1916  */
1917 static void
1918 qla2x00_flash_disable(struct qla_hw_data *ha)
1919 {
1920         uint16_t data;
1921         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1922
1923         data = RD_REG_WORD(&reg->ctrl_status);
1924         data &= ~(CSR_FLASH_ENABLE);
1925         WRT_REG_WORD(&reg->ctrl_status, data);
1926         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1927 }
1928
1929 /**
1930  * qla2x00_read_flash_byte() - Reads a byte from flash
1931  * @ha: HA context
1932  * @addr: Address in flash to read
1933  *
1934  * A word is read from the chip, but, only the lower byte is valid.
1935  *
1936  * Returns the byte read from flash @addr.
1937  */
1938 static uint8_t
1939 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1940 {
1941         uint16_t data;
1942         uint16_t bank_select;
1943         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1944
1945         bank_select = RD_REG_WORD(&reg->ctrl_status);
1946
1947         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1948                 /* Specify 64K address range: */
1949                 /*  clear out Module Select and Flash Address bits [19:16]. */
1950                 bank_select &= ~0xf8;
1951                 bank_select |= addr >> 12 & 0xf0;
1952                 bank_select |= CSR_FLASH_64K_BANK;
1953                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1954                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1955
1956                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1957                 data = RD_REG_WORD(&reg->flash_data);
1958
1959                 return (uint8_t)data;
1960         }
1961
1962         /* Setup bit 16 of flash address. */
1963         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1964                 bank_select |= CSR_FLASH_64K_BANK;
1965                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1966                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1967         } else if (((addr & BIT_16) == 0) &&
1968             (bank_select & CSR_FLASH_64K_BANK)) {
1969                 bank_select &= ~(CSR_FLASH_64K_BANK);
1970                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1971                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1972         }
1973
1974         /* Always perform IO mapped accesses to the FLASH registers. */
1975         if (ha->pio_address) {
1976                 uint16_t data2;
1977
1978                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1979                 do {
1980                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1981                         barrier();
1982                         cpu_relax();
1983                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1984                 } while (data != data2);
1985         } else {
1986                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1987                 data = qla2x00_debounce_register(&reg->flash_data);
1988         }
1989
1990         return (uint8_t)data;
1991 }
1992
1993 /**
1994  * qla2x00_write_flash_byte() - Write a byte to flash
1995  * @ha: HA context
1996  * @addr: Address in flash to write
1997  * @data: Data to write
1998  */
1999 static void
2000 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
2001 {
2002         uint16_t bank_select;
2003         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2004
2005         bank_select = RD_REG_WORD(&reg->ctrl_status);
2006         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2007                 /* Specify 64K address range: */
2008                 /*  clear out Module Select and Flash Address bits [19:16]. */
2009                 bank_select &= ~0xf8;
2010                 bank_select |= addr >> 12 & 0xf0;
2011                 bank_select |= CSR_FLASH_64K_BANK;
2012                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
2013                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2014
2015                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
2016                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
2017                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
2018                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
2019
2020                 return;
2021         }
2022
2023         /* Setup bit 16 of flash address. */
2024         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
2025                 bank_select |= CSR_FLASH_64K_BANK;
2026                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
2027                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2028         } else if (((addr & BIT_16) == 0) &&
2029             (bank_select & CSR_FLASH_64K_BANK)) {
2030                 bank_select &= ~(CSR_FLASH_64K_BANK);
2031                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
2032                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2033         }
2034
2035         /* Always perform IO mapped accesses to the FLASH registers. */
2036         if (ha->pio_address) {
2037                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
2038                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
2039         } else {
2040                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
2041                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
2042                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
2043                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
2044         }
2045 }
2046
2047 /**
2048  * qla2x00_poll_flash() - Polls flash for completion.
2049  * @ha: HA context
2050  * @addr: Address in flash to poll
2051  * @poll_data: Data to be polled
2052  * @man_id: Flash manufacturer ID
2053  * @flash_id: Flash ID
2054  *
2055  * This function polls the device until bit 7 of what is read matches data
2056  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
2057  * out (a fatal error).  The flash book recommeds reading bit 7 again after
2058  * reading bit 5 as a 1.
2059  *
2060  * Returns 0 on success, else non-zero.
2061  */
2062 static int
2063 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
2064     uint8_t man_id, uint8_t flash_id)
2065 {
2066         int status;
2067         uint8_t flash_data;
2068         uint32_t cnt;
2069
2070         status = 1;
2071
2072         /* Wait for 30 seconds for command to finish. */
2073         poll_data &= BIT_7;
2074         for (cnt = 3000000; cnt; cnt--) {
2075                 flash_data = qla2x00_read_flash_byte(ha, addr);
2076                 if ((flash_data & BIT_7) == poll_data) {
2077                         status = 0;
2078                         break;
2079                 }
2080
2081                 if (man_id != 0x40 && man_id != 0xda) {
2082                         if ((flash_data & BIT_5) && cnt > 2)
2083                                 cnt = 2;
2084                 }
2085                 udelay(10);
2086                 barrier();
2087                 cond_resched();
2088         }
2089         return status;
2090 }
2091
2092 /**
2093  * qla2x00_program_flash_address() - Programs a flash address
2094  * @ha: HA context
2095  * @addr: Address in flash to program
2096  * @data: Data to be written in flash
2097  * @man_id: Flash manufacturer ID
2098  * @flash_id: Flash ID
2099  *
2100  * Returns 0 on success, else non-zero.
2101  */
2102 static int
2103 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
2104     uint8_t data, uint8_t man_id, uint8_t flash_id)
2105 {
2106         /* Write Program Command Sequence. */
2107         if (IS_OEM_001(ha)) {
2108                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2109                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2110                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
2111                 qla2x00_write_flash_byte(ha, addr, data);
2112         } else {
2113                 if (man_id == 0xda && flash_id == 0xc1) {
2114                         qla2x00_write_flash_byte(ha, addr, data);
2115                         if (addr & 0x7e)
2116                                 return 0;
2117                 } else {
2118                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2119                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2120                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
2121                         qla2x00_write_flash_byte(ha, addr, data);
2122                 }
2123         }
2124
2125         udelay(150);
2126
2127         /* Wait for write to complete. */
2128         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
2129 }
2130
2131 /**
2132  * qla2x00_erase_flash() - Erase the flash.
2133  * @ha: HA context
2134  * @man_id: Flash manufacturer ID
2135  * @flash_id: Flash ID
2136  *
2137  * Returns 0 on success, else non-zero.
2138  */
2139 static int
2140 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
2141 {
2142         /* Individual Sector Erase Command Sequence */
2143         if (IS_OEM_001(ha)) {
2144                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2145                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2146                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
2147                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2148                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2149                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
2150         } else {
2151                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2152                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2153                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2154                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2155                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2156                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
2157         }
2158
2159         udelay(150);
2160
2161         /* Wait for erase to complete. */
2162         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
2163 }
2164
2165 /**
2166  * qla2x00_erase_flash_sector() - Erase a flash sector.
2167  * @ha: HA context
2168  * @addr: Flash sector to erase
2169  * @sec_mask: Sector address mask
2170  * @man_id: Flash manufacturer ID
2171  * @flash_id: Flash ID
2172  *
2173  * Returns 0 on success, else non-zero.
2174  */
2175 static int
2176 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
2177     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
2178 {
2179         /* Individual Sector Erase Command Sequence */
2180         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2181         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2182         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2183         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2184         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2185         if (man_id == 0x1f && flash_id == 0x13)
2186                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2187         else
2188                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2189
2190         udelay(150);
2191
2192         /* Wait for erase to complete. */
2193         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2194 }
2195
2196 /**
2197  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2198  * @man_id: Flash manufacturer ID
2199  * @flash_id: Flash ID
2200  */
2201 static void
2202 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
2203     uint8_t *flash_id)
2204 {
2205         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2206         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2207         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2208         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2209         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2210         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2211         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2212         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2213 }
2214
2215 static void
2216 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2217         uint32_t saddr, uint32_t length)
2218 {
2219         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2220         uint32_t midpoint, ilength;
2221         uint8_t data;
2222
2223         midpoint = length / 2;
2224
2225         WRT_REG_WORD(&reg->nvram, 0);
2226         RD_REG_WORD(&reg->nvram);
2227         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2228                 if (ilength == midpoint) {
2229                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2230                         RD_REG_WORD(&reg->nvram);
2231                 }
2232                 data = qla2x00_read_flash_byte(ha, saddr);
2233                 if (saddr % 100)
2234                         udelay(10);
2235                 *tmp_buf = data;
2236                 cond_resched();
2237         }
2238 }
2239
2240 static inline void
2241 qla2x00_suspend_hba(struct scsi_qla_host *vha)
2242 {
2243         int cnt;
2244         unsigned long flags;
2245         struct qla_hw_data *ha = vha->hw;
2246         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2247
2248         /* Suspend HBA. */
2249         scsi_block_requests(vha->host);
2250         ha->isp_ops->disable_intrs(ha);
2251         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2252
2253         /* Pause RISC. */
2254         spin_lock_irqsave(&ha->hardware_lock, flags);
2255         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2256         RD_REG_WORD(&reg->hccr);
2257         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2258                 for (cnt = 0; cnt < 30000; cnt++) {
2259                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
2260                                 break;
2261                         udelay(100);
2262                 }
2263         } else {
2264                 udelay(10);
2265         }
2266         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2267 }
2268
2269 static inline void
2270 qla2x00_resume_hba(struct scsi_qla_host *vha)
2271 {
2272         struct qla_hw_data *ha = vha->hw;
2273
2274         /* Resume HBA. */
2275         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2276         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2277         qla2xxx_wake_dpc(vha);
2278         qla2x00_wait_for_chip_reset(vha);
2279         scsi_unblock_requests(vha->host);
2280 }
2281
2282 uint8_t *
2283 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2284     uint32_t offset, uint32_t length)
2285 {
2286         uint32_t addr, midpoint;
2287         uint8_t *data;
2288         struct qla_hw_data *ha = vha->hw;
2289         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2290
2291         /* Suspend HBA. */
2292         qla2x00_suspend_hba(vha);
2293
2294         /* Go with read. */
2295         midpoint = ha->optrom_size / 2;
2296
2297         qla2x00_flash_enable(ha);
2298         WRT_REG_WORD(&reg->nvram, 0);
2299         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
2300         for (addr = offset, data = buf; addr < length; addr++, data++) {
2301                 if (addr == midpoint) {
2302                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2303                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
2304                 }
2305
2306                 *data = qla2x00_read_flash_byte(ha, addr);
2307         }
2308         qla2x00_flash_disable(ha);
2309
2310         /* Resume HBA. */
2311         qla2x00_resume_hba(vha);
2312
2313         return buf;
2314 }
2315
2316 int
2317 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2318     uint32_t offset, uint32_t length)
2319 {
2320
2321         int rval;
2322         uint8_t man_id, flash_id, sec_number, data;
2323         uint16_t wd;
2324         uint32_t addr, liter, sec_mask, rest_addr;
2325         struct qla_hw_data *ha = vha->hw;
2326         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2327
2328         /* Suspend HBA. */
2329         qla2x00_suspend_hba(vha);
2330
2331         rval = QLA_SUCCESS;
2332         sec_number = 0;
2333
2334         /* Reset ISP chip. */
2335         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2336         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2337
2338         /* Go with write. */
2339         qla2x00_flash_enable(ha);
2340         do {    /* Loop once to provide quick error exit */
2341                 /* Structure of flash memory based on manufacturer */
2342                 if (IS_OEM_001(ha)) {
2343                         /* OEM variant with special flash part. */
2344                         man_id = flash_id = 0;
2345                         rest_addr = 0xffff;
2346                         sec_mask   = 0x10000;
2347                         goto update_flash;
2348                 }
2349                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2350                 switch (man_id) {
2351                 case 0x20: /* ST flash. */
2352                         if (flash_id == 0xd2 || flash_id == 0xe3) {
2353                                 /*
2354                                  * ST m29w008at part - 64kb sector size with
2355                                  * 32kb,8kb,8kb,16kb sectors at memory address
2356                                  * 0xf0000.
2357                                  */
2358                                 rest_addr = 0xffff;
2359                                 sec_mask = 0x10000;
2360                                 break;
2361                         }
2362                         /*
2363                          * ST m29w010b part - 16kb sector size
2364                          * Default to 16kb sectors
2365                          */
2366                         rest_addr = 0x3fff;
2367                         sec_mask = 0x1c000;
2368                         break;
2369                 case 0x40: /* Mostel flash. */
2370                         /* Mostel v29c51001 part - 512 byte sector size. */
2371                         rest_addr = 0x1ff;
2372                         sec_mask = 0x1fe00;
2373                         break;
2374                 case 0xbf: /* SST flash. */
2375                         /* SST39sf10 part - 4kb sector size. */
2376                         rest_addr = 0xfff;
2377                         sec_mask = 0x1f000;
2378                         break;
2379                 case 0xda: /* Winbond flash. */
2380                         /* Winbond W29EE011 part - 256 byte sector size. */
2381                         rest_addr = 0x7f;
2382                         sec_mask = 0x1ff80;
2383                         break;
2384                 case 0xc2: /* Macronix flash. */
2385                         /* 64k sector size. */
2386                         if (flash_id == 0x38 || flash_id == 0x4f) {
2387                                 rest_addr = 0xffff;
2388                                 sec_mask = 0x10000;
2389                                 break;
2390                         }
2391                         /* Fall through... */
2392
2393                 case 0x1f: /* Atmel flash. */
2394                         /* 512k sector size. */
2395                         if (flash_id == 0x13) {
2396                                 rest_addr = 0x7fffffff;
2397                                 sec_mask =   0x80000000;
2398                                 break;
2399                         }
2400                         /* Fall through... */
2401
2402                 case 0x01: /* AMD flash. */
2403                         if (flash_id == 0x38 || flash_id == 0x40 ||
2404                             flash_id == 0x4f) {
2405                                 /* Am29LV081 part - 64kb sector size. */
2406                                 /* Am29LV002BT part - 64kb sector size. */
2407                                 rest_addr = 0xffff;
2408                                 sec_mask = 0x10000;
2409                                 break;
2410                         } else if (flash_id == 0x3e) {
2411                                 /*
2412                                  * Am29LV008b part - 64kb sector size with
2413                                  * 32kb,8kb,8kb,16kb sector at memory address
2414                                  * h0xf0000.
2415                                  */
2416                                 rest_addr = 0xffff;
2417                                 sec_mask = 0x10000;
2418                                 break;
2419                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
2420                                 /*
2421                                  * Am29LV010 part or AM29f010 - 16kb sector
2422                                  * size.
2423                                  */
2424                                 rest_addr = 0x3fff;
2425                                 sec_mask = 0x1c000;
2426                                 break;
2427                         } else if (flash_id == 0x6d) {
2428                                 /* Am29LV001 part - 8kb sector size. */
2429                                 rest_addr = 0x1fff;
2430                                 sec_mask = 0x1e000;
2431                                 break;
2432                         }
2433                 default:
2434                         /* Default to 16 kb sector size. */
2435                         rest_addr = 0x3fff;
2436                         sec_mask = 0x1c000;
2437                         break;
2438                 }
2439
2440 update_flash:
2441                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2442                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2443                                 rval = QLA_FUNCTION_FAILED;
2444                                 break;
2445                         }
2446                 }
2447
2448                 for (addr = offset, liter = 0; liter < length; liter++,
2449                     addr++) {
2450                         data = buf[liter];
2451                         /* Are we at the beginning of a sector? */
2452                         if ((addr & rest_addr) == 0) {
2453                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2454                                         if (addr >= 0x10000UL) {
2455                                                 if (((addr >> 12) & 0xf0) &&
2456                                                     ((man_id == 0x01 &&
2457                                                         flash_id == 0x3e) ||
2458                                                      (man_id == 0x20 &&
2459                                                          flash_id == 0xd2))) {
2460                                                         sec_number++;
2461                                                         if (sec_number == 1) {
2462                                                                 rest_addr =
2463                                                                     0x7fff;
2464                                                                 sec_mask =
2465                                                                     0x18000;
2466                                                         } else if (
2467                                                             sec_number == 2 ||
2468                                                             sec_number == 3) {
2469                                                                 rest_addr =
2470                                                                     0x1fff;
2471                                                                 sec_mask =
2472                                                                     0x1e000;
2473                                                         } else if (
2474                                                             sec_number == 4) {
2475                                                                 rest_addr =
2476                                                                     0x3fff;
2477                                                                 sec_mask =
2478                                                                     0x1c000;
2479                                                         }
2480                                                 }
2481                                         }
2482                                 } else if (addr == ha->optrom_size / 2) {
2483                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2484                                         RD_REG_WORD(&reg->nvram);
2485                                 }
2486
2487                                 if (flash_id == 0xda && man_id == 0xc1) {
2488                                         qla2x00_write_flash_byte(ha, 0x5555,
2489                                             0xaa);
2490                                         qla2x00_write_flash_byte(ha, 0x2aaa,
2491                                             0x55);
2492                                         qla2x00_write_flash_byte(ha, 0x5555,
2493                                             0xa0);
2494                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2495                                         /* Then erase it */
2496                                         if (qla2x00_erase_flash_sector(ha,
2497                                             addr, sec_mask, man_id,
2498                                             flash_id)) {
2499                                                 rval = QLA_FUNCTION_FAILED;
2500                                                 break;
2501                                         }
2502                                         if (man_id == 0x01 && flash_id == 0x6d)
2503                                                 sec_number++;
2504                                 }
2505                         }
2506
2507                         if (man_id == 0x01 && flash_id == 0x6d) {
2508                                 if (sec_number == 1 &&
2509                                     addr == (rest_addr - 1)) {
2510                                         rest_addr = 0x0fff;
2511                                         sec_mask   = 0x1f000;
2512                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2513                                         rest_addr = 0x3fff;
2514                                         sec_mask   = 0x1c000;
2515                                 }
2516                         }
2517
2518                         if (qla2x00_program_flash_address(ha, addr, data,
2519                             man_id, flash_id)) {
2520                                 rval = QLA_FUNCTION_FAILED;
2521                                 break;
2522                         }
2523                         cond_resched();
2524                 }
2525         } while (0);
2526         qla2x00_flash_disable(ha);
2527
2528         /* Resume HBA. */
2529         qla2x00_resume_hba(vha);
2530
2531         return rval;
2532 }
2533
2534 uint8_t *
2535 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2536     uint32_t offset, uint32_t length)
2537 {
2538         struct qla_hw_data *ha = vha->hw;
2539
2540         /* Suspend HBA. */
2541         scsi_block_requests(vha->host);
2542         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2543
2544         /* Go with read. */
2545         qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2546
2547         /* Resume HBA. */
2548         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2549         scsi_unblock_requests(vha->host);
2550
2551         return buf;
2552 }
2553
2554 int
2555 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2556     uint32_t offset, uint32_t length)
2557 {
2558         int rval;
2559         struct qla_hw_data *ha = vha->hw;
2560
2561         /* Suspend HBA. */
2562         scsi_block_requests(vha->host);
2563         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2564
2565         /* Go with write. */
2566         rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2567             length >> 2);
2568
2569         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2570         scsi_unblock_requests(vha->host);
2571
2572         return rval;
2573 }
2574
2575 uint8_t *
2576 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2577     uint32_t offset, uint32_t length)
2578 {
2579         int rval;
2580         dma_addr_t optrom_dma;
2581         void *optrom;
2582         uint8_t *pbuf;
2583         uint32_t faddr, left, burst;
2584         struct qla_hw_data *ha = vha->hw;
2585
2586         if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
2587             IS_QLA27XX(ha))
2588                 goto try_fast;
2589         if (offset & 0xfff)
2590                 goto slow_read;
2591         if (length < OPTROM_BURST_SIZE)
2592                 goto slow_read;
2593
2594 try_fast:
2595         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2596             &optrom_dma, GFP_KERNEL);
2597         if (!optrom) {
2598                 ql_log(ql_log_warn, vha, 0x00cc,
2599                     "Unable to allocate memory for optrom burst read (%x KB).\n",
2600                     OPTROM_BURST_SIZE / 1024);
2601                 goto slow_read;
2602         }
2603
2604         pbuf = buf;
2605         faddr = offset >> 2;
2606         left = length >> 2;
2607         burst = OPTROM_BURST_DWORDS;
2608         while (left != 0) {
2609                 if (burst > left)
2610                         burst = left;
2611
2612                 rval = qla2x00_dump_ram(vha, optrom_dma,
2613                     flash_data_addr(ha, faddr), burst);
2614                 if (rval) {
2615                         ql_log(ql_log_warn, vha, 0x00f5,
2616                             "Unable to burst-read optrom segment (%x/%x/%llx).\n",
2617                             rval, flash_data_addr(ha, faddr),
2618                             (unsigned long long)optrom_dma);
2619                         ql_log(ql_log_warn, vha, 0x00f6,
2620                             "Reverting to slow-read.\n");
2621
2622                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2623                             optrom, optrom_dma);
2624                         goto slow_read;
2625                 }
2626
2627                 memcpy(pbuf, optrom, burst * 4);
2628
2629                 left -= burst;
2630                 faddr += burst;
2631                 pbuf += burst * 4;
2632         }
2633
2634         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2635             optrom_dma);
2636
2637         return buf;
2638
2639 slow_read:
2640     return qla24xx_read_optrom_data(vha, buf, offset, length);
2641 }
2642
2643 /**
2644  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2645  * @ha: HA context
2646  * @pcids: Pointer to the FCODE PCI data structure
2647  *
2648  * The process of retrieving the FCODE version information is at best
2649  * described as interesting.
2650  *
2651  * Within the first 100h bytes of the image an ASCII string is present
2652  * which contains several pieces of information including the FCODE
2653  * version.  Unfortunately it seems the only reliable way to retrieve
2654  * the version is by scanning for another sentinel within the string,
2655  * the FCODE build date:
2656  *
2657  *      ... 2.00.02 10/17/02 ...
2658  *
2659  * Returns QLA_SUCCESS on successful retrieval of version.
2660  */
2661 static void
2662 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2663 {
2664         int ret = QLA_FUNCTION_FAILED;
2665         uint32_t istart, iend, iter, vend;
2666         uint8_t do_next, rbyte, *vbyte;
2667
2668         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2669
2670         /* Skip the PCI data structure. */
2671         istart = pcids +
2672             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2673                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2674         iend = istart + 0x100;
2675         do {
2676                 /* Scan for the sentinel date string...eeewww. */
2677                 do_next = 0;
2678                 iter = istart;
2679                 while ((iter < iend) && !do_next) {
2680                         iter++;
2681                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2682                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2683                                     '/')
2684                                         do_next++;
2685                                 else if (qla2x00_read_flash_byte(ha,
2686                                     iter + 3) == '/')
2687                                         do_next++;
2688                         }
2689                 }
2690                 if (!do_next)
2691                         break;
2692
2693                 /* Backtrack to previous ' ' (space). */
2694                 do_next = 0;
2695                 while ((iter > istart) && !do_next) {
2696                         iter--;
2697                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2698                                 do_next++;
2699                 }
2700                 if (!do_next)
2701                         break;
2702
2703                 /*
2704                  * Mark end of version tag, and find previous ' ' (space) or
2705                  * string length (recent FCODE images -- major hack ahead!!!).
2706                  */
2707                 vend = iter - 1;
2708                 do_next = 0;
2709                 while ((iter > istart) && !do_next) {
2710                         iter--;
2711                         rbyte = qla2x00_read_flash_byte(ha, iter);
2712                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2713                                 do_next++;
2714                 }
2715                 if (!do_next)
2716                         break;
2717
2718                 /* Mark beginning of version tag, and copy data. */
2719                 iter++;
2720                 if ((vend - iter) &&
2721                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2722                         vbyte = ha->fcode_revision;
2723                         while (iter <= vend) {
2724                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2725                                 iter++;
2726                         }
2727                         ret = QLA_SUCCESS;
2728                 }
2729         } while (0);
2730
2731         if (ret != QLA_SUCCESS)
2732                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2733 }
2734
2735 int
2736 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2737 {
2738         int ret = QLA_SUCCESS;
2739         uint8_t code_type, last_image;
2740         uint32_t pcihdr, pcids;
2741         uint8_t *dbyte;
2742         uint16_t *dcode;
2743         struct qla_hw_data *ha = vha->hw;
2744
2745         if (!ha->pio_address || !mbuf)
2746                 return QLA_FUNCTION_FAILED;
2747
2748         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2749         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2750         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2751         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2752
2753         qla2x00_flash_enable(ha);
2754
2755         /* Begin with first PCI expansion ROM header. */
2756         pcihdr = 0;
2757         last_image = 1;
2758         do {
2759                 /* Verify PCI expansion ROM header. */
2760                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2761                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2762                         /* No signature */
2763                         ql_log(ql_log_fatal, vha, 0x0050,
2764                             "No matching ROM signature.\n");
2765                         ret = QLA_FUNCTION_FAILED;
2766                         break;
2767                 }
2768
2769                 /* Locate PCI data structure. */
2770                 pcids = pcihdr +
2771                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2772                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2773
2774                 /* Validate signature of PCI data structure. */
2775                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2776                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2777                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2778                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2779                         /* Incorrect header. */
2780                         ql_log(ql_log_fatal, vha, 0x0051,
2781                             "PCI data struct not found pcir_adr=%x.\n", pcids);
2782                         ret = QLA_FUNCTION_FAILED;
2783                         break;
2784                 }
2785
2786                 /* Read version */
2787                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2788                 switch (code_type) {
2789                 case ROM_CODE_TYPE_BIOS:
2790                         /* Intel x86, PC-AT compatible. */
2791                         ha->bios_revision[0] =
2792                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2793                         ha->bios_revision[1] =
2794                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2795                         ql_dbg(ql_dbg_init, vha, 0x0052,
2796                             "Read BIOS %d.%d.\n",
2797                             ha->bios_revision[1], ha->bios_revision[0]);
2798                         break;
2799                 case ROM_CODE_TYPE_FCODE:
2800                         /* Open Firmware standard for PCI (FCode). */
2801                         /* Eeeewww... */
2802                         qla2x00_get_fcode_version(ha, pcids);
2803                         break;
2804                 case ROM_CODE_TYPE_EFI:
2805                         /* Extensible Firmware Interface (EFI). */
2806                         ha->efi_revision[0] =
2807                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2808                         ha->efi_revision[1] =
2809                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2810                         ql_dbg(ql_dbg_init, vha, 0x0053,
2811                             "Read EFI %d.%d.\n",
2812                             ha->efi_revision[1], ha->efi_revision[0]);
2813                         break;
2814                 default:
2815                         ql_log(ql_log_warn, vha, 0x0054,
2816                             "Unrecognized code type %x at pcids %x.\n",
2817                             code_type, pcids);
2818                         break;
2819                 }
2820
2821                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2822
2823                 /* Locate next PCI expansion ROM. */
2824                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2825                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2826         } while (!last_image);
2827
2828         if (IS_QLA2322(ha)) {
2829                 /* Read firmware image information. */
2830                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2831                 dbyte = mbuf;
2832                 memset(dbyte, 0, 8);
2833                 dcode = (uint16_t *)dbyte;
2834
2835                 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2836                     8);
2837                 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
2838                     "Dumping fw "
2839                     "ver from flash:.\n");
2840                 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
2841                     (uint8_t *)dbyte, 8);
2842
2843                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2844                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2845                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2846                     dcode[3] == 0)) {
2847                         ql_log(ql_log_warn, vha, 0x0057,
2848                             "Unrecognized fw revision at %x.\n",
2849                             ha->flt_region_fw * 4);
2850                 } else {
2851                         /* values are in big endian */
2852                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2853                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2854                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2855                         ql_dbg(ql_dbg_init, vha, 0x0058,
2856                             "FW Version: "
2857                             "%d.%d.%d.\n", ha->fw_revision[0],
2858                             ha->fw_revision[1], ha->fw_revision[2]);
2859                 }
2860         }
2861
2862         qla2x00_flash_disable(ha);
2863
2864         return ret;
2865 }
2866
2867 int
2868 qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2869 {
2870         int ret = QLA_SUCCESS;
2871         uint32_t pcihdr, pcids;
2872         uint32_t *dcode;
2873         uint8_t *bcode;
2874         uint8_t code_type, last_image;
2875         struct qla_hw_data *ha = vha->hw;
2876
2877         if (!mbuf)
2878                 return QLA_FUNCTION_FAILED;
2879
2880         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2881         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2882         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2883         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2884
2885         dcode = mbuf;
2886
2887         /* Begin with first PCI expansion ROM header. */
2888         pcihdr = ha->flt_region_boot << 2;
2889         last_image = 1;
2890         do {
2891                 /* Verify PCI expansion ROM header. */
2892                 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcihdr,
2893                     0x20 * 4);
2894                 bcode = mbuf + (pcihdr % 4);
2895                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2896                         /* No signature */
2897                         ql_log(ql_log_fatal, vha, 0x0154,
2898                             "No matching ROM signature.\n");
2899                         ret = QLA_FUNCTION_FAILED;
2900                         break;
2901                 }
2902
2903                 /* Locate PCI data structure. */
2904                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2905
2906                 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcids,
2907                     0x20 * 4);
2908                 bcode = mbuf + (pcihdr % 4);
2909
2910                 /* Validate signature of PCI data structure. */
2911                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2912                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2913                         /* Incorrect header. */
2914                         ql_log(ql_log_fatal, vha, 0x0155,
2915                             "PCI data struct not found pcir_adr=%x.\n", pcids);
2916                         ret = QLA_FUNCTION_FAILED;
2917                         break;
2918                 }
2919
2920                 /* Read version */
2921                 code_type = bcode[0x14];
2922                 switch (code_type) {
2923                 case ROM_CODE_TYPE_BIOS:
2924                         /* Intel x86, PC-AT compatible. */
2925                         ha->bios_revision[0] = bcode[0x12];
2926                         ha->bios_revision[1] = bcode[0x13];
2927                         ql_dbg(ql_dbg_init, vha, 0x0156,
2928                             "Read BIOS %d.%d.\n",
2929                             ha->bios_revision[1], ha->bios_revision[0]);
2930                         break;
2931                 case ROM_CODE_TYPE_FCODE:
2932                         /* Open Firmware standard for PCI (FCode). */
2933                         ha->fcode_revision[0] = bcode[0x12];
2934                         ha->fcode_revision[1] = bcode[0x13];
2935                         ql_dbg(ql_dbg_init, vha, 0x0157,
2936                             "Read FCODE %d.%d.\n",
2937                             ha->fcode_revision[1], ha->fcode_revision[0]);
2938                         break;
2939                 case ROM_CODE_TYPE_EFI:
2940                         /* Extensible Firmware Interface (EFI). */
2941                         ha->efi_revision[0] = bcode[0x12];
2942                         ha->efi_revision[1] = bcode[0x13];
2943                         ql_dbg(ql_dbg_init, vha, 0x0158,
2944                             "Read EFI %d.%d.\n",
2945                             ha->efi_revision[1], ha->efi_revision[0]);
2946                         break;
2947                 default:
2948                         ql_log(ql_log_warn, vha, 0x0159,
2949                             "Unrecognized code type %x at pcids %x.\n",
2950                             code_type, pcids);
2951                         break;
2952                 }
2953
2954                 last_image = bcode[0x15] & BIT_7;
2955
2956                 /* Locate next PCI expansion ROM. */
2957                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2958         } while (!last_image);
2959
2960         /* Read firmware image information. */
2961         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2962         dcode = mbuf;
2963         ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, ha->flt_region_fw << 2,
2964             0x20);
2965         bcode = mbuf + (pcihdr % 4);
2966
2967         /* Validate signature of PCI data structure. */
2968         if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 &&
2969             bcode[0x2] == 0x40 && bcode[0x3] == 0x40) {
2970                 ha->fw_revision[0] = bcode[0x4];
2971                 ha->fw_revision[1] = bcode[0x5];
2972                 ha->fw_revision[2] = bcode[0x6];
2973                 ql_dbg(ql_dbg_init, vha, 0x0153,
2974                     "Firmware revision %d.%d.%d\n",
2975                     ha->fw_revision[0], ha->fw_revision[1],
2976                     ha->fw_revision[2]);
2977         }
2978
2979         return ret;
2980 }
2981
2982 int
2983 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2984 {
2985         int ret = QLA_SUCCESS;
2986         uint32_t pcihdr, pcids;
2987         uint32_t *dcode;
2988         uint8_t *bcode;
2989         uint8_t code_type, last_image;
2990         int i;
2991         struct qla_hw_data *ha = vha->hw;
2992
2993         if (IS_P3P_TYPE(ha))
2994                 return ret;
2995
2996         if (!mbuf)
2997                 return QLA_FUNCTION_FAILED;
2998
2999         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
3000         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
3001         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3002         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3003
3004         dcode = mbuf;
3005
3006         /* Begin with first PCI expansion ROM header. */
3007         pcihdr = ha->flt_region_boot << 2;
3008         last_image = 1;
3009         do {
3010                 /* Verify PCI expansion ROM header. */
3011                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
3012                 bcode = mbuf + (pcihdr % 4);
3013                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
3014                         /* No signature */
3015                         ql_log(ql_log_fatal, vha, 0x0059,
3016                             "No matching ROM signature.\n");
3017                         ret = QLA_FUNCTION_FAILED;
3018                         break;
3019                 }
3020
3021                 /* Locate PCI data structure. */
3022                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
3023
3024                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
3025                 bcode = mbuf + (pcihdr % 4);
3026
3027                 /* Validate signature of PCI data structure. */
3028                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
3029                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
3030                         /* Incorrect header. */
3031                         ql_log(ql_log_fatal, vha, 0x005a,
3032                             "PCI data struct not found pcir_adr=%x.\n", pcids);
3033                         ret = QLA_FUNCTION_FAILED;
3034                         break;
3035                 }
3036
3037                 /* Read version */
3038                 code_type = bcode[0x14];
3039                 switch (code_type) {
3040                 case ROM_CODE_TYPE_BIOS:
3041                         /* Intel x86, PC-AT compatible. */
3042                         ha->bios_revision[0] = bcode[0x12];
3043                         ha->bios_revision[1] = bcode[0x13];
3044                         ql_dbg(ql_dbg_init, vha, 0x005b,
3045                             "Read BIOS %d.%d.\n",
3046                             ha->bios_revision[1], ha->bios_revision[0]);
3047                         break;
3048                 case ROM_CODE_TYPE_FCODE:
3049                         /* Open Firmware standard for PCI (FCode). */
3050                         ha->fcode_revision[0] = bcode[0x12];
3051                         ha->fcode_revision[1] = bcode[0x13];
3052                         ql_dbg(ql_dbg_init, vha, 0x005c,
3053                             "Read FCODE %d.%d.\n",
3054                             ha->fcode_revision[1], ha->fcode_revision[0]);
3055                         break;
3056                 case ROM_CODE_TYPE_EFI:
3057                         /* Extensible Firmware Interface (EFI). */
3058                         ha->efi_revision[0] = bcode[0x12];
3059                         ha->efi_revision[1] = bcode[0x13];
3060                         ql_dbg(ql_dbg_init, vha, 0x005d,
3061                             "Read EFI %d.%d.\n",
3062                             ha->efi_revision[1], ha->efi_revision[0]);
3063                         break;
3064                 default:
3065                         ql_log(ql_log_warn, vha, 0x005e,
3066                             "Unrecognized code type %x at pcids %x.\n",
3067                             code_type, pcids);
3068                         break;
3069                 }
3070
3071                 last_image = bcode[0x15] & BIT_7;
3072
3073                 /* Locate next PCI expansion ROM. */
3074                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
3075         } while (!last_image);
3076
3077         /* Read firmware image information. */
3078         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3079         dcode = mbuf;
3080
3081         qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
3082         for (i = 0; i < 4; i++)
3083                 dcode[i] = be32_to_cpu(dcode[i]);
3084
3085         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
3086             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
3087             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
3088             dcode[3] == 0)) {
3089                 ql_log(ql_log_warn, vha, 0x005f,
3090                     "Unrecognized fw revision at %x.\n",
3091                     ha->flt_region_fw * 4);
3092         } else {
3093                 ha->fw_revision[0] = dcode[0];
3094                 ha->fw_revision[1] = dcode[1];
3095                 ha->fw_revision[2] = dcode[2];
3096                 ha->fw_revision[3] = dcode[3];
3097                 ql_dbg(ql_dbg_init, vha, 0x0060,
3098                     "Firmware revision %d.%d.%d (%x).\n",
3099                     ha->fw_revision[0], ha->fw_revision[1],
3100                     ha->fw_revision[2], ha->fw_revision[3]);
3101         }
3102
3103         /* Check for golden firmware and get version if available */
3104         if (!IS_QLA81XX(ha)) {
3105                 /* Golden firmware is not present in non 81XX adapters */
3106                 return ret;
3107         }
3108
3109         memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
3110         dcode = mbuf;
3111         ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
3112             ha->flt_region_gold_fw << 2, 32);
3113
3114         if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
3115             dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
3116                 ql_log(ql_log_warn, vha, 0x0056,
3117                     "Unrecognized golden fw at 0x%x.\n",
3118                     ha->flt_region_gold_fw * 4);
3119                 return ret;
3120         }
3121
3122         for (i = 4; i < 8; i++)
3123                 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
3124
3125         return ret;
3126 }
3127
3128 static int
3129 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
3130 {
3131         if (pos >= end || *pos != 0x82)
3132                 return 0;
3133
3134         pos += 3 + pos[1];
3135         if (pos >= end || *pos != 0x90)
3136                 return 0;
3137
3138         pos += 3 + pos[1];
3139         if (pos >= end || *pos != 0x78)
3140                 return 0;
3141
3142         return 1;
3143 }
3144
3145 int
3146 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
3147 {
3148         struct qla_hw_data *ha = vha->hw;
3149         uint8_t *pos = ha->vpd;
3150         uint8_t *end = pos + ha->vpd_size;
3151         int len = 0;
3152
3153         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
3154                 return 0;
3155
3156         while (pos < end && *pos != 0x78) {
3157                 len = (*pos == 0x82) ? pos[1] : pos[2];
3158
3159                 if (!strncmp(pos, key, strlen(key)))
3160                         break;
3161
3162                 if (*pos != 0x90 && *pos != 0x91)
3163                         pos += len;
3164
3165                 pos += 3;
3166         }
3167
3168         if (pos < end - len && *pos != 0x78)
3169                 return scnprintf(str, size, "%.*s", len, pos + 3);
3170
3171         return 0;
3172 }
3173
3174 int
3175 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
3176 {
3177         int len, max_len;
3178         uint32_t fcp_prio_addr;
3179         struct qla_hw_data *ha = vha->hw;
3180
3181         if (!ha->fcp_prio_cfg) {
3182                 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
3183                 if (!ha->fcp_prio_cfg) {
3184                         ql_log(ql_log_warn, vha, 0x00d5,
3185                             "Unable to allocate memory for fcp priorty data (%x).\n",
3186                             FCP_PRIO_CFG_SIZE);
3187                         return QLA_FUNCTION_FAILED;
3188                 }
3189         }
3190         memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
3191
3192         fcp_prio_addr = ha->flt_region_fcp_prio;
3193
3194         /* first read the fcp priority data header from flash */
3195         ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
3196                         fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
3197
3198         if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
3199                 goto fail;
3200
3201         /* read remaining FCP CMD config data from flash */
3202         fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
3203         len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
3204         max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
3205
3206         ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
3207                         fcp_prio_addr << 2, (len < max_len ? len : max_len));
3208
3209         /* revalidate the entire FCP priority config data, including entries */
3210         if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
3211                 goto fail;
3212
3213         ha->flags.fcp_prio_enabled = 1;
3214         return QLA_SUCCESS;
3215 fail:
3216         vfree(ha->fcp_prio_cfg);
3217         ha->fcp_prio_cfg = NULL;
3218         return QLA_FUNCTION_FAILED;
3219 }