kernel/drivers/scsi/pm8001/pm8001_hwi.c

   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm8001_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 /**
  47  * read_main_config_table - read the configure table and save it.
  48  * @pm8001_ha: our hba card information
  49  */
  50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  51 {
  52         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  53         pm8001_ha->main_cfg_tbl.pm8001_tbl.signature    =
  54                                 pm8001_mr32(address, 0x00);
  55         pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
  56                                 pm8001_mr32(address, 0x04);
  57         pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
  58                                 pm8001_mr32(address, 0x08);
  59         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io   =
  60                                 pm8001_mr32(address, 0x0C);
  61         pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl      =
  62                                 pm8001_mr32(address, 0x10);
  63         pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
  64                                 pm8001_mr32(address, 0x14);
  65         pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset   =
  66                                 pm8001_mr32(address, 0x18);
  67         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
  68                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  69         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
  70                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  71         pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag        =
  72                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  73
  74         /* read analog Setting offset from the configuration table */
  75         pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
  76                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  77
  78         /* read Error Dump Offset and Length */
  79         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
  80                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  81         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
  82                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  83         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
  84                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  85         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
  86                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  87 }
  88
  89 /**
  90  * read_general_status_table - read the general status table and save it.
  91  * @pm8001_ha: our hba card information
  92  */
  93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  94 {
  95         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  96         pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate   =
  97                                 pm8001_mr32(address, 0x00);
  98         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0   =
  99                                 pm8001_mr32(address, 0x04);
 100         pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1   =
 101                                 pm8001_mr32(address, 0x08);
 102         pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt          =
 103                                 pm8001_mr32(address, 0x0C);
 104         pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt           =
 105                                 pm8001_mr32(address, 0x10);
 106         pm8001_ha->gs_tbl.pm8001_tbl.rsvd               =
 107                                 pm8001_mr32(address, 0x14);
 108         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0]       =
 109                                 pm8001_mr32(address, 0x18);
 110         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1]       =
 111                                 pm8001_mr32(address, 0x1C);
 112         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2]       =
 113                                 pm8001_mr32(address, 0x20);
 114         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3]       =
 115                                 pm8001_mr32(address, 0x24);
 116         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4]       =
 117                                 pm8001_mr32(address, 0x28);
 118         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5]       =
 119                                 pm8001_mr32(address, 0x2C);
 120         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6]       =
 121                                 pm8001_mr32(address, 0x30);
 122         pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7]       =
 123                                 pm8001_mr32(address, 0x34);
 124         pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val     =
 125                                 pm8001_mr32(address, 0x38);
 126         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0]           =
 127                                 pm8001_mr32(address, 0x3C);
 128         pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1]           =
 129                                 pm8001_mr32(address, 0x40);
 130         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0]        =
 131                                 pm8001_mr32(address, 0x44);
 132         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1]        =
 133                                 pm8001_mr32(address, 0x48);
 134         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2]        =
 135                                 pm8001_mr32(address, 0x4C);
 136         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3]        =
 137                                 pm8001_mr32(address, 0x50);
 138         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4]        =
 139                                 pm8001_mr32(address, 0x54);
 140         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5]        =
 141                                 pm8001_mr32(address, 0x58);
 142         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6]        =
 143                                 pm8001_mr32(address, 0x5C);
 144         pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7]        =
 145                                 pm8001_mr32(address, 0x60);
 146 }
 147
 148 /**
 149  * read_inbnd_queue_table - read the inbound queue table and save it.
 150  * @pm8001_ha: our hba card information
 151  */
 152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 153 {
 154         int i;
 155         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 156         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 157                 u32 offset = i * 0x20;
 158                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 159                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 160                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 161                         pm8001_mr32(address, (offset + 0x18));
 162         }
 163 }
 164
 165 /**
 166  * read_outbnd_queue_table - read the outbound queue table and save it.
 167  * @pm8001_ha: our hba card information
 168  */
 169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 170 {
 171         int i;
 172         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 173         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 174                 u32 offset = i * 0x24;
 175                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 176                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 177                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 178                         pm8001_mr32(address, (offset + 0x18));
 179         }
 180 }
 181
 182 /**
 183  * init_default_table_values - init the default table.
 184  * @pm8001_ha: our hba card information
 185  */
 186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 187 {
 188         int i;
 189         u32 offsetib, offsetob;
 190         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 191         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 192
 193         pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd          = 0;
 194         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3     = 0;
 195         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7     = 0;
 196         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3    = 0;
 197         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7    = 0;
 198         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
 199                                                                          0;
 200         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
 201                                                                          0;
 202         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
 203         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
 204         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
 205         pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
 206
 207         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr         =
 208                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 209         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr         =
 210                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 211         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size               =
 212                 PM8001_EVENT_LOG_SIZE;
 213         pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option             = 0x01;
 214         pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr     =
 215                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 216         pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr     =
 217                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 218         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size           =
 219                 PM8001_EVENT_LOG_SIZE;
 220         pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option         = 0x01;
 221         pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt          = 0x01;
 222         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 223                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 224                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 225                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 226                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 227                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 228                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 229                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 230                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 231                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 232                         pm8001_ha->memoryMap.region[IB + i].total_len;
 233                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 234                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 235                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 236                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 237                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 238                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 239                 offsetib = i * 0x20;
 240                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 241                         get_pci_bar_index(pm8001_mr32(addressib,
 242                                 (offsetib + 0x14)));
 243                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 244                         pm8001_mr32(addressib, (offsetib + 0x18));
 245                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 246                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 247         }
 248         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 249                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 250                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 251                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 252                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 253                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 254                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 255                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 256                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 257                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 258                         pm8001_ha->memoryMap.region[OB + i].total_len;
 259                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 260                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 261                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 262                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 263                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 264                         0 | (10 << 16) | (i << 24);
 265                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 266                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 267                 offsetob = i * 0x24;
 268                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 269                         get_pci_bar_index(pm8001_mr32(addressob,
 270                         offsetob + 0x14));
 271                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 272                         pm8001_mr32(addressob, (offsetob + 0x18));
 273                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 274                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 275         }
 276 }
 277
 278 /**
 279  * update_main_config_table - update the main default table to the HBA.
 280  * @pm8001_ha: our hba card information
 281  */
 282 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 283 {
 284         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 285         pm8001_mw32(address, 0x24,
 286                 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
 287         pm8001_mw32(address, 0x28,
 288                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
 289         pm8001_mw32(address, 0x2C,
 290                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
 291         pm8001_mw32(address, 0x30,
 292                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
 293         pm8001_mw32(address, 0x34,
 294                 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
 295         pm8001_mw32(address, 0x38,
 296                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 297                                         outbound_tgt_ITNexus_event_pid0_3);
 298         pm8001_mw32(address, 0x3C,
 299                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 300                                         outbound_tgt_ITNexus_event_pid4_7);
 301         pm8001_mw32(address, 0x40,
 302                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 303                                         outbound_tgt_ssp_event_pid0_3);
 304         pm8001_mw32(address, 0x44,
 305                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 306                                         outbound_tgt_ssp_event_pid4_7);
 307         pm8001_mw32(address, 0x48,
 308                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 309                                         outbound_tgt_smp_event_pid0_3);
 310         pm8001_mw32(address, 0x4C,
 311                 pm8001_ha->main_cfg_tbl.pm8001_tbl.
 312                                         outbound_tgt_smp_event_pid4_7);
 313         pm8001_mw32(address, 0x50,
 314                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
 315         pm8001_mw32(address, 0x54,
 316                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
 317         pm8001_mw32(address, 0x58,
 318                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
 319         pm8001_mw32(address, 0x5C,
 320                 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
 321         pm8001_mw32(address, 0x60,
 322                 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
 323         pm8001_mw32(address, 0x64,
 324                 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
 325         pm8001_mw32(address, 0x68,
 326                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
 327         pm8001_mw32(address, 0x6C,
 328                 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
 329         pm8001_mw32(address, 0x70,
 330                 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
 331 }
 332
 333 /**
 334  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 335  * @pm8001_ha: our hba card information
 336  */
 337 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 338                                      int number)
 339 {
 340         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 341         u16 offset = number * 0x20;
 342         pm8001_mw32(address, offset + 0x00,
 343                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 344         pm8001_mw32(address, offset + 0x04,
 345                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 346         pm8001_mw32(address, offset + 0x08,
 347                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 348         pm8001_mw32(address, offset + 0x0C,
 349                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 350         pm8001_mw32(address, offset + 0x10,
 351                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 352 }
 353
 354 /**
 355  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 356  * @pm8001_ha: our hba card information
 357  */
 358 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 359                                       int number)
 360 {
 361         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 362         u16 offset = number * 0x24;
 363         pm8001_mw32(address, offset + 0x00,
 364                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 365         pm8001_mw32(address, offset + 0x04,
 366                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 367         pm8001_mw32(address, offset + 0x08,
 368                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 369         pm8001_mw32(address, offset + 0x0C,
 370                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 371         pm8001_mw32(address, offset + 0x10,
 372                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 373         pm8001_mw32(address, offset + 0x1C,
 374                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 375 }
 376
 377 /**
 378  * pm8001_bar4_shift - function is called to shift BAR base address
 379  * @pm8001_ha : our hba card infomation
 380  * @shiftValue : shifting value in memory bar.
 381  */
 382 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 383 {
 384         u32 regVal;
 385         unsigned long start;
 386
 387         /* program the inbound AXI translation Lower Address */
 388         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 389
 390         /* confirm the setting is written */
 391         start = jiffies + HZ; /* 1 sec */
 392         do {
 393                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 394         } while ((regVal != shiftValue) && time_before(jiffies, start));
 395
 396         if (regVal != shiftValue) {
 397                 PM8001_INIT_DBG(pm8001_ha,
 398                         pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
 399                         " = 0x%x\n", regVal));
 400                 return -1;
 401         }
 402         return 0;
 403 }
 404
 405 /**
 406  * mpi_set_phys_g3_with_ssc
 407  * @pm8001_ha: our hba card information
 408  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 409  */
 410 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
 411                                      u32 SSCbit)
 412 {
 413         u32 value, offset, i;
 414         unsigned long flags;
 415
 416 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 417 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 418 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 419 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 420 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 421 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
 422 #define SNW3_PHY_CAPABILITIES_PARITY 31
 423
 424    /*
 425     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 426     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 427     */
 428         spin_lock_irqsave(&pm8001_ha->lock, flags);
 429         if (-1 == pm8001_bar4_shift(pm8001_ha,
 430                                 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
 431                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 432                 return;
 433         }
 434
 435         for (i = 0; i < 4; i++) {
 436                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 437                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 438         }
 439         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 440         if (-1 == pm8001_bar4_shift(pm8001_ha,
 441                                 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
 442                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 443                 return;
 444         }
 445         for (i = 4; i < 8; i++) {
 446                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 447                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 448         }
 449         /*************************************************************
 450         Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 451         Device MABC SMOD0 Controls
 452         Address: (via MEMBASE-III):
 453         Using shifted destination address 0x0_0000: with Offset 0xD8
 454
 455         31:28 R/W Reserved Do not change
 456         27:24 R/W SAS_SMOD_SPRDUP 0000
 457         23:20 R/W SAS_SMOD_SPRDDN 0000
 458         19:0  R/W  Reserved Do not change
 459         Upon power-up this register will read as 0x8990c016,
 460         and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 461         so that the written value will be 0x8090c016.
 462         This will ensure only down-spreading SSC is enabled on the SPC.
 463         *************************************************************/
 464         value = pm8001_cr32(pm8001_ha, 2, 0xd8);
 465         pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 466
 467         /*set the shifted destination address to 0x0 to avoid error operation */
 468         pm8001_bar4_shift(pm8001_ha, 0x0);
 469         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 470         return;
 471 }
 472
 473 /**
 474  * mpi_set_open_retry_interval_reg
 475  * @pm8001_ha: our hba card information
 476  * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 477  */
 478 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 479                                             u32 interval)
 480 {
 481         u32 offset;
 482         u32 value;
 483         u32 i;
 484         unsigned long flags;
 485
 486 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 487 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 488 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 489 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 490 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 491
 492         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 493         spin_lock_irqsave(&pm8001_ha->lock, flags);
 494         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 495         if (-1 == pm8001_bar4_shift(pm8001_ha,
 496                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
 497                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 498                 return;
 499         }
 500         for (i = 0; i < 4; i++) {
 501                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 502                 pm8001_cw32(pm8001_ha, 2, offset, value);
 503         }
 504
 505         if (-1 == pm8001_bar4_shift(pm8001_ha,
 506                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
 507                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 508                 return;
 509         }
 510         for (i = 4; i < 8; i++) {
 511                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 512                 pm8001_cw32(pm8001_ha, 2, offset, value);
 513         }
 514         /*set the shifted destination address to 0x0 to avoid error operation */
 515         pm8001_bar4_shift(pm8001_ha, 0x0);
 516         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 517         return;
 518 }
 519
 520 /**
 521  * mpi_init_check - check firmware initialization status.
 522  * @pm8001_ha: our hba card information
 523  */
 524 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 525 {
 526         u32 max_wait_count;
 527         u32 value;
 528         u32 gst_len_mpistate;
 529         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 530         table is updated */
 531         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 532         /* wait until Inbound DoorBell Clear Register toggled */
 533         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 534         do {
 535                 udelay(1);
 536                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 537                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 538         } while ((value != 0) && (--max_wait_count));
 539
 540         if (!max_wait_count)
 541                 return -1;
 542         /* check the MPI-State for initialization */
 543         gst_len_mpistate =
 544                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 545                 GST_GSTLEN_MPIS_OFFSET);
 546         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 547                 return -1;
 548         /* check MPI Initialization error */
 549         gst_len_mpistate = gst_len_mpistate >> 16;
 550         if (0x0000 != gst_len_mpistate)
 551                 return -1;
 552         return 0;
 553 }
 554
 555 /**
 556  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 557  * @pm8001_ha: our hba card information
 558  */
 559 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 560 {
 561         u32 value, value1;
 562         u32 max_wait_count;
 563         /* check error state */
 564         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 565         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 566         /* check AAP error */
 567         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 568                 /* error state */
 569                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 570                 return -1;
 571         }
 572
 573         /* check IOP error */
 574         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 575                 /* error state */
 576                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 577                 return -1;
 578         }
 579
 580         /* bit 4-31 of scratch pad1 should be zeros if it is not
 581         in error state*/
 582         if (value & SCRATCH_PAD1_STATE_MASK) {
 583                 /* error case */
 584                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 585                 return -1;
 586         }
 587
 588         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 589         in error state */
 590         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 591                 /* error case */
 592                 return -1;
 593         }
 594
 595         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 596
 597         /* wait until scratch pad 1 and 2 registers in ready state  */
 598         do {
 599                 udelay(1);
 600                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 601                         & SCRATCH_PAD1_RDY;
 602                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 603                         & SCRATCH_PAD2_RDY;
 604                 if ((--max_wait_count) == 0)
 605                         return -1;
 606         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 607         return 0;
 608 }
 609
 610 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 611 {
 612         void __iomem *base_addr;
 613         u32     value;
 614         u32     offset;
 615         u32     pcibar;
 616         u32     pcilogic;
 617
 618         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 619         offset = value & 0x03FFFFFF;
 620         PM8001_INIT_DBG(pm8001_ha,
 621                 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
 622         pcilogic = (value & 0xFC000000) >> 26;
 623         pcibar = get_pci_bar_index(pcilogic);
 624         PM8001_INIT_DBG(pm8001_ha,
 625                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 626         pm8001_ha->main_cfg_tbl_addr = base_addr =
 627                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 628         pm8001_ha->general_stat_tbl_addr =
 629                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 630         pm8001_ha->inbnd_q_tbl_addr =
 631                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 632         pm8001_ha->outbnd_q_tbl_addr =
 633                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 634 }
 635
 636 /**
 637  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 638  * @pm8001_ha: our hba card information
 639  */
 640 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 641 {
 642         u8 i = 0;
 643         u16 deviceid;
 644         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 645         /* 8081 controllers need BAR shift to access MPI space
 646         * as this is shared with BIOS data */
 647         if (deviceid == 0x8081 || deviceid == 0x0042) {
 648                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 649                         PM8001_FAIL_DBG(pm8001_ha,
 650                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 651                                         GSM_SM_BASE));
 652                         return -1;
 653                 }
 654         }
 655         /* check the firmware status */
 656         if (-1 == check_fw_ready(pm8001_ha)) {
 657                 PM8001_FAIL_DBG(pm8001_ha,
 658                         pm8001_printk("Firmware is not ready!\n"));
 659                 return -EBUSY;
 660         }
 661
 662         /* Initialize pci space address eg: mpi offset */
 663         init_pci_device_addresses(pm8001_ha);
 664         init_default_table_values(pm8001_ha);
 665         read_main_config_table(pm8001_ha);
 666         read_general_status_table(pm8001_ha);
 667         read_inbnd_queue_table(pm8001_ha);
 668         read_outbnd_queue_table(pm8001_ha);
 669         /* update main config table ,inbound table and outbound table */
 670         update_main_config_table(pm8001_ha);
 671         for (i = 0; i < PM8001_MAX_INB_NUM; i++)
 672                 update_inbnd_queue_table(pm8001_ha, i);
 673         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++)
 674                 update_outbnd_queue_table(pm8001_ha, i);
 675         /* 8081 controller donot require these operations */
 676         if (deviceid != 0x8081 && deviceid != 0x0042) {
 677                 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 678                 /* 7->130ms, 34->500ms, 119->1.5s */
 679                 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
 680         }
 681         /* notify firmware update finished and check initialization status */
 682         if (0 == mpi_init_check(pm8001_ha)) {
 683                 PM8001_INIT_DBG(pm8001_ha,
 684                         pm8001_printk("MPI initialize successful!\n"));
 685         } else
 686                 return -EBUSY;
 687         /*This register is a 16-bit timer with a resolution of 1us. This is the
 688         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 689         Zero is not a valid value. A value of 1 in the register will cause the
 690         interrupts to be normal. A value greater than 1 will cause coalescing
 691         delays.*/
 692         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 693         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 694         return 0;
 695 }
 696
 697 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 698 {
 699         u32 max_wait_count;
 700         u32 value;
 701         u32 gst_len_mpistate;
 702         u16 deviceid;
 703         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 704         if (deviceid == 0x8081 || deviceid == 0x0042) {
 705                 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 706                         PM8001_FAIL_DBG(pm8001_ha,
 707                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 708                                         GSM_SM_BASE));
 709                         return -1;
 710                 }
 711         }
 712         init_pci_device_addresses(pm8001_ha);
 713         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 714         table is stop */
 715         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 716
 717         /* wait until Inbound DoorBell Clear Register toggled */
 718         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 719         do {
 720                 udelay(1);
 721                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 722                 value &= SPC_MSGU_CFG_TABLE_RESET;
 723         } while ((value != 0) && (--max_wait_count));
 724
 725         if (!max_wait_count) {
 726                 PM8001_FAIL_DBG(pm8001_ha,
 727                         pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
 728                 return -1;
 729         }
 730
 731         /* check the MPI-State for termination in progress */
 732         /* wait until Inbound DoorBell Clear Register toggled */
 733         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 734         do {
 735                 udelay(1);
 736                 gst_len_mpistate =
 737                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 738                         GST_GSTLEN_MPIS_OFFSET);
 739                 if (GST_MPI_STATE_UNINIT ==
 740                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 741                         break;
 742         } while (--max_wait_count);
 743         if (!max_wait_count) {
 744                 PM8001_FAIL_DBG(pm8001_ha,
 745                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
 746                                 gst_len_mpistate & GST_MPI_STATE_MASK));
 747                 return -1;
 748         }
 749         return 0;
 750 }
 751
 752 /**
 753  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 754  * @pm8001_ha: our hba card information
 755  */
 756 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 757 {
 758         u32 regVal, regVal1, regVal2;
 759         if (mpi_uninit_check(pm8001_ha) != 0) {
 760                 PM8001_FAIL_DBG(pm8001_ha,
 761                         pm8001_printk("MPI state is not ready\n"));
 762                 return -1;
 763         }
 764         /* read the scratch pad 2 register bit 2 */
 765         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 766                 & SCRATCH_PAD2_FWRDY_RST;
 767         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 768                 PM8001_INIT_DBG(pm8001_ha,
 769                         pm8001_printk("Firmware is ready for reset .\n"));
 770         } else {
 771                 unsigned long flags;
 772                 /* Trigger NMI twice via RB6 */
 773                 spin_lock_irqsave(&pm8001_ha->lock, flags);
 774                 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 775                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 776                         PM8001_FAIL_DBG(pm8001_ha,
 777                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 778                                         RB6_ACCESS_REG));
 779                         return -1;
 780                 }
 781                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 782                         RB6_MAGIC_NUMBER_RST);
 783                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 784                 /* wait for 100 ms */
 785                 mdelay(100);
 786                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 787                         SCRATCH_PAD2_FWRDY_RST;
 788                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 789                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 790                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 791                         PM8001_FAIL_DBG(pm8001_ha,
 792                                 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
 793                                 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 794                                 regVal1, regVal2));
 795                         PM8001_FAIL_DBG(pm8001_ha,
 796                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
 797                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
 798                         PM8001_FAIL_DBG(pm8001_ha,
 799                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
 800                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
 801                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 802                         return -1;
 803                 }
 804                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 805         }
 806         return 0;
 807 }
 808
 809 /**
 810  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 811  * the FW register status to the originated status.
 812  * @pm8001_ha: our hba card information
 813  */
 814 static int
 815 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
 816 {
 817         u32     regVal, toggleVal;
 818         u32     max_wait_count;
 819         u32     regVal1, regVal2, regVal3;
 820         u32     signature = 0x252acbcd; /* for host scratch pad0 */
 821         unsigned long flags;
 822
 823         /* step1: Check FW is ready for soft reset */
 824         if (soft_reset_ready_check(pm8001_ha) != 0) {
 825                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
 826                 return -1;
 827         }
 828
 829         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 830         value to clear */
 831         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 832         spin_lock_irqsave(&pm8001_ha->lock, flags);
 833         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 834                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 835                 PM8001_FAIL_DBG(pm8001_ha,
 836                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 837                         MBIC_AAP1_ADDR_BASE));
 838                 return -1;
 839         }
 840         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 841         PM8001_INIT_DBG(pm8001_ha,
 842                 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
 843         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 844         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 845         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 846                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 847                 PM8001_FAIL_DBG(pm8001_ha,
 848                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 849                         MBIC_IOP_ADDR_BASE));
 850                 return -1;
 851         }
 852         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 853         PM8001_INIT_DBG(pm8001_ha,
 854                 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
 855         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 856
 857         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 858         PM8001_INIT_DBG(pm8001_ha,
 859                 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
 860         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 861
 862         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 863         PM8001_INIT_DBG(pm8001_ha,
 864                 pm8001_printk("PCIE - Event Interrupt  = 0x%x\n", regVal));
 865         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 866
 867         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 868         PM8001_INIT_DBG(pm8001_ha,
 869                 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
 870         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 871
 872         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 873         PM8001_INIT_DBG(pm8001_ha,
 874                 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
 875         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 876
 877         /* read the scratch pad 1 register bit 2 */
 878         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 879                 & SCRATCH_PAD1_RST;
 880         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 881
 882         /* set signature in host scratch pad0 register to tell SPC that the
 883         host performs the soft reset */
 884         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 885
 886         /* read required registers for confirmming */
 887         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 888         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 889                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 890                 PM8001_FAIL_DBG(pm8001_ha,
 891                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 892                         GSM_ADDR_BASE));
 893                 return -1;
 894         }
 895         PM8001_INIT_DBG(pm8001_ha,
 896                 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
 897                 " Reset = 0x%x\n",
 898                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 899
 900         /* step 3: host read GSM Configuration and Reset register */
 901         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 902         /* Put those bits to low */
 903         /* GSM XCBI offset = 0x70 0000
 904         0x00 Bit 13 COM_SLV_SW_RSTB 1
 905         0x00 Bit 12 QSSP_SW_RSTB 1
 906         0x00 Bit 11 RAAE_SW_RSTB 1
 907         0x00 Bit 9 RB_1_SW_RSTB 1
 908         0x00 Bit 8 SM_SW_RSTB 1
 909         */
 910         regVal &= ~(0x00003b00);
 911         /* host write GSM Configuration and Reset register */
 912         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 913         PM8001_INIT_DBG(pm8001_ha,
 914                 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
 915                 "Configuration and Reset is set to = 0x%x\n",
 916                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 917
 918         /* step 4: */
 919         /* disable GSM - Read Address Parity Check */
 920         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 921         PM8001_INIT_DBG(pm8001_ha,
 922                 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
 923                 "Enable = 0x%x\n", regVal1));
 924         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 925         PM8001_INIT_DBG(pm8001_ha,
 926                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 927                 "is set to = 0x%x\n",
 928                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 929
 930         /* disable GSM - Write Address Parity Check */
 931         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 932         PM8001_INIT_DBG(pm8001_ha,
 933                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 934                 " Enable = 0x%x\n", regVal2));
 935         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 936         PM8001_INIT_DBG(pm8001_ha,
 937                 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
 938                 "Enable is set to = 0x%x\n",
 939                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 940
 941         /* disable GSM - Write Data Parity Check */
 942         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 943         PM8001_INIT_DBG(pm8001_ha,
 944                 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
 945                 " Enable = 0x%x\n", regVal3));
 946         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 947         PM8001_INIT_DBG(pm8001_ha,
 948                 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
 949                 "is set to = 0x%x\n",
 950         pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 951
 952         /* step 5: delay 10 usec */
 953         udelay(10);
 954         /* step 5-b: set GPIO-0 output control to tristate anyway */
 955         if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 956                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 957                 PM8001_INIT_DBG(pm8001_ha,
 958                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 959                                 GPIO_ADDR_BASE));
 960                 return -1;
 961         }
 962         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 963                 PM8001_INIT_DBG(pm8001_ha,
 964                                 pm8001_printk("GPIO Output Control Register:"
 965                                 " = 0x%x\n", regVal));
 966         /* set GPIO-0 output control to tri-state */
 967         regVal &= 0xFFFFFFFC;
 968         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 969
 970         /* Step 6: Reset the IOP and AAP1 */
 971         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 972         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 973                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 974                 PM8001_FAIL_DBG(pm8001_ha,
 975                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 976                         SPC_TOP_LEVEL_ADDR_BASE));
 977                 return -1;
 978         }
 979         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 980         PM8001_INIT_DBG(pm8001_ha,
 981                 pm8001_printk("Top Register before resetting IOP/AAP1"
 982                 ":= 0x%x\n", regVal));
 983         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 984         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 985
 986         /* step 7: Reset the BDMA/OSSP */
 987         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 988         PM8001_INIT_DBG(pm8001_ha,
 989                 pm8001_printk("Top Register before resetting BDMA/OSSP"
 990                 ": = 0x%x\n", regVal));
 991         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 992         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 993
 994         /* step 8: delay 10 usec */
 995         udelay(10);
 996
 997         /* step 9: bring the BDMA and OSSP out of reset */
 998         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 999         PM8001_INIT_DBG(pm8001_ha,
1000                 pm8001_printk("Top Register before bringing up BDMA/OSSP"
1001                 ":= 0x%x\n", regVal));
1002         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
1003         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1004
1005         /* step 10: delay 10 usec */
1006         udelay(10);
1007
1008         /* step 11: reads and sets the GSM Configuration and Reset Register */
1009         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
1010         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
1011                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1012                 PM8001_FAIL_DBG(pm8001_ha,
1013                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
1014                         GSM_ADDR_BASE));
1015                 return -1;
1016         }
1017         PM8001_INIT_DBG(pm8001_ha,
1018                 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
1019                 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1020         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1021         /* Put those bits to high */
1022         /* GSM XCBI offset = 0x70 0000
1023         0x00 Bit 13 COM_SLV_SW_RSTB 1
1024         0x00 Bit 12 QSSP_SW_RSTB 1
1025         0x00 Bit 11 RAAE_SW_RSTB 1
1026         0x00 Bit 9   RB_1_SW_RSTB 1
1027         0x00 Bit 8   SM_SW_RSTB 1
1028         */
1029         regVal |= (GSM_CONFIG_RESET_VALUE);
1030         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1031         PM8001_INIT_DBG(pm8001_ha,
1032                 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
1033                 " Configuration and Reset is set to = 0x%x\n",
1034                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1035
1036         /* step 12: Restore GSM - Read Address Parity Check */
1037         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1038         /* just for debugging */
1039         PM8001_INIT_DBG(pm8001_ha,
1040                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
1041                 " = 0x%x\n", regVal));
1042         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1043         PM8001_INIT_DBG(pm8001_ha,
1044                 pm8001_printk("GSM 0x700038 - Read Address Parity"
1045                 " Check Enable is set to = 0x%x\n",
1046                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
1047         /* Restore GSM - Write Address Parity Check */
1048         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1049         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1050         PM8001_INIT_DBG(pm8001_ha,
1051                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
1052                 " Enable is set to = 0x%x\n",
1053                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
1054         /* Restore GSM - Write Data Parity Check */
1055         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1056         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1057         PM8001_INIT_DBG(pm8001_ha,
1058                 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
1059                 "is set to = 0x%x\n",
1060                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
1061
1062         /* step 13: bring the IOP and AAP1 out of reset */
1063         /* map 0x00000 to BAR4(0x20), BAR2(win) */
1064         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1065                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1066                 PM8001_FAIL_DBG(pm8001_ha,
1067                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
1068                         SPC_TOP_LEVEL_ADDR_BASE));
1069                 return -1;
1070         }
1071         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1072         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1073         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1074
1075         /* step 14: delay 10 usec - Normal Mode */
1076         udelay(10);
1077         /* check Soft Reset Normal mode or Soft Reset HDA mode */
1078         if (signature == SPC_SOFT_RESET_SIGNATURE) {
1079                 /* step 15 (Normal Mode): wait until scratch pad1 register
1080                 bit 2 toggled */
1081                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1082                 do {
1083                         udelay(1);
1084                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1085                                 SCRATCH_PAD1_RST;
1086                 } while ((regVal != toggleVal) && (--max_wait_count));
1087
1088                 if (!max_wait_count) {
1089                         regVal = pm8001_cr32(pm8001_ha, 0,
1090                                 MSGU_SCRATCH_PAD_1);
1091                         PM8001_FAIL_DBG(pm8001_ha,
1092                                 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1093                                 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1094                                 toggleVal, regVal));
1095                         PM8001_FAIL_DBG(pm8001_ha,
1096                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1097                                 pm8001_cr32(pm8001_ha, 0,
1098                                 MSGU_SCRATCH_PAD_0)));
1099                         PM8001_FAIL_DBG(pm8001_ha,
1100                                 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1101                                 pm8001_cr32(pm8001_ha, 0,
1102                                 MSGU_SCRATCH_PAD_2)));
1103                         PM8001_FAIL_DBG(pm8001_ha,
1104                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1105                                 pm8001_cr32(pm8001_ha, 0,
1106                                 MSGU_SCRATCH_PAD_3)));
1107                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1108                         return -1;
1109                 }
1110
1111                 /* step 16 (Normal) - Clear ODMR and ODCR */
1112                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1113                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1114
1115                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1116                 ready - 1 sec timeout */
1117                 /* Wait for the SPC Configuration Table to be ready */
1118                 if (check_fw_ready(pm8001_ha) == -1) {
1119                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1120                         /* return error if MPI Configuration Table not ready */
1121                         PM8001_INIT_DBG(pm8001_ha,
1122                                 pm8001_printk("FW not ready SCRATCH_PAD1"
1123                                 " = 0x%x\n", regVal));
1124                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1125                         /* return error if MPI Configuration Table not ready */
1126                         PM8001_INIT_DBG(pm8001_ha,
1127                                 pm8001_printk("FW not ready SCRATCH_PAD2"
1128                                 " = 0x%x\n", regVal));
1129                         PM8001_INIT_DBG(pm8001_ha,
1130                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1131                                 pm8001_cr32(pm8001_ha, 0,
1132                                 MSGU_SCRATCH_PAD_0)));
1133                         PM8001_INIT_DBG(pm8001_ha,
1134                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1135                                 pm8001_cr32(pm8001_ha, 0,
1136                                 MSGU_SCRATCH_PAD_3)));
1137                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1138                         return -1;
1139                 }
1140         }
1141         pm8001_bar4_shift(pm8001_ha, 0);
1142         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1143
1144         PM8001_INIT_DBG(pm8001_ha,
1145                 pm8001_printk("SPC soft reset Complete\n"));
1146         return 0;
1147 }
1148
1149 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1150 {
1151         u32 i;
1152         u32 regVal;
1153         PM8001_INIT_DBG(pm8001_ha,
1154                 pm8001_printk("chip reset start\n"));
1155
1156         /* do SPC chip reset. */
1157         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1158         regVal &= ~(SPC_REG_RESET_DEVICE);
1159         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1160
1161         /* delay 10 usec */
1162         udelay(10);
1163
1164         /* bring chip reset out of reset */
1165         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1166         regVal |= SPC_REG_RESET_DEVICE;
1167         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1168
1169         /* delay 10 usec */
1170         udelay(10);
1171
1172         /* wait for 20 msec until the firmware gets reloaded */
1173         i = 20;
1174         do {
1175                 mdelay(1);
1176         } while ((--i) != 0);
1177
1178         PM8001_INIT_DBG(pm8001_ha,
1179                 pm8001_printk("chip reset finished\n"));
1180 }
1181
1182 /**
1183  * pm8001_chip_iounmap - which maped when initialized.
1184  * @pm8001_ha: our hba card information
1185  */
1186 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1187 {
1188         s8 bar, logical = 0;
1189         for (bar = 0; bar < 6; bar++) {
1190                 /*
1191                 ** logical BARs for SPC:
1192                 ** bar 0 and 1 - logical BAR0
1193                 ** bar 2 and 3 - logical BAR1
1194                 ** bar4 - logical BAR2
1195                 ** bar5 - logical BAR3
1196                 ** Skip the appropriate assignments:
1197                 */
1198                 if ((bar == 1) || (bar == 3))
1199                         continue;
1200                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1201                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1202                         logical++;
1203                 }
1204         }
1205 }
1206
1207 /**
1208  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1209  * @pm8001_ha: our hba card information
1210  */
1211 static void
1212 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1213 {
1214         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1215         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1216 }
1217
1218  /**
1219   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1220   * @pm8001_ha: our hba card information
1221   */
1222 static void
1223 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1224 {
1225         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1226 }
1227
1228 /**
1229  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1230  * @pm8001_ha: our hba card information
1231  */
1232 static void
1233 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1234         u32 int_vec_idx)
1235 {
1236         u32 msi_index;
1237         u32 value;
1238         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1239         msi_index += MSIX_TABLE_BASE;
1240         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1241         value = (1 << int_vec_idx);
1242         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1243
1244 }
1245
1246 /**
1247  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1248  * @pm8001_ha: our hba card information
1249  */
1250 static void
1251 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1252         u32 int_vec_idx)
1253 {
1254         u32 msi_index;
1255         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1256         msi_index += MSIX_TABLE_BASE;
1257         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1258 }
1259
1260 /**
1261  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1262  * @pm8001_ha: our hba card information
1263  */
1264 static void
1265 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1266 {
1267 #ifdef PM8001_USE_MSIX
1268         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1269         return;
1270 #endif
1271         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1272
1273 }
1274
1275 /**
1276  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1277  * @pm8001_ha: our hba card information
1278  */
1279 static void
1280 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1281 {
1282 #ifdef PM8001_USE_MSIX
1283         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1284         return;
1285 #endif
1286         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1287
1288 }
1289
1290 /**
1291  * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1292  * inbound queue.
1293  * @circularQ: the inbound queue  we want to transfer to HBA.
1294  * @messageSize: the message size of this transfer, normally it is 64 bytes
1295  * @messagePtr: the pointer to message.
1296  */
1297 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1298                             u16 messageSize, void **messagePtr)
1299 {
1300         u32 offset, consumer_index;
1301         struct mpi_msg_hdr *msgHeader;
1302         u8 bcCount = 1; /* only support single buffer */
1303
1304         /* Checks is the requested message size can be allocated in this queue*/
1305         if (messageSize > IOMB_SIZE_SPCV) {
1306                 *messagePtr = NULL;
1307                 return -1;
1308         }
1309
1310         /* Stores the new consumer index */
1311         consumer_index = pm8001_read_32(circularQ->ci_virt);
1312         circularQ->consumer_index = cpu_to_le32(consumer_index);
1313         if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1314                 le32_to_cpu(circularQ->consumer_index)) {
1315                 *messagePtr = NULL;
1316                 return -1;
1317         }
1318         /* get memory IOMB buffer address */
1319         offset = circularQ->producer_idx * messageSize;
1320         /* increment to next bcCount element */
1321         circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1322                                 % PM8001_MPI_QUEUE;
1323         /* Adds that distance to the base of the region virtual address plus
1324         the message header size*/
1325         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1326         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1327         return 0;
1328 }
1329
1330 /**
1331  * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1332  * FW to tell the fw to get this message from IOMB.
1333  * @pm8001_ha: our hba card information
1334  * @circularQ: the inbound queue we want to transfer to HBA.
1335  * @opCode: the operation code represents commands which LLDD and fw recognized.
1336  * @payload: the command payload of each operation command.
1337  */
1338 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1339                          struct inbound_queue_table *circularQ,
1340                          u32 opCode, void *payload, u32 responseQueue)
1341 {
1342         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1343         void *pMessage;
1344
1345         if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1346                 &pMessage) < 0) {
1347                 PM8001_IO_DBG(pm8001_ha,
1348                         pm8001_printk("No free mpi buffer\n"));
1349                 return -ENOMEM;
1350         }
1351         BUG_ON(!payload);
1352         /*Copy to the payload*/
1353         memcpy(pMessage, payload, (pm8001_ha->iomb_size -
1354                                 sizeof(struct mpi_msg_hdr)));
1355
1356         /*Build the header*/
1357         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1358                 | ((responseQueue & 0x3F) << 16)
1359                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1360
1361         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1362         /*Update the PI to the firmware*/
1363         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1364                 circularQ->pi_offset, circularQ->producer_idx);
1365         PM8001_IO_DBG(pm8001_ha,
1366                 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1367                         responseQueue, opCode, circularQ->producer_idx,
1368                         circularQ->consumer_index));
1369         return 0;
1370 }
1371
1372 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1373                             struct outbound_queue_table *circularQ, u8 bc)
1374 {
1375         u32 producer_index;
1376         struct mpi_msg_hdr *msgHeader;
1377         struct mpi_msg_hdr *pOutBoundMsgHeader;
1378
1379         msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1380         pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1381                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1382         if (pOutBoundMsgHeader != msgHeader) {
1383                 PM8001_FAIL_DBG(pm8001_ha,
1384                         pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1385                         circularQ->consumer_idx, msgHeader));
1386
1387                 /* Update the producer index from SPC */
1388                 producer_index = pm8001_read_32(circularQ->pi_virt);
1389                 circularQ->producer_index = cpu_to_le32(producer_index);
1390                 PM8001_FAIL_DBG(pm8001_ha,
1391                         pm8001_printk("consumer_idx = %d producer_index = %d"
1392                         "msgHeader = %p\n", circularQ->consumer_idx,
1393                         circularQ->producer_index, msgHeader));
1394                 return 0;
1395         }
1396         /* free the circular queue buffer elements associated with the message*/
1397         circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1398                                 % PM8001_MPI_QUEUE;
1399         /* update the CI of outbound queue */
1400         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1401                 circularQ->consumer_idx);
1402         /* Update the producer index from SPC*/
1403         producer_index = pm8001_read_32(circularQ->pi_virt);
1404         circularQ->producer_index = cpu_to_le32(producer_index);
1405         PM8001_IO_DBG(pm8001_ha,
1406                 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1407                 circularQ->producer_index));
1408         return 0;
1409 }
1410
1411 /**
1412  * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1413  * message table.
1414  * @pm8001_ha: our hba card information
1415  * @circularQ: the outbound queue  table.
1416  * @messagePtr1: the message contents of this outbound message.
1417  * @pBC: the message size.
1418  */
1419 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1420                            struct outbound_queue_table *circularQ,
1421                            void **messagePtr1, u8 *pBC)
1422 {
1423         struct mpi_msg_hdr      *msgHeader;
1424         __le32  msgHeader_tmp;
1425         u32 header_tmp;
1426         do {
1427                 /* If there are not-yet-delivered messages ... */
1428                 if (le32_to_cpu(circularQ->producer_index)
1429                         != circularQ->consumer_idx) {
1430                         /*Get the pointer to the circular queue buffer element*/
1431                         msgHeader = (struct mpi_msg_hdr *)
1432                                 (circularQ->base_virt +
1433                                 circularQ->consumer_idx * pm8001_ha->iomb_size);
1434                         /* read header */
1435                         header_tmp = pm8001_read_32(msgHeader);
1436                         msgHeader_tmp = cpu_to_le32(header_tmp);
1437                         if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1438                                 if (OPC_OUB_SKIP_ENTRY !=
1439                                         (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1440                                         *messagePtr1 =
1441                                                 ((u8 *)msgHeader) +
1442                                                 sizeof(struct mpi_msg_hdr);
1443                                         *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1444                                                 >> 24) & 0x1f);
1445                                         PM8001_IO_DBG(pm8001_ha,
1446                                                 pm8001_printk(": CI=%d PI=%d "
1447                                                 "msgHeader=%x\n",
1448                                                 circularQ->consumer_idx,
1449                                                 circularQ->producer_index,
1450                                                 msgHeader_tmp));
1451                                         return MPI_IO_STATUS_SUCCESS;
1452                                 } else {
1453                                         circularQ->consumer_idx =
1454                                                 (circularQ->consumer_idx +
1455                                                 ((le32_to_cpu(msgHeader_tmp)
1456                                                  >> 24) & 0x1f))
1457                                                         % PM8001_MPI_QUEUE;
1458                                         msgHeader_tmp = 0;
1459                                         pm8001_write_32(msgHeader, 0, 0);
1460                                         /* update the CI of outbound queue */
1461                                         pm8001_cw32(pm8001_ha,
1462                                                 circularQ->ci_pci_bar,
1463                                                 circularQ->ci_offset,
1464                                                 circularQ->consumer_idx);
1465                                 }
1466                         } else {
1467                                 circularQ->consumer_idx =
1468                                         (circularQ->consumer_idx +
1469                                         ((le32_to_cpu(msgHeader_tmp) >> 24) &
1470                                         0x1f)) % PM8001_MPI_QUEUE;
1471                                 msgHeader_tmp = 0;
1472                                 pm8001_write_32(msgHeader, 0, 0);
1473                                 /* update the CI of outbound queue */
1474                                 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1475                                         circularQ->ci_offset,
1476                                         circularQ->consumer_idx);
1477                                 return MPI_IO_STATUS_FAIL;
1478                         }
1479                 } else {
1480                         u32 producer_index;
1481                         void *pi_virt = circularQ->pi_virt;
1482                         /* Update the producer index from SPC */
1483                         producer_index = pm8001_read_32(pi_virt);
1484                         circularQ->producer_index = cpu_to_le32(producer_index);
1485                 }
1486         } while (le32_to_cpu(circularQ->producer_index) !=
1487                 circularQ->consumer_idx);
1488         /* while we don't have any more not-yet-delivered message */
1489         /* report empty */
1490         return MPI_IO_STATUS_BUSY;
1491 }
1492
1493 void pm8001_work_fn(struct work_struct *work)
1494 {
1495         struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1496         struct pm8001_device *pm8001_dev;
1497         struct domain_device *dev;
1498
1499         /*
1500          * So far, all users of this stash an associated structure here.
1501          * If we get here, and this pointer is null, then the action
1502          * was cancelled. This nullification happens when the device
1503          * goes away.
1504          */
1505         pm8001_dev = pw->data; /* Most stash device structure */
1506         if ((pm8001_dev == NULL)
1507          || ((pw->handler != IO_XFER_ERROR_BREAK)
1508           && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1509                 kfree(pw);
1510                 return;
1511         }
1512
1513         switch (pw->handler) {
1514         case IO_XFER_ERROR_BREAK:
1515         {       /* This one stashes the sas_task instead */
1516                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1517                 u32 tag;
1518                 struct pm8001_ccb_info *ccb;
1519                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1520                 unsigned long flags, flags1;
1521                 struct task_status_struct *ts;
1522                 int i;
1523
1524                 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1525                         break; /* Task still on lu */
1526                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1527
1528                 spin_lock_irqsave(&t->task_state_lock, flags1);
1529                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1530                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1531                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1532                         break; /* Task got completed by another */
1533                 }
1534                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1535
1536                 /* Search for a possible ccb that matches the task */
1537                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1538                         ccb = &pm8001_ha->ccb_info[i];
1539                         tag = ccb->ccb_tag;
1540                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1541                                 break;
1542                 }
1543                 if (!ccb) {
1544                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1545                         break; /* Task got freed by another */
1546                 }
1547                 ts = &t->task_status;
1548                 ts->resp = SAS_TASK_COMPLETE;
1549                 /* Force the midlayer to retry */
1550                 ts->stat = SAS_QUEUE_FULL;
1551                 pm8001_dev = ccb->device;
1552                 if (pm8001_dev)
1553                         pm8001_dev->running_req--;
1554                 spin_lock_irqsave(&t->task_state_lock, flags1);
1555                 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1556                 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1557                 t->task_state_flags |= SAS_TASK_STATE_DONE;
1558                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1559                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1560                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1561                                 " done with event 0x%x resp 0x%x stat 0x%x but"
1562                                 " aborted by upper layer!\n",
1563                                 t, pw->handler, ts->resp, ts->stat));
1564                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1565                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1566                 } else {
1567                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1568                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1569                         mb();/* in order to force CPU ordering */
1570                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1571                         t->task_done(t);
1572                 }
1573         }       break;
1574         case IO_XFER_OPEN_RETRY_TIMEOUT:
1575         {       /* This one stashes the sas_task instead */
1576                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1577                 u32 tag;
1578                 struct pm8001_ccb_info *ccb;
1579                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1580                 unsigned long flags, flags1;
1581                 int i, ret = 0;
1582
1583                 PM8001_IO_DBG(pm8001_ha,
1584                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1585
1586                 ret = pm8001_query_task(t);
1587
1588                 PM8001_IO_DBG(pm8001_ha,
1589                         switch (ret) {
1590                         case TMF_RESP_FUNC_SUCC:
1591                                 pm8001_printk("...Task on lu\n");
1592                                 break;
1593
1594                         case TMF_RESP_FUNC_COMPLETE:
1595                                 pm8001_printk("...Task NOT on lu\n");
1596                                 break;
1597
1598                         default:
1599                                 pm8001_printk("...query task failed!!!\n");
1600                                 break;
1601                         });
1602
1603                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1604
1605                 spin_lock_irqsave(&t->task_state_lock, flags1);
1606
1607                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1608                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1609                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1610                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1611                                 (void)pm8001_abort_task(t);
1612                         break; /* Task got completed by another */
1613                 }
1614
1615                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1616
1617                 /* Search for a possible ccb that matches the task */
1618                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1619                         ccb = &pm8001_ha->ccb_info[i];
1620                         tag = ccb->ccb_tag;
1621                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1622                                 break;
1623                 }
1624                 if (!ccb) {
1625                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1626                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1627                                 (void)pm8001_abort_task(t);
1628                         break; /* Task got freed by another */
1629                 }
1630
1631                 pm8001_dev = ccb->device;
1632                 dev = pm8001_dev->sas_device;
1633
1634                 switch (ret) {
1635                 case TMF_RESP_FUNC_SUCC: /* task on lu */
1636                         ccb->open_retry = 1; /* Snub completion */
1637                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1638                         ret = pm8001_abort_task(t);
1639                         ccb->open_retry = 0;
1640                         switch (ret) {
1641                         case TMF_RESP_FUNC_SUCC:
1642                         case TMF_RESP_FUNC_COMPLETE:
1643                                 break;
1644                         default: /* device misbehavior */
1645                                 ret = TMF_RESP_FUNC_FAILED;
1646                                 PM8001_IO_DBG(pm8001_ha,
1647                                         pm8001_printk("...Reset phy\n"));
1648                                 pm8001_I_T_nexus_reset(dev);
1649                                 break;
1650                         }
1651                         break;
1652
1653                 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1654                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1655                         /* Do we need to abort the task locally? */
1656                         break;
1657
1658                 default: /* device misbehavior */
1659                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1660                         ret = TMF_RESP_FUNC_FAILED;
1661                         PM8001_IO_DBG(pm8001_ha,
1662                                 pm8001_printk("...Reset phy\n"));
1663                         pm8001_I_T_nexus_reset(dev);
1664                 }
1665
1666                 if (ret == TMF_RESP_FUNC_FAILED)
1667                         t = NULL;
1668                 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1669                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1670         }       break;
1671         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1672                 dev = pm8001_dev->sas_device;
1673                 pm8001_I_T_nexus_event_handler(dev);
1674                 break;
1675         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1676                 dev = pm8001_dev->sas_device;
1677                 pm8001_I_T_nexus_reset(dev);
1678                 break;
1679         case IO_DS_IN_ERROR:
1680                 dev = pm8001_dev->sas_device;
1681                 pm8001_I_T_nexus_reset(dev);
1682                 break;
1683         case IO_DS_NON_OPERATIONAL:
1684                 dev = pm8001_dev->sas_device;
1685                 pm8001_I_T_nexus_reset(dev);
1686                 break;
1687         }
1688         kfree(pw);
1689 }
1690
1691 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1692                                int handler)
1693 {
1694         struct pm8001_work *pw;
1695         int ret = 0;
1696
1697         pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1698         if (pw) {
1699                 pw->pm8001_ha = pm8001_ha;
1700                 pw->data = data;
1701                 pw->handler = handler;
1702                 INIT_WORK(&pw->work, pm8001_work_fn);
1703                 queue_work(pm8001_wq, &pw->work);
1704         } else
1705                 ret = -ENOMEM;
1706
1707         return ret;
1708 }
1709
1710 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1711                 struct pm8001_device *pm8001_ha_dev)
1712 {
1713         int res;
1714         u32 ccb_tag;
1715         struct pm8001_ccb_info *ccb;
1716         struct sas_task *task = NULL;
1717         struct task_abort_req task_abort;
1718         struct inbound_queue_table *circularQ;
1719         u32 opc = OPC_INB_SATA_ABORT;
1720         int ret;
1721
1722         if (!pm8001_ha_dev) {
1723                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1724                 return;
1725         }
1726
1727         task = sas_alloc_slow_task(GFP_ATOMIC);
1728
1729         if (!task) {
1730                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1731                                                 "allocate task\n"));
1732                 return;
1733         }
1734
1735         task->task_done = pm8001_task_done;
1736
1737         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1738         if (res)
1739                 return;
1740
1741         ccb = &pm8001_ha->ccb_info[ccb_tag];
1742         ccb->device = pm8001_ha_dev;
1743         ccb->ccb_tag = ccb_tag;
1744         ccb->task = task;
1745
1746         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1747
1748         memset(&task_abort, 0, sizeof(task_abort));
1749         task_abort.abort_all = cpu_to_le32(1);
1750         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1751         task_abort.tag = cpu_to_le32(ccb_tag);
1752
1753         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1754         if (ret)
1755                 pm8001_tag_free(pm8001_ha, ccb_tag);
1756
1757 }
1758
1759 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1760                 struct pm8001_device *pm8001_ha_dev)
1761 {
1762         struct sata_start_req sata_cmd;
1763         int res;
1764         u32 ccb_tag;
1765         struct pm8001_ccb_info *ccb;
1766         struct sas_task *task = NULL;
1767         struct host_to_dev_fis fis;
1768         struct domain_device *dev;
1769         struct inbound_queue_table *circularQ;
1770         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1771
1772         task = sas_alloc_slow_task(GFP_ATOMIC);
1773
1774         if (!task) {
1775                 PM8001_FAIL_DBG(pm8001_ha,
1776                         pm8001_printk("cannot allocate task !!!\n"));
1777                 return;
1778         }
1779         task->task_done = pm8001_task_done;
1780
1781         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1782         if (res) {
1783                 sas_free_task(task);
1784                 PM8001_FAIL_DBG(pm8001_ha,
1785                         pm8001_printk("cannot allocate tag !!!\n"));
1786                 return;
1787         }
1788
1789         /* allocate domain device by ourselves as libsas
1790          * is not going to provide any
1791         */
1792         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1793         if (!dev) {
1794                 sas_free_task(task);
1795                 pm8001_tag_free(pm8001_ha, ccb_tag);
1796                 PM8001_FAIL_DBG(pm8001_ha,
1797                         pm8001_printk("Domain device cannot be allocated\n"));
1798                 return;
1799         }
1800         task->dev = dev;
1801         task->dev->lldd_dev = pm8001_ha_dev;
1802
1803         ccb = &pm8001_ha->ccb_info[ccb_tag];
1804         ccb->device = pm8001_ha_dev;
1805         ccb->ccb_tag = ccb_tag;
1806         ccb->task = task;
1807         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1808         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1809
1810         memset(&sata_cmd, 0, sizeof(sata_cmd));
1811         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1812
1813         /* construct read log FIS */
1814         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1815         fis.fis_type = 0x27;
1816         fis.flags = 0x80;
1817         fis.command = ATA_CMD_READ_LOG_EXT;
1818         fis.lbal = 0x10;
1819         fis.sector_count = 0x1;
1820
1821         sata_cmd.tag = cpu_to_le32(ccb_tag);
1822         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1823         sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9));
1824         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1825
1826         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1827         if (res) {
1828                 sas_free_task(task);
1829                 pm8001_tag_free(pm8001_ha, ccb_tag);
1830                 kfree(dev);
1831         }
1832 }
1833
1834 /**
1835  * mpi_ssp_completion- process the event that FW response to the SSP request.
1836  * @pm8001_ha: our hba card information
1837  * @piomb: the message contents of this outbound message.
1838  *
1839  * When FW has completed a ssp request for example a IO request, after it has
1840  * filled the SG data with the data, it will trigger this event represent
1841  * that he has finished the job,please check the coresponding buffer.
1842  * So we will tell the caller who maybe waiting the result to tell upper layer
1843  * that the task has been finished.
1844  */
1845 static void
1846 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1847 {
1848         struct sas_task *t;
1849         struct pm8001_ccb_info *ccb;
1850         unsigned long flags;
1851         u32 status;
1852         u32 param;
1853         u32 tag;
1854         struct ssp_completion_resp *psspPayload;
1855         struct task_status_struct *ts;
1856         struct ssp_response_iu *iu;
1857         struct pm8001_device *pm8001_dev;
1858         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1859         status = le32_to_cpu(psspPayload->status);
1860         tag = le32_to_cpu(psspPayload->tag);
1861         ccb = &pm8001_ha->ccb_info[tag];
1862         if ((status == IO_ABORTED) && ccb->open_retry) {
1863                 /* Being completed by another */
1864                 ccb->open_retry = 0;
1865                 return;
1866         }
1867         pm8001_dev = ccb->device;
1868         param = le32_to_cpu(psspPayload->param);
1869
1870         t = ccb->task;
1871
1872         if (status && status != IO_UNDERFLOW)
1873                 PM8001_FAIL_DBG(pm8001_ha,
1874                         pm8001_printk("sas IO status 0x%x\n", status));
1875         if (unlikely(!t || !t->lldd_task || !t->dev))
1876                 return;
1877         ts = &t->task_status;
1878         /* Print sas address of IO failed device */
1879         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1880                 (status != IO_UNDERFLOW))
1881                 PM8001_FAIL_DBG(pm8001_ha,
1882                         pm8001_printk("SAS Address of IO Failure Drive:"
1883                         "%016llx", SAS_ADDR(t->dev->sas_addr)));
1884
1885         switch (status) {
1886         case IO_SUCCESS:
1887                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1888                         ",param = %d\n", param));
1889                 if (param == 0) {
1890                         ts->resp = SAS_TASK_COMPLETE;
1891                         ts->stat = SAM_STAT_GOOD;
1892                 } else {
1893                         ts->resp = SAS_TASK_COMPLETE;
1894                         ts->stat = SAS_PROTO_RESPONSE;
1895                         ts->residual = param;
1896                         iu = &psspPayload->ssp_resp_iu;
1897                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1898                 }
1899                 if (pm8001_dev)
1900                         pm8001_dev->running_req--;
1901                 break;
1902         case IO_ABORTED:
1903                 PM8001_IO_DBG(pm8001_ha,
1904                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1905                 ts->resp = SAS_TASK_COMPLETE;
1906                 ts->stat = SAS_ABORTED_TASK;
1907                 break;
1908         case IO_UNDERFLOW:
1909                 /* SSP Completion with error */
1910                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1911                         ",param = %d\n", param));
1912                 ts->resp = SAS_TASK_COMPLETE;
1913                 ts->stat = SAS_DATA_UNDERRUN;
1914                 ts->residual = param;
1915                 if (pm8001_dev)
1916                         pm8001_dev->running_req--;
1917                 break;
1918         case IO_NO_DEVICE:
1919                 PM8001_IO_DBG(pm8001_ha,
1920                         pm8001_printk("IO_NO_DEVICE\n"));
1921                 ts->resp = SAS_TASK_UNDELIVERED;
1922                 ts->stat = SAS_PHY_DOWN;
1923                 break;
1924         case IO_XFER_ERROR_BREAK:
1925                 PM8001_IO_DBG(pm8001_ha,
1926                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1927                 ts->resp = SAS_TASK_COMPLETE;
1928                 ts->stat = SAS_OPEN_REJECT;
1929                 /* Force the midlayer to retry */
1930                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1931                 break;
1932         case IO_XFER_ERROR_PHY_NOT_READY:
1933                 PM8001_IO_DBG(pm8001_ha,
1934                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1935                 ts->resp = SAS_TASK_COMPLETE;
1936                 ts->stat = SAS_OPEN_REJECT;
1937                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1938                 break;
1939         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1940                 PM8001_IO_DBG(pm8001_ha,
1941                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1942                 ts->resp = SAS_TASK_COMPLETE;
1943                 ts->stat = SAS_OPEN_REJECT;
1944                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1945                 break;
1946         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1947                 PM8001_IO_DBG(pm8001_ha,
1948                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1949                 ts->resp = SAS_TASK_COMPLETE;
1950                 ts->stat = SAS_OPEN_REJECT;
1951                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1952                 break;
1953         case IO_OPEN_CNX_ERROR_BREAK:
1954                 PM8001_IO_DBG(pm8001_ha,
1955                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1956                 ts->resp = SAS_TASK_COMPLETE;
1957                 ts->stat = SAS_OPEN_REJECT;
1958                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1959                 break;
1960         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1961                 PM8001_IO_DBG(pm8001_ha,
1962                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1963                 ts->resp = SAS_TASK_COMPLETE;
1964                 ts->stat = SAS_OPEN_REJECT;
1965                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1966                 if (!t->uldd_task)
1967                         pm8001_handle_event(pm8001_ha,
1968                                 pm8001_dev,
1969                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1970                 break;
1971         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1972                 PM8001_IO_DBG(pm8001_ha,
1973                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1974                 ts->resp = SAS_TASK_COMPLETE;
1975                 ts->stat = SAS_OPEN_REJECT;
1976                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1977                 break;
1978         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1979                 PM8001_IO_DBG(pm8001_ha,
1980                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1981                         "NOT_SUPPORTED\n"));
1982                 ts->resp = SAS_TASK_COMPLETE;
1983                 ts->stat = SAS_OPEN_REJECT;
1984                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1985                 break;
1986         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1987                 PM8001_IO_DBG(pm8001_ha,
1988                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1989                 ts->resp = SAS_TASK_UNDELIVERED;
1990                 ts->stat = SAS_OPEN_REJECT;
1991                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1992                 break;
1993         case IO_XFER_ERROR_NAK_RECEIVED:
1994                 PM8001_IO_DBG(pm8001_ha,
1995                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1996                 ts->resp = SAS_TASK_COMPLETE;
1997                 ts->stat = SAS_OPEN_REJECT;
1998                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1999                 break;
2000         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2001                 PM8001_IO_DBG(pm8001_ha,
2002                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2003                 ts->resp = SAS_TASK_COMPLETE;
2004                 ts->stat = SAS_NAK_R_ERR;
2005                 break;
2006         case IO_XFER_ERROR_DMA:
2007                 PM8001_IO_DBG(pm8001_ha,
2008                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2009                 ts->resp = SAS_TASK_COMPLETE;
2010                 ts->stat = SAS_OPEN_REJECT;
2011                 break;
2012         case IO_XFER_OPEN_RETRY_TIMEOUT:
2013                 PM8001_IO_DBG(pm8001_ha,
2014                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2015                 ts->resp = SAS_TASK_COMPLETE;
2016                 ts->stat = SAS_OPEN_REJECT;
2017                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2018                 break;
2019         case IO_XFER_ERROR_OFFSET_MISMATCH:
2020                 PM8001_IO_DBG(pm8001_ha,
2021                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2022                 ts->resp = SAS_TASK_COMPLETE;
2023                 ts->stat = SAS_OPEN_REJECT;
2024                 break;
2025         case IO_PORT_IN_RESET:
2026                 PM8001_IO_DBG(pm8001_ha,
2027                         pm8001_printk("IO_PORT_IN_RESET\n"));
2028                 ts->resp = SAS_TASK_COMPLETE;
2029                 ts->stat = SAS_OPEN_REJECT;
2030                 break;
2031         case IO_DS_NON_OPERATIONAL:
2032                 PM8001_IO_DBG(pm8001_ha,
2033                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2034                 ts->resp = SAS_TASK_COMPLETE;
2035                 ts->stat = SAS_OPEN_REJECT;
2036                 if (!t->uldd_task)
2037                         pm8001_handle_event(pm8001_ha,
2038                                 pm8001_dev,
2039                                 IO_DS_NON_OPERATIONAL);
2040                 break;
2041         case IO_DS_IN_RECOVERY:
2042                 PM8001_IO_DBG(pm8001_ha,
2043                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2044                 ts->resp = SAS_TASK_COMPLETE;
2045                 ts->stat = SAS_OPEN_REJECT;
2046                 break;
2047         case IO_TM_TAG_NOT_FOUND:
2048                 PM8001_IO_DBG(pm8001_ha,
2049                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
2050                 ts->resp = SAS_TASK_COMPLETE;
2051                 ts->stat = SAS_OPEN_REJECT;
2052                 break;
2053         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2054                 PM8001_IO_DBG(pm8001_ha,
2055                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
2056                 ts->resp = SAS_TASK_COMPLETE;
2057                 ts->stat = SAS_OPEN_REJECT;
2058                 break;
2059         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2060                 PM8001_IO_DBG(pm8001_ha,
2061                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2062                 ts->resp = SAS_TASK_COMPLETE;
2063                 ts->stat = SAS_OPEN_REJECT;
2064                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2065                 break;
2066         default:
2067                 PM8001_IO_DBG(pm8001_ha,
2068                         pm8001_printk("Unknown status 0x%x\n", status));
2069                 /* not allowed case. Therefore, return failed status */
2070                 ts->resp = SAS_TASK_COMPLETE;
2071                 ts->stat = SAS_OPEN_REJECT;
2072                 break;
2073         }
2074         PM8001_IO_DBG(pm8001_ha,
2075                 pm8001_printk("scsi_status = %x\n ",
2076                 psspPayload->ssp_resp_iu.status));
2077         spin_lock_irqsave(&t->task_state_lock, flags);
2078         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2079         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2080         t->task_state_flags |= SAS_TASK_STATE_DONE;
2081         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2082                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2083                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2084                         " io_status 0x%x resp 0x%x "
2085                         "stat 0x%x but aborted by upper layer!\n",
2086                         t, status, ts->resp, ts->stat));
2087                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2088         } else {
2089                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2090                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2091                 mb();/* in order to force CPU ordering */
2092                 t->task_done(t);
2093         }
2094 }
2095
2096 /*See the comments for mpi_ssp_completion */
2097 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2098 {
2099         struct sas_task *t;
2100         unsigned long flags;
2101         struct task_status_struct *ts;
2102         struct pm8001_ccb_info *ccb;
2103         struct pm8001_device *pm8001_dev;
2104         struct ssp_event_resp *psspPayload =
2105                 (struct ssp_event_resp *)(piomb + 4);
2106         u32 event = le32_to_cpu(psspPayload->event);
2107         u32 tag = le32_to_cpu(psspPayload->tag);
2108         u32 port_id = le32_to_cpu(psspPayload->port_id);
2109         u32 dev_id = le32_to_cpu(psspPayload->device_id);
2110
2111         ccb = &pm8001_ha->ccb_info[tag];
2112         t = ccb->task;
2113         pm8001_dev = ccb->device;
2114         if (event)
2115                 PM8001_FAIL_DBG(pm8001_ha,
2116                         pm8001_printk("sas IO status 0x%x\n", event));
2117         if (unlikely(!t || !t->lldd_task || !t->dev))
2118                 return;
2119         ts = &t->task_status;
2120         PM8001_IO_DBG(pm8001_ha,
2121                 pm8001_printk("port_id = %x,device_id = %x\n",
2122                 port_id, dev_id));
2123         switch (event) {
2124         case IO_OVERFLOW:
2125                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
2126                 ts->resp = SAS_TASK_COMPLETE;
2127                 ts->stat = SAS_DATA_OVERRUN;
2128                 ts->residual = 0;
2129                 if (pm8001_dev)
2130                         pm8001_dev->running_req--;
2131                 break;
2132         case IO_XFER_ERROR_BREAK:
2133                 PM8001_IO_DBG(pm8001_ha,
2134                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2135                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2136                 return;
2137         case IO_XFER_ERROR_PHY_NOT_READY:
2138                 PM8001_IO_DBG(pm8001_ha,
2139                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2140                 ts->resp = SAS_TASK_COMPLETE;
2141                 ts->stat = SAS_OPEN_REJECT;
2142                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2143                 break;
2144         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2145                 PM8001_IO_DBG(pm8001_ha,
2146                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2147                         "_SUPPORTED\n"));
2148                 ts->resp = SAS_TASK_COMPLETE;
2149                 ts->stat = SAS_OPEN_REJECT;
2150                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2151                 break;
2152         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2153                 PM8001_IO_DBG(pm8001_ha,
2154                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2155                 ts->resp = SAS_TASK_COMPLETE;
2156                 ts->stat = SAS_OPEN_REJECT;
2157                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2158                 break;
2159         case IO_OPEN_CNX_ERROR_BREAK:
2160                 PM8001_IO_DBG(pm8001_ha,
2161                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2162                 ts->resp = SAS_TASK_COMPLETE;
2163                 ts->stat = SAS_OPEN_REJECT;
2164                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2165                 break;
2166         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2167                 PM8001_IO_DBG(pm8001_ha,
2168                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2169                 ts->resp = SAS_TASK_COMPLETE;
2170                 ts->stat = SAS_OPEN_REJECT;
2171                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2172                 if (!t->uldd_task)
2173                         pm8001_handle_event(pm8001_ha,
2174                                 pm8001_dev,
2175                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2176                 break;
2177         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2178                 PM8001_IO_DBG(pm8001_ha,
2179                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2180                 ts->resp = SAS_TASK_COMPLETE;
2181                 ts->stat = SAS_OPEN_REJECT;
2182                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2183                 break;
2184         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2185                 PM8001_IO_DBG(pm8001_ha,
2186                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2187                         "NOT_SUPPORTED\n"));
2188                 ts->resp = SAS_TASK_COMPLETE;
2189                 ts->stat = SAS_OPEN_REJECT;
2190                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2191                 break;
2192         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2193                 PM8001_IO_DBG(pm8001_ha,
2194                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2195                 ts->resp = SAS_TASK_COMPLETE;
2196                 ts->stat = SAS_OPEN_REJECT;
2197                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2198                 break;
2199         case IO_XFER_ERROR_NAK_RECEIVED:
2200                 PM8001_IO_DBG(pm8001_ha,
2201                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2202                 ts->resp = SAS_TASK_COMPLETE;
2203                 ts->stat = SAS_OPEN_REJECT;
2204                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2205                 break;
2206         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2207                 PM8001_IO_DBG(pm8001_ha,
2208                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2209                 ts->resp = SAS_TASK_COMPLETE;
2210                 ts->stat = SAS_NAK_R_ERR;
2211                 break;
2212         case IO_XFER_OPEN_RETRY_TIMEOUT:
2213                 PM8001_IO_DBG(pm8001_ha,
2214                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2215                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2216                 return;
2217         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2218                 PM8001_IO_DBG(pm8001_ha,
2219                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2220                 ts->resp = SAS_TASK_COMPLETE;
2221                 ts->stat = SAS_DATA_OVERRUN;
2222                 break;
2223         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2224                 PM8001_IO_DBG(pm8001_ha,
2225                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2226                 ts->resp = SAS_TASK_COMPLETE;
2227                 ts->stat = SAS_DATA_OVERRUN;
2228                 break;
2229         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2230                 PM8001_IO_DBG(pm8001_ha,
2231                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2232                 ts->resp = SAS_TASK_COMPLETE;
2233                 ts->stat = SAS_DATA_OVERRUN;
2234                 break;
2235         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2236                 PM8001_IO_DBG(pm8001_ha,
2237                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2238                 ts->resp = SAS_TASK_COMPLETE;
2239                 ts->stat = SAS_DATA_OVERRUN;
2240                 break;
2241         case IO_XFER_ERROR_OFFSET_MISMATCH:
2242                 PM8001_IO_DBG(pm8001_ha,
2243                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2244                 ts->resp = SAS_TASK_COMPLETE;
2245                 ts->stat = SAS_DATA_OVERRUN;
2246                 break;
2247         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2248                 PM8001_IO_DBG(pm8001_ha,
2249                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2250                 ts->resp = SAS_TASK_COMPLETE;
2251                 ts->stat = SAS_DATA_OVERRUN;
2252                 break;
2253         case IO_XFER_CMD_FRAME_ISSUED:
2254                 PM8001_IO_DBG(pm8001_ha,
2255                         pm8001_printk("  IO_XFER_CMD_FRAME_ISSUED\n"));
2256                 return;
2257         default:
2258                 PM8001_IO_DBG(pm8001_ha,
2259                         pm8001_printk("Unknown status 0x%x\n", event));
2260                 /* not allowed case. Therefore, return failed status */
2261                 ts->resp = SAS_TASK_COMPLETE;
2262                 ts->stat = SAS_DATA_OVERRUN;
2263                 break;
2264         }
2265         spin_lock_irqsave(&t->task_state_lock, flags);
2266         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2267         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2268         t->task_state_flags |= SAS_TASK_STATE_DONE;
2269         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2270                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2271                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2272                         " event 0x%x resp 0x%x "
2273                         "stat 0x%x but aborted by upper layer!\n",
2274                         t, event, ts->resp, ts->stat));
2275                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2276         } else {
2277                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2278                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2279                 mb();/* in order to force CPU ordering */
2280                 t->task_done(t);
2281         }
2282 }
2283
2284 /*See the comments for mpi_ssp_completion */
2285 static void
2286 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2287 {
2288         struct sas_task *t;
2289         struct pm8001_ccb_info *ccb;
2290         u32 param;
2291         u32 status;
2292         u32 tag;
2293         int i, j;
2294         u8 sata_addr_low[4];
2295         u32 temp_sata_addr_low;
2296         u8 sata_addr_hi[4];
2297         u32 temp_sata_addr_hi;
2298         struct sata_completion_resp *psataPayload;
2299         struct task_status_struct *ts;
2300         struct ata_task_resp *resp ;
2301         u32 *sata_resp;
2302         struct pm8001_device *pm8001_dev;
2303         unsigned long flags;
2304
2305         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2306         status = le32_to_cpu(psataPayload->status);
2307         tag = le32_to_cpu(psataPayload->tag);
2308
2309         if (!tag) {
2310                 PM8001_FAIL_DBG(pm8001_ha,
2311                         pm8001_printk("tag null\n"));
2312                 return;
2313         }
2314         ccb = &pm8001_ha->ccb_info[tag];
2315         param = le32_to_cpu(psataPayload->param);
2316         if (ccb) {
2317                 t = ccb->task;
2318                 pm8001_dev = ccb->device;
2319         } else {
2320                 PM8001_FAIL_DBG(pm8001_ha,
2321                         pm8001_printk("ccb null\n"));
2322                 return;
2323         }
2324
2325         if (t) {
2326                 if (t->dev && (t->dev->lldd_dev))
2327                         pm8001_dev = t->dev->lldd_dev;
2328         } else {
2329                 PM8001_FAIL_DBG(pm8001_ha,
2330                         pm8001_printk("task null\n"));
2331                 return;
2332         }
2333
2334         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2335                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2336                 PM8001_FAIL_DBG(pm8001_ha,
2337                         pm8001_printk("task or dev null\n"));
2338                 return;
2339         }
2340
2341         ts = &t->task_status;
2342         if (!ts) {
2343                 PM8001_FAIL_DBG(pm8001_ha,
2344                         pm8001_printk("ts null\n"));
2345                 return;
2346         }
2347         /* Print sas address of IO failed device */
2348         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2349                 (status != IO_UNDERFLOW)) {
2350                 if (!((t->dev->parent) &&
2351                         (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2352                         for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++)
2353                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2354                         for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++)
2355                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2356                         memcpy(&temp_sata_addr_low, sata_addr_low,
2357                                 sizeof(sata_addr_low));
2358                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2359                                 sizeof(sata_addr_hi));
2360                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2361                                                 |((temp_sata_addr_hi << 8) &
2362                                                 0xff0000) |
2363                                                 ((temp_sata_addr_hi >> 8)
2364                                                 & 0xff00) |
2365                                                 ((temp_sata_addr_hi << 24) &
2366                                                 0xff000000));
2367                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2368                                                 & 0xff) |
2369                                                 ((temp_sata_addr_low << 8)
2370                                                 & 0xff0000) |
2371                                                 ((temp_sata_addr_low >> 8)
2372                                                 & 0xff00) |
2373                                                 ((temp_sata_addr_low << 24)
2374                                                 & 0xff000000)) +
2375                                                 pm8001_dev->attached_phy +
2376                                                 0x10);
2377                         PM8001_FAIL_DBG(pm8001_ha,
2378                                 pm8001_printk("SAS Address of IO Failure Drive:"
2379                                 "%08x%08x", temp_sata_addr_hi,
2380                                         temp_sata_addr_low));
2381                 } else {
2382                         PM8001_FAIL_DBG(pm8001_ha,
2383                                 pm8001_printk("SAS Address of IO Failure Drive:"
2384                                 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2385                 }
2386         }
2387         switch (status) {
2388         case IO_SUCCESS:
2389                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2390                 if (param == 0) {
2391                         ts->resp = SAS_TASK_COMPLETE;
2392                         ts->stat = SAM_STAT_GOOD;
2393                         /* check if response is for SEND READ LOG */
2394                         if (pm8001_dev &&
2395                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2396                                 /* set new bit for abort_all */
2397                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2398                                 /* clear bit for read log */
2399                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2400                                 pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2401                                 /* Free the tag */
2402                                 pm8001_tag_free(pm8001_ha, tag);
2403                                 sas_free_task(t);
2404                                 return;
2405                         }
2406                 } else {
2407                         u8 len;
2408                         ts->resp = SAS_TASK_COMPLETE;
2409                         ts->stat = SAS_PROTO_RESPONSE;
2410                         ts->residual = param;
2411                         PM8001_IO_DBG(pm8001_ha,
2412                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2413                                 param));
2414                         sata_resp = &psataPayload->sata_resp[0];
2415                         resp = (struct ata_task_resp *)ts->buf;
2416                         if (t->ata_task.dma_xfer == 0 &&
2417                         t->data_dir == PCI_DMA_FROMDEVICE) {
2418                                 len = sizeof(struct pio_setup_fis);
2419                                 PM8001_IO_DBG(pm8001_ha,
2420                                 pm8001_printk("PIO read len = %d\n", len));
2421                         } else if (t->ata_task.use_ncq) {
2422                                 len = sizeof(struct set_dev_bits_fis);
2423                                 PM8001_IO_DBG(pm8001_ha,
2424                                         pm8001_printk("FPDMA len = %d\n", len));
2425                         } else {
2426                                 len = sizeof(struct dev_to_host_fis);
2427                                 PM8001_IO_DBG(pm8001_ha,
2428                                 pm8001_printk("other len = %d\n", len));
2429                         }
2430                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2431                                 resp->frame_len = len;
2432                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2433                                 ts->buf_valid_size = sizeof(*resp);
2434                         } else
2435                                 PM8001_IO_DBG(pm8001_ha,
2436                                         pm8001_printk("response to large\n"));
2437                 }
2438                 if (pm8001_dev)
2439                         pm8001_dev->running_req--;
2440                 break;
2441         case IO_ABORTED:
2442                 PM8001_IO_DBG(pm8001_ha,
2443                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2444                 ts->resp = SAS_TASK_COMPLETE;
2445                 ts->stat = SAS_ABORTED_TASK;
2446                 if (pm8001_dev)
2447                         pm8001_dev->running_req--;
2448                 break;
2449                 /* following cases are to do cases */
2450         case IO_UNDERFLOW:
2451                 /* SATA Completion with error */
2452                 PM8001_IO_DBG(pm8001_ha,
2453                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2454                 ts->resp = SAS_TASK_COMPLETE;
2455                 ts->stat = SAS_DATA_UNDERRUN;
2456                 ts->residual =  param;
2457                 if (pm8001_dev)
2458                         pm8001_dev->running_req--;
2459                 break;
2460         case IO_NO_DEVICE:
2461                 PM8001_IO_DBG(pm8001_ha,
2462                         pm8001_printk("IO_NO_DEVICE\n"));
2463                 ts->resp = SAS_TASK_UNDELIVERED;
2464                 ts->stat = SAS_PHY_DOWN;
2465                 break;
2466         case IO_XFER_ERROR_BREAK:
2467                 PM8001_IO_DBG(pm8001_ha,
2468                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2469                 ts->resp = SAS_TASK_COMPLETE;
2470                 ts->stat = SAS_INTERRUPTED;
2471                 break;
2472         case IO_XFER_ERROR_PHY_NOT_READY:
2473                 PM8001_IO_DBG(pm8001_ha,
2474                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2475                 ts->resp = SAS_TASK_COMPLETE;
2476                 ts->stat = SAS_OPEN_REJECT;
2477                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2478                 break;
2479         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2480                 PM8001_IO_DBG(pm8001_ha,
2481                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2482                         "_SUPPORTED\n"));
2483                 ts->resp = SAS_TASK_COMPLETE;
2484                 ts->stat = SAS_OPEN_REJECT;
2485                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2486                 break;
2487         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2488                 PM8001_IO_DBG(pm8001_ha,
2489                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2490                 ts->resp = SAS_TASK_COMPLETE;
2491                 ts->stat = SAS_OPEN_REJECT;
2492                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2493                 break;
2494         case IO_OPEN_CNX_ERROR_BREAK:
2495                 PM8001_IO_DBG(pm8001_ha,
2496                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2497                 ts->resp = SAS_TASK_COMPLETE;
2498                 ts->stat = SAS_OPEN_REJECT;
2499                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2500                 break;
2501         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2502                 PM8001_IO_DBG(pm8001_ha,
2503                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2504                 ts->resp = SAS_TASK_COMPLETE;
2505                 ts->stat = SAS_DEV_NO_RESPONSE;
2506                 if (!t->uldd_task) {
2507                         pm8001_handle_event(pm8001_ha,
2508                                 pm8001_dev,
2509                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2510                         ts->resp = SAS_TASK_UNDELIVERED;
2511                         ts->stat = SAS_QUEUE_FULL;
2512                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2513                         return;
2514                 }
2515                 break;
2516         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2517                 PM8001_IO_DBG(pm8001_ha,
2518                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2519                 ts->resp = SAS_TASK_UNDELIVERED;
2520                 ts->stat = SAS_OPEN_REJECT;
2521                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2522                 if (!t->uldd_task) {
2523                         pm8001_handle_event(pm8001_ha,
2524                                 pm8001_dev,
2525                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2526                         ts->resp = SAS_TASK_UNDELIVERED;
2527                         ts->stat = SAS_QUEUE_FULL;
2528                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2529                         return;
2530                 }
2531                 break;
2532         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2533                 PM8001_IO_DBG(pm8001_ha,
2534                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2535                         "NOT_SUPPORTED\n"));
2536                 ts->resp = SAS_TASK_COMPLETE;
2537                 ts->stat = SAS_OPEN_REJECT;
2538                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2539                 break;
2540         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2541                 PM8001_IO_DBG(pm8001_ha,
2542                         pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2543                         "_BUSY\n"));
2544                 ts->resp = SAS_TASK_COMPLETE;
2545                 ts->stat = SAS_DEV_NO_RESPONSE;
2546                 if (!t->uldd_task) {
2547                         pm8001_handle_event(pm8001_ha,
2548                                 pm8001_dev,
2549                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2550                         ts->resp = SAS_TASK_UNDELIVERED;
2551                         ts->stat = SAS_QUEUE_FULL;
2552                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2553                         return;
2554                 }
2555                 break;
2556         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2557                 PM8001_IO_DBG(pm8001_ha,
2558                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2559                 ts->resp = SAS_TASK_COMPLETE;
2560                 ts->stat = SAS_OPEN_REJECT;
2561                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2562                 break;
2563         case IO_XFER_ERROR_NAK_RECEIVED:
2564                 PM8001_IO_DBG(pm8001_ha,
2565                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2566                 ts->resp = SAS_TASK_COMPLETE;
2567                 ts->stat = SAS_NAK_R_ERR;
2568                 break;
2569         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2570                 PM8001_IO_DBG(pm8001_ha,
2571                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2572                 ts->resp = SAS_TASK_COMPLETE;
2573                 ts->stat = SAS_NAK_R_ERR;
2574                 break;
2575         case IO_XFER_ERROR_DMA:
2576                 PM8001_IO_DBG(pm8001_ha,
2577                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2578                 ts->resp = SAS_TASK_COMPLETE;
2579                 ts->stat = SAS_ABORTED_TASK;
2580                 break;
2581         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2582                 PM8001_IO_DBG(pm8001_ha,
2583                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2584                 ts->resp = SAS_TASK_UNDELIVERED;
2585                 ts->stat = SAS_DEV_NO_RESPONSE;
2586                 break;
2587         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2588                 PM8001_IO_DBG(pm8001_ha,
2589                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2590                 ts->resp = SAS_TASK_COMPLETE;
2591                 ts->stat = SAS_DATA_UNDERRUN;
2592                 break;
2593         case IO_XFER_OPEN_RETRY_TIMEOUT:
2594                 PM8001_IO_DBG(pm8001_ha,
2595                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2596                 ts->resp = SAS_TASK_COMPLETE;
2597                 ts->stat = SAS_OPEN_TO;
2598                 break;
2599         case IO_PORT_IN_RESET:
2600                 PM8001_IO_DBG(pm8001_ha,
2601                         pm8001_printk("IO_PORT_IN_RESET\n"));
2602                 ts->resp = SAS_TASK_COMPLETE;
2603                 ts->stat = SAS_DEV_NO_RESPONSE;
2604                 break;
2605         case IO_DS_NON_OPERATIONAL:
2606                 PM8001_IO_DBG(pm8001_ha,
2607                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2608                 ts->resp = SAS_TASK_COMPLETE;
2609                 ts->stat = SAS_DEV_NO_RESPONSE;
2610                 if (!t->uldd_task) {
2611                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2612                                     IO_DS_NON_OPERATIONAL);
2613                         ts->resp = SAS_TASK_UNDELIVERED;
2614                         ts->stat = SAS_QUEUE_FULL;
2615                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2616                         return;
2617                 }
2618                 break;
2619         case IO_DS_IN_RECOVERY:
2620                 PM8001_IO_DBG(pm8001_ha,
2621                         pm8001_printk("  IO_DS_IN_RECOVERY\n"));
2622                 ts->resp = SAS_TASK_COMPLETE;
2623                 ts->stat = SAS_DEV_NO_RESPONSE;
2624                 break;
2625         case IO_DS_IN_ERROR:
2626                 PM8001_IO_DBG(pm8001_ha,
2627                         pm8001_printk("IO_DS_IN_ERROR\n"));
2628                 ts->resp = SAS_TASK_COMPLETE;
2629                 ts->stat = SAS_DEV_NO_RESPONSE;
2630                 if (!t->uldd_task) {
2631                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2632                                     IO_DS_IN_ERROR);
2633                         ts->resp = SAS_TASK_UNDELIVERED;
2634                         ts->stat = SAS_QUEUE_FULL;
2635                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2636                         return;
2637                 }
2638                 break;
2639         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2640                 PM8001_IO_DBG(pm8001_ha,
2641                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2642                 ts->resp = SAS_TASK_COMPLETE;
2643                 ts->stat = SAS_OPEN_REJECT;
2644                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2645         default:
2646                 PM8001_IO_DBG(pm8001_ha,
2647                         pm8001_printk("Unknown status 0x%x\n", status));
2648                 /* not allowed case. Therefore, return failed status */
2649                 ts->resp = SAS_TASK_COMPLETE;
2650                 ts->stat = SAS_DEV_NO_RESPONSE;
2651                 break;
2652         }
2653         spin_lock_irqsave(&t->task_state_lock, flags);
2654         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2655         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2656         t->task_state_flags |= SAS_TASK_STATE_DONE;
2657         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2658                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2659                 PM8001_FAIL_DBG(pm8001_ha,
2660                         pm8001_printk("task 0x%p done with io_status 0x%x"
2661                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2662                         t, status, ts->resp, ts->stat));
2663                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2664         } else {
2665                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2666                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2667         }
2668 }
2669
2670 /*See the comments for mpi_ssp_completion */
2671 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2672 {
2673         struct sas_task *t;
2674         struct task_status_struct *ts;
2675         struct pm8001_ccb_info *ccb;
2676         struct pm8001_device *pm8001_dev;
2677         struct sata_event_resp *psataPayload =
2678                 (struct sata_event_resp *)(piomb + 4);
2679         u32 event = le32_to_cpu(psataPayload->event);
2680         u32 tag = le32_to_cpu(psataPayload->tag);
2681         u32 port_id = le32_to_cpu(psataPayload->port_id);
2682         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2683         unsigned long flags;
2684
2685         ccb = &pm8001_ha->ccb_info[tag];
2686
2687         if (ccb) {
2688                 t = ccb->task;
2689                 pm8001_dev = ccb->device;
2690         } else {
2691                 PM8001_FAIL_DBG(pm8001_ha,
2692                         pm8001_printk("No CCB !!!. returning\n"));
2693         }
2694         if (event)
2695                 PM8001_FAIL_DBG(pm8001_ha,
2696                         pm8001_printk("SATA EVENT 0x%x\n", event));
2697
2698         /* Check if this is NCQ error */
2699         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2700                 /* find device using device id */
2701                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2702                 /* send read log extension */
2703                 if (pm8001_dev)
2704                         pm8001_send_read_log(pm8001_ha, pm8001_dev);
2705                 return;
2706         }
2707
2708         ccb = &pm8001_ha->ccb_info[tag];
2709         t = ccb->task;
2710         pm8001_dev = ccb->device;
2711         if (event)
2712                 PM8001_FAIL_DBG(pm8001_ha,
2713                         pm8001_printk("sata IO status 0x%x\n", event));
2714         if (unlikely(!t || !t->lldd_task || !t->dev))
2715                 return;
2716         ts = &t->task_status;
2717         PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2718                 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2719                 port_id, dev_id, tag, event));
2720         switch (event) {
2721         case IO_OVERFLOW:
2722                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2723                 ts->resp = SAS_TASK_COMPLETE;
2724                 ts->stat = SAS_DATA_OVERRUN;
2725                 ts->residual = 0;
2726                 if (pm8001_dev)
2727                         pm8001_dev->running_req--;
2728                 break;
2729         case IO_XFER_ERROR_BREAK:
2730                 PM8001_IO_DBG(pm8001_ha,
2731                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2732                 ts->resp = SAS_TASK_COMPLETE;
2733                 ts->stat = SAS_INTERRUPTED;
2734                 break;
2735         case IO_XFER_ERROR_PHY_NOT_READY:
2736                 PM8001_IO_DBG(pm8001_ha,
2737                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2738                 ts->resp = SAS_TASK_COMPLETE;
2739                 ts->stat = SAS_OPEN_REJECT;
2740                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2741                 break;
2742         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2743                 PM8001_IO_DBG(pm8001_ha,
2744                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2745                         "_SUPPORTED\n"));
2746                 ts->resp = SAS_TASK_COMPLETE;
2747                 ts->stat = SAS_OPEN_REJECT;
2748                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2749                 break;
2750         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2751                 PM8001_IO_DBG(pm8001_ha,
2752                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2753                 ts->resp = SAS_TASK_COMPLETE;
2754                 ts->stat = SAS_OPEN_REJECT;
2755                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2756                 break;
2757         case IO_OPEN_CNX_ERROR_BREAK:
2758                 PM8001_IO_DBG(pm8001_ha,
2759                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2760                 ts->resp = SAS_TASK_COMPLETE;
2761                 ts->stat = SAS_OPEN_REJECT;
2762                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2763                 break;
2764         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2765                 PM8001_IO_DBG(pm8001_ha,
2766                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2767                 ts->resp = SAS_TASK_UNDELIVERED;
2768                 ts->stat = SAS_DEV_NO_RESPONSE;
2769                 if (!t->uldd_task) {
2770                         pm8001_handle_event(pm8001_ha,
2771                                 pm8001_dev,
2772                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2773                         ts->resp = SAS_TASK_COMPLETE;
2774                         ts->stat = SAS_QUEUE_FULL;
2775                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2776                         return;
2777                 }
2778                 break;
2779         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2780                 PM8001_IO_DBG(pm8001_ha,
2781                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2782                 ts->resp = SAS_TASK_UNDELIVERED;
2783                 ts->stat = SAS_OPEN_REJECT;
2784                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2785                 break;
2786         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2787                 PM8001_IO_DBG(pm8001_ha,
2788                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2789                         "NOT_SUPPORTED\n"));
2790                 ts->resp = SAS_TASK_COMPLETE;
2791                 ts->stat = SAS_OPEN_REJECT;
2792                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2793                 break;
2794         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2795                 PM8001_IO_DBG(pm8001_ha,
2796                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2797                 ts->resp = SAS_TASK_COMPLETE;
2798                 ts->stat = SAS_OPEN_REJECT;
2799                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2800                 break;
2801         case IO_XFER_ERROR_NAK_RECEIVED:
2802                 PM8001_IO_DBG(pm8001_ha,
2803                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2804                 ts->resp = SAS_TASK_COMPLETE;
2805                 ts->stat = SAS_NAK_R_ERR;
2806                 break;
2807         case IO_XFER_ERROR_PEER_ABORTED:
2808                 PM8001_IO_DBG(pm8001_ha,
2809                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2810                 ts->resp = SAS_TASK_COMPLETE;
2811                 ts->stat = SAS_NAK_R_ERR;
2812                 break;
2813         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2814                 PM8001_IO_DBG(pm8001_ha,
2815                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2816                 ts->resp = SAS_TASK_COMPLETE;
2817                 ts->stat = SAS_DATA_UNDERRUN;
2818                 break;
2819         case IO_XFER_OPEN_RETRY_TIMEOUT:
2820                 PM8001_IO_DBG(pm8001_ha,
2821                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2822                 ts->resp = SAS_TASK_COMPLETE;
2823                 ts->stat = SAS_OPEN_TO;
2824                 break;
2825         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2826                 PM8001_IO_DBG(pm8001_ha,
2827                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2828                 ts->resp = SAS_TASK_COMPLETE;
2829                 ts->stat = SAS_OPEN_TO;
2830                 break;
2831         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2832                 PM8001_IO_DBG(pm8001_ha,
2833                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2834                 ts->resp = SAS_TASK_COMPLETE;
2835                 ts->stat = SAS_OPEN_TO;
2836                 break;
2837         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2838                 PM8001_IO_DBG(pm8001_ha,
2839                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2840                 ts->resp = SAS_TASK_COMPLETE;
2841                 ts->stat = SAS_OPEN_TO;
2842                 break;
2843         case IO_XFER_ERROR_OFFSET_MISMATCH:
2844                 PM8001_IO_DBG(pm8001_ha,
2845                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2846                 ts->resp = SAS_TASK_COMPLETE;
2847                 ts->stat = SAS_OPEN_TO;
2848                 break;
2849         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2850                 PM8001_IO_DBG(pm8001_ha,
2851                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2852                 ts->resp = SAS_TASK_COMPLETE;
2853                 ts->stat = SAS_OPEN_TO;
2854                 break;
2855         case IO_XFER_CMD_FRAME_ISSUED:
2856                 PM8001_IO_DBG(pm8001_ha,
2857                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2858                 break;
2859         case IO_XFER_PIO_SETUP_ERROR:
2860                 PM8001_IO_DBG(pm8001_ha,
2861                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2862                 ts->resp = SAS_TASK_COMPLETE;
2863                 ts->stat = SAS_OPEN_TO;
2864                 break;
2865         default:
2866                 PM8001_IO_DBG(pm8001_ha,
2867                         pm8001_printk("Unknown status 0x%x\n", event));
2868                 /* not allowed case. Therefore, return failed status */
2869                 ts->resp = SAS_TASK_COMPLETE;
2870                 ts->stat = SAS_OPEN_TO;
2871                 break;
2872         }
2873         spin_lock_irqsave(&t->task_state_lock, flags);
2874         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2875         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2876         t->task_state_flags |= SAS_TASK_STATE_DONE;
2877         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2878                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2879                 PM8001_FAIL_DBG(pm8001_ha,
2880                         pm8001_printk("task 0x%p done with io_status 0x%x"
2881                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2882                         t, event, ts->resp, ts->stat));
2883                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2884         } else {
2885                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2886                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2887         }
2888 }
2889
2890 /*See the comments for mpi_ssp_completion */
2891 static void
2892 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2893 {
2894         u32 param;
2895         struct sas_task *t;
2896         struct pm8001_ccb_info *ccb;
2897         unsigned long flags;
2898         u32 status;
2899         u32 tag;
2900         struct smp_completion_resp *psmpPayload;
2901         struct task_status_struct *ts;
2902         struct pm8001_device *pm8001_dev;
2903
2904         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2905         status = le32_to_cpu(psmpPayload->status);
2906         tag = le32_to_cpu(psmpPayload->tag);
2907
2908         ccb = &pm8001_ha->ccb_info[tag];
2909         param = le32_to_cpu(psmpPayload->param);
2910         t = ccb->task;
2911         ts = &t->task_status;
2912         pm8001_dev = ccb->device;
2913         if (status)
2914                 PM8001_FAIL_DBG(pm8001_ha,
2915                         pm8001_printk("smp IO status 0x%x\n", status));
2916         if (unlikely(!t || !t->lldd_task || !t->dev))
2917                 return;
2918
2919         switch (status) {
2920         case IO_SUCCESS:
2921                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2922                 ts->resp = SAS_TASK_COMPLETE;
2923                 ts->stat = SAM_STAT_GOOD;
2924         if (pm8001_dev)
2925                         pm8001_dev->running_req--;
2926                 break;
2927         case IO_ABORTED:
2928                 PM8001_IO_DBG(pm8001_ha,
2929                         pm8001_printk("IO_ABORTED IOMB\n"));
2930                 ts->resp = SAS_TASK_COMPLETE;
2931                 ts->stat = SAS_ABORTED_TASK;
2932                 if (pm8001_dev)
2933                         pm8001_dev->running_req--;
2934                 break;
2935         case IO_OVERFLOW:
2936                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2937                 ts->resp = SAS_TASK_COMPLETE;
2938                 ts->stat = SAS_DATA_OVERRUN;
2939                 ts->residual = 0;
2940                 if (pm8001_dev)
2941                         pm8001_dev->running_req--;
2942                 break;
2943         case IO_NO_DEVICE:
2944                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2945                 ts->resp = SAS_TASK_COMPLETE;
2946                 ts->stat = SAS_PHY_DOWN;
2947                 break;
2948         case IO_ERROR_HW_TIMEOUT:
2949                 PM8001_IO_DBG(pm8001_ha,
2950                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2951                 ts->resp = SAS_TASK_COMPLETE;
2952                 ts->stat = SAM_STAT_BUSY;
2953                 break;
2954         case IO_XFER_ERROR_BREAK:
2955                 PM8001_IO_DBG(pm8001_ha,
2956                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2957                 ts->resp = SAS_TASK_COMPLETE;
2958                 ts->stat = SAM_STAT_BUSY;
2959                 break;
2960         case IO_XFER_ERROR_PHY_NOT_READY:
2961                 PM8001_IO_DBG(pm8001_ha,
2962                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2963                 ts->resp = SAS_TASK_COMPLETE;
2964                 ts->stat = SAM_STAT_BUSY;
2965                 break;
2966         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2967                 PM8001_IO_DBG(pm8001_ha,
2968                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2969                 ts->resp = SAS_TASK_COMPLETE;
2970                 ts->stat = SAS_OPEN_REJECT;
2971                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2972                 break;
2973         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2974                 PM8001_IO_DBG(pm8001_ha,
2975                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2976                 ts->resp = SAS_TASK_COMPLETE;
2977                 ts->stat = SAS_OPEN_REJECT;
2978                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2979                 break;
2980         case IO_OPEN_CNX_ERROR_BREAK:
2981                 PM8001_IO_DBG(pm8001_ha,
2982                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2983                 ts->resp = SAS_TASK_COMPLETE;
2984                 ts->stat = SAS_OPEN_REJECT;
2985                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2986                 break;
2987         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2988                 PM8001_IO_DBG(pm8001_ha,
2989                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2990                 ts->resp = SAS_TASK_COMPLETE;
2991                 ts->stat = SAS_OPEN_REJECT;
2992                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2993                 pm8001_handle_event(pm8001_ha,
2994                                 pm8001_dev,
2995                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2996                 break;
2997         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2998                 PM8001_IO_DBG(pm8001_ha,
2999                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
3000                 ts->resp = SAS_TASK_COMPLETE;
3001                 ts->stat = SAS_OPEN_REJECT;
3002                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3003                 break;
3004         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3005                 PM8001_IO_DBG(pm8001_ha,
3006                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
3007                         "NOT_SUPPORTED\n"));
3008                 ts->resp = SAS_TASK_COMPLETE;
3009                 ts->stat = SAS_OPEN_REJECT;
3010                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3011                 break;
3012         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3013                 PM8001_IO_DBG(pm8001_ha,
3014                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
3015                 ts->resp = SAS_TASK_COMPLETE;
3016                 ts->stat = SAS_OPEN_REJECT;
3017                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3018                 break;
3019         case IO_XFER_ERROR_RX_FRAME:
3020                 PM8001_IO_DBG(pm8001_ha,
3021                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
3022                 ts->resp = SAS_TASK_COMPLETE;
3023                 ts->stat = SAS_DEV_NO_RESPONSE;
3024                 break;
3025         case IO_XFER_OPEN_RETRY_TIMEOUT:
3026                 PM8001_IO_DBG(pm8001_ha,
3027                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
3028                 ts->resp = SAS_TASK_COMPLETE;
3029                 ts->stat = SAS_OPEN_REJECT;
3030                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3031                 break;
3032         case IO_ERROR_INTERNAL_SMP_RESOURCE:
3033                 PM8001_IO_DBG(pm8001_ha,
3034                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
3035                 ts->resp = SAS_TASK_COMPLETE;
3036                 ts->stat = SAS_QUEUE_FULL;
3037                 break;
3038         case IO_PORT_IN_RESET:
3039                 PM8001_IO_DBG(pm8001_ha,
3040                         pm8001_printk("IO_PORT_IN_RESET\n"));
3041                 ts->resp = SAS_TASK_COMPLETE;
3042                 ts->stat = SAS_OPEN_REJECT;
3043                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3044                 break;
3045         case IO_DS_NON_OPERATIONAL:
3046                 PM8001_IO_DBG(pm8001_ha,
3047                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
3048                 ts->resp = SAS_TASK_COMPLETE;
3049                 ts->stat = SAS_DEV_NO_RESPONSE;
3050                 break;
3051         case IO_DS_IN_RECOVERY:
3052                 PM8001_IO_DBG(pm8001_ha,
3053                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
3054                 ts->resp = SAS_TASK_COMPLETE;
3055                 ts->stat = SAS_OPEN_REJECT;
3056                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3057                 break;
3058         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3059                 PM8001_IO_DBG(pm8001_ha,
3060                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
3061                 ts->resp = SAS_TASK_COMPLETE;
3062                 ts->stat = SAS_OPEN_REJECT;
3063                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3064                 break;
3065         default:
3066                 PM8001_IO_DBG(pm8001_ha,
3067                         pm8001_printk("Unknown status 0x%x\n", status));
3068                 ts->resp = SAS_TASK_COMPLETE;
3069                 ts->stat = SAS_DEV_NO_RESPONSE;
3070                 /* not allowed case. Therefore, return failed status */
3071                 break;
3072         }
3073         spin_lock_irqsave(&t->task_state_lock, flags);
3074         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3075         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3076         t->task_state_flags |= SAS_TASK_STATE_DONE;
3077         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3078                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3079                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
3080                         " io_status 0x%x resp 0x%x "
3081                         "stat 0x%x but aborted by upper layer!\n",
3082                         t, status, ts->resp, ts->stat));
3083                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3084         } else {
3085                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3086                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3087                 mb();/* in order to force CPU ordering */
3088                 t->task_done(t);
3089         }
3090 }
3091
3092 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3093                 void *piomb)
3094 {
3095         struct set_dev_state_resp *pPayload =
3096                 (struct set_dev_state_resp *)(piomb + 4);
3097         u32 tag = le32_to_cpu(pPayload->tag);
3098         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3099         struct pm8001_device *pm8001_dev = ccb->device;
3100         u32 status = le32_to_cpu(pPayload->status);
3101         u32 device_id = le32_to_cpu(pPayload->device_id);
3102         u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3103         u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3104         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
3105                 "from 0x%x to 0x%x status = 0x%x!\n",
3106                 device_id, pds, nds, status));
3107         complete(pm8001_dev->setds_completion);
3108         ccb->task = NULL;
3109         ccb->ccb_tag = 0xFFFFFFFF;
3110         pm8001_tag_free(pm8001_ha, tag);
3111 }
3112
3113 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3114 {
3115         struct get_nvm_data_resp *pPayload =
3116                 (struct get_nvm_data_resp *)(piomb + 4);
3117         u32 tag = le32_to_cpu(pPayload->tag);
3118         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3119         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3120         complete(pm8001_ha->nvmd_completion);
3121         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
3122         if ((dlen_status & NVMD_STAT) != 0) {
3123                 PM8001_FAIL_DBG(pm8001_ha,
3124                         pm8001_printk("Set nvm data error!\n"));
3125                 return;
3126         }
3127         ccb->task = NULL;
3128         ccb->ccb_tag = 0xFFFFFFFF;
3129         pm8001_tag_free(pm8001_ha, tag);
3130 }
3131
3132 void
3133 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3134 {
3135         struct fw_control_ex    *fw_control_context;
3136         struct get_nvm_data_resp *pPayload =
3137                 (struct get_nvm_data_resp *)(piomb + 4);
3138         u32 tag = le32_to_cpu(pPayload->tag);
3139         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3140         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3141         u32 ir_tds_bn_dps_das_nvm =
3142                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3143         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3144         fw_control_context = ccb->fw_control_context;
3145
3146         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
3147         if ((dlen_status & NVMD_STAT) != 0) {
3148                 PM8001_FAIL_DBG(pm8001_ha,
3149                         pm8001_printk("Get nvm data error!\n"));
3150                 complete(pm8001_ha->nvmd_completion);
3151                 return;
3152         }
3153
3154         if (ir_tds_bn_dps_das_nvm & IPMode) {
3155                 /* indirect mode - IR bit set */
3156                 PM8001_MSG_DBG(pm8001_ha,
3157                         pm8001_printk("Get NVMD success, IR=1\n"));
3158                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3159                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3160                                 memcpy(pm8001_ha->sas_addr,
3161                                       ((u8 *)virt_addr + 4),
3162                                        SAS_ADDR_SIZE);
3163                                 PM8001_MSG_DBG(pm8001_ha,
3164                                         pm8001_printk("Get SAS address"
3165                                         " from VPD successfully!\n"));
3166                         }
3167                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3168                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3169                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3170                                 ;
3171                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3172                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3173                         ;
3174                 } else {
3175                         /* Should not be happened*/
3176                         PM8001_MSG_DBG(pm8001_ha,
3177                                 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
3178                                 ir_tds_bn_dps_das_nvm));
3179                 }
3180         } else /* direct mode */{
3181                 PM8001_MSG_DBG(pm8001_ha,
3182                         pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
3183                         (dlen_status & NVMD_LEN) >> 24));
3184         }
3185         /* Though fw_control_context is freed below, usrAddr still needs
3186          * to be updated as this holds the response to the request function
3187          */
3188         memcpy(fw_control_context->usrAddr,
3189                 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3190                 fw_control_context->len);
3191         kfree(ccb->fw_control_context);
3192         ccb->task = NULL;
3193         ccb->ccb_tag = 0xFFFFFFFF;
3194         pm8001_tag_free(pm8001_ha, tag);
3195         complete(pm8001_ha->nvmd_completion);
3196 }
3197
3198 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3199 {
3200         struct local_phy_ctl_resp *pPayload =
3201                 (struct local_phy_ctl_resp *)(piomb + 4);
3202         u32 status = le32_to_cpu(pPayload->status);
3203         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3204         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3205         if (status != 0) {
3206                 PM8001_MSG_DBG(pm8001_ha,
3207                         pm8001_printk("%x phy execute %x phy op failed!\n",
3208                         phy_id, phy_op));
3209         } else
3210                 PM8001_MSG_DBG(pm8001_ha,
3211                         pm8001_printk("%x phy execute %x phy op success!\n",
3212                         phy_id, phy_op));
3213         return 0;
3214 }
3215
3216 /**
3217  * pm8001_bytes_dmaed - one of the interface function communication with libsas
3218  * @pm8001_ha: our hba card information
3219  * @i: which phy that received the event.
3220  *
3221  * when HBA driver received the identify done event or initiate FIS received
3222  * event(for SATA), it will invoke this function to notify the sas layer that
3223  * the sas toplogy has formed, please discover the the whole sas domain,
3224  * while receive a broadcast(change) primitive just tell the sas
3225  * layer to discover the changed domain rather than the whole domain.
3226  */
3227 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3228 {
3229         struct pm8001_phy *phy = &pm8001_ha->phy[i];
3230         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3231         struct sas_ha_struct *sas_ha;
3232         if (!phy->phy_attached)
3233                 return;
3234
3235         sas_ha = pm8001_ha->sas;
3236         if (sas_phy->phy) {
3237                 struct sas_phy *sphy = sas_phy->phy;
3238                 sphy->negotiated_linkrate = sas_phy->linkrate;
3239                 sphy->minimum_linkrate = phy->minimum_linkrate;
3240                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3241                 sphy->maximum_linkrate = phy->maximum_linkrate;
3242                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3243         }
3244
3245         if (phy->phy_type & PORT_TYPE_SAS) {
3246                 struct sas_identify_frame *id;
3247                 id = (struct sas_identify_frame *)phy->frame_rcvd;
3248                 id->dev_type = phy->identify.device_type;
3249                 id->initiator_bits = SAS_PROTOCOL_ALL;
3250                 id->target_bits = phy->identify.target_port_protocols;
3251         } else if (phy->phy_type & PORT_TYPE_SATA) {
3252                 /*Nothing*/
3253         }
3254         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
3255
3256         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3257         pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
3258 }
3259
3260 /* Get the link rate speed  */
3261 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3262 {
3263         struct sas_phy *sas_phy = phy->sas_phy.phy;
3264
3265         switch (link_rate) {
3266         case PHY_SPEED_60:
3267                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3268                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3269                 break;
3270         case PHY_SPEED_30:
3271                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3272                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3273                 break;
3274         case PHY_SPEED_15:
3275                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3276                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3277                 break;
3278         }
3279         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3280         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3281         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3282         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3283         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3284 }
3285
3286 /**
3287  * asd_get_attached_sas_addr -- extract/generate attached SAS address
3288  * @phy: pointer to asd_phy
3289  * @sas_addr: pointer to buffer where the SAS address is to be written
3290  *
3291  * This function extracts the SAS address from an IDENTIFY frame
3292  * received.  If OOB is SATA, then a SAS address is generated from the
3293  * HA tables.
3294  *
3295  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3296  * buffer.
3297  */
3298 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3299         u8 *sas_addr)
3300 {
3301         if (phy->sas_phy.frame_rcvd[0] == 0x34
3302                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3303                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3304                 /* FIS device-to-host */
3305                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3306                 addr += phy->sas_phy.id;
3307                 *(__be64 *)sas_addr = cpu_to_be64(addr);
3308         } else {
3309                 struct sas_identify_frame *idframe =
3310                         (void *) phy->sas_phy.frame_rcvd;
3311                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3312         }
3313 }
3314
3315 /**
3316  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3317  * @pm8001_ha: our hba card information
3318  * @Qnum: the outbound queue message number.
3319  * @SEA: source of event to ack
3320  * @port_id: port id.
3321  * @phyId: phy id.
3322  * @param0: parameter 0.
3323  * @param1: parameter 1.
3324  */
3325 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3326         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3327 {
3328         struct hw_event_ack_req  payload;
3329         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3330
3331         struct inbound_queue_table *circularQ;
3332
3333         memset((u8 *)&payload, 0, sizeof(payload));
3334         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3335         payload.tag = cpu_to_le32(1);
3336         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3337                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3338         payload.param0 = cpu_to_le32(param0);
3339         payload.param1 = cpu_to_le32(param1);
3340         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
3341 }
3342
3343 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3344         u32 phyId, u32 phy_op);
3345
3346 /**
3347  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3348  * @pm8001_ha: our hba card information
3349  * @piomb: IO message buffer
3350  */
3351 static void
3352 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3353 {
3354         struct hw_event_resp *pPayload =
3355                 (struct hw_event_resp *)(piomb + 4);
3356         u32 lr_evt_status_phyid_portid =
3357                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3358         u8 link_rate =
3359                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3360         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3361         u8 phy_id =
3362                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3363         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3364         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3365         struct pm8001_port *port = &pm8001_ha->port[port_id];
3366         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3367         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3368         unsigned long flags;
3369         u8 deviceType = pPayload->sas_identify.dev_type;
3370         port->port_state =  portstate;
3371         phy->phy_state = PHY_STATE_LINK_UP_SPC;
3372         PM8001_MSG_DBG(pm8001_ha,
3373                 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3374                 port_id, phy_id));
3375
3376         switch (deviceType) {
3377         case SAS_PHY_UNUSED:
3378                 PM8001_MSG_DBG(pm8001_ha,
3379                         pm8001_printk("device type no device.\n"));
3380                 break;
3381         case SAS_END_DEVICE:
3382                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3383                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3384                         PHY_NOTIFY_ENABLE_SPINUP);
3385                 port->port_attached = 1;
3386                 pm8001_get_lrate_mode(phy, link_rate);
3387                 break;
3388         case SAS_EDGE_EXPANDER_DEVICE:
3389                 PM8001_MSG_DBG(pm8001_ha,
3390                         pm8001_printk("expander device.\n"));
3391                 port->port_attached = 1;
3392                 pm8001_get_lrate_mode(phy, link_rate);
3393                 break;
3394         case SAS_FANOUT_EXPANDER_DEVICE:
3395                 PM8001_MSG_DBG(pm8001_ha,
3396                         pm8001_printk("fanout expander device.\n"));
3397                 port->port_attached = 1;
3398                 pm8001_get_lrate_mode(phy, link_rate);
3399                 break;
3400         default:
3401                 PM8001_MSG_DBG(pm8001_ha,
3402                         pm8001_printk("unknown device type(%x)\n", deviceType));
3403                 break;
3404         }
3405         phy->phy_type |= PORT_TYPE_SAS;
3406         phy->identify.device_type = deviceType;
3407         phy->phy_attached = 1;
3408         if (phy->identify.device_type == SAS_END_DEVICE)
3409                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3410         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3411                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3412         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3413         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3414         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3415         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3416                 sizeof(struct sas_identify_frame)-4);
3417         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3418         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3419         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3420         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3421                 mdelay(200);/*delay a moment to wait disk to spinup*/
3422         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3423 }
3424
3425 /**
3426  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3427  * @pm8001_ha: our hba card information
3428  * @piomb: IO message buffer
3429  */
3430 static void
3431 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3432 {
3433         struct hw_event_resp *pPayload =
3434                 (struct hw_event_resp *)(piomb + 4);
3435         u32 lr_evt_status_phyid_portid =
3436                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3437         u8 link_rate =
3438                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3439         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3440         u8 phy_id =
3441                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3442         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3443         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3444         struct pm8001_port *port = &pm8001_ha->port[port_id];
3445         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3446         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3447         unsigned long flags;
3448         PM8001_MSG_DBG(pm8001_ha,
3449                 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3450                 " phy id = %d\n", port_id, phy_id));
3451         port->port_state =  portstate;
3452         phy->phy_state = PHY_STATE_LINK_UP_SPC;
3453         port->port_attached = 1;
3454         pm8001_get_lrate_mode(phy, link_rate);
3455         phy->phy_type |= PORT_TYPE_SATA;
3456         phy->phy_attached = 1;
3457         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3458         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3459         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3460         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3461                 sizeof(struct dev_to_host_fis));
3462         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3463         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3464         phy->identify.device_type = SAS_SATA_DEV;
3465         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3466         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3467         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3468 }
3469
3470 /**
3471  * hw_event_phy_down -we should notify the libsas the phy is down.
3472  * @pm8001_ha: our hba card information
3473  * @piomb: IO message buffer
3474  */
3475 static void
3476 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3477 {
3478         struct hw_event_resp *pPayload =
3479                 (struct hw_event_resp *)(piomb + 4);
3480         u32 lr_evt_status_phyid_portid =
3481                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3482         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3483         u8 phy_id =
3484                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3485         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3486         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3487         struct pm8001_port *port = &pm8001_ha->port[port_id];
3488         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3489         port->port_state =  portstate;
3490         phy->phy_type = 0;
3491         phy->identify.device_type = 0;
3492         phy->phy_attached = 0;
3493         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3494         switch (portstate) {
3495         case PORT_VALID:
3496                 break;
3497         case PORT_INVALID:
3498                 PM8001_MSG_DBG(pm8001_ha,
3499                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3500                 PM8001_MSG_DBG(pm8001_ha,
3501                         pm8001_printk(" Last phy Down and port invalid\n"));
3502                 port->port_attached = 0;
3503                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3504                         port_id, phy_id, 0, 0);
3505                 break;
3506         case PORT_IN_RESET:
3507                 PM8001_MSG_DBG(pm8001_ha,
3508                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3509                 break;
3510         case PORT_NOT_ESTABLISHED:
3511                 PM8001_MSG_DBG(pm8001_ha,
3512                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3513                 port->port_attached = 0;
3514                 break;
3515         case PORT_LOSTCOMM:
3516                 PM8001_MSG_DBG(pm8001_ha,
3517                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3518                 PM8001_MSG_DBG(pm8001_ha,
3519                         pm8001_printk(" Last phy Down and port invalid\n"));
3520                 port->port_attached = 0;
3521                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3522                         port_id, phy_id, 0, 0);
3523                 break;
3524         default:
3525                 port->port_attached = 0;
3526                 PM8001_MSG_DBG(pm8001_ha,
3527                         pm8001_printk(" phy Down and(default) = %x\n",
3528                         portstate));
3529                 break;
3530
3531         }
3532 }
3533
3534 /**
3535  * pm8001_mpi_reg_resp -process register device ID response.
3536  * @pm8001_ha: our hba card information
3537  * @piomb: IO message buffer
3538  *
3539  * when sas layer find a device it will notify LLDD, then the driver register
3540  * the domain device to FW, this event is the return device ID which the FW
3541  * has assigned, from now,inter-communication with FW is no longer using the
3542  * SAS address, use device ID which FW assigned.
3543  */
3544 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3545 {
3546         u32 status;
3547         u32 device_id;
3548         u32 htag;
3549         struct pm8001_ccb_info *ccb;
3550         struct pm8001_device *pm8001_dev;
3551         struct dev_reg_resp *registerRespPayload =
3552                 (struct dev_reg_resp *)(piomb + 4);
3553
3554         htag = le32_to_cpu(registerRespPayload->tag);
3555         ccb = &pm8001_ha->ccb_info[htag];
3556         pm8001_dev = ccb->device;
3557         status = le32_to_cpu(registerRespPayload->status);
3558         device_id = le32_to_cpu(registerRespPayload->device_id);
3559         PM8001_MSG_DBG(pm8001_ha,
3560                 pm8001_printk(" register device is status = %d\n", status));
3561         switch (status) {
3562         case DEVREG_SUCCESS:
3563                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3564                 pm8001_dev->device_id = device_id;
3565                 break;
3566         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3567                 PM8001_MSG_DBG(pm8001_ha,
3568                         pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3569                 break;
3570         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3571                 PM8001_MSG_DBG(pm8001_ha,
3572                    pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3573                 break;
3574         case DEVREG_FAILURE_INVALID_PHY_ID:
3575                 PM8001_MSG_DBG(pm8001_ha,
3576                         pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3577                 break;
3578         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3579                 PM8001_MSG_DBG(pm8001_ha,
3580                    pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3581                 break;
3582         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3583                 PM8001_MSG_DBG(pm8001_ha,
3584                         pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3585                 break;
3586         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3587                 PM8001_MSG_DBG(pm8001_ha,
3588                         pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3589                 break;
3590         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3591                 PM8001_MSG_DBG(pm8001_ha,
3592                        pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3593                 break;
3594         default:
3595                 PM8001_MSG_DBG(pm8001_ha,
3596                  pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3597                 break;
3598         }
3599         complete(pm8001_dev->dcompletion);
3600         ccb->task = NULL;
3601         ccb->ccb_tag = 0xFFFFFFFF;
3602         pm8001_tag_free(pm8001_ha, htag);
3603         return 0;
3604 }
3605
3606 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3607 {
3608         u32 status;
3609         u32 device_id;
3610         struct dev_reg_resp *registerRespPayload =
3611                 (struct dev_reg_resp *)(piomb + 4);
3612
3613         status = le32_to_cpu(registerRespPayload->status);
3614         device_id = le32_to_cpu(registerRespPayload->device_id);
3615         if (status != 0)
3616                 PM8001_MSG_DBG(pm8001_ha,
3617                         pm8001_printk(" deregister device failed ,status = %x"
3618                         ", device_id = %x\n", status, device_id));
3619         return 0;
3620 }
3621
3622 /**
3623  * fw_flash_update_resp - Response from FW for flash update command.
3624  * @pm8001_ha: our hba card information
3625  * @piomb: IO message buffer
3626  */
3627 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3628                 void *piomb)
3629 {
3630         u32 status;
3631         struct fw_flash_Update_resp *ppayload =
3632                 (struct fw_flash_Update_resp *)(piomb + 4);
3633         u32 tag = le32_to_cpu(ppayload->tag);
3634         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3635         status = le32_to_cpu(ppayload->status);
3636         switch (status) {
3637         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3638                 PM8001_MSG_DBG(pm8001_ha,
3639                 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3640                 break;
3641         case FLASH_UPDATE_IN_PROGRESS:
3642                 PM8001_MSG_DBG(pm8001_ha,
3643                         pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3644                 break;
3645         case FLASH_UPDATE_HDR_ERR:
3646                 PM8001_MSG_DBG(pm8001_ha,
3647                         pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3648                 break;
3649         case FLASH_UPDATE_OFFSET_ERR:
3650                 PM8001_MSG_DBG(pm8001_ha,
3651                         pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3652                 break;
3653         case FLASH_UPDATE_CRC_ERR:
3654                 PM8001_MSG_DBG(pm8001_ha,
3655                         pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3656                 break;
3657         case FLASH_UPDATE_LENGTH_ERR:
3658                 PM8001_MSG_DBG(pm8001_ha,
3659                         pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3660                 break;
3661         case FLASH_UPDATE_HW_ERR:
3662                 PM8001_MSG_DBG(pm8001_ha,
3663                         pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3664                 break;
3665         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3666                 PM8001_MSG_DBG(pm8001_ha,
3667                         pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3668                 break;
3669         case FLASH_UPDATE_DISABLED:
3670                 PM8001_MSG_DBG(pm8001_ha,
3671                         pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3672                 break;
3673         default:
3674                 PM8001_MSG_DBG(pm8001_ha,
3675                         pm8001_printk("No matched status = %d\n", status));
3676                 break;
3677         }
3678         kfree(ccb->fw_control_context);
3679         ccb->task = NULL;
3680         ccb->ccb_tag = 0xFFFFFFFF;
3681         pm8001_tag_free(pm8001_ha, tag);
3682         complete(pm8001_ha->nvmd_completion);
3683         return 0;
3684 }
3685
3686 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3687 {
3688         u32 status;
3689         int i;
3690         struct general_event_resp *pPayload =
3691                 (struct general_event_resp *)(piomb + 4);
3692         status = le32_to_cpu(pPayload->status);
3693         PM8001_MSG_DBG(pm8001_ha,
3694                 pm8001_printk(" status = 0x%x\n", status));
3695         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3696                 PM8001_MSG_DBG(pm8001_ha,
3697                         pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3698                         pPayload->inb_IOMB_payload[i]));
3699         return 0;
3700 }
3701
3702 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3703 {
3704         struct sas_task *t;
3705         struct pm8001_ccb_info *ccb;
3706         unsigned long flags;
3707         u32 status ;
3708         u32 tag, scp;
3709         struct task_status_struct *ts;
3710         struct pm8001_device *pm8001_dev;
3711
3712         struct task_abort_resp *pPayload =
3713                 (struct task_abort_resp *)(piomb + 4);
3714
3715         status = le32_to_cpu(pPayload->status);
3716         tag = le32_to_cpu(pPayload->tag);
3717         if (!tag) {
3718                 PM8001_FAIL_DBG(pm8001_ha,
3719                         pm8001_printk(" TAG NULL. RETURNING !!!"));
3720                 return -1;
3721         }
3722
3723         scp = le32_to_cpu(pPayload->scp);
3724         ccb = &pm8001_ha->ccb_info[tag];
3725         t = ccb->task;
3726         pm8001_dev = ccb->device; /* retrieve device */
3727
3728         if (!t) {
3729                 PM8001_FAIL_DBG(pm8001_ha,
3730                         pm8001_printk(" TASK NULL. RETURNING !!!"));
3731                 return -1;
3732         }
3733         ts = &t->task_status;
3734         if (status != 0)
3735                 PM8001_FAIL_DBG(pm8001_ha,
3736                         pm8001_printk("task abort failed status 0x%x ,"
3737                         "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3738         switch (status) {
3739         case IO_SUCCESS:
3740                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3741                 ts->resp = SAS_TASK_COMPLETE;
3742                 ts->stat = SAM_STAT_GOOD;
3743                 break;
3744         case IO_NOT_VALID:
3745                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3746                 ts->resp = TMF_RESP_FUNC_FAILED;
3747                 break;
3748         }
3749         spin_lock_irqsave(&t->task_state_lock, flags);
3750         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3751         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3752         t->task_state_flags |= SAS_TASK_STATE_DONE;
3753         spin_unlock_irqrestore(&t->task_state_lock, flags);
3754         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3755         mb();
3756
3757         if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3758                 pm8001_tag_free(pm8001_ha, tag);
3759                 sas_free_task(t);
3760                 /* clear the flag */
3761                 pm8001_dev->id &= 0xBFFFFFFF;
3762         } else
3763                 t->task_done(t);
3764
3765         return 0;
3766 }
3767
3768 /**
3769  * mpi_hw_event -The hw event has come.
3770  * @pm8001_ha: our hba card information
3771  * @piomb: IO message buffer
3772  */
3773 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3774 {
3775         unsigned long flags;
3776         struct hw_event_resp *pPayload =
3777                 (struct hw_event_resp *)(piomb + 4);
3778         u32 lr_evt_status_phyid_portid =
3779                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3780         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3781         u8 phy_id =
3782                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3783         u16 eventType =
3784                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3785         u8 status =
3786                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3787         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3788         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3789         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3790         PM8001_MSG_DBG(pm8001_ha,
3791                 pm8001_printk("outbound queue HW event & event type : "));
3792         switch (eventType) {
3793         case HW_EVENT_PHY_START_STATUS:
3794                 PM8001_MSG_DBG(pm8001_ha,
3795                 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3796                         " status = %x\n", status));
3797                 if (status == 0) {
3798                         phy->phy_state = 1;
3799                         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3800                                 complete(phy->enable_completion);
3801                 }
3802                 break;
3803         case HW_EVENT_SAS_PHY_UP:
3804                 PM8001_MSG_DBG(pm8001_ha,
3805                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3806                 hw_event_sas_phy_up(pm8001_ha, piomb);
3807                 break;
3808         case HW_EVENT_SATA_PHY_UP:
3809                 PM8001_MSG_DBG(pm8001_ha,
3810                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3811                 hw_event_sata_phy_up(pm8001_ha, piomb);
3812                 break;
3813         case HW_EVENT_PHY_STOP_STATUS:
3814                 PM8001_MSG_DBG(pm8001_ha,
3815                         pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3816                         "status = %x\n", status));
3817                 if (status == 0)
3818                         phy->phy_state = 0;
3819                 break;
3820         case HW_EVENT_SATA_SPINUP_HOLD:
3821                 PM8001_MSG_DBG(pm8001_ha,
3822                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3823                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3824                 break;
3825         case HW_EVENT_PHY_DOWN:
3826                 PM8001_MSG_DBG(pm8001_ha,
3827                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3828                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3829                 phy->phy_attached = 0;
3830                 phy->phy_state = 0;
3831                 hw_event_phy_down(pm8001_ha, piomb);
3832                 break;
3833         case HW_EVENT_PORT_INVALID:
3834                 PM8001_MSG_DBG(pm8001_ha,
3835                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3836                 sas_phy_disconnected(sas_phy);
3837                 phy->phy_attached = 0;
3838                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3839                 break;
3840         /* the broadcast change primitive received, tell the LIBSAS this event
3841         to revalidate the sas domain*/
3842         case HW_EVENT_BROADCAST_CHANGE:
3843                 PM8001_MSG_DBG(pm8001_ha,
3844                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3845                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3846                         port_id, phy_id, 1, 0);
3847                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3848                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3849                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3850                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3851                 break;
3852         case HW_EVENT_PHY_ERROR:
3853                 PM8001_MSG_DBG(pm8001_ha,
3854                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3855                 sas_phy_disconnected(&phy->sas_phy);
3856                 phy->phy_attached = 0;
3857                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3858                 break;
3859         case HW_EVENT_BROADCAST_EXP:
3860                 PM8001_MSG_DBG(pm8001_ha,
3861                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3862                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3863                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3864                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3865                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3866                 break;
3867         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3868                 PM8001_MSG_DBG(pm8001_ha,
3869                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3870                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3871                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3872                 sas_phy_disconnected(sas_phy);
3873                 phy->phy_attached = 0;
3874                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3875                 break;
3876         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3877                 PM8001_MSG_DBG(pm8001_ha,
3878                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3879                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3880                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3881                         port_id, phy_id, 0, 0);
3882                 sas_phy_disconnected(sas_phy);
3883                 phy->phy_attached = 0;
3884                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3885                 break;
3886         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3887                 PM8001_MSG_DBG(pm8001_ha,
3888                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3889                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3890                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3891                         port_id, phy_id, 0, 0);
3892                 sas_phy_disconnected(sas_phy);
3893                 phy->phy_attached = 0;
3894                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3895                 break;
3896         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3897                 PM8001_MSG_DBG(pm8001_ha,
3898                       pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3899                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3900                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3901                         port_id, phy_id, 0, 0);
3902                 sas_phy_disconnected(sas_phy);
3903                 phy->phy_attached = 0;
3904                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3905                 break;
3906         case HW_EVENT_MALFUNCTION:
3907                 PM8001_MSG_DBG(pm8001_ha,
3908                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3909                 break;
3910         case HW_EVENT_BROADCAST_SES:
3911                 PM8001_MSG_DBG(pm8001_ha,
3912                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3913                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3914                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3915                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3916                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3917                 break;
3918         case HW_EVENT_INBOUND_CRC_ERROR:
3919                 PM8001_MSG_DBG(pm8001_ha,
3920                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3921                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3922                         HW_EVENT_INBOUND_CRC_ERROR,
3923                         port_id, phy_id, 0, 0);
3924                 break;
3925         case HW_EVENT_HARD_RESET_RECEIVED:
3926                 PM8001_MSG_DBG(pm8001_ha,
3927                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3928                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3929                 break;
3930         case HW_EVENT_ID_FRAME_TIMEOUT:
3931                 PM8001_MSG_DBG(pm8001_ha,
3932                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3933                 sas_phy_disconnected(sas_phy);
3934                 phy->phy_attached = 0;
3935                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3936                 break;
3937         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3938                 PM8001_MSG_DBG(pm8001_ha,
3939                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3940                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3941                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3942                         port_id, phy_id, 0, 0);
3943                 sas_phy_disconnected(sas_phy);
3944                 phy->phy_attached = 0;
3945                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3946                 break;
3947         case HW_EVENT_PORT_RESET_TIMER_TMO:
3948                 PM8001_MSG_DBG(pm8001_ha,
3949                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3950                 sas_phy_disconnected(sas_phy);
3951                 phy->phy_attached = 0;
3952                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3953                 break;
3954         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3955                 PM8001_MSG_DBG(pm8001_ha,
3956                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3957                 sas_phy_disconnected(sas_phy);
3958                 phy->phy_attached = 0;
3959                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3960                 break;
3961         case HW_EVENT_PORT_RECOVER:
3962                 PM8001_MSG_DBG(pm8001_ha,
3963                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3964                 break;
3965         case HW_EVENT_PORT_RESET_COMPLETE:
3966                 PM8001_MSG_DBG(pm8001_ha,
3967                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3968                 break;
3969         case EVENT_BROADCAST_ASYNCH_EVENT:
3970                 PM8001_MSG_DBG(pm8001_ha,
3971                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3972                 break;
3973         default:
3974                 PM8001_MSG_DBG(pm8001_ha,
3975                         pm8001_printk("Unknown event type = %x\n", eventType));
3976                 break;
3977         }
3978         return 0;
3979 }
3980
3981 /**
3982  * process_one_iomb - process one outbound Queue memory block
3983  * @pm8001_ha: our hba card information
3984  * @piomb: IO message buffer
3985  */
3986 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3987 {
3988         __le32 pHeader = *(__le32 *)piomb;
3989         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3990
3991         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3992
3993         switch (opc) {
3994         case OPC_OUB_ECHO:
3995                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3996                 break;
3997         case OPC_OUB_HW_EVENT:
3998                 PM8001_MSG_DBG(pm8001_ha,
3999                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
4000                 mpi_hw_event(pm8001_ha, piomb);
4001                 break;
4002         case OPC_OUB_SSP_COMP:
4003                 PM8001_MSG_DBG(pm8001_ha,
4004                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
4005                 mpi_ssp_completion(pm8001_ha, piomb);
4006                 break;
4007         case OPC_OUB_SMP_COMP:
4008                 PM8001_MSG_DBG(pm8001_ha,
4009                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
4010                 mpi_smp_completion(pm8001_ha, piomb);
4011                 break;
4012         case OPC_OUB_LOCAL_PHY_CNTRL:
4013                 PM8001_MSG_DBG(pm8001_ha,
4014                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
4015                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
4016                 break;
4017         case OPC_OUB_DEV_REGIST:
4018                 PM8001_MSG_DBG(pm8001_ha,
4019                         pm8001_printk("OPC_OUB_DEV_REGIST\n"));
4020                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
4021                 break;
4022         case OPC_OUB_DEREG_DEV:
4023                 PM8001_MSG_DBG(pm8001_ha,
4024                         pm8001_printk("unregister the device\n"));
4025                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
4026                 break;
4027         case OPC_OUB_GET_DEV_HANDLE:
4028                 PM8001_MSG_DBG(pm8001_ha,
4029                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
4030                 break;
4031         case OPC_OUB_SATA_COMP:
4032                 PM8001_MSG_DBG(pm8001_ha,
4033                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
4034                 mpi_sata_completion(pm8001_ha, piomb);
4035                 break;
4036         case OPC_OUB_SATA_EVENT:
4037                 PM8001_MSG_DBG(pm8001_ha,
4038                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
4039                 mpi_sata_event(pm8001_ha, piomb);
4040                 break;
4041         case OPC_OUB_SSP_EVENT:
4042                 PM8001_MSG_DBG(pm8001_ha,
4043                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
4044                 mpi_ssp_event(pm8001_ha, piomb);
4045                 break;
4046         case OPC_OUB_DEV_HANDLE_ARRIV:
4047                 PM8001_MSG_DBG(pm8001_ha,
4048                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
4049                 /*This is for target*/
4050                 break;
4051         case OPC_OUB_SSP_RECV_EVENT:
4052                 PM8001_MSG_DBG(pm8001_ha,
4053                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
4054                 /*This is for target*/
4055                 break;
4056         case OPC_OUB_DEV_INFO:
4057                 PM8001_MSG_DBG(pm8001_ha,
4058                         pm8001_printk("OPC_OUB_DEV_INFO\n"));
4059                 break;
4060         case OPC_OUB_FW_FLASH_UPDATE:
4061                 PM8001_MSG_DBG(pm8001_ha,
4062                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
4063                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
4064                 break;
4065         case OPC_OUB_GPIO_RESPONSE:
4066                 PM8001_MSG_DBG(pm8001_ha,
4067                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
4068                 break;
4069         case OPC_OUB_GPIO_EVENT:
4070                 PM8001_MSG_DBG(pm8001_ha,
4071                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
4072                 break;
4073         case OPC_OUB_GENERAL_EVENT:
4074                 PM8001_MSG_DBG(pm8001_ha,
4075                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
4076                 pm8001_mpi_general_event(pm8001_ha, piomb);
4077                 break;
4078         case OPC_OUB_SSP_ABORT_RSP:
4079                 PM8001_MSG_DBG(pm8001_ha,
4080                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
4081                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4082                 break;
4083         case OPC_OUB_SATA_ABORT_RSP:
4084                 PM8001_MSG_DBG(pm8001_ha,
4085                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
4086                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4087                 break;
4088         case OPC_OUB_SAS_DIAG_MODE_START_END:
4089                 PM8001_MSG_DBG(pm8001_ha,
4090                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
4091                 break;
4092         case OPC_OUB_SAS_DIAG_EXECUTE:
4093                 PM8001_MSG_DBG(pm8001_ha,
4094                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
4095                 break;
4096         case OPC_OUB_GET_TIME_STAMP:
4097                 PM8001_MSG_DBG(pm8001_ha,
4098                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
4099                 break;
4100         case OPC_OUB_SAS_HW_EVENT_ACK:
4101                 PM8001_MSG_DBG(pm8001_ha,
4102                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
4103                 break;
4104         case OPC_OUB_PORT_CONTROL:
4105                 PM8001_MSG_DBG(pm8001_ha,
4106                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
4107                 break;
4108         case OPC_OUB_SMP_ABORT_RSP:
4109                 PM8001_MSG_DBG(pm8001_ha,
4110                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
4111                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4112                 break;
4113         case OPC_OUB_GET_NVMD_DATA:
4114                 PM8001_MSG_DBG(pm8001_ha,
4115                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
4116                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4117                 break;
4118         case OPC_OUB_SET_NVMD_DATA:
4119                 PM8001_MSG_DBG(pm8001_ha,
4120                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
4121                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4122                 break;
4123         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4124                 PM8001_MSG_DBG(pm8001_ha,
4125                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
4126                 break;
4127         case OPC_OUB_SET_DEVICE_STATE:
4128                 PM8001_MSG_DBG(pm8001_ha,
4129                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
4130                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4131                 break;
4132         case OPC_OUB_GET_DEVICE_STATE:
4133                 PM8001_MSG_DBG(pm8001_ha,
4134                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
4135                 break;
4136         case OPC_OUB_SET_DEV_INFO:
4137                 PM8001_MSG_DBG(pm8001_ha,
4138                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
4139                 break;
4140         case OPC_OUB_SAS_RE_INITIALIZE:
4141                 PM8001_MSG_DBG(pm8001_ha,
4142                         pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
4143                 break;
4144         default:
4145                 PM8001_MSG_DBG(pm8001_ha,
4146                         pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
4147                         opc));
4148                 break;
4149         }
4150 }
4151
4152 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4153 {
4154         struct outbound_queue_table *circularQ;
4155         void *pMsg1 = NULL;
4156         u8 uninitialized_var(bc);
4157         u32 ret = MPI_IO_STATUS_FAIL;
4158         unsigned long flags;
4159
4160         spin_lock_irqsave(&pm8001_ha->lock, flags);
4161         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4162         do {
4163                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4164                 if (MPI_IO_STATUS_SUCCESS == ret) {
4165                         /* process the outbound message */
4166                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4167                         /* free the message from the outbound circular buffer */
4168                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4169                                                         circularQ, bc);
4170                 }
4171                 if (MPI_IO_STATUS_BUSY == ret) {
4172                         /* Update the producer index from SPC */
4173                         circularQ->producer_index =
4174                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4175                         if (le32_to_cpu(circularQ->producer_index) ==
4176                                 circularQ->consumer_idx)
4177                                 /* OQ is empty */
4178                                 break;
4179                 }
4180         } while (1);
4181         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4182         return ret;
4183 }
4184
4185 /* PCI_DMA_... to our direction translation. */
4186 static const u8 data_dir_flags[] = {
4187         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
4188         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
4189         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
4190         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
4191 };
4192 void
4193 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4194 {
4195         int i;
4196         struct scatterlist *sg;
4197         struct pm8001_prd *buf_prd = prd;
4198
4199         for_each_sg(scatter, sg, nr, i) {
4200                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4201                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4202                 buf_prd->im_len.e = 0;
4203                 buf_prd++;
4204         }
4205 }
4206
4207 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4208 {
4209         psmp_cmd->tag = hTag;
4210         psmp_cmd->device_id = cpu_to_le32(deviceID);
4211         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4212 }
4213
4214 /**
4215  * pm8001_chip_smp_req - send a SMP task to FW
4216  * @pm8001_ha: our hba card information.
4217  * @ccb: the ccb information this request used.
4218  */
4219 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4220         struct pm8001_ccb_info *ccb)
4221 {
4222         int elem, rc;
4223         struct sas_task *task = ccb->task;
4224         struct domain_device *dev = task->dev;
4225         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4226         struct scatterlist *sg_req, *sg_resp;
4227         u32 req_len, resp_len;
4228         struct smp_req smp_cmd;
4229         u32 opc;
4230         struct inbound_queue_table *circularQ;
4231
4232         memset(&smp_cmd, 0, sizeof(smp_cmd));
4233         /*
4234          * DMA-map SMP request, response buffers
4235          */
4236         sg_req = &task->smp_task.smp_req;
4237         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
4238         if (!elem)
4239                 return -ENOMEM;
4240         req_len = sg_dma_len(sg_req);
4241
4242         sg_resp = &task->smp_task.smp_resp;
4243         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
4244         if (!elem) {
4245                 rc = -ENOMEM;
4246                 goto err_out;
4247         }
4248         resp_len = sg_dma_len(sg_resp);
4249         /* must be in dwords */
4250         if ((req_len & 0x3) || (resp_len & 0x3)) {
4251                 rc = -EINVAL;
4252                 goto err_out_2;
4253         }
4254
4255         opc = OPC_INB_SMP_REQUEST;
4256         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4257         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4258         smp_cmd.long_smp_req.long_req_addr =
4259                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4260         smp_cmd.long_smp_req.long_req_size =
4261                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4262         smp_cmd.long_smp_req.long_resp_addr =
4263                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4264         smp_cmd.long_smp_req.long_resp_size =
4265                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4266         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4267         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4268                                         (u32 *)&smp_cmd, 0);
4269         if (rc)
4270                 goto err_out_2;
4271
4272         return 0;
4273
4274 err_out_2:
4275         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4276                         PCI_DMA_FROMDEVICE);
4277 err_out:
4278         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4279                         PCI_DMA_TODEVICE);
4280         return rc;
4281 }
4282
4283 /**
4284  * pm8001_chip_ssp_io_req - send a SSP task to FW
4285  * @pm8001_ha: our hba card information.
4286  * @ccb: the ccb information this request used.
4287  */
4288 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4289         struct pm8001_ccb_info *ccb)
4290 {
4291         struct sas_task *task = ccb->task;
4292         struct domain_device *dev = task->dev;
4293         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4294         struct ssp_ini_io_start_req ssp_cmd;
4295         u32 tag = ccb->ccb_tag;
4296         int ret;
4297         u64 phys_addr;
4298         struct inbound_queue_table *circularQ;
4299         u32 opc = OPC_INB_SSPINIIOSTART;
4300         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4301         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4302         ssp_cmd.dir_m_tlr =
4303                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4304         SAS 1.1 compatible TLR*/
4305         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4306         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4307         ssp_cmd.tag = cpu_to_le32(tag);
4308         if (task->ssp_task.enable_first_burst)
4309                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4310         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4311         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4312         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4313                task->ssp_task.cmd->cmd_len);
4314         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4315
4316         /* fill in PRD (scatter/gather) table, if any */
4317         if (task->num_scatter > 1) {
4318                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4319                 phys_addr = ccb->ccb_dma_handle +
4320                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4321                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4322                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4323                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4324         } else if (task->num_scatter == 1) {
4325                 u64 dma_addr = sg_dma_address(task->scatter);
4326                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4327                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4328                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4329                 ssp_cmd.esgl = 0;
4330         } else if (task->num_scatter == 0) {
4331                 ssp_cmd.addr_low = 0;
4332                 ssp_cmd.addr_high = 0;
4333                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4334                 ssp_cmd.esgl = 0;
4335         }
4336         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 0);
4337         return ret;
4338 }
4339
4340 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4341         struct pm8001_ccb_info *ccb)
4342 {
4343         struct sas_task *task = ccb->task;
4344         struct domain_device *dev = task->dev;
4345         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4346         u32 tag = ccb->ccb_tag;
4347         int ret;
4348         struct sata_start_req sata_cmd;
4349         u32 hdr_tag, ncg_tag = 0;
4350         u64 phys_addr;
4351         u32 ATAP = 0x0;
4352         u32 dir;
4353         struct inbound_queue_table *circularQ;
4354         unsigned long flags;
4355         u32  opc = OPC_INB_SATA_HOST_OPSTART;
4356         memset(&sata_cmd, 0, sizeof(sata_cmd));
4357         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4358         if (task->data_dir == PCI_DMA_NONE) {
4359                 ATAP = 0x04;  /* no data*/
4360                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4361         } else if (likely(!task->ata_task.device_control_reg_update)) {
4362                 if (task->ata_task.dma_xfer) {
4363                         ATAP = 0x06; /* DMA */
4364                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4365                 } else {
4366                         ATAP = 0x05; /* PIO*/
4367                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4368                 }
4369                 if (task->ata_task.use_ncq &&
4370                         dev->sata_dev.class != ATA_DEV_ATAPI) {
4371                         ATAP = 0x07; /* FPDMA */
4372                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4373                 }
4374         }
4375         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4376                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4377                 ncg_tag = hdr_tag;
4378         }
4379         dir = data_dir_flags[task->data_dir] << 8;
4380         sata_cmd.tag = cpu_to_le32(tag);
4381         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4382         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4383         sata_cmd.ncqtag_atap_dir_m =
4384                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4385         sata_cmd.sata_fis = task->ata_task.fis;
4386         if (likely(!task->ata_task.device_control_reg_update))
4387                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4388         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4389         /* fill in PRD (scatter/gather) table, if any */
4390         if (task->num_scatter > 1) {
4391                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4392                 phys_addr = ccb->ccb_dma_handle +
4393                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4394                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4395                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4396                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4397         } else if (task->num_scatter == 1) {
4398                 u64 dma_addr = sg_dma_address(task->scatter);
4399                 sata_cmd.addr_low = lower_32_bits(dma_addr);
4400                 sata_cmd.addr_high = upper_32_bits(dma_addr);
4401                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4402                 sata_cmd.esgl = 0;
4403         } else if (task->num_scatter == 0) {
4404                 sata_cmd.addr_low = 0;
4405                 sata_cmd.addr_high = 0;
4406                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4407                 sata_cmd.esgl = 0;
4408         }
4409
4410         /* Check for read log for failed drive and return */
4411         if (sata_cmd.sata_fis.command == 0x2f) {
4412                 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4413                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4414                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4415                         struct task_status_struct *ts;
4416
4417                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4418                         ts = &task->task_status;
4419
4420                         spin_lock_irqsave(&task->task_state_lock, flags);
4421                         ts->resp = SAS_TASK_COMPLETE;
4422                         ts->stat = SAM_STAT_GOOD;
4423                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4424                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4425                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4426                         if (unlikely((task->task_state_flags &
4427                                         SAS_TASK_STATE_ABORTED))) {
4428                                 spin_unlock_irqrestore(&task->task_state_lock,
4429                                                         flags);
4430                                 PM8001_FAIL_DBG(pm8001_ha,
4431                                         pm8001_printk("task 0x%p resp 0x%x "
4432                                         " stat 0x%x but aborted by upper layer "
4433                                         "\n", task, ts->resp, ts->stat));
4434                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4435                         } else {
4436                                 spin_unlock_irqrestore(&task->task_state_lock,
4437                                                         flags);
4438                                 pm8001_ccb_task_free_done(pm8001_ha, task,
4439                                                                 ccb, tag);
4440                                 return 0;
4441                         }
4442                 }
4443         }
4444
4445         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
4446         return ret;
4447 }
4448
4449 /**
4450  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4451  * @pm8001_ha: our hba card information.
4452  * @num: the inbound queue number
4453  * @phy_id: the phy id which we wanted to start up.
4454  */
4455 static int
4456 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4457 {
4458         struct phy_start_req payload;
4459         struct inbound_queue_table *circularQ;
4460         int ret;
4461         u32 tag = 0x01;
4462         u32 opcode = OPC_INB_PHYSTART;
4463         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4464         memset(&payload, 0, sizeof(payload));
4465         payload.tag = cpu_to_le32(tag);
4466         /*
4467          ** [0:7]   PHY Identifier
4468          ** [8:11]  link rate 1.5G, 3G, 6G
4469          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4470          ** [14]    0b disable spin up hold; 1b enable spin up hold
4471          */
4472         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4473                 LINKMODE_AUTO | LINKRATE_15 |
4474                 LINKRATE_30 | LINKRATE_60 | phy_id);
4475         payload.sas_identify.dev_type = SAS_END_DEVICE;
4476         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4477         memcpy(payload.sas_identify.sas_addr,
4478                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4479         payload.sas_identify.phy_id = phy_id;
4480         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4481         return ret;
4482 }
4483
4484 /**
4485  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4486  * @pm8001_ha: our hba card information.
4487  * @num: the inbound queue number
4488  * @phy_id: the phy id which we wanted to start up.
4489  */
4490 int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4491         u8 phy_id)
4492 {
4493         struct phy_stop_req payload;
4494         struct inbound_queue_table *circularQ;
4495         int ret;
4496         u32 tag = 0x01;
4497         u32 opcode = OPC_INB_PHYSTOP;
4498         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4499         memset(&payload, 0, sizeof(payload));
4500         payload.tag = cpu_to_le32(tag);
4501         payload.phy_id = cpu_to_le32(phy_id);
4502         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4503         return ret;
4504 }
4505
4506 /**
4507  * see comments on pm8001_mpi_reg_resp.
4508  */
4509 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4510         struct pm8001_device *pm8001_dev, u32 flag)
4511 {
4512         struct reg_dev_req payload;
4513         u32     opc;
4514         u32 stp_sspsmp_sata = 0x4;
4515         struct inbound_queue_table *circularQ;
4516         u32 linkrate, phy_id;
4517         int rc, tag = 0xdeadbeef;
4518         struct pm8001_ccb_info *ccb;
4519         u8 retryFlag = 0x1;
4520         u16 firstBurstSize = 0;
4521         u16 ITNT = 2000;
4522         struct domain_device *dev = pm8001_dev->sas_device;
4523         struct domain_device *parent_dev = dev->parent;
4524         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4525
4526         memset(&payload, 0, sizeof(payload));
4527         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4528         if (rc)
4529                 return rc;
4530         ccb = &pm8001_ha->ccb_info[tag];
4531         ccb->device = pm8001_dev;
4532         ccb->ccb_tag = tag;
4533         payload.tag = cpu_to_le32(tag);
4534         if (flag == 1)
4535                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4536         else {
4537                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4538                         stp_sspsmp_sata = 0x00; /* stp*/
4539                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4540                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4541                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4542                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4543         }
4544         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4545                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4546         else
4547                 phy_id = pm8001_dev->attached_phy;
4548         opc = OPC_INB_REG_DEV;
4549         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4550                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4551         payload.phyid_portid =
4552                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4553                 ((phy_id & 0x0F) << 4));
4554         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4555                 ((linkrate & 0x0F) * 0x1000000) |
4556                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4557         payload.firstburstsize_ITNexustimeout =
4558                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4559         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4560                 SAS_ADDR_SIZE);
4561         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4562         return rc;
4563 }
4564
4565 /**
4566  * see comments on pm8001_mpi_reg_resp.
4567  */
4568 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4569         u32 device_id)
4570 {
4571         struct dereg_dev_req payload;
4572         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4573         int ret;
4574         struct inbound_queue_table *circularQ;
4575
4576         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4577         memset(&payload, 0, sizeof(payload));
4578         payload.tag = cpu_to_le32(1);
4579         payload.device_id = cpu_to_le32(device_id);
4580         PM8001_MSG_DBG(pm8001_ha,
4581                 pm8001_printk("unregister device device_id = %d\n", device_id));
4582         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4583         return ret;
4584 }
4585
4586 /**
4587  * pm8001_chip_phy_ctl_req - support the local phy operation
4588  * @pm8001_ha: our hba card information.
4589  * @num: the inbound queue number
4590  * @phy_id: the phy id which we wanted to operate
4591  * @phy_op:
4592  */
4593 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4594         u32 phyId, u32 phy_op)
4595 {
4596         struct local_phy_ctl_req payload;
4597         struct inbound_queue_table *circularQ;
4598         int ret;
4599         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4600         memset(&payload, 0, sizeof(payload));
4601         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4602         payload.tag = cpu_to_le32(1);
4603         payload.phyop_phyid =
4604                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4605         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4606         return ret;
4607 }
4608
4609 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4610 {
4611         u32 value;
4612 #ifdef PM8001_USE_MSIX
4613         return 1;
4614 #endif
4615         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4616         if (value)
4617                 return 1;
4618         return 0;
4619
4620 }
4621
4622 /**
4623  * pm8001_chip_isr - PM8001 isr handler.
4624  * @pm8001_ha: our hba card information.
4625  * @irq: irq number.
4626  * @stat: stat.
4627  */
4628 static irqreturn_t
4629 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4630 {
4631         pm8001_chip_interrupt_disable(pm8001_ha, vec);
4632         process_oq(pm8001_ha, vec);
4633         pm8001_chip_interrupt_enable(pm8001_ha, vec);
4634         return IRQ_HANDLED;
4635 }
4636
4637 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4638         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4639 {
4640         struct task_abort_req task_abort;
4641         struct inbound_queue_table *circularQ;
4642         int ret;
4643         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4644         memset(&task_abort, 0, sizeof(task_abort));
4645         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4646                 task_abort.abort_all = 0;
4647                 task_abort.device_id = cpu_to_le32(dev_id);
4648                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4649                 task_abort.tag = cpu_to_le32(cmd_tag);
4650         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4651                 task_abort.abort_all = cpu_to_le32(1);
4652                 task_abort.device_id = cpu_to_le32(dev_id);
4653                 task_abort.tag = cpu_to_le32(cmd_tag);
4654         }
4655         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
4656         return ret;
4657 }
4658
4659 /**
4660  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4661  * @task: the task we wanted to aborted.
4662  * @flag: the abort flag.
4663  */
4664 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4665         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4666 {
4667         u32 opc, device_id;
4668         int rc = TMF_RESP_FUNC_FAILED;
4669         PM8001_EH_DBG(pm8001_ha,
4670                 pm8001_printk("cmd_tag = %x, abort task tag = 0x%x",
4671                         cmd_tag, task_tag));
4672         if (pm8001_dev->dev_type == SAS_END_DEVICE)
4673                 opc = OPC_INB_SSP_ABORT;
4674         else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4675                 opc = OPC_INB_SATA_ABORT;
4676         else
4677                 opc = OPC_INB_SMP_ABORT;/* SMP */
4678         device_id = pm8001_dev->device_id;
4679         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4680                 task_tag, cmd_tag);
4681         if (rc != TMF_RESP_FUNC_COMPLETE)
4682                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4683         return rc;
4684 }
4685
4686 /**
4687  * pm8001_chip_ssp_tm_req - built the task management command.
4688  * @pm8001_ha: our hba card information.
4689  * @ccb: the ccb information.
4690  * @tmf: task management function.
4691  */
4692 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4693         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4694 {
4695         struct sas_task *task = ccb->task;
4696         struct domain_device *dev = task->dev;
4697         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4698         u32 opc = OPC_INB_SSPINITMSTART;
4699         struct inbound_queue_table *circularQ;
4700         struct ssp_ini_tm_start_req sspTMCmd;
4701         int ret;
4702
4703         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4704         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4705         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4706         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4707         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4708         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4709         if (pm8001_ha->chip_id != chip_8001)
4710                 sspTMCmd.ds_ads_m = 0x08;
4711         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4712         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 0);
4713         return ret;
4714 }
4715
4716 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4717         void *payload)
4718 {
4719         u32 opc = OPC_INB_GET_NVMD_DATA;
4720         u32 nvmd_type;
4721         int rc;
4722         u32 tag;
4723         struct pm8001_ccb_info *ccb;
4724         struct inbound_queue_table *circularQ;
4725         struct get_nvm_data_req nvmd_req;
4726         struct fw_control_ex *fw_control_context;
4727         struct pm8001_ioctl_payload *ioctl_payload = payload;
4728
4729         nvmd_type = ioctl_payload->minor_function;
4730         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4731         if (!fw_control_context)
4732                 return -ENOMEM;
4733         fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4734         fw_control_context->len = ioctl_payload->length;
4735         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4736         memset(&nvmd_req, 0, sizeof(nvmd_req));
4737         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4738         if (rc) {
4739                 kfree(fw_control_context);
4740                 return rc;
4741         }
4742         ccb = &pm8001_ha->ccb_info[tag];
4743         ccb->ccb_tag = tag;
4744         ccb->fw_control_context = fw_control_context;
4745         nvmd_req.tag = cpu_to_le32(tag);
4746
4747         switch (nvmd_type) {
4748         case TWI_DEVICE: {
4749                 u32 twi_addr, twi_page_size;
4750                 twi_addr = 0xa8;
4751                 twi_page_size = 2;
4752
4753                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4754                         twi_page_size << 8 | TWI_DEVICE);
4755                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4756                 nvmd_req.resp_addr_hi =
4757                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4758                 nvmd_req.resp_addr_lo =
4759                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4760                 break;
4761         }
4762         case C_SEEPROM: {
4763                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4764                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4765                 nvmd_req.resp_addr_hi =
4766                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4767                 nvmd_req.resp_addr_lo =
4768                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4769                 break;
4770         }
4771         case VPD_FLASH: {
4772                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4773                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4774                 nvmd_req.resp_addr_hi =
4775                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4776                 nvmd_req.resp_addr_lo =
4777                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4778                 break;
4779         }
4780         case EXPAN_ROM: {
4781                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4782                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4783                 nvmd_req.resp_addr_hi =
4784                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4785                 nvmd_req.resp_addr_lo =
4786                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4787                 break;
4788         }
4789         case IOP_RDUMP: {
4790                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4791                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4792                 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4793                 nvmd_req.resp_addr_hi =
4794                 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4795                 nvmd_req.resp_addr_lo =
4796                 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4797                 break;
4798         }
4799         default:
4800                 break;
4801         }
4802         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4803         if (rc) {
4804                 kfree(fw_control_context);
4805                 pm8001_tag_free(pm8001_ha, tag);
4806         }
4807         return rc;
4808 }
4809
4810 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4811         void *payload)
4812 {
4813         u32 opc = OPC_INB_SET_NVMD_DATA;
4814         u32 nvmd_type;
4815         int rc;
4816         u32 tag;
4817         struct pm8001_ccb_info *ccb;
4818         struct inbound_queue_table *circularQ;
4819         struct set_nvm_data_req nvmd_req;
4820         struct fw_control_ex *fw_control_context;
4821         struct pm8001_ioctl_payload *ioctl_payload = payload;
4822
4823         nvmd_type = ioctl_payload->minor_function;
4824         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4825         if (!fw_control_context)
4826                 return -ENOMEM;
4827         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4828         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4829                 &ioctl_payload->func_specific,
4830                 ioctl_payload->length);
4831         memset(&nvmd_req, 0, sizeof(nvmd_req));
4832         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4833         if (rc) {
4834                 kfree(fw_control_context);
4835                 return -EBUSY;
4836         }
4837         ccb = &pm8001_ha->ccb_info[tag];
4838         ccb->fw_control_context = fw_control_context;
4839         ccb->ccb_tag = tag;
4840         nvmd_req.tag = cpu_to_le32(tag);
4841         switch (nvmd_type) {
4842         case TWI_DEVICE: {
4843                 u32 twi_addr, twi_page_size;
4844                 twi_addr = 0xa8;
4845                 twi_page_size = 2;
4846                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4847                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4848                         twi_page_size << 8 | TWI_DEVICE);
4849                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4850                 nvmd_req.resp_addr_hi =
4851                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4852                 nvmd_req.resp_addr_lo =
4853                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4854                 break;
4855         }
4856         case C_SEEPROM:
4857                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4858                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4859                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4860                 nvmd_req.resp_addr_hi =
4861                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4862                 nvmd_req.resp_addr_lo =
4863                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4864                 break;
4865         case VPD_FLASH:
4866                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4867                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4868                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4869                 nvmd_req.resp_addr_hi =
4870                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4871                 nvmd_req.resp_addr_lo =
4872                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4873                 break;
4874         case EXPAN_ROM:
4875                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4876                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4877                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4878                 nvmd_req.resp_addr_hi =
4879                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4880                 nvmd_req.resp_addr_lo =
4881                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4882                 break;
4883         default:
4884                 break;
4885         }
4886         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
4887         if (rc) {
4888                 kfree(fw_control_context);
4889                 pm8001_tag_free(pm8001_ha, tag);
4890         }
4891         return rc;
4892 }
4893
4894 /**
4895  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4896  * @pm8001_ha: our hba card information.
4897  * @fw_flash_updata_info: firmware flash update param
4898  */
4899 int
4900 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4901         void *fw_flash_updata_info, u32 tag)
4902 {
4903         struct fw_flash_Update_req payload;
4904         struct fw_flash_updata_info *info;
4905         struct inbound_queue_table *circularQ;
4906         int ret;
4907         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4908
4909         memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4910         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4911         info = fw_flash_updata_info;
4912         payload.tag = cpu_to_le32(tag);
4913         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4914         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4915         payload.total_image_len = cpu_to_le32(info->total_image_len);
4916         payload.len = info->sgl.im_len.len ;
4917         payload.sgl_addr_lo =
4918                 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4919         payload.sgl_addr_hi =
4920                 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4921         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4922         return ret;
4923 }
4924
4925 int
4926 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4927         void *payload)
4928 {
4929         struct fw_flash_updata_info flash_update_info;
4930         struct fw_control_info *fw_control;
4931         struct fw_control_ex *fw_control_context;
4932         int rc;
4933         u32 tag;
4934         struct pm8001_ccb_info *ccb;
4935         void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4936         dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4937         struct pm8001_ioctl_payload *ioctl_payload = payload;
4938
4939         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4940         if (!fw_control_context)
4941                 return -ENOMEM;
4942         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4943         memcpy(buffer, fw_control->buffer, fw_control->len);
4944         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4945         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4946         flash_update_info.sgl.im_len.e = 0;
4947         flash_update_info.cur_image_offset = fw_control->offset;
4948         flash_update_info.cur_image_len = fw_control->len;
4949         flash_update_info.total_image_len = fw_control->size;
4950         fw_control_context->fw_control = fw_control;
4951         fw_control_context->virtAddr = buffer;
4952         fw_control_context->phys_addr = phys_addr;
4953         fw_control_context->len = fw_control->len;
4954         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4955         if (rc) {
4956                 kfree(fw_control_context);
4957                 return -EBUSY;
4958         }
4959         ccb = &pm8001_ha->ccb_info[tag];
4960         ccb->fw_control_context = fw_control_context;
4961         ccb->ccb_tag = tag;
4962         rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4963                 tag);
4964         return rc;
4965 }
4966
4967 ssize_t
4968 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
4969 {
4970         u32 value, rem, offset = 0, bar = 0;
4971         u32 index, work_offset, dw_length;
4972         u32 shift_value, gsm_base, gsm_dump_offset;
4973         char *direct_data;
4974         struct Scsi_Host *shost = class_to_shost(cdev);
4975         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
4976         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
4977
4978         direct_data = buf;
4979         gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
4980
4981         /* check max is 1 Mbytes */
4982         if ((length > 0x100000) || (gsm_dump_offset & 3) ||
4983                 ((gsm_dump_offset + length) > 0x1000000))
4984                         return -EINVAL;
4985
4986         if (pm8001_ha->chip_id == chip_8001)
4987                 bar = 2;
4988         else
4989                 bar = 1;
4990
4991         work_offset = gsm_dump_offset & 0xFFFF0000;
4992         offset = gsm_dump_offset & 0x0000FFFF;
4993         gsm_dump_offset = work_offset;
4994         /* adjust length to dword boundary */
4995         rem = length & 3;
4996         dw_length = length >> 2;
4997
4998         for (index = 0; index < dw_length; index++) {
4999                 if ((work_offset + offset) & 0xFFFF0000) {
5000                         if (pm8001_ha->chip_id == chip_8001)
5001                                 shift_value = ((gsm_dump_offset + offset) &
5002                                                 SHIFT_REG_64K_MASK);
5003                         else
5004                                 shift_value = (((gsm_dump_offset + offset) &
5005                                                 SHIFT_REG_64K_MASK) >>
5006                                                 SHIFT_REG_BIT_SHIFT);
5007
5008                         if (pm8001_ha->chip_id == chip_8001) {
5009                                 gsm_base = GSM_BASE;
5010                                 if (-1 == pm8001_bar4_shift(pm8001_ha,
5011                                                 (gsm_base + shift_value)))
5012                                         return -EIO;
5013                         } else {
5014                                 gsm_base = 0;
5015                                 if (-1 == pm80xx_bar4_shift(pm8001_ha,
5016                                                 (gsm_base + shift_value)))
5017                                         return -EIO;
5018                         }
5019                         gsm_dump_offset = (gsm_dump_offset + offset) &
5020                                                 0xFFFF0000;
5021                         work_offset = 0;
5022                         offset = offset & 0x0000FFFF;
5023                 }
5024                 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
5025                                                 0x0000FFFF);
5026                 direct_data += sprintf(direct_data, "%08x ", value);
5027                 offset += 4;
5028         }
5029         if (rem != 0) {
5030                 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
5031                                                 0x0000FFFF);
5032                 /* xfr for non_dw */
5033                 direct_data += sprintf(direct_data, "%08x ", value);
5034         }
5035         /* Shift back to BAR4 original address */
5036         if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
5037                         return -EIO;
5038         pm8001_ha->fatal_forensic_shift_offset += 1024;
5039
5040         if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
5041                 pm8001_ha->fatal_forensic_shift_offset = 0;
5042         return direct_data - buf;
5043 }
5044
5045 int
5046 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
5047         struct pm8001_device *pm8001_dev, u32 state)
5048 {
5049         struct set_dev_state_req payload;
5050         struct inbound_queue_table *circularQ;
5051         struct pm8001_ccb_info *ccb;
5052         int rc;
5053         u32 tag;
5054         u32 opc = OPC_INB_SET_DEVICE_STATE;
5055         memset(&payload, 0, sizeof(payload));
5056         rc = pm8001_tag_alloc(pm8001_ha, &tag);
5057         if (rc)
5058                 return -1;
5059         ccb = &pm8001_ha->ccb_info[tag];
5060         ccb->ccb_tag = tag;
5061         ccb->device = pm8001_dev;
5062         circularQ = &pm8001_ha->inbnd_q_tbl[0];
5063         payload.tag = cpu_to_le32(tag);
5064         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
5065         payload.nds = cpu_to_le32(state);
5066         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
5067         return rc;
5068
5069 }
5070
5071 static int
5072 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
5073 {
5074         struct sas_re_initialization_req payload;
5075         struct inbound_queue_table *circularQ;
5076         struct pm8001_ccb_info *ccb;
5077         int rc;
5078         u32 tag;
5079         u32 opc = OPC_INB_SAS_RE_INITIALIZE;
5080         memset(&payload, 0, sizeof(payload));
5081         rc = pm8001_tag_alloc(pm8001_ha, &tag);
5082         if (rc)
5083                 return -ENOMEM;
5084         ccb = &pm8001_ha->ccb_info[tag];
5085         ccb->ccb_tag = tag;
5086         circularQ = &pm8001_ha->inbnd_q_tbl[0];
5087         payload.tag = cpu_to_le32(tag);
5088         payload.SSAHOLT = cpu_to_le32(0xd << 25);
5089         payload.sata_hol_tmo = cpu_to_le32(80);
5090         payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
5091         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
5092         if (rc)
5093                 pm8001_tag_free(pm8001_ha, tag);
5094         return rc;
5095
5096 }
5097
5098 const struct pm8001_dispatch pm8001_8001_dispatch = {
5099         .name                   = "pmc8001",
5100         .chip_init              = pm8001_chip_init,
5101         .chip_soft_rst          = pm8001_chip_soft_rst,
5102         .chip_rst               = pm8001_hw_chip_rst,
5103         .chip_iounmap           = pm8001_chip_iounmap,
5104         .isr                    = pm8001_chip_isr,
5105         .is_our_interupt        = pm8001_chip_is_our_interupt,
5106         .isr_process_oq         = process_oq,
5107         .interrupt_enable       = pm8001_chip_interrupt_enable,
5108         .interrupt_disable      = pm8001_chip_interrupt_disable,
5109         .make_prd               = pm8001_chip_make_sg,
5110         .smp_req                = pm8001_chip_smp_req,
5111         .ssp_io_req             = pm8001_chip_ssp_io_req,
5112         .sata_req               = pm8001_chip_sata_req,
5113         .phy_start_req          = pm8001_chip_phy_start_req,
5114         .phy_stop_req           = pm8001_chip_phy_stop_req,
5115         .reg_dev_req            = pm8001_chip_reg_dev_req,
5116         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
5117         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
5118         .task_abort             = pm8001_chip_abort_task,
5119         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
5120         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
5121         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
5122         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
5123         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
5124         .sas_re_init_req        = pm8001_chip_sas_re_initialization,
5125 };