2 * Copyright (c) 2000-2014 LSI Corporation.
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
9 * mpi2_cnfg.h Version: 02.00.29
11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
12 * prefix are for use only on MPI v2.5 products, and must not be used
13 * with MPI v2.0 products. Unless otherwise noted, names beginning with
14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
19 * Date Version Description
20 * -------- -------- ------------------------------------------------------
21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
22 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
23 * Added Manufacturing Page 11.
24 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
26 * 06-26-07 02.00.02 Adding generic structure for product-specific
27 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
28 * Rework of BIOS Page 2 configuration page.
29 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
31 * Added configuration pages IOC Page 8 and Driver
32 * Persistent Mapping Page 0.
33 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
34 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
35 * RAID Physical Disk Pages 0 and 1, RAID Configuration
37 * Added new value for AccessStatus field of SAS Device
38 * Page 0 (_SATA_NEEDS_INITIALIZATION).
39 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
40 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
41 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
43 * Modified IOC Page 7 to use masks and added field for
44 * SASBroadcastPrimitiveMasks.
45 * Added MPI2_CONFIG_PAGE_BIOS_4.
46 * Added MPI2_CONFIG_PAGE_LOG_0.
47 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
48 * Added SAS Device IDs.
49 * Updated Integrated RAID configuration pages including
50 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
52 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
53 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
54 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
55 * Added missing MaxNumRoutedSasAddresses field to
56 * MPI2_CONFIG_PAGE_EXPANDER_0.
57 * Added SAS Port Page 0.
58 * Modified structure layout for
59 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
60 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
61 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
62 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
64 * Added two new values for the Physical Disk Coercion Size
65 * bits in the Flags field of Manufacturing Page 4.
66 * Added product-specific Manufacturing pages 16 to 31.
67 * Modified Flags bits for controlling write cache on SATA
68 * drives in IO Unit Page 1.
69 * Added new bit to AdditionalControlFlags of SAS IO Unit
70 * Page 1 to control Invalid Topology Correction.
71 * Added additional defines for RAID Volume Page 0
72 * VolumeStatusFlags field.
73 * Modified meaning of RAID Volume Page 0 VolumeSettings
74 * define for auto-configure of hot-swap drives.
75 * Added SupportedPhysDisks field to RAID Volume Page 1 and
76 * added related defines.
77 * Added PhysDiskAttributes field (and related defines) to
78 * RAID Physical Disk Page 0.
79 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
80 * Added three new DiscoveryStatus bits for SAS IO Unit
81 * Page 0 and SAS Expander Page 0.
82 * Removed multiplexing information from SAS IO Unit pages.
83 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
84 * Removed Zone Address Resolved bit from PhyInfo and from
85 * Expander Page 0 Flags field.
86 * Added two new AccessStatus values to SAS Device Page 0
87 * for indicating routing problems. Added 3 reserved words
89 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
90 * Inserted missing reserved field into structure for IOC
92 * Added more pending task bits to RAID Volume Page 0
93 * VolumeStatusFlags defines.
94 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
95 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
96 * and SAS Expander Page 0 to flag a downstream initiator
97 * when in simplified routing mode.
98 * Removed SATA Init Failure defines for DiscoveryStatus
99 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
100 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
101 * Added PortGroups, DmaGroup, and ControlGroup fields to
103 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
105 * Added expander reduced functionality data to SAS
107 * Added SAS PHY Page 2 and SAS PHY Page 3.
108 * 07-30-09 02.00.12 Added IO Unit Page 7.
109 * Added new device ids.
110 * Added SAS IO Unit Page 5.
111 * Added partial and slumber power management capable flags
112 * to SAS Device Page 0 Flags field.
113 * Added PhyInfo defines for power condition.
114 * Added Ethernet configuration pages.
115 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
116 * Added SAS PHY Page 4 structure and defines.
117 * 02-10-10 02.00.14 Modified the comments for the configuration page
118 * structures that contain an array of data. The host
119 * should use the "count" field in the page data (e.g. the
120 * NumPhys field) to determine the number of valid elements
122 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
123 * Added PowerManagementCapabilities to IO Unit Page 7.
124 * Added PortWidthModGroup field to
125 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
126 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
129 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
131 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
132 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
133 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
135 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
136 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
138 * Added BoardTemperature and BoardTemperatureUnits fields
139 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
140 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
141 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
142 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
143 * Added IO Unit Page 8, IO Unit Page 9,
144 * and IO Unit Page 10.
145 * Added SASNotifyPrimitiveMasks field to
146 * MPI2_CONFIG_PAGE_IOC_7.
147 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
148 * 05-25-11 02.00.20 Cleaned up a few comments.
149 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
150 * for PCIe link as obsolete.
151 * Added SpinupFlags field containing a Disable Spin-up bit
152 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
154 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
155 * Added UEFIVersion field to BIOS Page 1 and defined new
157 * Incorporating additions for MPI v2.5.
158 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
159 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
160 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
161 * obsolete for MPI v2.5 and later.
162 * Added some defines for 12G SAS speeds.
163 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
164 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
165 * match the specification.
166 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
168 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
169 * MPI2_CONFIG_PAGE_MAN_7.
170 * Added EnclosureLevel and ConnectorName fields to
171 * MPI2_CONFIG_PAGE_SAS_DEV_0.
172 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
173 * MPI2_CONFIG_PAGE_SAS_DEV_0.
174 * Added EnclosureLevel field to
175 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
176 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
177 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
178 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of
179 * MPI2_CONFIG_PAGE_BIOS_1.
180 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and
181 * more defines for the BiosOptions field..
182 * --------------------------------------------------------------------------
188 /*****************************************************************************
189 * Configuration Page Header and defines
190 *****************************************************************************/
192 /*Config Page Header */
193 typedef struct _MPI2_CONFIG_PAGE_HEADER {
194 U8 PageVersion; /*0x00 */
195 U8 PageLength; /*0x01 */
196 U8 PageNumber; /*0x02 */
197 U8 PageType; /*0x03 */
198 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER,
199 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t;
201 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION {
202 MPI2_CONFIG_PAGE_HEADER Struct;
206 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
207 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion;
209 /*Extended Config Page Header */
210 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER {
211 U8 PageVersion; /*0x00 */
212 U8 Reserved1; /*0x01 */
213 U8 PageNumber; /*0x02 */
214 U8 PageType; /*0x03 */
215 U16 ExtPageLength; /*0x04 */
216 U8 ExtPageType; /*0x06 */
217 U8 Reserved2; /*0x07 */
218 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
219 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
220 Mpi2ConfigExtendedPageHeader_t,
221 *pMpi2ConfigExtendedPageHeader_t;
223 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION {
224 MPI2_CONFIG_PAGE_HEADER Struct;
225 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
229 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
230 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
231 Mpi2ConfigPageExtendedHeaderUnion,
232 *pMpi2ConfigPageExtendedHeaderUnion;
235 /*PageType field values */
236 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
237 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
238 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
239 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
241 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
242 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
243 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
244 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
245 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
246 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
247 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
248 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
250 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
253 /*ExtPageType field values */
254 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
255 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
256 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
257 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
258 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
259 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
260 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
261 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
262 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
263 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
264 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
267 /*****************************************************************************
268 * PageAddress defines
269 *****************************************************************************/
271 /*RAID Volume PageAddress format */
272 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
273 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
274 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
276 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
279 /*RAID Physical Disk PageAddress format */
280 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
281 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
282 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
283 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
285 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
286 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
289 /*SAS Expander PageAddress format */
290 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
291 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
292 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
293 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
295 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
296 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
297 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
300 /*SAS Device PageAddress format */
301 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
302 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
303 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
305 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
308 /*SAS PHY PageAddress format */
309 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
310 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
311 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
313 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
314 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
317 /*SAS Port PageAddress format */
318 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
319 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
320 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
322 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
325 /*SAS Enclosure PageAddress format */
326 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
327 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
328 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
330 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
333 /*RAID Configuration PageAddress format */
334 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
335 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
336 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
337 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
339 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
342 /*Driver Persistent Mapping PageAddress format */
343 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
344 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
346 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
347 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
348 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
351 /*Ethernet PageAddress format */
352 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
353 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
355 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
359 /****************************************************************************
360 * Configuration messages
361 ****************************************************************************/
363 /*Configuration Request Message */
364 typedef struct _MPI2_CONFIG_REQUEST {
366 U8 SGLFlags; /*0x01 */
367 U8 ChainOffset; /*0x02 */
368 U8 Function; /*0x03 */
369 U16 ExtPageLength; /*0x04 */
370 U8 ExtPageType; /*0x06 */
371 U8 MsgFlags; /*0x07 */
374 U16 Reserved1; /*0x0A */
375 U8 Reserved2; /*0x0C */
376 U8 ProxyVF_ID; /*0x0D */
377 U16 Reserved4; /*0x0E */
378 U32 Reserved3; /*0x10 */
379 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
380 U32 PageAddress; /*0x18 */
381 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */
382 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST,
383 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t;
385 /*values for the Action field */
386 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
387 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
388 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
389 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
390 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
391 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
392 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
393 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
395 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
398 /*Config Reply Message */
399 typedef struct _MPI2_CONFIG_REPLY {
401 U8 SGLFlags; /*0x01 */
402 U8 MsgLength; /*0x02 */
403 U8 Function; /*0x03 */
404 U16 ExtPageLength; /*0x04 */
405 U8 ExtPageType; /*0x06 */
406 U8 MsgFlags; /*0x07 */
409 U16 Reserved1; /*0x0A */
410 U16 Reserved2; /*0x0C */
411 U16 IOCStatus; /*0x0E */
412 U32 IOCLogInfo; /*0x10 */
413 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
414 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY,
415 Mpi2ConfigReply_t, *pMpi2ConfigReply_t;
419 /*****************************************************************************
421 * C o n f i g u r a t i o n P a g e s
423 *****************************************************************************/
425 /****************************************************************************
426 * Manufacturing Config pages
427 ****************************************************************************/
429 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
431 /*MPI v2.0 SAS products */
432 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
433 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
434 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
435 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
436 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
437 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
438 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
440 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
442 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
443 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
444 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
445 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
446 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
447 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
448 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
449 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
450 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
452 /*MPI v2.5 SAS products */
453 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096)
454 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097)
455 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090)
456 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091)
457 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094)
458 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095)
463 /*Manufacturing Page 0 */
465 typedef struct _MPI2_CONFIG_PAGE_MAN_0 {
466 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
467 U8 ChipName[16]; /*0x04 */
468 U8 ChipRevision[8]; /*0x14 */
469 U8 BoardName[16]; /*0x1C */
470 U8 BoardAssembly[16]; /*0x2C */
471 U8 BoardTracerNumber[16]; /*0x3C */
472 } MPI2_CONFIG_PAGE_MAN_0,
473 *PTR_MPI2_CONFIG_PAGE_MAN_0,
474 Mpi2ManufacturingPage0_t,
475 *pMpi2ManufacturingPage0_t;
477 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
480 /*Manufacturing Page 1 */
482 typedef struct _MPI2_CONFIG_PAGE_MAN_1 {
483 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
484 U8 VPD[256]; /*0x04 */
485 } MPI2_CONFIG_PAGE_MAN_1,
486 *PTR_MPI2_CONFIG_PAGE_MAN_1,
487 Mpi2ManufacturingPage1_t,
488 *pMpi2ManufacturingPage1_t;
490 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
493 typedef struct _MPI2_CHIP_REVISION_ID {
494 U16 DeviceID; /*0x00 */
495 U8 PCIRevisionID; /*0x02 */
496 U8 Reserved; /*0x03 */
497 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID,
498 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t;
501 /*Manufacturing Page 2 */
504 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
505 *one and check Header.PageLength at runtime.
507 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
508 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
511 typedef struct _MPI2_CONFIG_PAGE_MAN_2 {
512 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
513 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
515 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */
516 } MPI2_CONFIG_PAGE_MAN_2,
517 *PTR_MPI2_CONFIG_PAGE_MAN_2,
518 Mpi2ManufacturingPage2_t,
519 *pMpi2ManufacturingPage2_t;
521 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
524 /*Manufacturing Page 3 */
527 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
528 *one and check Header.PageLength at runtime.
530 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
531 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
534 typedef struct _MPI2_CONFIG_PAGE_MAN_3 {
535 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
536 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
538 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */
539 } MPI2_CONFIG_PAGE_MAN_3,
540 *PTR_MPI2_CONFIG_PAGE_MAN_3,
541 Mpi2ManufacturingPage3_t,
542 *pMpi2ManufacturingPage3_t;
544 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
547 /*Manufacturing Page 4 */
549 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS {
550 U8 PowerSaveFlags; /*0x00 */
551 U8 InternalOperationsSleepTime; /*0x01 */
552 U8 InternalOperationsRunTime; /*0x02 */
553 U8 HostIdleTime; /*0x03 */
554 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
555 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
556 Mpi2ManPage4PwrSaveSettings_t,
557 *pMpi2ManPage4PwrSaveSettings_t;
559 /*defines for the PowerSaveFlags field */
560 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
561 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
562 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
563 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
565 typedef struct _MPI2_CONFIG_PAGE_MAN_4 {
566 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
567 U32 Reserved1; /*0x04 */
569 U8 InquirySize; /*0x0C */
570 U8 Reserved2; /*0x0D */
571 U16 Reserved3; /*0x0E */
572 U8 InquiryData[56]; /*0x10 */
573 U32 RAID0VolumeSettings; /*0x48 */
574 U32 RAID1EVolumeSettings; /*0x4C */
575 U32 RAID1VolumeSettings; /*0x50 */
576 U32 RAID10VolumeSettings; /*0x54 */
577 U32 Reserved4; /*0x58 */
578 U32 Reserved5; /*0x5C */
579 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */
580 U8 MaxOCEDisks; /*0x64 */
581 U8 ResyncRate; /*0x65 */
582 U16 DataScrubDuration; /*0x66 */
583 U8 MaxHotSpares; /*0x68 */
584 U8 MaxPhysDisksPerVol; /*0x69 */
585 U8 MaxPhysDisks; /*0x6A */
586 U8 MaxVolumes; /*0x6B */
587 } MPI2_CONFIG_PAGE_MAN_4,
588 *PTR_MPI2_CONFIG_PAGE_MAN_4,
589 Mpi2ManufacturingPage4_t,
590 *pMpi2ManufacturingPage4_t;
592 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
594 /*Manufacturing Page 4 Flags field */
595 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
596 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
598 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
599 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
600 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
602 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
603 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
604 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
605 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
606 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
608 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
609 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
610 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
611 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
613 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
614 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
615 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
616 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
617 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
618 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
619 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
620 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
623 /*Manufacturing Page 5 */
626 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
627 *one and check the value returned for NumPhys at runtime.
629 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
630 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
633 typedef struct _MPI2_MANUFACTURING5_ENTRY {
635 U64 DeviceName; /*0x08 */
636 } MPI2_MANUFACTURING5_ENTRY,
637 *PTR_MPI2_MANUFACTURING5_ENTRY,
638 Mpi2Manufacturing5Entry_t,
639 *pMpi2Manufacturing5Entry_t;
641 typedef struct _MPI2_CONFIG_PAGE_MAN_5 {
642 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
643 U8 NumPhys; /*0x04 */
644 U8 Reserved1; /*0x05 */
645 U16 Reserved2; /*0x06 */
646 U32 Reserved3; /*0x08 */
647 U32 Reserved4; /*0x0C */
648 MPI2_MANUFACTURING5_ENTRY
649 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */
650 } MPI2_CONFIG_PAGE_MAN_5,
651 *PTR_MPI2_CONFIG_PAGE_MAN_5,
652 Mpi2ManufacturingPage5_t,
653 *pMpi2ManufacturingPage5_t;
655 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
658 /*Manufacturing Page 6 */
660 typedef struct _MPI2_CONFIG_PAGE_MAN_6 {
661 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
662 U32 ProductSpecificInfo;/*0x04 */
663 } MPI2_CONFIG_PAGE_MAN_6,
664 *PTR_MPI2_CONFIG_PAGE_MAN_6,
665 Mpi2ManufacturingPage6_t,
666 *pMpi2ManufacturingPage6_t;
668 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
671 /*Manufacturing Page 7 */
673 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO {
674 U32 Pinout; /*0x00 */
675 U8 Connector[16]; /*0x04 */
676 U8 Location; /*0x14 */
677 U8 ReceptacleID; /*0x15 */
679 U32 Reserved2; /*0x18 */
680 } MPI2_MANPAGE7_CONNECTOR_INFO,
681 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
682 Mpi2ManPage7ConnectorInfo_t,
683 *pMpi2ManPage7ConnectorInfo_t;
685 /*defines for the Pinout field */
686 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
687 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
689 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
690 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
691 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
692 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
693 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
694 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
695 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
696 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
697 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
698 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
699 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
700 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
701 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
702 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
703 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
705 /*defines for the Location field */
706 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
707 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
708 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
709 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
710 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
711 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
712 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
715 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
716 *one and check the value returned for NumPhys at runtime.
718 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
719 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
722 typedef struct _MPI2_CONFIG_PAGE_MAN_7 {
723 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
724 U32 Reserved1; /*0x04 */
725 U32 Reserved2; /*0x08 */
727 U8 EnclosureName[16]; /*0x10 */
728 U8 NumPhys; /*0x20 */
729 U8 Reserved3; /*0x21 */
730 U16 Reserved4; /*0x22 */
731 MPI2_MANPAGE7_CONNECTOR_INFO
732 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */
733 } MPI2_CONFIG_PAGE_MAN_7,
734 *PTR_MPI2_CONFIG_PAGE_MAN_7,
735 Mpi2ManufacturingPage7_t,
736 *pMpi2ManufacturingPage7_t;
738 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
740 /*defines for the Flags field */
741 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008)
742 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002)
743 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
747 *Generic structure to use for product-specific manufacturing pages
748 *(currently Manufacturing Page 8 through Manufacturing Page 31).
751 typedef struct _MPI2_CONFIG_PAGE_MAN_PS {
752 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
753 U32 ProductSpecificInfo;/*0x04 */
754 } MPI2_CONFIG_PAGE_MAN_PS,
755 *PTR_MPI2_CONFIG_PAGE_MAN_PS,
756 Mpi2ManufacturingPagePS_t,
757 *pMpi2ManufacturingPagePS_t;
759 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
760 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
761 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
762 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
763 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
764 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
765 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
766 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
767 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
768 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
769 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
770 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
771 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
772 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
773 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
774 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
775 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
776 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
777 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
778 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
779 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
780 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
781 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
782 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
785 /****************************************************************************
786 * IO Unit Config Pages
787 ****************************************************************************/
791 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 {
792 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
793 U64 UniqueValue; /*0x04 */
794 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */
795 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */
796 } MPI2_CONFIG_PAGE_IO_UNIT_0,
797 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
798 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t;
800 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
805 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
806 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
808 } MPI2_CONFIG_PAGE_IO_UNIT_1,
809 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
810 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t;
812 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
814 /*IO Unit Page 1 Flags defines */
815 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000)
816 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
817 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
818 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
819 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
820 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
821 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
822 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
823 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
824 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
825 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
826 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
827 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
833 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
834 *one and check the value returned for GPIOCount at runtime.
836 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
837 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
840 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 {
841 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
842 U8 GPIOCount; /*0x04 */
843 U8 Reserved1; /*0x05 */
844 U16 Reserved2; /*0x06 */
846 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */
847 } MPI2_CONFIG_PAGE_IO_UNIT_3,
848 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
849 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t;
851 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
853 /*defines for IO Unit Page 3 GPIOVal field */
854 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
855 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
856 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
857 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
863 *Upper layer code (drivers, utilities, etc.) should leave this define set to
864 *one and check the value returned for NumDmaEngines at runtime.
866 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
867 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
870 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
871 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
873 RaidAcceleratorBufferBaseAddress; /*0x04 */
875 RaidAcceleratorBufferSize; /*0x0C */
877 RaidAcceleratorControlBaseAddress; /*0x14 */
878 U8 RAControlSize; /*0x1C */
879 U8 NumDmaEngines; /*0x1D */
880 U8 RAMinControlSize; /*0x1E */
881 U8 RAMaxControlSize; /*0x1F */
882 U32 Reserved1; /*0x20 */
883 U32 Reserved2; /*0x24 */
884 U32 Reserved3; /*0x28 */
886 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */
887 } MPI2_CONFIG_PAGE_IO_UNIT_5,
888 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
889 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t;
891 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
893 /*defines for IO Unit Page 5 DmaEngineCapabilities field */
894 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000)
895 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
897 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
898 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
899 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
900 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
905 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
906 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
908 U8 RAHostControlSize; /*0x06 */
909 U8 Reserved0; /*0x07 */
911 RaidAcceleratorHostControlBaseAddress; /*0x08 */
912 U32 Reserved1; /*0x10 */
913 U32 Reserved2; /*0x14 */
914 U32 Reserved3; /*0x18 */
915 } MPI2_CONFIG_PAGE_IO_UNIT_6,
916 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
917 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t;
919 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
921 /*defines for IO Unit Page 6 Flags field */
922 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
927 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
928 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
929 U8 CurrentPowerMode; /*0x04 */
930 U8 PreviousPowerMode; /*0x05 */
931 U8 PCIeWidth; /*0x06 */
932 U8 PCIeSpeed; /*0x07 */
933 U32 ProcessorState; /*0x08 */
935 PowerManagementCapabilities; /*0x0C */
936 U16 IOCTemperature; /*0x10 */
938 IOCTemperatureUnits; /*0x12 */
939 U8 IOCSpeed; /*0x13 */
940 U16 BoardTemperature; /*0x14 */
942 BoardTemperatureUnits; /*0x16 */
943 U8 Reserved3; /*0x17 */
944 U32 Reserved4; /* 0x18 */
945 U32 Reserved5; /* 0x1C */
946 U32 Reserved6; /* 0x20 */
947 U32 Reserved7; /* 0x24 */
948 } MPI2_CONFIG_PAGE_IO_UNIT_7,
949 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
950 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t;
952 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x04)
954 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
955 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0)
956 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00)
957 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40)
958 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80)
959 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0)
961 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07)
962 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00)
963 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01)
964 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04)
965 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05)
966 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06)
969 /*defines for IO Unit Page 7 PCIeWidth field */
970 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
971 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
972 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
973 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
975 /*defines for IO Unit Page 7 PCIeSpeed field */
976 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
977 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
978 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
980 /*defines for IO Unit Page 7 ProcessorState field */
981 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
982 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
984 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
985 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
986 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
988 /*defines for IO Unit Page 7 PowerManagementCapabilities field */
989 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000)
990 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000)
991 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000)
992 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000)
993 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000)
994 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000)
995 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000)
996 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000)
997 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000)
998 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400)
999 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200)
1000 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100)
1001 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040)
1002 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020)
1003 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010)
1004 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008)
1005 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004)
1006 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002)
1007 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001)
1009 /*obsolete names for the PowerManagementCapabilities bits (above) */
1010 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
1011 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
1012 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
1013 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */
1014 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */
1017 /*defines for IO Unit Page 7 IOCTemperatureUnits field */
1018 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
1019 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
1020 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
1022 /*defines for IO Unit Page 7 IOCSpeed field */
1023 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
1024 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
1025 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
1026 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
1028 /*defines for IO Unit Page 7 BoardTemperatureUnits field */
1029 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
1030 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
1031 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
1036 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
1038 typedef struct _MPI2_IOUNIT8_SENSOR {
1039 U16 Flags; /*0x00 */
1040 U16 Reserved1; /*0x02 */
1042 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */
1043 U32 Reserved2; /*0x0C */
1044 U32 Reserved3; /*0x10 */
1045 U32 Reserved4; /*0x14 */
1046 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR,
1047 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t;
1049 /*defines for IO Unit Page 8 Sensor Flags field */
1050 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
1051 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
1052 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
1053 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
1056 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1057 *one and check the value returned for NumSensors at runtime.
1059 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1060 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
1063 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
1064 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1065 U32 Reserved1; /*0x04 */
1066 U32 Reserved2; /*0x08 */
1067 U8 NumSensors; /*0x0C */
1068 U8 PollingInterval; /*0x0D */
1069 U16 Reserved3; /*0x0E */
1071 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */
1072 } MPI2_CONFIG_PAGE_IO_UNIT_8,
1073 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1074 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t;
1076 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
1081 typedef struct _MPI2_IOUNIT9_SENSOR {
1082 U16 CurrentTemperature; /*0x00 */
1083 U16 Reserved1; /*0x02 */
1085 U8 Reserved2; /*0x05 */
1086 U16 Reserved3; /*0x06 */
1087 U32 Reserved4; /*0x08 */
1088 U32 Reserved5; /*0x0C */
1089 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR,
1090 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t;
1092 /*defines for IO Unit Page 9 Sensor Flags field */
1093 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
1096 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1097 *one and check the value returned for NumSensors at runtime.
1099 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1100 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
1103 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1104 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1105 U32 Reserved1; /*0x04 */
1106 U32 Reserved2; /*0x08 */
1107 U8 NumSensors; /*0x0C */
1108 U8 Reserved4; /*0x0D */
1109 U16 Reserved3; /*0x0E */
1111 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */
1112 } MPI2_CONFIG_PAGE_IO_UNIT_9,
1113 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1114 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t;
1116 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1119 /*IO Unit Page 10 */
1121 typedef struct _MPI2_IOUNIT10_FUNCTION {
1122 U8 CreditPercent; /*0x00 */
1123 U8 Reserved1; /*0x01 */
1124 U16 Reserved2; /*0x02 */
1125 } MPI2_IOUNIT10_FUNCTION,
1126 *PTR_MPI2_IOUNIT10_FUNCTION,
1127 Mpi2IOUnit10Function_t,
1128 *pMpi2IOUnit10Function_t;
1131 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1132 *one and check the value returned for NumFunctions at runtime.
1134 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1135 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
1138 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1139 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1140 U8 NumFunctions; /*0x04 */
1141 U8 Reserved1; /*0x05 */
1142 U16 Reserved2; /*0x06 */
1143 U32 Reserved3; /*0x08 */
1144 U32 Reserved4; /*0x0C */
1145 MPI2_IOUNIT10_FUNCTION
1146 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */
1147 } MPI2_CONFIG_PAGE_IO_UNIT_10,
1148 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1149 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t;
1151 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1155 /****************************************************************************
1157 ****************************************************************************/
1161 typedef struct _MPI2_CONFIG_PAGE_IOC_0 {
1162 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1163 U32 Reserved1; /*0x04 */
1164 U32 Reserved2; /*0x08 */
1165 U16 VendorID; /*0x0C */
1166 U16 DeviceID; /*0x0E */
1167 U8 RevisionID; /*0x10 */
1168 U8 Reserved3; /*0x11 */
1169 U16 Reserved4; /*0x12 */
1170 U32 ClassCode; /*0x14 */
1171 U16 SubsystemVendorID; /*0x18 */
1172 U16 SubsystemID; /*0x1A */
1173 } MPI2_CONFIG_PAGE_IOC_0,
1174 *PTR_MPI2_CONFIG_PAGE_IOC_0,
1175 Mpi2IOCPage0_t, *pMpi2IOCPage0_t;
1177 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1182 typedef struct _MPI2_CONFIG_PAGE_IOC_1 {
1183 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1184 U32 Flags; /*0x04 */
1185 U32 CoalescingTimeout; /*0x08 */
1186 U8 CoalescingDepth; /*0x0C */
1187 U8 PCISlotNum; /*0x0D */
1188 U8 PCIBusNum; /*0x0E */
1189 U8 PCIDomainSegment; /*0x0F */
1190 U32 Reserved1; /*0x10 */
1191 U32 Reserved2; /*0x14 */
1192 } MPI2_CONFIG_PAGE_IOC_1,
1193 *PTR_MPI2_CONFIG_PAGE_IOC_1,
1194 Mpi2IOCPage1_t, *pMpi2IOCPage1_t;
1196 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1198 /*defines for IOC Page 1 Flags field */
1199 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1201 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1202 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1203 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1207 typedef struct _MPI2_CONFIG_PAGE_IOC_6 {
1208 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1210 CapabilitiesFlags; /*0x04 */
1211 U8 MaxDrivesRAID0; /*0x08 */
1212 U8 MaxDrivesRAID1; /*0x09 */
1214 MaxDrivesRAID1E; /*0x0A */
1216 MaxDrivesRAID10; /*0x0B */
1217 U8 MinDrivesRAID0; /*0x0C */
1218 U8 MinDrivesRAID1; /*0x0D */
1220 MinDrivesRAID1E; /*0x0E */
1222 MinDrivesRAID10; /*0x0F */
1223 U32 Reserved1; /*0x10 */
1225 MaxGlobalHotSpares; /*0x14 */
1226 U8 MaxPhysDisks; /*0x15 */
1227 U8 MaxVolumes; /*0x16 */
1228 U8 MaxConfigs; /*0x17 */
1229 U8 MaxOCEDisks; /*0x18 */
1230 U8 Reserved2; /*0x19 */
1231 U16 Reserved3; /*0x1A */
1233 SupportedStripeSizeMapRAID0; /*0x1C */
1235 SupportedStripeSizeMapRAID1E; /*0x20 */
1237 SupportedStripeSizeMapRAID10; /*0x24 */
1238 U32 Reserved4; /*0x28 */
1239 U32 Reserved5; /*0x2C */
1241 DefaultMetadataSize; /*0x30 */
1242 U16 Reserved6; /*0x32 */
1244 MaxBadBlockTableEntries; /*0x34 */
1245 U16 Reserved7; /*0x36 */
1247 IRNvsramVersion; /*0x38 */
1248 } MPI2_CONFIG_PAGE_IOC_6,
1249 *PTR_MPI2_CONFIG_PAGE_IOC_6,
1250 Mpi2IOCPage6_t, *pMpi2IOCPage6_t;
1252 #define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1254 /*defines for IOC Page 6 CapabilitiesFlags */
1255 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1256 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1257 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1258 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1259 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1260 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1265 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1267 typedef struct _MPI2_CONFIG_PAGE_IOC_7 {
1268 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1269 U32 Reserved1; /*0x04 */
1271 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */
1272 U16 SASBroadcastPrimitiveMasks; /*0x18 */
1273 U16 SASNotifyPrimitiveMasks; /*0x1A */
1274 U32 Reserved3; /*0x1C */
1275 } MPI2_CONFIG_PAGE_IOC_7,
1276 *PTR_MPI2_CONFIG_PAGE_IOC_7,
1277 Mpi2IOCPage7_t, *pMpi2IOCPage7_t;
1279 #define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1284 typedef struct _MPI2_CONFIG_PAGE_IOC_8 {
1285 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1286 U8 NumDevsPerEnclosure; /*0x04 */
1287 U8 Reserved1; /*0x05 */
1288 U16 Reserved2; /*0x06 */
1289 U16 MaxPersistentEntries; /*0x08 */
1290 U16 MaxNumPhysicalMappedIDs; /*0x0A */
1291 U16 Flags; /*0x0C */
1292 U16 Reserved3; /*0x0E */
1293 U16 IRVolumeMappingFlags; /*0x10 */
1294 U16 Reserved4; /*0x12 */
1295 U32 Reserved5; /*0x14 */
1296 } MPI2_CONFIG_PAGE_IOC_8,
1297 *PTR_MPI2_CONFIG_PAGE_IOC_8,
1298 Mpi2IOCPage8_t, *pMpi2IOCPage8_t;
1300 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1302 /*defines for IOC Page 8 Flags field */
1303 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1304 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1306 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1307 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1308 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1310 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1311 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1313 /*defines for IOC Page 8 IRVolumeMappingFlags */
1314 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1315 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1316 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1319 /****************************************************************************
1321 ****************************************************************************/
1325 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1326 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1327 U32 BiosOptions; /*0x04 */
1328 U32 IOCSettings; /*0x08 */
1329 U8 SSUTimeout; /*0x0C */
1330 U8 Reserved1; /*0x0D */
1331 U16 Reserved2; /*0x0E */
1332 U32 DeviceSettings; /*0x10 */
1333 U16 NumberOfDevices; /*0x14 */
1334 U16 UEFIVersion; /*0x16 */
1335 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */
1336 U16 IOTimeoutSequential; /*0x1A */
1337 U16 IOTimeoutOther; /*0x1C */
1338 U16 IOTimeoutBlockDevicesRM; /*0x1E */
1339 } MPI2_CONFIG_PAGE_BIOS_1,
1340 *PTR_MPI2_CONFIG_PAGE_BIOS_1,
1341 Mpi2BiosPage1_t, *pMpi2BiosPage1_t;
1343 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07)
1345 /*values for BIOS Page 1 BiosOptions field */
1346 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800)
1347 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000)
1348 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800)
1349 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000)
1350 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800)
1351 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000)
1353 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400)
1355 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300)
1356 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000)
1357 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100)
1358 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200)
1359 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300)
1361 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0)
1362 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000)
1364 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1365 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1366 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1367 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1369 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1371 /*values for BIOS Page 1 IOCSettings field */
1372 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1373 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1374 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1376 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1377 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1378 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1379 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1381 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1382 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1383 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1384 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1385 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1387 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1389 /*values for BIOS Page 1 DeviceSettings field */
1390 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1391 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1392 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1393 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1394 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1396 /*defines for BIOS Page 1 UEFIVersion field */
1397 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1398 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8)
1399 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1400 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1406 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER {
1407 U32 Reserved1; /*0x00 */
1408 U32 Reserved2; /*0x04 */
1409 U32 Reserved3; /*0x08 */
1410 U32 Reserved4; /*0x0C */
1411 U32 Reserved5; /*0x10 */
1412 U32 Reserved6; /*0x14 */
1413 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1414 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1415 Mpi2BootDeviceAdapterOrder_t,
1416 *pMpi2BootDeviceAdapterOrder_t;
1418 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID {
1419 U64 SASAddress; /*0x00 */
1420 U8 LUN[8]; /*0x08 */
1421 U32 Reserved1; /*0x10 */
1422 U32 Reserved2; /*0x14 */
1423 } MPI2_BOOT_DEVICE_SAS_WWID,
1424 *PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1425 Mpi2BootDeviceSasWwid_t,
1426 *pMpi2BootDeviceSasWwid_t;
1428 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT {
1429 U64 EnclosureLogicalID; /*0x00 */
1430 U32 Reserved1; /*0x08 */
1431 U32 Reserved2; /*0x0C */
1432 U16 SlotNumber; /*0x10 */
1433 U16 Reserved3; /*0x12 */
1434 U32 Reserved4; /*0x14 */
1435 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1436 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1437 Mpi2BootDeviceEnclosureSlot_t,
1438 *pMpi2BootDeviceEnclosureSlot_t;
1440 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME {
1441 U64 DeviceName; /*0x00 */
1442 U8 LUN[8]; /*0x08 */
1443 U32 Reserved1; /*0x10 */
1444 U32 Reserved2; /*0x14 */
1445 } MPI2_BOOT_DEVICE_DEVICE_NAME,
1446 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1447 Mpi2BootDeviceDeviceName_t,
1448 *pMpi2BootDeviceDeviceName_t;
1450 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE {
1451 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1452 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1453 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1454 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1455 } MPI2_BIOSPAGE2_BOOT_DEVICE,
1456 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1457 Mpi2BiosPage2BootDevice_t,
1458 *pMpi2BiosPage2BootDevice_t;
1460 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 {
1461 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1462 U32 Reserved1; /*0x04 */
1463 U32 Reserved2; /*0x08 */
1464 U32 Reserved3; /*0x0C */
1465 U32 Reserved4; /*0x10 */
1466 U32 Reserved5; /*0x14 */
1467 U32 Reserved6; /*0x18 */
1468 U8 ReqBootDeviceForm; /*0x1C */
1469 U8 Reserved7; /*0x1D */
1470 U16 Reserved8; /*0x1E */
1471 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */
1472 U8 ReqAltBootDeviceForm; /*0x38 */
1473 U8 Reserved9; /*0x39 */
1474 U16 Reserved10; /*0x3A */
1475 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */
1476 U8 CurrentBootDeviceForm; /*0x58 */
1477 U8 Reserved11; /*0x59 */
1478 U16 Reserved12; /*0x5A */
1479 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */
1480 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2,
1481 Mpi2BiosPage2_t, *pMpi2BiosPage2_t;
1483 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1485 /*values for BIOS Page 2 BootDeviceForm fields */
1486 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1487 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1488 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1489 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1490 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1495 typedef struct _MPI2_ADAPTER_INFO {
1496 U8 PciBusNumber; /*0x00 */
1497 U8 PciDeviceAndFunctionNumber; /*0x01 */
1498 U16 AdapterFlags; /*0x02 */
1499 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO,
1500 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t;
1502 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1503 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1505 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 {
1506 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1507 U32 GlobalFlags; /*0x04 */
1508 U32 BiosVersion; /*0x08 */
1509 MPI2_ADAPTER_INFO AdapterOrder[4]; /*0x0C */
1510 U32 Reserved1; /*0x1C */
1511 } MPI2_CONFIG_PAGE_BIOS_3,
1512 *PTR_MPI2_CONFIG_PAGE_BIOS_3,
1513 Mpi2BiosPage3_t, *pMpi2BiosPage3_t;
1515 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1517 /*values for BIOS Page 3 GlobalFlags */
1518 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1519 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1520 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1522 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1523 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1524 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1525 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1531 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1532 *one and check the value returned for NumPhys at runtime.
1534 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1535 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1538 typedef struct _MPI2_BIOS4_ENTRY {
1539 U64 ReassignmentWWID; /*0x00 */
1540 U64 ReassignmentDeviceName; /*0x08 */
1541 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY,
1542 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t;
1544 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 {
1545 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1546 U8 NumPhys; /*0x04 */
1547 U8 Reserved1; /*0x05 */
1548 U16 Reserved2; /*0x06 */
1550 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */
1551 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4,
1552 Mpi2BiosPage4_t, *pMpi2BiosPage4_t;
1554 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1557 /****************************************************************************
1558 * RAID Volume Config Pages
1559 ****************************************************************************/
1561 /*RAID Volume Page 0 */
1563 typedef struct _MPI2_RAIDVOL0_PHYS_DISK {
1564 U8 RAIDSetNum; /*0x00 */
1565 U8 PhysDiskMap; /*0x01 */
1566 U8 PhysDiskNum; /*0x02 */
1567 U8 Reserved; /*0x03 */
1568 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK,
1569 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t;
1571 /*defines for the PhysDiskMap field */
1572 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1573 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1575 typedef struct _MPI2_RAIDVOL0_SETTINGS {
1576 U16 Settings; /*0x00 */
1577 U8 HotSparePool; /*0x01 */
1578 U8 Reserved; /*0x02 */
1579 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS,
1580 Mpi2RaidVol0Settings_t,
1581 *pMpi2RaidVol0Settings_t;
1583 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1584 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1585 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1586 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1587 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1588 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1589 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1590 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1591 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1593 /*RAID Volume Page 0 VolumeSettings defines */
1594 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1595 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1597 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1598 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1599 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1600 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1603 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1604 *one and check the value returned for NumPhysDisks at runtime.
1606 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1607 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1610 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 {
1611 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1612 U16 DevHandle; /*0x04 */
1613 U8 VolumeState; /*0x06 */
1614 U8 VolumeType; /*0x07 */
1615 U32 VolumeStatusFlags; /*0x08 */
1616 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */
1617 U64 MaxLBA; /*0x10 */
1618 U32 StripeSize; /*0x18 */
1619 U16 BlockSize; /*0x1C */
1620 U16 Reserved1; /*0x1E */
1621 U8 SupportedPhysDisks;/*0x20 */
1622 U8 ResyncRate; /*0x21 */
1623 U16 DataScrubDuration; /*0x22 */
1624 U8 NumPhysDisks; /*0x24 */
1625 U8 Reserved2; /*0x25 */
1626 U8 Reserved3; /*0x26 */
1627 U8 InactiveStatus; /*0x27 */
1628 MPI2_RAIDVOL0_PHYS_DISK
1629 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */
1630 } MPI2_CONFIG_PAGE_RAID_VOL_0,
1631 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1632 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t;
1634 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1636 /*values for RAID VolumeState */
1637 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1638 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1639 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1640 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1641 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1642 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1644 /*values for RAID VolumeType */
1645 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1646 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1647 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1648 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1649 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1651 /*values for RAID Volume Page 0 VolumeStatusFlags field */
1652 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1653 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1654 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1655 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1656 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1657 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1658 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1659 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1660 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1661 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1662 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1663 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1664 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1665 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1666 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1667 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1668 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1669 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1670 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1672 /*values for RAID Volume Page 0 SupportedPhysDisks field */
1673 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1674 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1675 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1676 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1678 /*values for RAID Volume Page 0 InactiveStatus field */
1679 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1680 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1681 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1682 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1683 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1684 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1685 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1688 /*RAID Volume Page 1 */
1690 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 {
1691 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1692 U16 DevHandle; /*0x04 */
1693 U16 Reserved0; /*0x06 */
1694 U8 GUID[24]; /*0x08 */
1695 U8 Name[16]; /*0x20 */
1697 U32 Reserved1; /*0x38 */
1698 U32 Reserved2; /*0x3C */
1699 } MPI2_CONFIG_PAGE_RAID_VOL_1,
1700 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1701 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t;
1703 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1706 /****************************************************************************
1707 * RAID Physical Disk Config Pages
1708 ****************************************************************************/
1710 /*RAID Physical Disk Page 0 */
1712 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS {
1713 U16 Reserved1; /*0x00 */
1714 U8 HotSparePool; /*0x02 */
1715 U8 Reserved2; /*0x03 */
1716 } MPI2_RAIDPHYSDISK0_SETTINGS,
1717 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1718 Mpi2RaidPhysDisk0Settings_t,
1719 *pMpi2RaidPhysDisk0Settings_t;
1721 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1723 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA {
1724 U8 VendorID[8]; /*0x00 */
1725 U8 ProductID[16]; /*0x08 */
1726 U8 ProductRevLevel[4]; /*0x18 */
1727 U8 SerialNum[32]; /*0x1C */
1728 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1729 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1730 Mpi2RaidPhysDisk0InquiryData_t,
1731 *pMpi2RaidPhysDisk0InquiryData_t;
1733 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 {
1734 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1735 U16 DevHandle; /*0x04 */
1736 U8 Reserved1; /*0x06 */
1737 U8 PhysDiskNum; /*0x07 */
1738 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */
1739 U32 Reserved2; /*0x0C */
1740 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */
1741 U32 Reserved3; /*0x4C */
1742 U8 PhysDiskState; /*0x50 */
1743 U8 OfflineReason; /*0x51 */
1744 U8 IncompatibleReason; /*0x52 */
1745 U8 PhysDiskAttributes; /*0x53 */
1746 U32 PhysDiskStatusFlags;/*0x54 */
1747 U64 DeviceMaxLBA; /*0x58 */
1748 U64 HostMaxLBA; /*0x60 */
1749 U64 CoercedMaxLBA; /*0x68 */
1750 U16 BlockSize; /*0x70 */
1751 U16 Reserved5; /*0x72 */
1752 U32 Reserved6; /*0x74 */
1753 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1754 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1755 Mpi2RaidPhysDiskPage0_t,
1756 *pMpi2RaidPhysDiskPage0_t;
1758 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1760 /*PhysDiskState defines */
1761 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1762 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1763 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1764 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1765 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1766 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1767 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1768 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1770 /*OfflineReason defines */
1771 #define MPI2_PHYSDISK0_ONLINE (0x00)
1772 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1773 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1774 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1775 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1776 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1777 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1779 /*IncompatibleReason defines */
1780 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1781 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1782 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1783 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1784 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1785 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1786 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1787 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1789 /*PhysDiskAttributes defines */
1790 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1791 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1792 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1794 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1795 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1796 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1798 /*PhysDiskStatusFlags defines */
1799 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1800 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1801 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1802 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1803 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1804 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1805 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1806 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1809 /*RAID Physical Disk Page 1 */
1812 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1813 *one and check the value returned for NumPhysDiskPaths at runtime.
1815 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1816 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1819 typedef struct _MPI2_RAIDPHYSDISK1_PATH {
1820 U16 DevHandle; /*0x00 */
1821 U16 Reserved1; /*0x02 */
1823 U64 OwnerWWID; /*0x0C */
1824 U8 OwnerIdentifier; /*0x14 */
1825 U8 Reserved2; /*0x15 */
1826 U16 Flags; /*0x16 */
1827 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH,
1828 Mpi2RaidPhysDisk1Path_t,
1829 *pMpi2RaidPhysDisk1Path_t;
1831 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1832 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1833 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1834 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1836 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 {
1837 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1838 U8 NumPhysDiskPaths; /*0x04 */
1839 U8 PhysDiskNum; /*0x05 */
1840 U16 Reserved1; /*0x06 */
1841 U32 Reserved2; /*0x08 */
1842 MPI2_RAIDPHYSDISK1_PATH
1843 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */
1844 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1845 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1846 Mpi2RaidPhysDiskPage1_t,
1847 *pMpi2RaidPhysDiskPage1_t;
1849 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1852 /****************************************************************************
1853 * values for fields used by several types of SAS Config Pages
1854 ****************************************************************************/
1856 /*values for NegotiatedLinkRates fields */
1857 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1858 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1859 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1860 /*link rates used for Negotiated Physical and Logical Link Rate */
1861 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1862 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1863 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1864 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1865 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1866 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1867 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1868 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1869 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1870 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1871 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B)
1874 /*values for AttachedPhyInfo fields */
1875 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1876 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1877 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1879 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1880 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1881 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1882 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1883 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1884 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1885 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1886 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1887 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1888 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1891 /*values for PhyInfo fields */
1892 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1894 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1895 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1896 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1897 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1898 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1900 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1901 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1902 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1903 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1904 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1905 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1907 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1908 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1909 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1910 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1911 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1912 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1913 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1914 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1915 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1916 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1918 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1919 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1920 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1921 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1923 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1924 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1926 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1927 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1928 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1929 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1932 /*values for SAS ProgrammedLinkRate fields */
1933 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1934 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1935 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1936 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1937 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1938 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0)
1939 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1940 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1941 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1942 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1943 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1944 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B)
1947 /*values for SAS HwLinkRate fields */
1948 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1949 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1950 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1951 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1952 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0)
1953 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1954 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1955 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1956 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1957 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B)
1961 /****************************************************************************
1962 * SAS IO Unit Config Pages
1963 ****************************************************************************/
1965 /*SAS IO Unit Page 0 */
1967 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA {
1969 U8 PortFlags; /*0x01 */
1970 U8 PhyFlags; /*0x02 */
1971 U8 NegotiatedLinkRate; /*0x03 */
1972 U32 ControllerPhyDeviceInfo;/*0x04 */
1973 U16 AttachedDevHandle; /*0x08 */
1974 U16 ControllerDevHandle; /*0x0A */
1975 U32 DiscoveryStatus; /*0x0C */
1976 U32 Reserved; /*0x10 */
1977 } MPI2_SAS_IO_UNIT0_PHY_DATA,
1978 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1979 Mpi2SasIOUnit0PhyData_t,
1980 *pMpi2SasIOUnit0PhyData_t;
1983 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1984 *one and check the value returned for NumPhys at runtime.
1986 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1987 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1990 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 {
1991 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
1992 U32 Reserved1;/*0x08 */
1993 U8 NumPhys; /*0x0C */
1994 U8 Reserved2;/*0x0D */
1995 U16 Reserved3;/*0x0E */
1996 MPI2_SAS_IO_UNIT0_PHY_DATA
1997 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */
1998 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1999 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
2000 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t;
2002 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
2004 /*values for SAS IO Unit Page 0 PortFlags */
2005 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
2006 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
2008 /*values for SAS IO Unit Page 0 PhyFlags */
2009 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
2010 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
2012 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2014 /*see mpi2_sas.h for values for
2015 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2017 /*values for SAS IO Unit Page 0 DiscoveryStatus */
2018 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2019 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2020 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
2021 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2022 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2023 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2024 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2025 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
2026 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2027 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2028 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
2029 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2030 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2031 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2032 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2033 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2034 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2035 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2036 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2037 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
2040 /*SAS IO Unit Page 1 */
2042 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA {
2044 U8 PortFlags; /*0x01 */
2045 U8 PhyFlags; /*0x02 */
2046 U8 MaxMinLinkRate; /*0x03 */
2047 U32 ControllerPhyDeviceInfo; /*0x04 */
2048 U16 MaxTargetPortConnectTime; /*0x08 */
2049 U16 Reserved1; /*0x0A */
2050 } MPI2_SAS_IO_UNIT1_PHY_DATA,
2051 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2052 Mpi2SasIOUnit1PhyData_t,
2053 *pMpi2SasIOUnit1PhyData_t;
2056 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2057 *one and check the value returned for NumPhys at runtime.
2059 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2060 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
2063 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 {
2064 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2066 ControlFlags; /*0x08 */
2068 SASNarrowMaxQueueDepth; /*0x0A */
2070 AdditionalControlFlags; /*0x0C */
2072 SASWideMaxQueueDepth; /*0x0E */
2076 SATAMaxQDepth; /*0x11 */
2078 ReportDeviceMissingDelay; /*0x12 */
2080 IODeviceMissingDelay; /*0x13 */
2081 MPI2_SAS_IO_UNIT1_PHY_DATA
2082 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */
2083 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
2084 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2085 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t;
2087 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
2089 /*values for SAS IO Unit Page 1 ControlFlags */
2090 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2091 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2092 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2093 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2095 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2096 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2097 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
2098 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
2099 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
2101 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2102 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2103 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2104 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2105 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
2106 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2107 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2108 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2110 /*values for SAS IO Unit Page 1 AdditionalControlFlags */
2111 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2112 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2113 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
2114 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2115 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2116 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2117 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2118 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2120 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2121 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2122 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2124 /*values for SAS IO Unit Page 1 PortFlags */
2125 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2127 /*values for SAS IO Unit Page 1 PhyFlags */
2128 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
2129 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2131 /*values for SAS IO Unit Page 1 MaxMinLinkRate */
2132 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
2133 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
2134 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
2135 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
2136 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0)
2137 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
2138 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
2139 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
2140 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
2141 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B)
2143 /*see mpi2_sas.h for values for
2144 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2147 /*SAS IO Unit Page 4 */
2149 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP {
2150 U8 MaxTargetSpinup; /*0x00 */
2151 U8 SpinupDelay; /*0x01 */
2152 U8 SpinupFlags; /*0x02 */
2153 U8 Reserved1; /*0x03 */
2154 } MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2155 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2156 Mpi2SasIOUnit4SpinupGroup_t,
2157 *pMpi2SasIOUnit4SpinupGroup_t;
2158 /*defines for SAS IO Unit Page 4 SpinupFlags */
2159 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2163 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2164 *one and check the value returned for NumPhys at runtime.
2166 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2167 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
2170 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 {
2171 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */
2172 MPI2_SAS_IOUNIT4_SPINUP_GROUP
2173 SpinupGroupParameters[4]; /*0x08 */
2175 Reserved1; /*0x18 */
2177 Reserved2; /*0x1C */
2179 Reserved3; /*0x20 */
2181 BootDeviceWaitTime; /*0x24 */
2183 Reserved4; /*0x25 */
2185 Reserved5; /*0x26 */
2189 PEInitialSpinupDelay; /*0x29 */
2191 PEReplyDelay; /*0x2A */
2195 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */
2196 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2197 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2198 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t;
2200 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2202 /*defines for Flags field */
2203 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2205 /*defines for PHY field */
2206 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2209 /*SAS IO Unit Page 5 */
2211 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2212 U8 ControlFlags; /*0x00 */
2213 U8 PortWidthModGroup; /*0x01 */
2214 U16 InactivityTimerExponent; /*0x02 */
2215 U8 SATAPartialTimeout; /*0x04 */
2216 U8 Reserved2; /*0x05 */
2217 U8 SATASlumberTimeout; /*0x06 */
2218 U8 Reserved3; /*0x07 */
2219 U8 SASPartialTimeout; /*0x08 */
2220 U8 Reserved4; /*0x09 */
2221 U8 SASSlumberTimeout; /*0x0A */
2222 U8 Reserved5; /*0x0B */
2223 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2224 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2225 Mpi2SasIOUnit5PhyPmSettings_t,
2226 *pMpi2SasIOUnit5PhyPmSettings_t;
2228 /*defines for ControlFlags field */
2229 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2230 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2231 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2232 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2234 /*defines for PortWidthModeGroup field */
2235 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2237 /*defines for InactivityTimerExponent field */
2238 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2239 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2240 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2241 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2242 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2243 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2244 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2245 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2247 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2248 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2249 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2250 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2251 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2252 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2253 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2254 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2257 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2258 *one and check the value returned for NumPhys at runtime.
2260 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2261 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2264 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2265 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2266 U8 NumPhys; /*0x08 */
2267 U8 Reserved1;/*0x09 */
2268 U16 Reserved2;/*0x0A */
2269 U32 Reserved3;/*0x0C */
2270 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2271 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */
2272 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2273 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2274 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t;
2276 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2279 /*SAS IO Unit Page 6 */
2281 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2282 U8 CurrentStatus; /*0x00 */
2283 U8 CurrentModulation; /*0x01 */
2284 U8 CurrentUtilization; /*0x02 */
2285 U8 Reserved1; /*0x03 */
2286 U32 Reserved2; /*0x04 */
2287 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2288 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2289 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2290 *pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2292 /*defines for CurrentStatus field */
2293 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2294 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2295 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2296 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2297 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2298 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2299 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2300 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2302 /*defines for CurrentModulation field */
2303 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2304 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2305 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2306 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2309 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2310 *one and check the value returned for NumGroups at runtime.
2312 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2313 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2316 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2317 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2318 U32 Reserved1; /*0x08 */
2319 U32 Reserved2; /*0x0C */
2320 U8 NumGroups; /*0x10 */
2321 U8 Reserved3; /*0x11 */
2322 U16 Reserved4; /*0x12 */
2323 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2324 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */
2325 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2326 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2327 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t;
2329 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2332 /*SAS IO Unit Page 7 */
2334 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2336 U8 Reserved1; /*0x01 */
2337 U16 Reserved2; /*0x02 */
2338 U8 Threshold75Pct; /*0x04 */
2339 U8 Threshold50Pct; /*0x05 */
2340 U8 Threshold25Pct; /*0x06 */
2341 U8 Reserved3; /*0x07 */
2342 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2343 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2344 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2345 *pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2347 /*defines for Flags field */
2348 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2352 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2353 *one and check the value returned for NumGroups at runtime.
2355 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2356 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2359 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2360 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2361 U8 SamplingInterval; /*0x08 */
2362 U8 WindowLength; /*0x09 */
2363 U16 Reserved1; /*0x0A */
2364 U32 Reserved2; /*0x0C */
2365 U32 Reserved3; /*0x10 */
2366 U8 NumGroups; /*0x14 */
2367 U8 Reserved4; /*0x15 */
2368 U16 Reserved5; /*0x16 */
2369 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2370 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */
2371 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2372 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2373 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t;
2375 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2378 /*SAS IO Unit Page 8 */
2380 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2381 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2384 Reserved1; /*0x08 */
2386 PowerManagementCapabilities; /*0x0C */
2388 TxRxSleepStatus; /*0x10 */
2390 Reserved2; /*0x11 */
2392 Reserved3; /*0x12 */
2393 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2394 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2395 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t;
2397 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2399 /*defines for PowerManagementCapabilities field */
2400 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2401 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2402 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2403 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2404 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2405 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2406 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2407 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2408 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2409 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2411 /*defines for TxRxSleepStatus field */
2412 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00)
2413 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01)
2414 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02)
2415 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03)
2419 /*SAS IO Unit Page 16 */
2421 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2422 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2425 TimeStamp; /*0x08 */
2427 Reserved1; /*0x10 */
2429 Reserved2; /*0x14 */
2431 FastPathPendedRequests; /*0x18 */
2433 FastPathUnPendedRequests; /*0x1C */
2435 FastPathHostRequestStarts; /*0x20 */
2437 FastPathFirmwareRequestStarts; /*0x24 */
2439 FastPathHostCompletions; /*0x28 */
2441 FastPathFirmwareCompletions; /*0x2C */
2443 NonFastPathRequestStarts; /*0x30 */
2445 NonFastPathHostCompletions; /*0x30 */
2446 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2447 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2448 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t;
2450 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2453 /****************************************************************************
2454 * SAS Expander Config Pages
2455 ****************************************************************************/
2457 /*SAS Expander Page 0 */
2459 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 {
2460 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2463 PhysicalPort; /*0x08 */
2465 ReportGenLength; /*0x09 */
2467 EnclosureHandle; /*0x0A */
2469 SASAddress; /*0x0C */
2471 DiscoveryStatus; /*0x14 */
2473 DevHandle; /*0x18 */
2475 ParentDevHandle; /*0x1A */
2477 ExpanderChangeCount; /*0x1C */
2479 ExpanderRouteIndexes; /*0x1E */
2487 STPBusInactivityTimeLimit; /*0x24 */
2489 STPMaxConnectTimeLimit; /*0x26 */
2491 STP_SMP_NexusLossTime; /*0x28 */
2493 MaxNumRoutedSasAddresses; /*0x2A */
2495 ActiveZoneManagerSASAddress;/*0x2C */
2497 ZoneLockInactivityLimit; /*0x34 */
2499 Reserved1; /*0x36 */
2501 TimeToReducedFunc; /*0x38 */
2503 InitialTimeToReducedFunc; /*0x39 */
2505 MaxReducedFuncTime; /*0x3A */
2507 Reserved2; /*0x3B */
2508 } MPI2_CONFIG_PAGE_EXPANDER_0,
2509 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2510 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t;
2512 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2514 /*values for SAS Expander Page 0 DiscoveryStatus field */
2515 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2516 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2517 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2518 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2519 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2520 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2521 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2522 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2523 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2524 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2525 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2526 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2527 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2528 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2529 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2530 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2531 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2532 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2533 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2534 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2536 /*values for SAS Expander Page 0 Flags field */
2537 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2538 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2539 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2540 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2541 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2542 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2543 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2544 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2545 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2546 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2547 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2550 /*SAS Expander Page 1 */
2552 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 {
2553 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2556 PhysicalPort; /*0x08 */
2558 Reserved1; /*0x09 */
2560 Reserved2; /*0x0A */
2566 NumTableEntriesProgrammed; /*0x0E */
2568 ProgrammedLinkRate; /*0x10 */
2570 HwLinkRate; /*0x11 */
2572 AttachedDevHandle; /*0x12 */
2576 AttachedDeviceInfo; /*0x18 */
2578 ExpanderDevHandle; /*0x1C */
2580 ChangeCount; /*0x1E */
2582 NegotiatedLinkRate; /*0x1F */
2584 PhyIdentifier; /*0x20 */
2586 AttachedPhyIdentifier; /*0x21 */
2588 Reserved3; /*0x22 */
2590 DiscoveryInfo; /*0x23 */
2592 AttachedPhyInfo; /*0x24 */
2594 ZoneGroup; /*0x28 */
2596 SelfConfigStatus; /*0x29 */
2598 Reserved4; /*0x2A */
2599 } MPI2_CONFIG_PAGE_EXPANDER_1,
2600 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2601 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t;
2603 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2605 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2607 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2609 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2611 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines
2612 *used for the AttachedDeviceInfo field */
2614 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2616 /*values for SAS Expander Page 1 DiscoveryInfo field */
2617 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2618 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2619 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2621 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2624 /****************************************************************************
2625 * SAS Device Config Pages
2626 ****************************************************************************/
2628 /*SAS Device Page 0 */
2630 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 {
2631 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2636 EnclosureHandle; /*0x0A */
2638 SASAddress; /*0x0C */
2640 ParentDevHandle; /*0x14 */
2644 AccessStatus; /*0x17 */
2646 DevHandle; /*0x18 */
2648 AttachedPhyIdentifier; /*0x1A */
2650 ZoneGroup; /*0x1B */
2652 DeviceInfo; /*0x1C */
2656 PhysicalPort; /*0x22 */
2658 MaxPortConnections; /*0x23 */
2660 DeviceName; /*0x24 */
2662 PortGroups; /*0x2C */
2666 ControlGroup; /*0x2E */
2668 EnclosureLevel; /*0x2F */
2670 ConnectorName[4]; /*0x30 */
2672 Reserved3; /*0x34 */
2673 } MPI2_CONFIG_PAGE_SAS_DEV_0,
2674 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2675 Mpi2SasDevicePage0_t,
2676 *pMpi2SasDevicePage0_t;
2678 #define MPI2_SASDEVICE0_PAGEVERSION (0x09)
2680 /*values for SAS Device Page 0 AccessStatus field */
2681 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2682 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2683 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2684 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2685 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2686 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2687 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2688 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2689 /*specific values for SATA Init failures */
2690 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2691 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2692 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2693 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2694 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2695 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2696 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2697 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2698 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2699 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2700 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2702 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2704 /*values for SAS Device Page 0 Flags field */
2705 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2706 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000)
2707 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000)
2708 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2709 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2710 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2711 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2712 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2713 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2714 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2715 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2716 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2717 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2718 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002)
2719 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2722 /*SAS Device Page 1 */
2724 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 {
2725 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2728 Reserved1; /*0x08 */
2730 SASAddress; /*0x0C */
2732 Reserved2; /*0x14 */
2734 DevHandle; /*0x18 */
2736 Reserved3; /*0x1A */
2738 InitialRegDeviceFIS[20];/*0x1C */
2739 } MPI2_CONFIG_PAGE_SAS_DEV_1,
2740 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2741 Mpi2SasDevicePage1_t,
2742 *pMpi2SasDevicePage1_t;
2744 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2747 /****************************************************************************
2748 * SAS PHY Config Pages
2749 ****************************************************************************/
2753 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 {
2754 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2757 OwnerDevHandle; /*0x08 */
2759 Reserved1; /*0x0A */
2761 AttachedDevHandle; /*0x0C */
2763 AttachedPhyIdentifier; /*0x0E */
2765 Reserved2; /*0x0F */
2767 AttachedPhyInfo; /*0x10 */
2769 ProgrammedLinkRate; /*0x14 */
2771 HwLinkRate; /*0x15 */
2773 ChangeCount; /*0x16 */
2779 NegotiatedLinkRate; /*0x1C */
2781 Reserved3; /*0x1D */
2783 Reserved4; /*0x1E */
2784 } MPI2_CONFIG_PAGE_SAS_PHY_0,
2785 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2786 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t;
2788 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2790 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2792 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2794 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2796 /*values for SAS PHY Page 0 Flags field */
2797 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2799 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2801 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2806 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 {
2807 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2810 Reserved1; /*0x08 */
2812 InvalidDwordCount; /*0x0C */
2814 RunningDisparityErrorCount; /*0x10 */
2816 LossDwordSynchCount; /*0x14 */
2818 PhyResetProblemCount; /*0x18 */
2819 } MPI2_CONFIG_PAGE_SAS_PHY_1,
2820 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2821 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t;
2823 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2828 typedef struct _MPI2_SASPHY2_PHY_EVENT {
2829 U8 PhyEventCode; /*0x00 */
2830 U8 Reserved1; /*0x01 */
2831 U16 Reserved2; /*0x02 */
2832 U32 PhyEventInfo; /*0x04 */
2833 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT,
2834 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t;
2836 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2840 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2841 *one and check the value returned for NumPhyEvents at runtime.
2843 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2844 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2847 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2848 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2851 Reserved1; /*0x08 */
2853 NumPhyEvents; /*0x0C */
2855 Reserved2; /*0x0D */
2857 Reserved3; /*0x0E */
2858 MPI2_SASPHY2_PHY_EVENT
2859 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */
2860 } MPI2_CONFIG_PAGE_SAS_PHY_2,
2861 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2863 *pMpi2SasPhyPage2_t;
2865 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2870 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2871 U8 PhyEventCode; /*0x00 */
2872 U8 Reserved1; /*0x01 */
2873 U16 Reserved2; /*0x02 */
2874 U8 CounterType; /*0x04 */
2875 U8 ThresholdWindow; /*0x05 */
2876 U8 TimeUnits; /*0x06 */
2877 U8 Reserved3; /*0x07 */
2878 U32 EventThreshold; /*0x08 */
2879 U16 ThresholdFlags; /*0x0C */
2880 U16 Reserved4; /*0x0E */
2881 } MPI2_SASPHY3_PHY_EVENT_CONFIG,
2882 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2883 Mpi2SasPhy3PhyEventConfig_t,
2884 *pMpi2SasPhy3PhyEventConfig_t;
2886 /*values for PhyEventCode field */
2887 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2888 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2889 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2890 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2891 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2892 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2893 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2894 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2895 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2896 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2897 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2898 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2899 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2900 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2901 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2902 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2903 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2904 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2905 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2906 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2907 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2908 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2909 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2910 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2911 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2912 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2913 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2914 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2915 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2916 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2917 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2918 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2919 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2920 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2921 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2922 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2923 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2925 /*values for the CounterType field */
2926 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2927 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2928 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2930 /*values for the TimeUnits field */
2931 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2932 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2933 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2934 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2936 /*values for the ThresholdFlags field */
2937 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2938 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2941 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2942 *one and check the value returned for NumPhyEvents at runtime.
2944 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2945 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2948 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2949 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2952 Reserved1; /*0x08 */
2954 NumPhyEvents; /*0x0C */
2956 Reserved2; /*0x0D */
2958 Reserved3; /*0x0E */
2959 MPI2_SASPHY3_PHY_EVENT_CONFIG
2960 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */
2961 } MPI2_CONFIG_PAGE_SAS_PHY_3,
2962 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2963 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t;
2965 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2970 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2971 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2974 Reserved1; /*0x08 */
2976 Reserved2; /*0x0A */
2980 InitialFrame[28]; /*0x0C */
2981 } MPI2_CONFIG_PAGE_SAS_PHY_4,
2982 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2983 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t;
2985 #define MPI2_SASPHY4_PAGEVERSION (0x00)
2987 /*values for the Flags field */
2988 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2989 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2994 /****************************************************************************
2995 * SAS Port Config Pages
2996 ****************************************************************************/
2998 /*SAS Port Page 0 */
3000 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 {
3001 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3004 PortNumber; /*0x08 */
3006 PhysicalPort; /*0x09 */
3008 PortWidth; /*0x0A */
3010 PhysicalPortWidth; /*0x0B */
3012 ZoneGroup; /*0x0C */
3014 Reserved1; /*0x0D */
3016 Reserved2; /*0x0E */
3018 SASAddress; /*0x10 */
3020 DeviceInfo; /*0x18 */
3022 Reserved3; /*0x1C */
3024 Reserved4; /*0x20 */
3025 } MPI2_CONFIG_PAGE_SAS_PORT_0,
3026 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
3027 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t;
3029 #define MPI2_SASPORT0_PAGEVERSION (0x00)
3031 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
3034 /****************************************************************************
3035 * SAS Enclosure Config Pages
3036 ****************************************************************************/
3038 /*SAS Enclosure Page 0 */
3040 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
3041 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3044 Reserved1; /*0x08 */
3046 EnclosureLogicalID; /*0x0C */
3050 EnclosureHandle; /*0x16 */
3054 StartSlot; /*0x1A */
3056 Reserved2; /*0x1C */
3058 EnclosureLevel; /*0x1D */
3060 SEPDevHandle; /*0x1E */
3062 Reserved3; /*0x20 */
3064 Reserved4; /*0x24 */
3065 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3066 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3067 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t;
3069 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04)
3071 /*values for SAS Enclosure Page 0 Flags field */
3072 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3073 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
3074 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3075 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3076 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3077 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3078 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3079 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3082 /****************************************************************************
3084 ****************************************************************************/
3089 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3090 *one and check the value returned for NumLogEntries at runtime.
3092 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
3093 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
3096 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
3098 typedef struct _MPI2_LOG_0_ENTRY {
3099 U64 TimeStamp; /*0x00 */
3100 U32 Reserved1; /*0x08 */
3101 U16 LogSequence; /*0x0C */
3102 U16 LogEntryQualifier; /*0x0E */
3105 U16 Reserved2; /*0x12 */
3107 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */
3108 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY,
3109 Mpi2Log0Entry_t, *pMpi2Log0Entry_t;
3111 /*values for Log Page 0 LogEntry LogEntryQualifier field */
3112 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
3113 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
3114 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
3115 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
3116 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
3118 typedef struct _MPI2_CONFIG_PAGE_LOG_0 {
3119 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3120 U32 Reserved1; /*0x08 */
3121 U32 Reserved2; /*0x0C */
3122 U16 NumLogEntries;/*0x10 */
3123 U16 Reserved3; /*0x12 */
3125 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */
3126 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0,
3127 Mpi2LogPage0_t, *pMpi2LogPage0_t;
3129 #define MPI2_LOG_0_PAGEVERSION (0x02)
3132 /****************************************************************************
3134 ****************************************************************************/
3139 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3140 *one and check the value returned for NumElements at runtime.
3142 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
3143 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
3146 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT {
3147 U16 ElementFlags; /*0x00 */
3148 U16 VolDevHandle; /*0x02 */
3149 U8 HotSparePool; /*0x04 */
3150 U8 PhysDiskNum; /*0x05 */
3151 U16 PhysDiskDevHandle; /*0x06 */
3152 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3153 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3154 Mpi2RaidConfig0ConfigElement_t,
3155 *pMpi2RaidConfig0ConfigElement_t;
3157 /*values for the ElementFlags field */
3158 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
3159 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
3160 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
3161 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
3162 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
3165 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 {
3166 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3167 U8 NumHotSpares; /*0x08 */
3168 U8 NumPhysDisks; /*0x09 */
3169 U8 NumVolumes; /*0x0A */
3170 U8 ConfigNum; /*0x0B */
3171 U32 Flags; /*0x0C */
3172 U8 ConfigGUID[24]; /*0x10 */
3173 U32 Reserved1; /*0x28 */
3174 U8 NumElements; /*0x2C */
3175 U8 Reserved2; /*0x2D */
3176 U16 Reserved3; /*0x2E */
3177 MPI2_RAIDCONFIG0_CONFIG_ELEMENT
3178 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */
3179 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3180 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3181 Mpi2RaidConfigurationPage0_t,
3182 *pMpi2RaidConfigurationPage0_t;
3184 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
3186 /*values for RAID Configuration Page 0 Flags field */
3187 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
3190 /****************************************************************************
3191 * Driver Persistent Mapping Config Pages
3192 ****************************************************************************/
3194 /*Driver Persistent Mapping Page 0 */
3196 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY {
3197 U64 PhysicalIdentifier; /*0x00 */
3198 U16 MappingInformation; /*0x08 */
3199 U16 DeviceIndex; /*0x0A */
3200 U32 PhysicalBitsMapping; /*0x0C */
3201 U32 Reserved1; /*0x10 */
3202 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3203 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3204 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t;
3206 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 {
3207 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3208 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */
3209 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3210 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3211 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t;
3213 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
3215 /*values for Driver Persistent Mapping Page 0 MappingInformation field */
3216 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
3217 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
3218 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
3221 /****************************************************************************
3222 * Ethernet Config Pages
3223 ****************************************************************************/
3225 /*Ethernet Page 0 */
3227 /*IP address (union of IPv4 and IPv6) */
3228 typedef union _MPI2_ETHERNET_IP_ADDR {
3231 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR,
3232 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t;
3234 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
3236 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
3237 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3238 U8 NumInterfaces; /*0x08 */
3239 U8 Reserved0; /*0x09 */
3240 U16 Reserved1; /*0x0A */
3241 U32 Status; /*0x0C */
3242 U8 MediaState; /*0x10 */
3243 U8 Reserved2; /*0x11 */
3244 U16 Reserved3; /*0x12 */
3245 U8 MacAddress[6]; /*0x14 */
3246 U8 Reserved4; /*0x1A */
3247 U8 Reserved5; /*0x1B */
3248 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */
3249 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */
3250 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */
3251 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */
3252 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */
3253 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */
3255 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3256 } MPI2_CONFIG_PAGE_ETHERNET_0,
3257 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3258 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t;
3260 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
3262 /*values for Ethernet Page 0 Status field */
3263 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
3264 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
3265 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
3266 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
3267 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
3268 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
3269 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
3270 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
3271 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
3272 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
3273 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
3274 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
3276 /*values for Ethernet Page 0 MediaState field */
3277 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
3278 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
3279 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
3281 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
3282 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
3283 #define MPI2_ETHPG0_MS_10MBIT (0x01)
3284 #define MPI2_ETHPG0_MS_100MBIT (0x02)
3285 #define MPI2_ETHPG0_MS_1GBIT (0x03)
3288 /*Ethernet Page 1 */
3290 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
3291 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3294 Reserved0; /*0x08 */
3298 MediaState; /*0x10 */
3300 Reserved1; /*0x11 */
3302 Reserved2; /*0x12 */
3304 MacAddress[6]; /*0x14 */
3306 Reserved3; /*0x1A */
3308 Reserved4; /*0x1B */
3309 MPI2_ETHERNET_IP_ADDR
3310 StaticIpAddress; /*0x1C */
3311 MPI2_ETHERNET_IP_ADDR
3312 StaticSubnetMask; /*0x2C */
3313 MPI2_ETHERNET_IP_ADDR
3314 StaticGatewayIpAddress; /*0x3C */
3315 MPI2_ETHERNET_IP_ADDR
3316 StaticDNS1IpAddress; /*0x4C */
3317 MPI2_ETHERNET_IP_ADDR
3318 StaticDNS2IpAddress; /*0x5C */
3320 Reserved5; /*0x6C */
3322 Reserved6; /*0x70 */
3324 Reserved7; /*0x74 */
3326 Reserved8; /*0x78 */
3328 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3329 } MPI2_CONFIG_PAGE_ETHERNET_1,
3330 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3331 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t;
3333 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
3335 /*values for Ethernet Page 1 Flags field */
3336 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
3337 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
3338 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
3339 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
3340 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
3341 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
3342 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
3343 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
3344 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
3346 /*values for Ethernet Page 1 MediaState field */
3347 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
3348 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
3349 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
3351 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
3352 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
3353 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
3354 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
3355 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
3358 /****************************************************************************
3359 * Extended Manufacturing Config Pages
3360 ****************************************************************************/
3363 *Generic structure to use for product-specific extended manufacturing pages
3364 *(currently Extended Manufacturing Page 40 through Extended Manufacturing
3368 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3369 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3372 ProductSpecificInfo; /*0x08 */
3373 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3374 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3375 Mpi2ExtManufacturingPagePS_t,
3376 *pMpi2ExtManufacturingPagePS_t;
3378 /*PageVersion should be provided by product-specific code */
Code Review / kvmfornfv.git / blob