kernel/drivers/scsi/mpt2sas/mpi/mpi2_ioc.h

   1 /*
   2  *  Copyright (c) 2000-2014 LSI Corporation.
   3  *
   4  *
   5  *           Name:  mpi2_ioc.h
   6  *          Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
   7  *  Creation Date:  October 11, 2006
   8  *
   9  *  mpi2_ioc.h Version:  02.00.24
  10  *
  11  *  Version History
  12  *  ---------------
  13  *
  14  *  Date      Version   Description
  15  *  --------  --------  ------------------------------------------------------
  16  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  17  *  06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
  18  *                      MaxTargets.
  19  *                      Added TotalImageSize field to FWDownload Request.
  20  *                      Added reserved words to FWUpload Request.
  21  *  06-26-07  02.00.02  Added IR Configuration Change List Event.
  22  *  08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
  23  *                      request and replaced it with
  24  *                      ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  25  *                      Replaced the MinReplyQueueDepth field of the IOCFacts
  26  *                      reply with MaxReplyDescriptorPostQueueDepth.
  27  *                      Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  28  *                      depth for the Reply Descriptor Post Queue.
  29  *                      Added SASAddress field to Initiator Device Table
  30  *                      Overflow Event data.
  31  *  10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  32  *                      for SAS Initiator Device Status Change Event data.
  33  *                      Modified Reason Code defines for SAS Topology Change
  34  *                      List Event data, including adding a bit for PHY Vacant
  35  *                      status, and adding a mask for the Reason Code.
  36  *                      Added define for
  37  *                      MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  38  *                      Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  39  *  12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
  40  *                      the IOCFacts Reply.
  41  *                      Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  42  *                      Moved MPI2_VERSION_UNION to mpi2.h.
  43  *                      Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  44  *                      instead of enables, and added SASBroadcastPrimitiveMasks
  45  *                      field.
  46  *                      Added Log Entry Added Event and related structure.
  47  *  02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  48  *                      Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  49  *                      Added MaxVolumes and MaxPersistentEntries fields to
  50  *                      IOCFacts reply.
  51  *                      Added ProtocalFlags and IOCCapabilities fields to
  52  *                      MPI2_FW_IMAGE_HEADER.
  53  *                      Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  54  *  03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  55  *                      a U16 (from a U32).
  56  *                      Removed extra 's' from EventMasks name.
  57  *  06-27-08  02.00.08  Fixed an offset in a comment.
  58  *  10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  59  *                      Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
  60  *                      renamed MinReplyFrameSize to ReplyFrameSize.
  61  *                      Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
  62  *                      Added two new RAIDOperation values for Integrated RAID
  63  *                      Operations Status Event data.
  64  *                      Added four new IR Configuration Change List Event data
  65  *                      ReasonCode values.
  66  *                      Added two new ReasonCode defines for SAS Device Status
  67  *                      Change Event data.
  68  *                      Added three new DiscoveryStatus bits for the SAS
  69  *                      Discovery event data.
  70  *                      Added Multiplexing Status Change bit to the PhyStatus
  71  *                      field of the SAS Topology Change List event data.
  72  *                      Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  73  *                      BootFlags are now product-specific.
  74  *                      Added defines for the indivdual signature bytes
  75  *                      for MPI2_INIT_IMAGE_FOOTER.
  76  *  01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  77  *                      Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  78  *                      define.
  79  *                      Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  80  *                      define.
  81  *                      Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  82  *  05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
  83  *                      Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
  84  *                      Added two new reason codes for SAS Device Status Change
  85  *                      Event.
  86  *                      Added new event: SAS PHY Counter.
  87  *  07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
  88  *                      Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  89  *                      Added new product id family for 2208.
  90  *  10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
  91  *                      Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
  92  *                      Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
  93  *                      Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
  94  *                      Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
  95  *                      Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
  96  *                      Added Host Based Discovery Phy Event data.
  97  *                      Added defines for ProductID Product field
  98  *                      (MPI2_FW_HEADER_PID_).
  99  *                      Modified values for SAS ProductID Family
 100  *                      (MPI2_FW_HEADER_PID_FAMILY_).
 101  *  02-10-10  02.00.14  Added SAS Quiesce Event structure and defines.
 102  *                      Added PowerManagementControl Request structures and
 103  *                      defines.
 104  *  05-12-10  02.00.15  Marked Task Set Full Event as obsolete.
 105  *                      Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
 106  *  11-10-10  02.00.16  Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
 107  *  02-23-11  02.00.17  Added SAS NOTIFY Primitive event, and added
 108  *                      SASNotifyPrimitiveMasks field to
 109  *                      MPI2_EVENT_NOTIFICATION_REQUEST.
 110  *                      Added Temperature Threshold Event.
 111  *                      Added Host Message Event.
 112  *                      Added Send Host Message request and reply.
 113  *  05-25-11  02.00.18  For Extended Image Header, added
 114  *                      MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
 115  *                      MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
 116  *                      Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
 117  *  08-24-11  02.00.19  Added PhysicalPort field to
 118  *                      MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
 119  *                      Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
 120  *  03-29-12  02.00.21  Added a product specific range to event values.
 121  *  07-26-12  02.00.22  Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
 122  *                      Added ElapsedSeconds field to
 123  *                      MPI2_EVENT_DATA_IR_OPERATION_STATUS.
 124  *  08-19-13  02.00.23  For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
 125  *                      and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
 126  *                      Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
 127  *                      Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
 128  *                      Added Encrypted Hash Extended Image.
 129  *  12-05-13  02.00.24  Added MPI25_HASH_IMAGE_TYPE_BIOS.
 130  *  --------------------------------------------------------------------------
 131  */
 132
 133 #ifndef MPI2_IOC_H
 134 #define MPI2_IOC_H
 135
 136 /*****************************************************************************
 137 *
 138 *               IOC Messages
 139 *
 140 *****************************************************************************/
 141
 142 /****************************************************************************
 143 *  IOCInit message
 144 ****************************************************************************/
 145
 146 /* IOCInit Request message */
 147 typedef struct _MPI2_IOC_INIT_REQUEST
 148 {
 149     U8                      WhoInit;                        /* 0x00 */
 150     U8                      Reserved1;                      /* 0x01 */
 151     U8                      ChainOffset;                    /* 0x02 */
 152     U8                      Function;                       /* 0x03 */
 153     U16                     Reserved2;                      /* 0x04 */
 154     U8                      Reserved3;                      /* 0x06 */
 155     U8                      MsgFlags;                       /* 0x07 */
 156     U8                      VP_ID;                          /* 0x08 */
 157     U8                      VF_ID;                          /* 0x09 */
 158     U16                     Reserved4;                      /* 0x0A */
 159     U16                     MsgVersion;                     /* 0x0C */
 160     U16                     HeaderVersion;                  /* 0x0E */
 161     U32                     Reserved5;                      /* 0x10 */
 162     U16                     Reserved6;                      /* 0x14 */
 163     U8                      Reserved7;                      /* 0x16 */
 164     U8                      HostMSIxVectors;                /* 0x17 */
 165     U16                     Reserved8;                      /* 0x18 */
 166     U16                     SystemRequestFrameSize;         /* 0x1A */
 167     U16                     ReplyDescriptorPostQueueDepth;  /* 0x1C */
 168     U16                     ReplyFreeQueueDepth;            /* 0x1E */
 169     U32                     SenseBufferAddressHigh;         /* 0x20 */
 170     U32                     SystemReplyAddressHigh;         /* 0x24 */
 171     U64                     SystemRequestFrameBaseAddress;  /* 0x28 */
 172     U64                     ReplyDescriptorPostQueueAddress;/* 0x30 */
 173     U64                     ReplyFreeQueueAddress;          /* 0x38 */
 174     U64                     TimeStamp;                      /* 0x40 */
 175 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
 176   Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
 177
 178 /* WhoInit values */
 179 #define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 180 #define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 181 #define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 182 #define MPI2_WHOINIT_PCI_PEER                   (0x03)
 183 #define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 184 #define MPI2_WHOINIT_MANUFACTURER               (0x05)
 185
 186 /* MsgFlags */
 187 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
 188
 189 /* MsgVersion */
 190 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
 191 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
 192 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
 193 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
 194
 195 /* HeaderVersion */
 196 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
 197 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
 198 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
 199 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
 200
 201 /* minimum depth for a Reply Descriptor Post Queue */
 202 #define MPI2_RDPQ_DEPTH_MIN                     (16)
 203
 204 /* Reply Descriptor Post Queue Array Entry */
 205 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
 206         U64                 RDPQBaseAddress;                    /* 0x00 */
 207         U32                 Reserved1;                          /* 0x08 */
 208         U32                 Reserved2;                          /* 0x0C */
 209 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 210 MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 211 Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry;
 212
 213 /* IOCInit Reply message */
 214 typedef struct _MPI2_IOC_INIT_REPLY
 215 {
 216     U8                      WhoInit;                        /* 0x00 */
 217     U8                      Reserved1;                      /* 0x01 */
 218     U8                      MsgLength;                      /* 0x02 */
 219     U8                      Function;                       /* 0x03 */
 220     U16                     Reserved2;                      /* 0x04 */
 221     U8                      Reserved3;                      /* 0x06 */
 222     U8                      MsgFlags;                       /* 0x07 */
 223     U8                      VP_ID;                          /* 0x08 */
 224     U8                      VF_ID;                          /* 0x09 */
 225     U16                     Reserved4;                      /* 0x0A */
 226     U16                     Reserved5;                      /* 0x0C */
 227     U16                     IOCStatus;                      /* 0x0E */
 228     U32                     IOCLogInfo;                     /* 0x10 */
 229 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
 230   Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
 231
 232
 233 /****************************************************************************
 234 *  IOCFacts message
 235 ****************************************************************************/
 236
 237 /* IOCFacts Request message */
 238 typedef struct _MPI2_IOC_FACTS_REQUEST
 239 {
 240     U16                     Reserved1;                      /* 0x00 */
 241     U8                      ChainOffset;                    /* 0x02 */
 242     U8                      Function;                       /* 0x03 */
 243     U16                     Reserved2;                      /* 0x04 */
 244     U8                      Reserved3;                      /* 0x06 */
 245     U8                      MsgFlags;                       /* 0x07 */
 246     U8                      VP_ID;                          /* 0x08 */
 247     U8                      VF_ID;                          /* 0x09 */
 248     U16                     Reserved4;                      /* 0x0A */
 249 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
 250   Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
 251
 252
 253 /* IOCFacts Reply message */
 254 typedef struct _MPI2_IOC_FACTS_REPLY
 255 {
 256     U16                     MsgVersion;                     /* 0x00 */
 257     U8                      MsgLength;                      /* 0x02 */
 258     U8                      Function;                       /* 0x03 */
 259     U16                     HeaderVersion;                  /* 0x04 */
 260     U8                      IOCNumber;                      /* 0x06 */
 261     U8                      MsgFlags;                       /* 0x07 */
 262     U8                      VP_ID;                          /* 0x08 */
 263     U8                      VF_ID;                          /* 0x09 */
 264     U16                     Reserved1;                      /* 0x0A */
 265     U16                     IOCExceptions;                  /* 0x0C */
 266     U16                     IOCStatus;                      /* 0x0E */
 267     U32                     IOCLogInfo;                     /* 0x10 */
 268     U8                      MaxChainDepth;                  /* 0x14 */
 269     U8                      WhoInit;                        /* 0x15 */
 270     U8                      NumberOfPorts;                  /* 0x16 */
 271     U8                      MaxMSIxVectors;                 /* 0x17 */
 272     U16                     RequestCredit;                  /* 0x18 */
 273     U16                     ProductID;                      /* 0x1A */
 274     U32                     IOCCapabilities;                /* 0x1C */
 275     MPI2_VERSION_UNION      FWVersion;                      /* 0x20 */
 276     U16                     IOCRequestFrameSize;            /* 0x24 */
 277     U16                     Reserved3;                      /* 0x26 */
 278     U16                     MaxInitiators;                  /* 0x28 */
 279     U16                     MaxTargets;                     /* 0x2A */
 280     U16                     MaxSasExpanders;                /* 0x2C */
 281     U16                     MaxEnclosures;                  /* 0x2E */
 282     U16                     ProtocolFlags;                  /* 0x30 */
 283     U16                     HighPriorityCredit;             /* 0x32 */
 284     U16                     MaxReplyDescriptorPostQueueDepth; /* 0x34 */
 285     U8                      ReplyFrameSize;                 /* 0x36 */
 286     U8                      MaxVolumes;                     /* 0x37 */
 287     U16                     MaxDevHandle;                   /* 0x38 */
 288     U16                     MaxPersistentEntries;           /* 0x3A */
 289     U16                     MinDevHandle;                   /* 0x3C */
 290     U16                     Reserved4;                      /* 0x3E */
 291 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
 292   Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
 293
 294 /* MsgVersion */
 295 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
 296 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
 297 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
 298 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
 299
 300 /* HeaderVersion */
 301 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
 302 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
 303 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
 304 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
 305
 306 /* IOCExceptions */
 307 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE     (0x0200)
 308 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
 309
 310 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
 311 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
 312 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
 313 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
 314 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
 315
 316 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
 317 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
 318 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
 319 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
 320 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
 321
 322 /* defines for WhoInit field are after the IOCInit Request */
 323
 324 /* ProductID field uses MPI2_FW_HEADER_PID_ */
 325
 326 /* IOCCapabilities */
 327 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE     (0x00040000)
 328 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
 329 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
 330 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
 331 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
 332 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
 333 #define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
 334 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
 335 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
 336 #define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
 337 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
 338 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
 339 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
 340 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
 341
 342 /* ProtocolFlags */
 343 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
 344 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
 345
 346
 347 /****************************************************************************
 348 *  PortFacts message
 349 ****************************************************************************/
 350
 351 /* PortFacts Request message */
 352 typedef struct _MPI2_PORT_FACTS_REQUEST
 353 {
 354     U16                     Reserved1;                      /* 0x00 */
 355     U8                      ChainOffset;                    /* 0x02 */
 356     U8                      Function;                       /* 0x03 */
 357     U16                     Reserved2;                      /* 0x04 */
 358     U8                      PortNumber;                     /* 0x06 */
 359     U8                      MsgFlags;                       /* 0x07 */
 360     U8                      VP_ID;                          /* 0x08 */
 361     U8                      VF_ID;                          /* 0x09 */
 362     U16                     Reserved3;                      /* 0x0A */
 363 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
 364   Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
 365
 366 /* PortFacts Reply message */
 367 typedef struct _MPI2_PORT_FACTS_REPLY
 368 {
 369     U16                     Reserved1;                      /* 0x00 */
 370     U8                      MsgLength;                      /* 0x02 */
 371     U8                      Function;                       /* 0x03 */
 372     U16                     Reserved2;                      /* 0x04 */
 373     U8                      PortNumber;                     /* 0x06 */
 374     U8                      MsgFlags;                       /* 0x07 */
 375     U8                      VP_ID;                          /* 0x08 */
 376     U8                      VF_ID;                          /* 0x09 */
 377     U16                     Reserved3;                      /* 0x0A */
 378     U16                     Reserved4;                      /* 0x0C */
 379     U16                     IOCStatus;                      /* 0x0E */
 380     U32                     IOCLogInfo;                     /* 0x10 */
 381     U8                      Reserved5;                      /* 0x14 */
 382     U8                      PortType;                       /* 0x15 */
 383     U16                     Reserved6;                      /* 0x16 */
 384     U16                     MaxPostedCmdBuffers;            /* 0x18 */
 385     U16                     Reserved7;                      /* 0x1A */
 386 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
 387   Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
 388
 389 /* PortType values */
 390 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
 391 #define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
 392 #define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
 393 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
 394 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
 395
 396
 397 /****************************************************************************
 398 *  PortEnable message
 399 ****************************************************************************/
 400
 401 /* PortEnable Request message */
 402 typedef struct _MPI2_PORT_ENABLE_REQUEST
 403 {
 404     U16                     Reserved1;                      /* 0x00 */
 405     U8                      ChainOffset;                    /* 0x02 */
 406     U8                      Function;                       /* 0x03 */
 407     U8                      Reserved2;                      /* 0x04 */
 408     U8                      PortFlags;                      /* 0x05 */
 409     U8                      Reserved3;                      /* 0x06 */
 410     U8                      MsgFlags;                       /* 0x07 */
 411     U8                      VP_ID;                          /* 0x08 */
 412     U8                      VF_ID;                          /* 0x09 */
 413     U16                     Reserved4;                      /* 0x0A */
 414 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
 415   Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
 416
 417
 418 /* PortEnable Reply message */
 419 typedef struct _MPI2_PORT_ENABLE_REPLY
 420 {
 421     U16                     Reserved1;                      /* 0x00 */
 422     U8                      MsgLength;                      /* 0x02 */
 423     U8                      Function;                       /* 0x03 */
 424     U8                      Reserved2;                      /* 0x04 */
 425     U8                      PortFlags;                      /* 0x05 */
 426     U8                      Reserved3;                      /* 0x06 */
 427     U8                      MsgFlags;                       /* 0x07 */
 428     U8                      VP_ID;                          /* 0x08 */
 429     U8                      VF_ID;                          /* 0x09 */
 430     U16                     Reserved4;                      /* 0x0A */
 431     U16                     Reserved5;                      /* 0x0C */
 432     U16                     IOCStatus;                      /* 0x0E */
 433     U32                     IOCLogInfo;                     /* 0x10 */
 434 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
 435   Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
 436
 437
 438 /****************************************************************************
 439 *  EventNotification message
 440 ****************************************************************************/
 441
 442 /* EventNotification Request message */
 443 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 444
 445 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
 446 {
 447     U16                     Reserved1;                      /* 0x00 */
 448     U8                      ChainOffset;                    /* 0x02 */
 449     U8                      Function;                       /* 0x03 */
 450     U16                     Reserved2;                      /* 0x04 */
 451     U8                      Reserved3;                      /* 0x06 */
 452     U8                      MsgFlags;                       /* 0x07 */
 453     U8                      VP_ID;                          /* 0x08 */
 454     U8                      VF_ID;                          /* 0x09 */
 455     U16                     Reserved4;                      /* 0x0A */
 456     U32                     Reserved5;                      /* 0x0C */
 457     U32                     Reserved6;                      /* 0x10 */
 458     U32                     EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
 459     U16                     SASBroadcastPrimitiveMasks;     /* 0x24 */
 460          U16                     SASNotifyPrimitiveMasks;        /* 0x26 */
 461     U32                     Reserved8;                      /* 0x28 */
 462 } MPI2_EVENT_NOTIFICATION_REQUEST,
 463   MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
 464   Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
 465
 466
 467 /* EventNotification Reply message */
 468 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
 469 {
 470     U16                     EventDataLength;                /* 0x00 */
 471     U8                      MsgLength;                      /* 0x02 */
 472     U8                      Function;                       /* 0x03 */
 473     U16                     Reserved1;                      /* 0x04 */
 474     U8                      AckRequired;                    /* 0x06 */
 475     U8                      MsgFlags;                       /* 0x07 */
 476     U8                      VP_ID;                          /* 0x08 */
 477     U8                      VF_ID;                          /* 0x09 */
 478     U16                     Reserved2;                      /* 0x0A */
 479     U16                     Reserved3;                      /* 0x0C */
 480     U16                     IOCStatus;                      /* 0x0E */
 481     U32                     IOCLogInfo;                     /* 0x10 */
 482     U16                     Event;                          /* 0x14 */
 483     U16                     Reserved4;                      /* 0x16 */
 484     U32                     EventContext;                   /* 0x18 */
 485     U32                     EventData[1];                   /* 0x1C */
 486 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
 487   Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
 488
 489 /* AckRequired */
 490 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
 491 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
 492
 493 /* Event */
 494 #define MPI2_EVENT_LOG_DATA                         (0x0001)
 495 #define MPI2_EVENT_STATE_CHANGE                     (0x0002)
 496 #define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
 497 #define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
 498 #define MPI2_EVENT_TASK_SET_FULL                    (0x000E) /* obsolete */
 499 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
 500 #define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
 501 #define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
 502 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
 503 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
 504 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
 505 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
 506 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
 507 #define MPI2_EVENT_IR_VOLUME                        (0x001E)
 508 #define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
 509 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
 510 #define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
 511 #define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
 512 #define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
 513 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
 514 #define MPI2_EVENT_SAS_QUIESCE                      (0x0025)
 515 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE             (0x0026)
 516 #define MPI2_EVENT_TEMP_THRESHOLD                   (0x0027)
 517 #define MPI2_EVENT_HOST_MESSAGE                     (0x0028)
 518 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC             (0x006E)
 519 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC             (0x007F)
 520
 521 /* Log Entry Added Event data */
 522
 523 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
 524 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
 525
 526 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
 527 {
 528     U64         TimeStamp;                          /* 0x00 */
 529     U32         Reserved1;                          /* 0x08 */
 530     U16         LogSequence;                        /* 0x0C */
 531     U16         LogEntryQualifier;                  /* 0x0E */
 532     U8          VP_ID;                              /* 0x10 */
 533     U8          VF_ID;                              /* 0x11 */
 534     U16         Reserved2;                          /* 0x12 */
 535     U8          LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
 536 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 537   MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 538   Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
 539
 540 /* GPIO Interrupt Event data */
 541
 542 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
 543     U8          GPIONum;                            /* 0x00 */
 544     U8          Reserved1;                          /* 0x01 */
 545     U16         Reserved2;                          /* 0x02 */
 546 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
 547   MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
 548   Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
 549
 550 /* Temperature Threshold Event data */
 551
 552 typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
 553         U16         Status;                             /* 0x00 */
 554         U8          SensorNum;                          /* 0x02 */
 555         U8          Reserved1;                          /* 0x03 */
 556         U16         CurrentTemperature;                 /* 0x04 */
 557         U16         Reserved2;                          /* 0x06 */
 558         U32         Reserved3;                          /* 0x08 */
 559         U32         Reserved4;                          /* 0x0C */
 560 } MPI2_EVENT_DATA_TEMPERATURE,
 561 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE,
 562 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t;
 563
 564 /* Temperature Threshold Event data Status bits */
 565 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED            (0x0008)
 566 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED            (0x0004)
 567 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED            (0x0002)
 568 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED            (0x0001)
 569
 570
 571 /* Host Message Event data */
 572
 573 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
 574         U8          SourceVF_ID;                        /* 0x00 */
 575         U8          Reserved1;                          /* 0x01 */
 576         U16         Reserved2;                          /* 0x02 */
 577         U32         Reserved3;                          /* 0x04 */
 578         U32         HostData[1];                        /* 0x08 */
 579 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
 580 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
 581
 582
 583 /* Hard Reset Received Event data */
 584
 585 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
 586 {
 587     U8                      Reserved1;                      /* 0x00 */
 588     U8                      Port;                           /* 0x01 */
 589     U16                     Reserved2;                      /* 0x02 */
 590 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 591   MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 592   Mpi2EventDataHardResetReceived_t,
 593   MPI2_POINTER pMpi2EventDataHardResetReceived_t;
 594
 595 /* Task Set Full Event data */
 596 /*   this event is obsolete */
 597
 598 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
 599 {
 600     U16                     DevHandle;                      /* 0x00 */
 601     U16                     CurrentDepth;                   /* 0x02 */
 602 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
 603   Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
 604
 605
 606 /* SAS Device Status Change Event data */
 607
 608 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
 609 {
 610     U16                     TaskTag;                        /* 0x00 */
 611     U8                      ReasonCode;                     /* 0x02 */
 612         U8                      PhysicalPort;                   /* 0x03 */
 613     U8                      ASC;                            /* 0x04 */
 614     U8                      ASCQ;                           /* 0x05 */
 615     U16                     DevHandle;                      /* 0x06 */
 616     U32                     Reserved2;                      /* 0x08 */
 617     U64                     SASAddress;                     /* 0x0C */
 618     U8                      LUN[8];                         /* 0x14 */
 619 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 620   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 621   Mpi2EventDataSasDeviceStatusChange_t,
 622   MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
 623
 624 /* SAS Device Status Change Event data ReasonCode values */
 625 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
 626 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
 627 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
 628 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
 629 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
 630 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
 631 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
 632 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
 633 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
 634 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
 635 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
 636 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
 637 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
 638
 639
 640 /* Integrated RAID Operation Status Event data */
 641
 642 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
 643 {
 644     U16                     VolDevHandle;               /* 0x00 */
 645     U16                     Reserved1;                  /* 0x02 */
 646     U8                      RAIDOperation;              /* 0x04 */
 647     U8                      PercentComplete;            /* 0x05 */
 648     U16                     Reserved2;                  /* 0x06 */
 649         U32                     ElapsedSeconds;             /* 0x08 */
 650 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 651   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 652   Mpi2EventDataIrOperationStatus_t,
 653   MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
 654
 655 /* Integrated RAID Operation Status Event data RAIDOperation values */
 656 #define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
 657 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
 658 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
 659 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
 660 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
 661
 662
 663 /* Integrated RAID Volume Event data */
 664
 665 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
 666 {
 667     U16                     VolDevHandle;               /* 0x00 */
 668     U8                      ReasonCode;                 /* 0x02 */
 669     U8                      Reserved1;                  /* 0x03 */
 670     U32                     NewValue;                   /* 0x04 */
 671     U32                     PreviousValue;              /* 0x08 */
 672 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
 673   Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
 674
 675 /* Integrated RAID Volume Event data ReasonCode values */
 676 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
 677 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
 678 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
 679
 680
 681 /* Integrated RAID Physical Disk Event data */
 682
 683 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
 684 {
 685     U16                     Reserved1;                  /* 0x00 */
 686     U8                      ReasonCode;                 /* 0x02 */
 687     U8                      PhysDiskNum;                /* 0x03 */
 688     U16                     PhysDiskDevHandle;          /* 0x04 */
 689     U16                     Reserved2;                  /* 0x06 */
 690     U16                     Slot;                       /* 0x08 */
 691     U16                     EnclosureHandle;            /* 0x0A */
 692     U32                     NewValue;                   /* 0x0C */
 693     U32                     PreviousValue;              /* 0x10 */
 694 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 695   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 696   Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
 697
 698 /* Integrated RAID Physical Disk Event data ReasonCode values */
 699 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
 700 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
 701 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
 702
 703
 704 /* Integrated RAID Configuration Change List Event data */
 705
 706 /*
 707  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 708  * one and check NumElements at runtime.
 709  */
 710 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
 711 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
 712 #endif
 713
 714 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
 715 {
 716     U16                     ElementFlags;               /* 0x00 */
 717     U16                     VolDevHandle;               /* 0x02 */
 718     U8                      ReasonCode;                 /* 0x04 */
 719     U8                      PhysDiskNum;                /* 0x05 */
 720     U16                     PhysDiskDevHandle;          /* 0x06 */
 721 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
 722   Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
 723
 724 /* IR Configuration Change List Event data ElementFlags values */
 725 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
 726 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
 727 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
 728 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
 729
 730 /* IR Configuration Change List Event data ReasonCode values */
 731 #define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
 732 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
 733 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
 734 #define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
 735 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
 736 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
 737 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
 738 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
 739 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
 740
 741 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
 742 {
 743     U8                              NumElements;        /* 0x00 */
 744     U8                              Reserved1;          /* 0x01 */
 745     U8                              Reserved2;          /* 0x02 */
 746     U8                              ConfigNum;          /* 0x03 */
 747     U32                             Flags;              /* 0x04 */
 748     MPI2_EVENT_IR_CONFIG_ELEMENT    ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];    /* 0x08 */
 749 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 750   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 751   Mpi2EventDataIrConfigChangeList_t,
 752   MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
 753
 754 /* IR Configuration Change List Event data Flags values */
 755 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
 756
 757
 758 /* SAS Discovery Event data */
 759
 760 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
 761 {
 762     U8                      Flags;                      /* 0x00 */
 763     U8                      ReasonCode;                 /* 0x01 */
 764     U8                      PhysicalPort;               /* 0x02 */
 765     U8                      Reserved1;                  /* 0x03 */
 766     U32                     DiscoveryStatus;            /* 0x04 */
 767 } MPI2_EVENT_DATA_SAS_DISCOVERY,
 768   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
 769   Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
 770
 771 /* SAS Discovery Event data Flags values */
 772 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
 773 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
 774
 775 /* SAS Discovery Event data ReasonCode values */
 776 #define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
 777 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
 778
 779 /* SAS Discovery Event data DiscoveryStatus values */
 780 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 781 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
 782 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
 783 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 784 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
 785 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
 786 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
 787 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
 788 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
 789 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
 790 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
 791 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
 792 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
 793 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
 794 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
 795 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
 796 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
 797 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
 798 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
 799 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
 800
 801
 802 /* SAS Broadcast Primitive Event data */
 803
 804 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
 805 {
 806     U8                      PhyNum;                     /* 0x00 */
 807     U8                      Port;                       /* 0x01 */
 808     U8                      PortWidth;                  /* 0x02 */
 809     U8                      Primitive;                  /* 0x03 */
 810 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 811   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 812   Mpi2EventDataSasBroadcastPrimitive_t,
 813   MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
 814
 815 /* defines for the Primitive field */
 816 #define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
 817 #define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
 818 #define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
 819 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
 820 #define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
 821 #define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
 822 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
 823 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
 824
 825 /* SAS Notify Primitive Event data */
 826
 827 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
 828         U8                      PhyNum;                     /* 0x00 */
 829         U8                      Port;                       /* 0x01 */
 830         U8                      Reserved1;                  /* 0x02 */
 831         U8                      Primitive;                  /* 0x03 */
 832 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 833 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 834 Mpi2EventDataSasNotifyPrimitive_t,
 835 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t;
 836
 837 /* defines for the Primitive field */
 838 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP                     (0x01)
 839 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED               (0x02)
 840 #define MPI2_EVENT_NOTIFY_RESERVED1                         (0x03)
 841 #define MPI2_EVENT_NOTIFY_RESERVED2                         (0x04)
 842
 843
 844 /* SAS Initiator Device Status Change Event data */
 845
 846 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
 847 {
 848     U8                      ReasonCode;                 /* 0x00 */
 849     U8                      PhysicalPort;               /* 0x01 */
 850     U16                     DevHandle;                  /* 0x02 */
 851     U64                     SASAddress;                 /* 0x04 */
 852 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 853   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 854   Mpi2EventDataSasInitDevStatusChange_t,
 855   MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
 856
 857 /* SAS Initiator Device Status Change event ReasonCode values */
 858 #define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
 859 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 860
 861
 862 /* SAS Initiator Device Table Overflow Event data */
 863
 864 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
 865 {
 866     U16                     MaxInit;                    /* 0x00 */
 867     U16                     CurrentInit;                /* 0x02 */
 868     U64                     SASAddress;                 /* 0x04 */
 869 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 870   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 871   Mpi2EventDataSasInitTableOverflow_t,
 872   MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
 873
 874
 875 /* SAS Topology Change List Event data */
 876
 877 /*
 878  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 879  * one and check NumEntries at runtime.
 880  */
 881 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
 882 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
 883 #endif
 884
 885 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
 886 {
 887     U16                     AttachedDevHandle;          /* 0x00 */
 888     U8                      LinkRate;                   /* 0x02 */
 889     U8                      PhyStatus;                  /* 0x03 */
 890 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
 891   Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
 892
 893 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
 894 {
 895     U16                             EnclosureHandle;            /* 0x00 */
 896     U16                             ExpanderDevHandle;          /* 0x02 */
 897     U8                              NumPhys;                    /* 0x04 */
 898     U8                              Reserved1;                  /* 0x05 */
 899     U16                             Reserved2;                  /* 0x06 */
 900     U8                              NumEntries;                 /* 0x08 */
 901     U8                              StartPhyNum;                /* 0x09 */
 902     U8                              ExpStatus;                  /* 0x0A */
 903     U8                              PhysicalPort;               /* 0x0B */
 904     MPI2_EVENT_SAS_TOPO_PHY_ENTRY   PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
 905 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 906   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 907   Mpi2EventDataSasTopologyChangeList_t,
 908   MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
 909
 910 /* values for the ExpStatus field */
 911 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
 912 #define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
 913 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
 914 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
 915 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
 916
 917 /* defines for the LinkRate field */
 918 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
 919 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 920 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
 921 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
 922
 923 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
 924 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
 925 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
 926 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
 927 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
 928 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
 929 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
 930 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
 931 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
 932 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
 933
 934 /* values for the PhyStatus field */
 935 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
 936 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
 937 /* values for the PhyStatus ReasonCode sub-field */
 938 #define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
 939 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
 940 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
 941 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
 942 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
 943 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
 944
 945
 946 /* SAS Enclosure Device Status Change Event data */
 947
 948 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
 949 {
 950     U16                     EnclosureHandle;            /* 0x00 */
 951     U8                      ReasonCode;                 /* 0x02 */
 952     U8                      PhysicalPort;               /* 0x03 */
 953     U64                     EnclosureLogicalID;         /* 0x04 */
 954     U16                     NumSlots;                   /* 0x0C */
 955     U16                     StartSlot;                  /* 0x0E */
 956     U32                     PhyBits;                    /* 0x10 */
 957 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 958   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 959   Mpi2EventDataSasEnclDevStatusChange_t,
 960   MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
 961
 962 /* SAS Enclosure Device Status Change event ReasonCode values */
 963 #define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
 964 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
 965
 966
 967 /* SAS PHY Counter Event data */
 968
 969 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
 970     U64         TimeStamp;          /* 0x00 */
 971     U32         Reserved1;          /* 0x08 */
 972     U8          PhyEventCode;       /* 0x0C */
 973     U8          PhyNum;             /* 0x0D */
 974     U16         Reserved2;          /* 0x0E */
 975     U32         PhyEventInfo;       /* 0x10 */
 976     U8          CounterType;        /* 0x14 */
 977     U8          ThresholdWindow;    /* 0x15 */
 978     U8          TimeUnits;          /* 0x16 */
 979     U8          Reserved3;          /* 0x17 */
 980     U32         EventThreshold;     /* 0x18 */
 981     U16         ThresholdFlags;     /* 0x1C */
 982     U16         Reserved4;          /* 0x1E */
 983 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 984   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 985   Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
 986
 987 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the
 988  * PhyEventCode field
 989  * use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the
 990  * CounterType field
 991  * use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the
 992  * TimeUnits field
 993  * use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the
 994  * ThresholdFlags field
 995  * */
 996
 997
 998 /* SAS Quiesce Event data */
 999
1000 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
1001     U8                      ReasonCode;                 /* 0x00 */
1002     U8                      Reserved1;                  /* 0x01 */
1003     U16                     Reserved2;                  /* 0x02 */
1004     U32                     Reserved3;                  /* 0x04 */
1005 } MPI2_EVENT_DATA_SAS_QUIESCE,
1006   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1007   Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
1008
1009 /* SAS Quiesce Event data ReasonCode values */
1010 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED                   (0x01)
1011 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED                 (0x02)
1012
1013
1014 /* Host Based Discovery Phy Event data */
1015
1016 typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1017     U8          Flags;                      /* 0x00 */
1018     U8          NegotiatedLinkRate;         /* 0x01 */
1019     U8          PhyNum;                     /* 0x02 */
1020     U8          PhysicalPort;               /* 0x03 */
1021     U32         Reserved1;                  /* 0x04 */
1022     U8          InitialFrame[28];           /* 0x08 */
1023 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
1024   Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
1025
1026 /* values for the Flags field */
1027 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
1028 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
1029
1030 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for
1031  * the NegotiatedLinkRate field */
1032
1033 typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1034     MPI2_EVENT_HBD_PHY_SAS      Sas;
1035 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1036   Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
1037
1038 typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1039     U8                          DescriptorType;     /* 0x00 */
1040     U8                          Reserved1;          /* 0x01 */
1041     U16                         Reserved2;          /* 0x02 */
1042     U32                         Reserved3;          /* 0x04 */
1043     MPI2_EVENT_HBD_DESCRIPTOR   Descriptor;         /* 0x08 */
1044 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1045   Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1046
1047 /* values for the DescriptorType field */
1048 #define MPI2_EVENT_HBD_DT_SAS               (0x01)
1049
1050
1051
1052 /****************************************************************************
1053 *  EventAck message
1054 ****************************************************************************/
1055
1056 /* EventAck Request message */
1057 typedef struct _MPI2_EVENT_ACK_REQUEST
1058 {
1059     U16                     Reserved1;                      /* 0x00 */
1060     U8                      ChainOffset;                    /* 0x02 */
1061     U8                      Function;                       /* 0x03 */
1062     U16                     Reserved2;                      /* 0x04 */
1063     U8                      Reserved3;                      /* 0x06 */
1064     U8                      MsgFlags;                       /* 0x07 */
1065     U8                      VP_ID;                          /* 0x08 */
1066     U8                      VF_ID;                          /* 0x09 */
1067     U16                     Reserved4;                      /* 0x0A */
1068     U16                     Event;                          /* 0x0C */
1069     U16                     Reserved5;                      /* 0x0E */
1070     U32                     EventContext;                   /* 0x10 */
1071 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
1072   Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
1073
1074
1075 /* EventAck Reply message */
1076 typedef struct _MPI2_EVENT_ACK_REPLY
1077 {
1078     U16                     Reserved1;                      /* 0x00 */
1079     U8                      MsgLength;                      /* 0x02 */
1080     U8                      Function;                       /* 0x03 */
1081     U16                     Reserved2;                      /* 0x04 */
1082     U8                      Reserved3;                      /* 0x06 */
1083     U8                      MsgFlags;                       /* 0x07 */
1084     U8                      VP_ID;                          /* 0x08 */
1085     U8                      VF_ID;                          /* 0x09 */
1086     U16                     Reserved4;                      /* 0x0A */
1087     U16                     Reserved5;                      /* 0x0C */
1088     U16                     IOCStatus;                      /* 0x0E */
1089     U32                     IOCLogInfo;                     /* 0x10 */
1090 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1091   Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1092
1093
1094 /****************************************************************************
1095 *  SendHostMessage message
1096 ****************************************************************************/
1097
1098 /* SendHostMessage Request message */
1099 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1100         U16                     HostDataLength;                 /* 0x00 */
1101         U8                      ChainOffset;                    /* 0x02 */
1102         U8                      Function;                       /* 0x03 */
1103         U16                     Reserved1;                      /* 0x04 */
1104         U8                      Reserved2;                      /* 0x06 */
1105         U8                      MsgFlags;                       /* 0x07 */
1106         U8                      VP_ID;                          /* 0x08 */
1107         U8                      VF_ID;                          /* 0x09 */
1108         U16                     Reserved3;                      /* 0x0A */
1109         U8                      Reserved4;                      /* 0x0C */
1110         U8                      DestVF_ID;                      /* 0x0D */
1111         U16                     Reserved5;                      /* 0x0E */
1112         U32                     Reserved6;                      /* 0x10 */
1113         U32                     Reserved7;                      /* 0x14 */
1114         U32                     Reserved8;                      /* 0x18 */
1115         U32                     Reserved9;                      /* 0x1C */
1116         U32                     Reserved10;                     /* 0x20 */
1117         U32                     HostData[1];                    /* 0x24 */
1118 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1119 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1120 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t;
1121
1122
1123 /* SendHostMessage Reply message */
1124 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1125         U16                     HostDataLength;                 /* 0x00 */
1126         U8                      MsgLength;                      /* 0x02 */
1127         U8                      Function;                       /* 0x03 */
1128         U16                     Reserved1;                      /* 0x04 */
1129         U8                      Reserved2;                      /* 0x06 */
1130         U8                      MsgFlags;                       /* 0x07 */
1131         U8                      VP_ID;                          /* 0x08 */
1132         U8                      VF_ID;                          /* 0x09 */
1133         U16                     Reserved3;                      /* 0x0A */
1134         U16                     Reserved4;                      /* 0x0C */
1135         U16                     IOCStatus;                      /* 0x0E */
1136         U32                     IOCLogInfo;                     /* 0x10 */
1137 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1138 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t;
1139
1140
1141 /****************************************************************************
1142 *  FWDownload message
1143 ****************************************************************************/
1144
1145 /* FWDownload Request message */
1146 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1147 {
1148     U8                      ImageType;                  /* 0x00 */
1149     U8                      Reserved1;                  /* 0x01 */
1150     U8                      ChainOffset;                /* 0x02 */
1151     U8                      Function;                   /* 0x03 */
1152     U16                     Reserved2;                  /* 0x04 */
1153     U8                      Reserved3;                  /* 0x06 */
1154     U8                      MsgFlags;                   /* 0x07 */
1155     U8                      VP_ID;                      /* 0x08 */
1156     U8                      VF_ID;                      /* 0x09 */
1157     U16                     Reserved4;                  /* 0x0A */
1158     U32                     TotalImageSize;             /* 0x0C */
1159     U32                     Reserved5;                  /* 0x10 */
1160     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1161 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1162   Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1163
1164 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
1165
1166 #define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
1167 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
1168 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
1169 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
1170 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
1171 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
1172 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE             (0x0A)
1173 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
1174 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY           (0x0C)
1175 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1176
1177 /* FWDownload TransactionContext Element */
1178 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1179 {
1180     U8                      Reserved1;                  /* 0x00 */
1181     U8                      ContextSize;                /* 0x01 */
1182     U8                      DetailsLength;              /* 0x02 */
1183     U8                      Flags;                      /* 0x03 */
1184     U32                     Reserved2;                  /* 0x04 */
1185     U32                     ImageOffset;                /* 0x08 */
1186     U32                     ImageSize;                  /* 0x0C */
1187 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1188   Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1189
1190 /* FWDownload Reply message */
1191 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1192 {
1193     U8                      ImageType;                  /* 0x00 */
1194     U8                      Reserved1;                  /* 0x01 */
1195     U8                      MsgLength;                  /* 0x02 */
1196     U8                      Function;                   /* 0x03 */
1197     U16                     Reserved2;                  /* 0x04 */
1198     U8                      Reserved3;                  /* 0x06 */
1199     U8                      MsgFlags;                   /* 0x07 */
1200     U8                      VP_ID;                      /* 0x08 */
1201     U8                      VF_ID;                      /* 0x09 */
1202     U16                     Reserved4;                  /* 0x0A */
1203     U16                     Reserved5;                  /* 0x0C */
1204     U16                     IOCStatus;                  /* 0x0E */
1205     U32                     IOCLogInfo;                 /* 0x10 */
1206 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1207   Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1208
1209
1210 /****************************************************************************
1211 *  FWUpload message
1212 ****************************************************************************/
1213
1214 /* FWUpload Request message */
1215 typedef struct _MPI2_FW_UPLOAD_REQUEST
1216 {
1217     U8                      ImageType;                  /* 0x00 */
1218     U8                      Reserved1;                  /* 0x01 */
1219     U8                      ChainOffset;                /* 0x02 */
1220     U8                      Function;                   /* 0x03 */
1221     U16                     Reserved2;                  /* 0x04 */
1222     U8                      Reserved3;                  /* 0x06 */
1223     U8                      MsgFlags;                   /* 0x07 */
1224     U8                      VP_ID;                      /* 0x08 */
1225     U8                      VF_ID;                      /* 0x09 */
1226     U16                     Reserved4;                  /* 0x0A */
1227     U32                     Reserved5;                  /* 0x0C */
1228     U32                     Reserved6;                  /* 0x10 */
1229     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1230 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1231   Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1232
1233 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
1234 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
1235 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
1236 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
1237 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
1238 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
1239 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
1240 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
1241 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
1242 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
1243
1244 typedef struct _MPI2_FW_UPLOAD_TCSGE
1245 {
1246     U8                      Reserved1;                  /* 0x00 */
1247     U8                      ContextSize;                /* 0x01 */
1248     U8                      DetailsLength;              /* 0x02 */
1249     U8                      Flags;                      /* 0x03 */
1250     U32                     Reserved2;                  /* 0x04 */
1251     U32                     ImageOffset;                /* 0x08 */
1252     U32                     ImageSize;                  /* 0x0C */
1253 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1254   Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1255
1256 /* FWUpload Reply message */
1257 typedef struct _MPI2_FW_UPLOAD_REPLY
1258 {
1259     U8                      ImageType;                  /* 0x00 */
1260     U8                      Reserved1;                  /* 0x01 */
1261     U8                      MsgLength;                  /* 0x02 */
1262     U8                      Function;                   /* 0x03 */
1263     U16                     Reserved2;                  /* 0x04 */
1264     U8                      Reserved3;                  /* 0x06 */
1265     U8                      MsgFlags;                   /* 0x07 */
1266     U8                      VP_ID;                      /* 0x08 */
1267     U8                      VF_ID;                      /* 0x09 */
1268     U16                     Reserved4;                  /* 0x0A */
1269     U16                     Reserved5;                  /* 0x0C */
1270     U16                     IOCStatus;                  /* 0x0E */
1271     U32                     IOCLogInfo;                 /* 0x10 */
1272     U32                     ActualImageSize;            /* 0x14 */
1273 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1274   Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1275
1276
1277 /* FW Image Header */
1278 typedef struct _MPI2_FW_IMAGE_HEADER
1279 {
1280     U32                     Signature;                  /* 0x00 */
1281     U32                     Signature0;                 /* 0x04 */
1282     U32                     Signature1;                 /* 0x08 */
1283     U32                     Signature2;                 /* 0x0C */
1284     MPI2_VERSION_UNION      MPIVersion;                 /* 0x10 */
1285     MPI2_VERSION_UNION      FWVersion;                  /* 0x14 */
1286     MPI2_VERSION_UNION      NVDATAVersion;              /* 0x18 */
1287     MPI2_VERSION_UNION      PackageVersion;             /* 0x1C */
1288     U16                     VendorID;                   /* 0x20 */
1289     U16                     ProductID;                  /* 0x22 */
1290     U16                     ProtocolFlags;              /* 0x24 */
1291     U16                     Reserved26;                 /* 0x26 */
1292     U32                     IOCCapabilities;            /* 0x28 */
1293     U32                     ImageSize;                  /* 0x2C */
1294     U32                     NextImageHeaderOffset;      /* 0x30 */
1295     U32                     Checksum;                   /* 0x34 */
1296     U32                     Reserved38;                 /* 0x38 */
1297     U32                     Reserved3C;                 /* 0x3C */
1298     U32                     Reserved40;                 /* 0x40 */
1299     U32                     Reserved44;                 /* 0x44 */
1300     U32                     Reserved48;                 /* 0x48 */
1301     U32                     Reserved4C;                 /* 0x4C */
1302     U32                     Reserved50;                 /* 0x50 */
1303     U32                     Reserved54;                 /* 0x54 */
1304     U32                     Reserved58;                 /* 0x58 */
1305     U32                     Reserved5C;                 /* 0x5C */
1306     U32                     Reserved60;                 /* 0x60 */
1307     U32                     FirmwareVersionNameWhat;    /* 0x64 */
1308     U8                      FirmwareVersionName[32];    /* 0x68 */
1309     U32                     VendorNameWhat;             /* 0x88 */
1310     U8                      VendorName[32];             /* 0x8C */
1311     U32                     PackageNameWhat;            /* 0x88 */
1312     U8                      PackageName[32];            /* 0x8C */
1313     U32                     ReservedD0;                 /* 0xD0 */
1314     U32                     ReservedD4;                 /* 0xD4 */
1315     U32                     ReservedD8;                 /* 0xD8 */
1316     U32                     ReservedDC;                 /* 0xDC */
1317     U32                     ReservedE0;                 /* 0xE0 */
1318     U32                     ReservedE4;                 /* 0xE4 */
1319     U32                     ReservedE8;                 /* 0xE8 */
1320     U32                     ReservedEC;                 /* 0xEC */
1321     U32                     ReservedF0;                 /* 0xF0 */
1322     U32                     ReservedF4;                 /* 0xF4 */
1323     U32                     ReservedF8;                 /* 0xF8 */
1324     U32                     ReservedFC;                 /* 0xFC */
1325 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1326   Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1327
1328 /* Signature field */
1329 #define MPI2_FW_HEADER_SIGNATURE_OFFSET         (0x00)
1330 #define MPI2_FW_HEADER_SIGNATURE_MASK           (0xFF000000)
1331 #define MPI2_FW_HEADER_SIGNATURE                (0xEA000000)
1332
1333 /* Signature0 field */
1334 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET        (0x04)
1335 #define MPI2_FW_HEADER_SIGNATURE0               (0x5AFAA55A)
1336
1337 /* Signature1 field */
1338 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET        (0x08)
1339 #define MPI2_FW_HEADER_SIGNATURE1               (0xA55AFAA5)
1340
1341 /* Signature2 field */
1342 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET        (0x0C)
1343 #define MPI2_FW_HEADER_SIGNATURE2               (0x5AA55AFA)
1344
1345
1346 /* defines for using the ProductID field */
1347 #define MPI2_FW_HEADER_PID_TYPE_MASK            (0xF000)
1348 #define MPI2_FW_HEADER_PID_TYPE_SAS             (0x2000)
1349
1350 #define MPI2_FW_HEADER_PID_PROD_MASK                    (0x0F00)
1351 #define MPI2_FW_HEADER_PID_PROD_A                       (0x0000)
1352 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI   (0x0200)
1353 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI                 (0x0700)
1354
1355
1356 #define MPI2_FW_HEADER_PID_FAMILY_MASK          (0x00FF)
1357 /* SAS */
1358 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS      (0x0013)
1359 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS      (0x0014)
1360
1361 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1362
1363 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1364
1365
1366 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET         (0x2C)
1367 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET         (0x30)
1368 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET         (0x64)
1369
1370 #define MPI2_FW_HEADER_WHAT_SIGNATURE           (0x29232840)
1371
1372 #define MPI2_FW_HEADER_SIZE                     (0x100)
1373
1374
1375 /* Extended Image Header */
1376 typedef struct _MPI2_EXT_IMAGE_HEADER
1377
1378 {
1379     U8                      ImageType;                  /* 0x00 */
1380     U8                      Reserved1;                  /* 0x01 */
1381     U16                     Reserved2;                  /* 0x02 */
1382     U32                     Checksum;                   /* 0x04 */
1383     U32                     ImageSize;                  /* 0x08 */
1384     U32                     NextImageHeaderOffset;      /* 0x0C */
1385     U32                     PackageVersion;             /* 0x10 */
1386     U32                     Reserved3;                  /* 0x14 */
1387     U32                     Reserved4;                  /* 0x18 */
1388     U32                     Reserved5;                  /* 0x1C */
1389     U8                      IdentifyString[32];         /* 0x20 */
1390 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1391   Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1392
1393 /* useful offsets */
1394 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)
1395 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)
1396 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0C)
1397
1398 #define MPI2_EXT_IMAGE_HEADER_SIZE              (0x40)
1399
1400 /* defines for the ImageType field */
1401 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED             (0x00)
1402 #define MPI2_EXT_IMAGE_TYPE_FW                      (0x01)
1403 #define MPI2_EXT_IMAGE_TYPE_NVDATA                  (0x03)
1404 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER              (0x04)
1405 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION          (0x05)
1406 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT            (0x06)
1407 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES       (0x07)
1408 #define MPI2_EXT_IMAGE_TYPE_MEGARAID                (0x08)
1409 #define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH          (0x09)
1410 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC    (0x80)
1411 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC    (0xFF)
1412 #define MPI2_EXT_IMAGE_TYPE_MAX                   \
1413         (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)      /* deprecated */
1414
1415
1416
1417 /* FLASH Layout Extended Image Data */
1418
1419 /*
1420  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1421  * one and check RegionsPerLayout at runtime.
1422  */
1423 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1424 #define MPI2_FLASH_NUMBER_OF_REGIONS        (1)
1425 #endif
1426
1427 /*
1428  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1429  * one and check NumberOfLayouts at runtime.
1430  */
1431 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1432 #define MPI2_FLASH_NUMBER_OF_LAYOUTS        (1)
1433 #endif
1434
1435 typedef struct _MPI2_FLASH_REGION
1436 {
1437     U8                      RegionType;                 /* 0x00 */
1438     U8                      Reserved1;                  /* 0x01 */
1439     U16                     Reserved2;                  /* 0x02 */
1440     U32                     RegionOffset;               /* 0x04 */
1441     U32                     RegionSize;                 /* 0x08 */
1442     U32                     Reserved3;                  /* 0x0C */
1443 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1444   Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1445
1446 typedef struct _MPI2_FLASH_LAYOUT
1447 {
1448     U32                     FlashSize;                  /* 0x00 */
1449     U32                     Reserved1;                  /* 0x04 */
1450     U32                     Reserved2;                  /* 0x08 */
1451     U32                     Reserved3;                  /* 0x0C */
1452     MPI2_FLASH_REGION       Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1453 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1454   Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1455
1456 typedef struct _MPI2_FLASH_LAYOUT_DATA
1457 {
1458     U8                      ImageRevision;              /* 0x00 */
1459     U8                      Reserved1;                  /* 0x01 */
1460     U8                      SizeOfRegion;               /* 0x02 */
1461     U8                      Reserved2;                  /* 0x03 */
1462     U16                     NumberOfLayouts;            /* 0x04 */
1463     U16                     RegionsPerLayout;           /* 0x06 */
1464     U16                     MinimumSectorAlignment;     /* 0x08 */
1465     U16                     Reserved3;                  /* 0x0A */
1466     U32                     Reserved4;                  /* 0x0C */
1467     MPI2_FLASH_LAYOUT       Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1468 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1469   Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1470
1471 /* defines for the RegionType field */
1472 #define MPI2_FLASH_REGION_UNUSED                (0x00)
1473 #define MPI2_FLASH_REGION_FIRMWARE              (0x01)
1474 #define MPI2_FLASH_REGION_BIOS                  (0x02)
1475 #define MPI2_FLASH_REGION_NVDATA                (0x03)
1476 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP       (0x05)
1477 #define MPI2_FLASH_REGION_MFG_INFORMATION       (0x06)
1478 #define MPI2_FLASH_REGION_CONFIG_1              (0x07)
1479 #define MPI2_FLASH_REGION_CONFIG_2              (0x08)
1480 #define MPI2_FLASH_REGION_MEGARAID              (0x09)
1481 #define MPI2_FLASH_REGION_INIT                  (0x0A)
1482
1483 /* ImageRevision */
1484 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION        (0x00)
1485
1486
1487
1488 /* Supported Devices Extended Image Data */
1489
1490 /*
1491  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1492  * one and check NumberOfDevices at runtime.
1493  */
1494 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1495 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES    (1)
1496 #endif
1497
1498 typedef struct _MPI2_SUPPORTED_DEVICE
1499 {
1500     U16                     DeviceID;                   /* 0x00 */
1501     U16                     VendorID;                   /* 0x02 */
1502     U16                     DeviceIDMask;               /* 0x04 */
1503     U16                     Reserved1;                  /* 0x06 */
1504     U8                      LowPCIRev;                  /* 0x08 */
1505     U8                      HighPCIRev;                 /* 0x09 */
1506     U16                     Reserved2;                  /* 0x0A */
1507     U32                     Reserved3;                  /* 0x0C */
1508 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1509   Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1510
1511 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1512 {
1513     U8                      ImageRevision;              /* 0x00 */
1514     U8                      Reserved1;                  /* 0x01 */
1515     U8                      NumberOfDevices;            /* 0x02 */
1516     U8                      Reserved2;                  /* 0x03 */
1517     U32                     Reserved3;                  /* 0x04 */
1518     MPI2_SUPPORTED_DEVICE   SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1519 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1520   Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1521
1522 /* ImageRevision */
1523 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION   (0x00)
1524
1525
1526 /* Init Extended Image Data */
1527
1528 typedef struct _MPI2_INIT_IMAGE_FOOTER
1529
1530 {
1531     U32                     BootFlags;                  /* 0x00 */
1532     U32                     ImageSize;                  /* 0x04 */
1533     U32                     Signature0;                 /* 0x08 */
1534     U32                     Signature1;                 /* 0x0C */
1535     U32                     Signature2;                 /* 0x10 */
1536     U32                     ResetVector;                /* 0x14 */
1537 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1538   Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1539
1540 /* defines for the BootFlags field */
1541 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET        (0x00)
1542
1543 /* defines for the ImageSize field */
1544 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET        (0x04)
1545
1546 /* defines for the Signature0 field */
1547 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET       (0x08)
1548 #define MPI2_INIT_IMAGE_SIGNATURE0              (0x5AA55AEA)
1549
1550 /* defines for the Signature1 field */
1551 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET       (0x0C)
1552 #define MPI2_INIT_IMAGE_SIGNATURE1              (0xA55AEAA5)
1553
1554 /* defines for the Signature2 field */
1555 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET       (0x10)
1556 #define MPI2_INIT_IMAGE_SIGNATURE2              (0x5AEAA55A)
1557
1558 /* Signature fields as individual bytes */
1559 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0        (0xEA)
1560 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1        (0x5A)
1561 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2        (0xA5)
1562 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3        (0x5A)
1563
1564 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4        (0xA5)
1565 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5        (0xEA)
1566 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6        (0x5A)
1567 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7        (0xA5)
1568
1569 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8        (0x5A)
1570 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9        (0xA5)
1571 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A        (0xEA)
1572 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B        (0x5A)
1573
1574 /* defines for the ResetVector field */
1575 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET      (0x14)
1576
1577
1578 /* Encrypted Hash Extended Image Data */
1579
1580 typedef struct _MPI25_ENCRYPTED_HASH_ENTRY {
1581         U8                  HashImageType;          /* 0x00 */
1582         U8                  HashAlgorithm;          /* 0x01 */
1583         U8                  EncryptionAlgorithm;    /* 0x02 */
1584         U8                  Reserved1;              /* 0x03 */
1585         U32                 Reserved2;              /* 0x04 */
1586         U32                 EncryptedHash[1];       /* 0x08 */
1587 } MPI25_ENCRYPTED_HASH_ENTRY, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_ENTRY,
1588 Mpi25EncryptedHashEntry_t, MPI2_POINTER pMpi25EncryptedHashEntry_t;
1589
1590 /* values for HashImageType */
1591 #define MPI25_HASH_IMAGE_TYPE_UNUSED            (0x00)
1592 #define MPI25_HASH_IMAGE_TYPE_FIRMWARE          (0x01)
1593 #define MPI25_HASH_IMAGE_TYPE_BIOS              (0x02)
1594
1595 /* values for HashAlgorithm */
1596 #define MPI25_HASH_ALGORITHM_UNUSED             (0x00)
1597 #define MPI25_HASH_ALGORITHM_SHA256             (0x01)
1598
1599 /* values for EncryptionAlgorithm */
1600 #define MPI25_ENCRYPTION_ALG_UNUSED             (0x00)
1601 #define MPI25_ENCRYPTION_ALG_RSA256             (0x01)
1602
1603 typedef struct _MPI25_ENCRYPTED_HASH_DATA {
1604         U8                              ImageVersion;           /* 0x00 */
1605         U8                              NumHash;                /* 0x01 */
1606         U16                             Reserved1;              /* 0x02 */
1607         U32                             Reserved2;              /* 0x04 */
1608         MPI25_ENCRYPTED_HASH_ENTRY      EncryptedHashEntry[1];  /* 0x08 */
1609 } MPI25_ENCRYPTED_HASH_DATA, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_DATA,
1610 Mpi25EncryptedHashData_t, MPI2_POINTER pMpi25EncryptedHashData_t;
1611
1612 /****************************************************************************
1613 *  PowerManagementControl message
1614 ****************************************************************************/
1615
1616 /* PowerManagementControl Request message */
1617 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1618     U8                      Feature;                    /* 0x00 */
1619     U8                      Reserved1;                  /* 0x01 */
1620     U8                      ChainOffset;                /* 0x02 */
1621     U8                      Function;                   /* 0x03 */
1622     U16                     Reserved2;                  /* 0x04 */
1623     U8                      Reserved3;                  /* 0x06 */
1624     U8                      MsgFlags;                   /* 0x07 */
1625     U8                      VP_ID;                      /* 0x08 */
1626     U8                      VF_ID;                      /* 0x09 */
1627     U16                     Reserved4;                  /* 0x0A */
1628     U8                      Parameter1;                 /* 0x0C */
1629     U8                      Parameter2;                 /* 0x0D */
1630     U8                      Parameter3;                 /* 0x0E */
1631     U8                      Parameter4;                 /* 0x0F */
1632     U32                     Reserved5;                  /* 0x10 */
1633     U32                     Reserved6;                  /* 0x14 */
1634 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1635   Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1636
1637 /* defines for the Feature field */
1638 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND       (0x01)
1639 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION   (0x02)
1640 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK               (0x03) /* obsolete */
1641 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED               (0x04)
1642 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC    (0x80)
1643 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC    (0xFF)
1644
1645 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1646 /* Parameter1 contains a PHY number */
1647 /* Parameter2 indicates power condition action using these defines */
1648 #define MPI2_PM_CONTROL_PARAM2_PARTIAL                  (0x01)
1649 #define MPI2_PM_CONTROL_PARAM2_SLUMBER                  (0x02)
1650 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT            (0x03)
1651 /* Parameter3 and Parameter4 are reserved */
1652
1653 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1654  *  Feature */
1655 /* Parameter1 contains SAS port width modulation group number */
1656 /* Parameter2 indicates IOC action using these defines */
1657 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP        (0x01)
1658 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION        (0x02)
1659 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP     (0x03)
1660 /* Parameter3 indicates desired modulation level using these defines */
1661 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT               (0x00)
1662 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT               (0x01)
1663 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT               (0x02)
1664 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT              (0x03)
1665 /* Parameter4 is reserved */
1666
1667 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1668 /* Parameter1 indicates desired PCIe link speed using these defines */
1669 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS            (0x00) /* obsolete */
1670 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS            (0x01) /* obsolete */
1671 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS            (0x02) /* obsolete */
1672 /* Parameter2 indicates desired PCIe link width using these defines */
1673 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1                 (0x01) /* obsolete */
1674 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2                 (0x02) /* obsolete */
1675 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4                 (0x04) /* obsolete */
1676 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8                 (0x08) /* obsolete */
1677 /* Parameter3 and Parameter4 are reserved */
1678
1679 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1680 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
1681 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED           (0x01)
1682 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED           (0x02)
1683 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED        (0x04)
1684 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED         (0x08)
1685 /* Parameter2, Parameter3, and Parameter4 are reserved */
1686
1687
1688 /* PowerManagementControl Reply message */
1689 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1690     U8                      Feature;                    /* 0x00 */
1691     U8                      Reserved1;                  /* 0x01 */
1692     U8                      MsgLength;                  /* 0x02 */
1693     U8                      Function;                   /* 0x03 */
1694     U16                     Reserved2;                  /* 0x04 */
1695     U8                      Reserved3;                  /* 0x06 */
1696     U8                      MsgFlags;                   /* 0x07 */
1697     U8                      VP_ID;                      /* 0x08 */
1698     U8                      VF_ID;                      /* 0x09 */
1699     U16                     Reserved4;                  /* 0x0A */
1700     U16                     Reserved5;                  /* 0x0C */
1701     U16                     IOCStatus;                  /* 0x0E */
1702     U32                     IOCLogInfo;                 /* 0x10 */
1703 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1704   Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1705
1706
1707 #endif
1708