kernel/drivers/scsi/megaraid/megaraid_sas.h

   1 /*
   2  *  Linux MegaRAID driver for SAS based RAID controllers
   3  *
   4  *  Copyright (c) 2003-2013  LSI Corporation
   5  *  Copyright (c) 2013-2014  Avago Technologies
   6  *
   7  *  This program is free software; you can redistribute it and/or
   8  *  modify it under the terms of the GNU General Public License
   9  *  as published by the Free Software Foundation; either version 2
  10  *  of the License, or (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  FILE: megaraid_sas.h
  21  *
  22  *  Authors: Avago Technologies
  23  *           Kashyap Desai <kashyap.desai@avagotech.com>
  24  *           Sumit Saxena <sumit.saxena@avagotech.com>
  25  *
  26  *  Send feedback to: megaraidlinux.pdl@avagotech.com
  27  *
  28  *  Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
  29  *  San Jose, California 95131
  30  */
  31
  32 #ifndef LSI_MEGARAID_SAS_H
  33 #define LSI_MEGARAID_SAS_H
  34
  35 /*
  36  * MegaRAID SAS Driver meta data
  37  */
  38 #define MEGASAS_VERSION                         "06.808.16.00-rc1"
  39 #define MEGASAS_RELDATE                         "Oct. 8, 2015"
  40
  41 /*
  42  * Device IDs
  43  */
  44 #define PCI_DEVICE_ID_LSI_SAS1078R              0x0060
  45 #define PCI_DEVICE_ID_LSI_SAS1078DE             0x007C
  46 #define PCI_DEVICE_ID_LSI_VERDE_ZCR             0x0413
  47 #define PCI_DEVICE_ID_LSI_SAS1078GEN2           0x0078
  48 #define PCI_DEVICE_ID_LSI_SAS0079GEN2           0x0079
  49 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY         0x0073
  50 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY         0x0071
  51 #define PCI_DEVICE_ID_LSI_FUSION                0x005b
  52 #define PCI_DEVICE_ID_LSI_PLASMA                0x002f
  53 #define PCI_DEVICE_ID_LSI_INVADER               0x005d
  54 #define PCI_DEVICE_ID_LSI_FURY                  0x005f
  55 #define PCI_DEVICE_ID_LSI_INTRUDER              0x00ce
  56 #define PCI_DEVICE_ID_LSI_INTRUDER_24           0x00cf
  57 #define PCI_DEVICE_ID_LSI_CUTLASS_52            0x0052
  58 #define PCI_DEVICE_ID_LSI_CUTLASS_53            0x0053
  59
  60 /*
  61  * Intel HBA SSDIDs
  62  */
  63 #define MEGARAID_INTEL_RS3DC080_SSDID           0x9360
  64 #define MEGARAID_INTEL_RS3DC040_SSDID           0x9362
  65 #define MEGARAID_INTEL_RS3SC008_SSDID           0x9380
  66 #define MEGARAID_INTEL_RS3MC044_SSDID           0x9381
  67 #define MEGARAID_INTEL_RS3WC080_SSDID           0x9341
  68 #define MEGARAID_INTEL_RS3WC040_SSDID           0x9343
  69 #define MEGARAID_INTEL_RMS3BC160_SSDID          0x352B
  70
  71 /*
  72  * Intruder HBA SSDIDs
  73  */
  74 #define MEGARAID_INTRUDER_SSDID1                0x9371
  75 #define MEGARAID_INTRUDER_SSDID2                0x9390
  76 #define MEGARAID_INTRUDER_SSDID3                0x9370
  77
  78 /*
  79  * Intel HBA branding
  80  */
  81 #define MEGARAID_INTEL_RS3DC080_BRANDING        \
  82         "Intel(R) RAID Controller RS3DC080"
  83 #define MEGARAID_INTEL_RS3DC040_BRANDING        \
  84         "Intel(R) RAID Controller RS3DC040"
  85 #define MEGARAID_INTEL_RS3SC008_BRANDING        \
  86         "Intel(R) RAID Controller RS3SC008"
  87 #define MEGARAID_INTEL_RS3MC044_BRANDING        \
  88         "Intel(R) RAID Controller RS3MC044"
  89 #define MEGARAID_INTEL_RS3WC080_BRANDING        \
  90         "Intel(R) RAID Controller RS3WC080"
  91 #define MEGARAID_INTEL_RS3WC040_BRANDING        \
  92         "Intel(R) RAID Controller RS3WC040"
  93 #define MEGARAID_INTEL_RMS3BC160_BRANDING       \
  94         "Intel(R) Integrated RAID Module RMS3BC160"
  95
  96 /*
  97  * =====================================
  98  * MegaRAID SAS MFI firmware definitions
  99  * =====================================
 100  */
 101
 102 /*
 103  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
 104  * protocol between the software and firmware. Commands are issued using
 105  * "message frames"
 106  */
 107
 108 /*
 109  * FW posts its state in upper 4 bits of outbound_msg_0 register
 110  */
 111 #define MFI_STATE_MASK                          0xF0000000
 112 #define MFI_STATE_UNDEFINED                     0x00000000
 113 #define MFI_STATE_BB_INIT                       0x10000000
 114 #define MFI_STATE_FW_INIT                       0x40000000
 115 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
 116 #define MFI_STATE_FW_INIT_2                     0x70000000
 117 #define MFI_STATE_DEVICE_SCAN                   0x80000000
 118 #define MFI_STATE_BOOT_MESSAGE_PENDING          0x90000000
 119 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
 120 #define MFI_STATE_READY                         0xB0000000
 121 #define MFI_STATE_OPERATIONAL                   0xC0000000
 122 #define MFI_STATE_FAULT                         0xF0000000
 123 #define MFI_STATE_FORCE_OCR                     0x00000080
 124 #define MFI_STATE_DMADONE                       0x00000008
 125 #define MFI_STATE_CRASH_DUMP_DONE               0x00000004
 126 #define MFI_RESET_REQUIRED                      0x00000001
 127 #define MFI_RESET_ADAPTER                       0x00000002
 128 #define MEGAMFI_FRAME_SIZE                      64
 129
 130 /*
 131  * During FW init, clear pending cmds & reset state using inbound_msg_0
 132  *
 133  * ABORT        : Abort all pending cmds
 134  * READY        : Move from OPERATIONAL to READY state; discard queue info
 135  * MFIMODE      : Discard (possible) low MFA posted in 64-bit mode (??)
 136  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
 137  * HOTPLUG      : Resume from Hotplug
 138  * MFI_STOP_ADP : Send signal to FW to stop processing
 139  */
 140 #define WRITE_SEQUENCE_OFFSET           (0x0000000FC) /* I20 */
 141 #define HOST_DIAGNOSTIC_OFFSET          (0x000000F8)  /* I20 */
 142 #define DIAG_WRITE_ENABLE                       (0x00000080)
 143 #define DIAG_RESET_ADAPTER                      (0x00000004)
 144
 145 #define MFI_ADP_RESET                           0x00000040
 146 #define MFI_INIT_ABORT                          0x00000001
 147 #define MFI_INIT_READY                          0x00000002
 148 #define MFI_INIT_MFIMODE                        0x00000004
 149 #define MFI_INIT_CLEAR_HANDSHAKE                0x00000008
 150 #define MFI_INIT_HOTPLUG                        0x00000010
 151 #define MFI_STOP_ADP                            0x00000020
 152 #define MFI_RESET_FLAGS                         MFI_INIT_READY| \
 153                                                 MFI_INIT_MFIMODE| \
 154                                                 MFI_INIT_ABORT
 155
 156 /*
 157  * MFI frame flags
 158  */
 159 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
 160 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
 161 #define MFI_FRAME_SGL32                         0x0000
 162 #define MFI_FRAME_SGL64                         0x0002
 163 #define MFI_FRAME_SENSE32                       0x0000
 164 #define MFI_FRAME_SENSE64                       0x0004
 165 #define MFI_FRAME_DIR_NONE                      0x0000
 166 #define MFI_FRAME_DIR_WRITE                     0x0008
 167 #define MFI_FRAME_DIR_READ                      0x0010
 168 #define MFI_FRAME_DIR_BOTH                      0x0018
 169 #define MFI_FRAME_IEEE                          0x0020
 170
 171 /* Driver internal */
 172 #define DRV_DCMD_POLLED_MODE            0x1
 173
 174 /*
 175  * Definition for cmd_status
 176  */
 177 #define MFI_CMD_STATUS_POLL_MODE                0xFF
 178
 179 /*
 180  * MFI command opcodes
 181  */
 182 #define MFI_CMD_INIT                            0x00
 183 #define MFI_CMD_LD_READ                         0x01
 184 #define MFI_CMD_LD_WRITE                        0x02
 185 #define MFI_CMD_LD_SCSI_IO                      0x03
 186 #define MFI_CMD_PD_SCSI_IO                      0x04
 187 #define MFI_CMD_DCMD                            0x05
 188 #define MFI_CMD_ABORT                           0x06
 189 #define MFI_CMD_SMP                             0x07
 190 #define MFI_CMD_STP                             0x08
 191 #define MFI_CMD_INVALID                         0xff
 192
 193 #define MR_DCMD_CTRL_GET_INFO                   0x01010000
 194 #define MR_DCMD_LD_GET_LIST                     0x03010000
 195 #define MR_DCMD_LD_LIST_QUERY                   0x03010100
 196
 197 #define MR_DCMD_CTRL_CACHE_FLUSH                0x01101000
 198 #define MR_FLUSH_CTRL_CACHE                     0x01
 199 #define MR_FLUSH_DISK_CACHE                     0x02
 200
 201 #define MR_DCMD_CTRL_SHUTDOWN                   0x01050000
 202 #define MR_DCMD_HIBERNATE_SHUTDOWN              0x01060000
 203 #define MR_ENABLE_DRIVE_SPINDOWN                0x01
 204
 205 #define MR_DCMD_CTRL_EVENT_GET_INFO             0x01040100
 206 #define MR_DCMD_CTRL_EVENT_GET                  0x01040300
 207 #define MR_DCMD_CTRL_EVENT_WAIT                 0x01040500
 208 #define MR_DCMD_LD_GET_PROPERTIES               0x03030000
 209
 210 #define MR_DCMD_CLUSTER                         0x08000000
 211 #define MR_DCMD_CLUSTER_RESET_ALL               0x08010100
 212 #define MR_DCMD_CLUSTER_RESET_LD                0x08010200
 213 #define MR_DCMD_PD_LIST_QUERY                   0x02010100
 214
 215 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS      0x01190100
 216 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE        (0xF0010000 | 0x0600)
 217
 218 /*
 219  * Global functions
 220  */
 221 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
 222
 223
 224 /*
 225  * MFI command completion codes
 226  */
 227 enum MFI_STAT {
 228         MFI_STAT_OK = 0x00,
 229         MFI_STAT_INVALID_CMD = 0x01,
 230         MFI_STAT_INVALID_DCMD = 0x02,
 231         MFI_STAT_INVALID_PARAMETER = 0x03,
 232         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
 233         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
 234         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
 235         MFI_STAT_APP_IN_USE = 0x07,
 236         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
 237         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
 238         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
 239         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
 240         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
 241         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
 242         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
 243         MFI_STAT_FLASH_BUSY = 0x0f,
 244         MFI_STAT_FLASH_ERROR = 0x10,
 245         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
 246         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
 247         MFI_STAT_FLASH_NOT_OPEN = 0x13,
 248         MFI_STAT_FLASH_NOT_STARTED = 0x14,
 249         MFI_STAT_FLUSH_FAILED = 0x15,
 250         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
 251         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
 252         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
 253         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
 254         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
 255         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
 256         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
 257         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
 258         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
 259         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
 260         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
 261         MFI_STAT_MFC_HW_ERROR = 0x21,
 262         MFI_STAT_NO_HW_PRESENT = 0x22,
 263         MFI_STAT_NOT_FOUND = 0x23,
 264         MFI_STAT_NOT_IN_ENCL = 0x24,
 265         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
 266         MFI_STAT_PD_TYPE_WRONG = 0x26,
 267         MFI_STAT_PR_DISABLED = 0x27,
 268         MFI_STAT_ROW_INDEX_INVALID = 0x28,
 269         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
 270         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
 271         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
 272         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
 273         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
 274         MFI_STAT_SCSI_IO_FAILED = 0x2e,
 275         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
 276         MFI_STAT_SHUTDOWN_FAILED = 0x30,
 277         MFI_STAT_TIME_NOT_SET = 0x31,
 278         MFI_STAT_WRONG_STATE = 0x32,
 279         MFI_STAT_LD_OFFLINE = 0x33,
 280         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
 281         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
 282         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
 283         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
 284         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
 285         MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
 286
 287         MFI_STAT_INVALID_STATUS = 0xFF
 288 };
 289
 290 enum mfi_evt_class {
 291         MFI_EVT_CLASS_DEBUG =           -2,
 292         MFI_EVT_CLASS_PROGRESS =        -1,
 293         MFI_EVT_CLASS_INFO =            0,
 294         MFI_EVT_CLASS_WARNING =         1,
 295         MFI_EVT_CLASS_CRITICAL =        2,
 296         MFI_EVT_CLASS_FATAL =           3,
 297         MFI_EVT_CLASS_DEAD =            4
 298 };
 299
 300 /*
 301  * Crash dump related defines
 302  */
 303 #define MAX_CRASH_DUMP_SIZE 512
 304 #define CRASH_DMA_BUF_SIZE  (1024 * 1024)
 305
 306 enum MR_FW_CRASH_DUMP_STATE {
 307         UNAVAILABLE = 0,
 308         AVAILABLE = 1,
 309         COPYING = 2,
 310         COPIED = 3,
 311         COPY_ERROR = 4,
 312 };
 313
 314 enum _MR_CRASH_BUF_STATUS {
 315         MR_CRASH_BUF_TURN_OFF = 0,
 316         MR_CRASH_BUF_TURN_ON = 1,
 317 };
 318
 319 /*
 320  * Number of mailbox bytes in DCMD message frame
 321  */
 322 #define MFI_MBOX_SIZE                           12
 323
 324 enum MR_EVT_CLASS {
 325
 326         MR_EVT_CLASS_DEBUG = -2,
 327         MR_EVT_CLASS_PROGRESS = -1,
 328         MR_EVT_CLASS_INFO = 0,
 329         MR_EVT_CLASS_WARNING = 1,
 330         MR_EVT_CLASS_CRITICAL = 2,
 331         MR_EVT_CLASS_FATAL = 3,
 332         MR_EVT_CLASS_DEAD = 4,
 333
 334 };
 335
 336 enum MR_EVT_LOCALE {
 337
 338         MR_EVT_LOCALE_LD = 0x0001,
 339         MR_EVT_LOCALE_PD = 0x0002,
 340         MR_EVT_LOCALE_ENCL = 0x0004,
 341         MR_EVT_LOCALE_BBU = 0x0008,
 342         MR_EVT_LOCALE_SAS = 0x0010,
 343         MR_EVT_LOCALE_CTRL = 0x0020,
 344         MR_EVT_LOCALE_CONFIG = 0x0040,
 345         MR_EVT_LOCALE_CLUSTER = 0x0080,
 346         MR_EVT_LOCALE_ALL = 0xffff,
 347
 348 };
 349
 350 enum MR_EVT_ARGS {
 351
 352         MR_EVT_ARGS_NONE,
 353         MR_EVT_ARGS_CDB_SENSE,
 354         MR_EVT_ARGS_LD,
 355         MR_EVT_ARGS_LD_COUNT,
 356         MR_EVT_ARGS_LD_LBA,
 357         MR_EVT_ARGS_LD_OWNER,
 358         MR_EVT_ARGS_LD_LBA_PD_LBA,
 359         MR_EVT_ARGS_LD_PROG,
 360         MR_EVT_ARGS_LD_STATE,
 361         MR_EVT_ARGS_LD_STRIP,
 362         MR_EVT_ARGS_PD,
 363         MR_EVT_ARGS_PD_ERR,
 364         MR_EVT_ARGS_PD_LBA,
 365         MR_EVT_ARGS_PD_LBA_LD,
 366         MR_EVT_ARGS_PD_PROG,
 367         MR_EVT_ARGS_PD_STATE,
 368         MR_EVT_ARGS_PCI,
 369         MR_EVT_ARGS_RATE,
 370         MR_EVT_ARGS_STR,
 371         MR_EVT_ARGS_TIME,
 372         MR_EVT_ARGS_ECC,
 373         MR_EVT_ARGS_LD_PROP,
 374         MR_EVT_ARGS_PD_SPARE,
 375         MR_EVT_ARGS_PD_INDEX,
 376         MR_EVT_ARGS_DIAG_PASS,
 377         MR_EVT_ARGS_DIAG_FAIL,
 378         MR_EVT_ARGS_PD_LBA_LBA,
 379         MR_EVT_ARGS_PORT_PHY,
 380         MR_EVT_ARGS_PD_MISSING,
 381         MR_EVT_ARGS_PD_ADDRESS,
 382         MR_EVT_ARGS_BITMAP,
 383         MR_EVT_ARGS_CONNECTOR,
 384         MR_EVT_ARGS_PD_PD,
 385         MR_EVT_ARGS_PD_FRU,
 386         MR_EVT_ARGS_PD_PATHINFO,
 387         MR_EVT_ARGS_PD_POWER_STATE,
 388         MR_EVT_ARGS_GENERIC,
 389 };
 390
 391
 392 #define SGE_BUFFER_SIZE 4096
 393 /*
 394  * define constants for device list query options
 395  */
 396 enum MR_PD_QUERY_TYPE {
 397         MR_PD_QUERY_TYPE_ALL                = 0,
 398         MR_PD_QUERY_TYPE_STATE              = 1,
 399         MR_PD_QUERY_TYPE_POWER_STATE        = 2,
 400         MR_PD_QUERY_TYPE_MEDIA_TYPE         = 3,
 401         MR_PD_QUERY_TYPE_SPEED              = 4,
 402         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST    = 5,
 403 };
 404
 405 enum MR_LD_QUERY_TYPE {
 406         MR_LD_QUERY_TYPE_ALL             = 0,
 407         MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
 408         MR_LD_QUERY_TYPE_USED_TGT_IDS    = 2,
 409         MR_LD_QUERY_TYPE_CLUSTER_ACCESS  = 3,
 410         MR_LD_QUERY_TYPE_CLUSTER_LOCALE  = 4,
 411 };
 412
 413
 414 #define MR_EVT_CFG_CLEARED                              0x0004
 415 #define MR_EVT_LD_STATE_CHANGE                          0x0051
 416 #define MR_EVT_PD_INSERTED                              0x005b
 417 #define MR_EVT_PD_REMOVED                               0x0070
 418 #define MR_EVT_LD_CREATED                               0x008a
 419 #define MR_EVT_LD_DELETED                               0x008b
 420 #define MR_EVT_FOREIGN_CFG_IMPORTED                     0x00db
 421 #define MR_EVT_LD_OFFLINE                               0x00fc
 422 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
 423 #define MR_EVT_CTRL_PROP_CHANGED                        0x012f
 424
 425 enum MR_PD_STATE {
 426         MR_PD_STATE_UNCONFIGURED_GOOD   = 0x00,
 427         MR_PD_STATE_UNCONFIGURED_BAD    = 0x01,
 428         MR_PD_STATE_HOT_SPARE           = 0x02,
 429         MR_PD_STATE_OFFLINE             = 0x10,
 430         MR_PD_STATE_FAILED              = 0x11,
 431         MR_PD_STATE_REBUILD             = 0x14,
 432         MR_PD_STATE_ONLINE              = 0x18,
 433         MR_PD_STATE_COPYBACK            = 0x20,
 434         MR_PD_STATE_SYSTEM              = 0x40,
 435  };
 436
 437
 438  /*
 439  * defines the physical drive address structure
 440  */
 441 struct MR_PD_ADDRESS {
 442         __le16  deviceId;
 443         u16     enclDeviceId;
 444
 445         union {
 446                 struct {
 447                         u8  enclIndex;
 448                         u8  slotNumber;
 449                 } mrPdAddress;
 450                 struct {
 451                         u8  enclPosition;
 452                         u8  enclConnectorIndex;
 453                 } mrEnclAddress;
 454         };
 455         u8      scsiDevType;
 456         union {
 457                 u8      connectedPortBitmap;
 458                 u8      connectedPortNumbers;
 459         };
 460         u64     sasAddr[2];
 461 } __packed;
 462
 463 /*
 464  * defines the physical drive list structure
 465  */
 466 struct MR_PD_LIST {
 467         __le32          size;
 468         __le32          count;
 469         struct MR_PD_ADDRESS   addr[1];
 470 } __packed;
 471
 472 struct megasas_pd_list {
 473         u16             tid;
 474         u8             driveType;
 475         u8             driveState;
 476 } __packed;
 477
 478  /*
 479  * defines the logical drive reference structure
 480  */
 481 union  MR_LD_REF {
 482         struct {
 483                 u8      targetId;
 484                 u8      reserved;
 485                 __le16     seqNum;
 486         };
 487         __le32     ref;
 488 } __packed;
 489
 490 /*
 491  * defines the logical drive list structure
 492  */
 493 struct MR_LD_LIST {
 494         __le32     ldCount;
 495         __le32     reserved;
 496         struct {
 497                 union MR_LD_REF   ref;
 498                 u8          state;
 499                 u8          reserved[3];
 500                 __le64          size;
 501         } ldList[MAX_LOGICAL_DRIVES_EXT];
 502 } __packed;
 503
 504 struct MR_LD_TARGETID_LIST {
 505         __le32  size;
 506         __le32  count;
 507         u8      pad[3];
 508         u8      targetId[MAX_LOGICAL_DRIVES_EXT];
 509 };
 510
 511
 512 /*
 513  * SAS controller properties
 514  */
 515 struct megasas_ctrl_prop {
 516
 517         u16 seq_num;
 518         u16 pred_fail_poll_interval;
 519         u16 intr_throttle_count;
 520         u16 intr_throttle_timeouts;
 521         u8 rebuild_rate;
 522         u8 patrol_read_rate;
 523         u8 bgi_rate;
 524         u8 cc_rate;
 525         u8 recon_rate;
 526         u8 cache_flush_interval;
 527         u8 spinup_drv_count;
 528         u8 spinup_delay;
 529         u8 cluster_enable;
 530         u8 coercion_mode;
 531         u8 alarm_enable;
 532         u8 disable_auto_rebuild;
 533         u8 disable_battery_warn;
 534         u8 ecc_bucket_size;
 535         u16 ecc_bucket_leak_rate;
 536         u8 restore_hotspare_on_insertion;
 537         u8 expose_encl_devices;
 538         u8 maintainPdFailHistory;
 539         u8 disallowHostRequestReordering;
 540         u8 abortCCOnError;
 541         u8 loadBalanceMode;
 542         u8 disableAutoDetectBackplane;
 543
 544         u8 snapVDSpace;
 545
 546         /*
 547         * Add properties that can be controlled by
 548         * a bit in the following structure.
 549         */
 550         struct {
 551 #if   defined(__BIG_ENDIAN_BITFIELD)
 552                 u32     reserved:18;
 553                 u32     enableJBOD:1;
 554                 u32     disableSpinDownHS:1;
 555                 u32     allowBootWithPinnedCache:1;
 556                 u32     disableOnlineCtrlReset:1;
 557                 u32     enableSecretKeyControl:1;
 558                 u32     autoEnhancedImport:1;
 559                 u32     enableSpinDownUnconfigured:1;
 560                 u32     SSDPatrolReadEnabled:1;
 561                 u32     SSDSMARTerEnabled:1;
 562                 u32     disableNCQ:1;
 563                 u32     useFdeOnly:1;
 564                 u32     prCorrectUnconfiguredAreas:1;
 565                 u32     SMARTerEnabled:1;
 566                 u32     copyBackDisabled:1;
 567 #else
 568                 u32     copyBackDisabled:1;
 569                 u32     SMARTerEnabled:1;
 570                 u32     prCorrectUnconfiguredAreas:1;
 571                 u32     useFdeOnly:1;
 572                 u32     disableNCQ:1;
 573                 u32     SSDSMARTerEnabled:1;
 574                 u32     SSDPatrolReadEnabled:1;
 575                 u32     enableSpinDownUnconfigured:1;
 576                 u32     autoEnhancedImport:1;
 577                 u32     enableSecretKeyControl:1;
 578                 u32     disableOnlineCtrlReset:1;
 579                 u32     allowBootWithPinnedCache:1;
 580                 u32     disableSpinDownHS:1;
 581                 u32     enableJBOD:1;
 582                 u32     reserved:18;
 583 #endif
 584         } OnOffProperties;
 585         u8 autoSnapVDSpace;
 586         u8 viewSpace;
 587         __le16 spinDownTime;
 588         u8  reserved[24];
 589 } __packed;
 590
 591 /*
 592  * SAS controller information
 593  */
 594 struct megasas_ctrl_info {
 595
 596         /*
 597          * PCI device information
 598          */
 599         struct {
 600
 601                 __le16 vendor_id;
 602                 __le16 device_id;
 603                 __le16 sub_vendor_id;
 604                 __le16 sub_device_id;
 605                 u8 reserved[24];
 606
 607         } __attribute__ ((packed)) pci;
 608
 609         /*
 610          * Host interface information
 611          */
 612         struct {
 613
 614                 u8 PCIX:1;
 615                 u8 PCIE:1;
 616                 u8 iSCSI:1;
 617                 u8 SAS_3G:1;
 618                 u8 SRIOV:1;
 619                 u8 reserved_0:3;
 620                 u8 reserved_1[6];
 621                 u8 port_count;
 622                 u64 port_addr[8];
 623
 624         } __attribute__ ((packed)) host_interface;
 625
 626         /*
 627          * Device (backend) interface information
 628          */
 629         struct {
 630
 631                 u8 SPI:1;
 632                 u8 SAS_3G:1;
 633                 u8 SATA_1_5G:1;
 634                 u8 SATA_3G:1;
 635                 u8 reserved_0:4;
 636                 u8 reserved_1[6];
 637                 u8 port_count;
 638                 u64 port_addr[8];
 639
 640         } __attribute__ ((packed)) device_interface;
 641
 642         /*
 643          * List of components residing in flash. All str are null terminated
 644          */
 645         __le32 image_check_word;
 646         __le32 image_component_count;
 647
 648         struct {
 649
 650                 char name[8];
 651                 char version[32];
 652                 char build_date[16];
 653                 char built_time[16];
 654
 655         } __attribute__ ((packed)) image_component[8];
 656
 657         /*
 658          * List of flash components that have been flashed on the card, but
 659          * are not in use, pending reset of the adapter. This list will be
 660          * empty if a flash operation has not occurred. All stings are null
 661          * terminated
 662          */
 663         __le32 pending_image_component_count;
 664
 665         struct {
 666
 667                 char name[8];
 668                 char version[32];
 669                 char build_date[16];
 670                 char build_time[16];
 671
 672         } __attribute__ ((packed)) pending_image_component[8];
 673
 674         u8 max_arms;
 675         u8 max_spans;
 676         u8 max_arrays;
 677         u8 max_lds;
 678
 679         char product_name[80];
 680         char serial_no[32];
 681
 682         /*
 683          * Other physical/controller/operation information. Indicates the
 684          * presence of the hardware
 685          */
 686         struct {
 687
 688                 u32 bbu:1;
 689                 u32 alarm:1;
 690                 u32 nvram:1;
 691                 u32 uart:1;
 692                 u32 reserved:28;
 693
 694         } __attribute__ ((packed)) hw_present;
 695
 696         __le32 current_fw_time;
 697
 698         /*
 699          * Maximum data transfer sizes
 700          */
 701         __le16 max_concurrent_cmds;
 702         __le16 max_sge_count;
 703         __le32 max_request_size;
 704
 705         /*
 706          * Logical and physical device counts
 707          */
 708         __le16 ld_present_count;
 709         __le16 ld_degraded_count;
 710         __le16 ld_offline_count;
 711
 712         __le16 pd_present_count;
 713         __le16 pd_disk_present_count;
 714         __le16 pd_disk_pred_failure_count;
 715         __le16 pd_disk_failed_count;
 716
 717         /*
 718          * Memory size information
 719          */
 720         __le16 nvram_size;
 721         __le16 memory_size;
 722         __le16 flash_size;
 723
 724         /*
 725          * Error counters
 726          */
 727         __le16 mem_correctable_error_count;
 728         __le16 mem_uncorrectable_error_count;
 729
 730         /*
 731          * Cluster information
 732          */
 733         u8 cluster_permitted;
 734         u8 cluster_active;
 735
 736         /*
 737          * Additional max data transfer sizes
 738          */
 739         __le16 max_strips_per_io;
 740
 741         /*
 742          * Controller capabilities structures
 743          */
 744         struct {
 745
 746                 u32 raid_level_0:1;
 747                 u32 raid_level_1:1;
 748                 u32 raid_level_5:1;
 749                 u32 raid_level_1E:1;
 750                 u32 raid_level_6:1;
 751                 u32 reserved:27;
 752
 753         } __attribute__ ((packed)) raid_levels;
 754
 755         struct {
 756
 757                 u32 rbld_rate:1;
 758                 u32 cc_rate:1;
 759                 u32 bgi_rate:1;
 760                 u32 recon_rate:1;
 761                 u32 patrol_rate:1;
 762                 u32 alarm_control:1;
 763                 u32 cluster_supported:1;
 764                 u32 bbu:1;
 765                 u32 spanning_allowed:1;
 766                 u32 dedicated_hotspares:1;
 767                 u32 revertible_hotspares:1;
 768                 u32 foreign_config_import:1;
 769                 u32 self_diagnostic:1;
 770                 u32 mixed_redundancy_arr:1;
 771                 u32 global_hot_spares:1;
 772                 u32 reserved:17;
 773
 774         } __attribute__ ((packed)) adapter_operations;
 775
 776         struct {
 777
 778                 u32 read_policy:1;
 779                 u32 write_policy:1;
 780                 u32 io_policy:1;
 781                 u32 access_policy:1;
 782                 u32 disk_cache_policy:1;
 783                 u32 reserved:27;
 784
 785         } __attribute__ ((packed)) ld_operations;
 786
 787         struct {
 788
 789                 u8 min;
 790                 u8 max;
 791                 u8 reserved[2];
 792
 793         } __attribute__ ((packed)) stripe_sz_ops;
 794
 795         struct {
 796
 797                 u32 force_online:1;
 798                 u32 force_offline:1;
 799                 u32 force_rebuild:1;
 800                 u32 reserved:29;
 801
 802         } __attribute__ ((packed)) pd_operations;
 803
 804         struct {
 805
 806                 u32 ctrl_supports_sas:1;
 807                 u32 ctrl_supports_sata:1;
 808                 u32 allow_mix_in_encl:1;
 809                 u32 allow_mix_in_ld:1;
 810                 u32 allow_sata_in_cluster:1;
 811                 u32 reserved:27;
 812
 813         } __attribute__ ((packed)) pd_mix_support;
 814
 815         /*
 816          * Define ECC single-bit-error bucket information
 817          */
 818         u8 ecc_bucket_count;
 819         u8 reserved_2[11];
 820
 821         /*
 822          * Include the controller properties (changeable items)
 823          */
 824         struct megasas_ctrl_prop properties;
 825
 826         /*
 827          * Define FW pkg version (set in envt v'bles on OEM basis)
 828          */
 829         char package_version[0x60];
 830
 831
 832         /*
 833         * If adapterOperations.supportMoreThan8Phys is set,
 834         * and deviceInterface.portCount is greater than 8,
 835         * SAS Addrs for first 8 ports shall be populated in
 836         * deviceInterface.portAddr, and the rest shall be
 837         * populated in deviceInterfacePortAddr2.
 838         */
 839         __le64      deviceInterfacePortAddr2[8]; /*6a0h */
 840         u8          reserved3[128];              /*6e0h */
 841
 842         struct {                                /*760h */
 843                 u16 minPdRaidLevel_0:4;
 844                 u16 maxPdRaidLevel_0:12;
 845
 846                 u16 minPdRaidLevel_1:4;
 847                 u16 maxPdRaidLevel_1:12;
 848
 849                 u16 minPdRaidLevel_5:4;
 850                 u16 maxPdRaidLevel_5:12;
 851
 852                 u16 minPdRaidLevel_1E:4;
 853                 u16 maxPdRaidLevel_1E:12;
 854
 855                 u16 minPdRaidLevel_6:4;
 856                 u16 maxPdRaidLevel_6:12;
 857
 858                 u16 minPdRaidLevel_10:4;
 859                 u16 maxPdRaidLevel_10:12;
 860
 861                 u16 minPdRaidLevel_50:4;
 862                 u16 maxPdRaidLevel_50:12;
 863
 864                 u16 minPdRaidLevel_60:4;
 865                 u16 maxPdRaidLevel_60:12;
 866
 867                 u16 minPdRaidLevel_1E_RLQ0:4;
 868                 u16 maxPdRaidLevel_1E_RLQ0:12;
 869
 870                 u16 minPdRaidLevel_1E0_RLQ0:4;
 871                 u16 maxPdRaidLevel_1E0_RLQ0:12;
 872
 873                 u16 reserved[6];
 874         } pdsForRaidLevels;
 875
 876         __le16 maxPds;                          /*780h */
 877         __le16 maxDedHSPs;                      /*782h */
 878         __le16 maxGlobalHSP;                    /*784h */
 879         __le16 ddfSize;                         /*786h */
 880         u8  maxLdsPerArray;                     /*788h */
 881         u8  partitionsInDDF;                    /*789h */
 882         u8  lockKeyBinding;                     /*78ah */
 883         u8  maxPITsPerLd;                       /*78bh */
 884         u8  maxViewsPerLd;                      /*78ch */
 885         u8  maxTargetId;                        /*78dh */
 886         __le16 maxBvlVdSize;                    /*78eh */
 887
 888         __le16 maxConfigurableSSCSize;          /*790h */
 889         __le16 currentSSCsize;                  /*792h */
 890
 891         char    expanderFwVersion[12];          /*794h */
 892
 893         __le16 PFKTrialTimeRemaining;           /*7A0h */
 894
 895         __le16 cacheMemorySize;                 /*7A2h */
 896
 897         struct {                                /*7A4h */
 898 #if   defined(__BIG_ENDIAN_BITFIELD)
 899                 u32     reserved:5;
 900                 u32     activePassive:2;
 901                 u32     supportConfigAutoBalance:1;
 902                 u32     mpio:1;
 903                 u32     supportDataLDonSSCArray:1;
 904                 u32     supportPointInTimeProgress:1;
 905                 u32     supportUnevenSpans:1;
 906                 u32     dedicatedHotSparesLimited:1;
 907                 u32     headlessMode:1;
 908                 u32     supportEmulatedDrives:1;
 909                 u32     supportResetNow:1;
 910                 u32     realTimeScheduler:1;
 911                 u32     supportSSDPatrolRead:1;
 912                 u32     supportPerfTuning:1;
 913                 u32     disableOnlinePFKChange:1;
 914                 u32     supportJBOD:1;
 915                 u32     supportBootTimePFKChange:1;
 916                 u32     supportSetLinkSpeed:1;
 917                 u32     supportEmergencySpares:1;
 918                 u32     supportSuspendResumeBGops:1;
 919                 u32     blockSSDWriteCacheChange:1;
 920                 u32     supportShieldState:1;
 921                 u32     supportLdBBMInfo:1;
 922                 u32     supportLdPIType3:1;
 923                 u32     supportLdPIType2:1;
 924                 u32     supportLdPIType1:1;
 925                 u32     supportPIcontroller:1;
 926 #else
 927                 u32     supportPIcontroller:1;
 928                 u32     supportLdPIType1:1;
 929                 u32     supportLdPIType2:1;
 930                 u32     supportLdPIType3:1;
 931                 u32     supportLdBBMInfo:1;
 932                 u32     supportShieldState:1;
 933                 u32     blockSSDWriteCacheChange:1;
 934                 u32     supportSuspendResumeBGops:1;
 935                 u32     supportEmergencySpares:1;
 936                 u32     supportSetLinkSpeed:1;
 937                 u32     supportBootTimePFKChange:1;
 938                 u32     supportJBOD:1;
 939                 u32     disableOnlinePFKChange:1;
 940                 u32     supportPerfTuning:1;
 941                 u32     supportSSDPatrolRead:1;
 942                 u32     realTimeScheduler:1;
 943
 944                 u32     supportResetNow:1;
 945                 u32     supportEmulatedDrives:1;
 946                 u32     headlessMode:1;
 947                 u32     dedicatedHotSparesLimited:1;
 948
 949
 950                 u32     supportUnevenSpans:1;
 951                 u32     supportPointInTimeProgress:1;
 952                 u32     supportDataLDonSSCArray:1;
 953                 u32     mpio:1;
 954                 u32     supportConfigAutoBalance:1;
 955                 u32     activePassive:2;
 956                 u32     reserved:5;
 957 #endif
 958         } adapterOperations2;
 959
 960         u8  driverVersion[32];                  /*7A8h */
 961         u8  maxDAPdCountSpinup60;               /*7C8h */
 962         u8  temperatureROC;                     /*7C9h */
 963         u8  temperatureCtrl;                    /*7CAh */
 964         u8  reserved4;                          /*7CBh */
 965         __le16 maxConfigurablePds;              /*7CCh */
 966
 967
 968         u8  reserved5[2];                       /*0x7CDh */
 969
 970         /*
 971         * HA cluster information
 972         */
 973         struct {
 974 #if defined(__BIG_ENDIAN_BITFIELD)
 975                 u32     reserved:26;
 976                 u32     premiumFeatureMismatch:1;
 977                 u32     ctrlPropIncompatible:1;
 978                 u32     fwVersionMismatch:1;
 979                 u32     hwIncompatible:1;
 980                 u32     peerIsIncompatible:1;
 981                 u32     peerIsPresent:1;
 982 #else
 983                 u32     peerIsPresent:1;
 984                 u32     peerIsIncompatible:1;
 985                 u32     hwIncompatible:1;
 986                 u32     fwVersionMismatch:1;
 987                 u32     ctrlPropIncompatible:1;
 988                 u32     premiumFeatureMismatch:1;
 989                 u32     reserved:26;
 990 #endif
 991         } cluster;
 992
 993         char clusterId[16];                     /*7D4h */
 994         struct {
 995                 u8  maxVFsSupported;            /*0x7E4*/
 996                 u8  numVFsEnabled;              /*0x7E5*/
 997                 u8  requestorId;                /*0x7E6 0:PF, 1:VF1, 2:VF2*/
 998                 u8  reserved;                   /*0x7E7*/
 999         } iov;
1000
1001         struct {
1002 #if defined(__BIG_ENDIAN_BITFIELD)
1003                 u32     reserved:7;
1004                 u32     useSeqNumJbodFP:1;
1005                 u32     supportExtendedSSCSize:1;
1006                 u32     supportDiskCacheSettingForSysPDs:1;
1007                 u32     supportCPLDUpdate:1;
1008                 u32     supportTTYLogCompression:1;
1009                 u32     discardCacheDuringLDDelete:1;
1010                 u32     supportSecurityonJBOD:1;
1011                 u32     supportCacheBypassModes:1;
1012                 u32     supportDisableSESMonitoring:1;
1013                 u32     supportForceFlash:1;
1014                 u32     supportNVDRAM:1;
1015                 u32     supportDrvActivityLEDSetting:1;
1016                 u32     supportAllowedOpsforDrvRemoval:1;
1017                 u32     supportHOQRebuild:1;
1018                 u32     supportForceTo512e:1;
1019                 u32     supportNVCacheErase:1;
1020                 u32     supportDebugQueue:1;
1021                 u32     supportSwZone:1;
1022                 u32     supportCrashDump:1;
1023                 u32     supportMaxExtLDs:1;
1024                 u32     supportT10RebuildAssist:1;
1025                 u32     supportDisableImmediateIO:1;
1026                 u32     supportThermalPollInterval:1;
1027                 u32     supportPersonalityChange:2;
1028 #else
1029                 u32     supportPersonalityChange:2;
1030                 u32     supportThermalPollInterval:1;
1031                 u32     supportDisableImmediateIO:1;
1032                 u32     supportT10RebuildAssist:1;
1033                 u32     supportMaxExtLDs:1;
1034                 u32     supportCrashDump:1;
1035                 u32     supportSwZone:1;
1036                 u32     supportDebugQueue:1;
1037                 u32     supportNVCacheErase:1;
1038                 u32     supportForceTo512e:1;
1039                 u32     supportHOQRebuild:1;
1040                 u32     supportAllowedOpsforDrvRemoval:1;
1041                 u32     supportDrvActivityLEDSetting:1;
1042                 u32     supportNVDRAM:1;
1043                 u32     supportForceFlash:1;
1044                 u32     supportDisableSESMonitoring:1;
1045                 u32     supportCacheBypassModes:1;
1046                 u32     supportSecurityonJBOD:1;
1047                 u32     discardCacheDuringLDDelete:1;
1048                 u32     supportTTYLogCompression:1;
1049                 u32     supportCPLDUpdate:1;
1050                 u32     supportDiskCacheSettingForSysPDs:1;
1051                 u32     supportExtendedSSCSize:1;
1052                 u32     useSeqNumJbodFP:1;
1053                 u32     reserved:7;
1054 #endif
1055         } adapterOperations3;
1056
1057         u8          pad[0x800-0x7EC];
1058 } __packed;
1059
1060 /*
1061  * ===============================
1062  * MegaRAID SAS driver definitions
1063  * ===============================
1064  */
1065 #define MEGASAS_MAX_PD_CHANNELS                 2
1066 #define MEGASAS_MAX_LD_CHANNELS                 2
1067 #define MEGASAS_MAX_CHANNELS                    (MEGASAS_MAX_PD_CHANNELS + \
1068                                                 MEGASAS_MAX_LD_CHANNELS)
1069 #define MEGASAS_MAX_DEV_PER_CHANNEL             128
1070 #define MEGASAS_DEFAULT_INIT_ID                 -1
1071 #define MEGASAS_MAX_LUN                         8
1072 #define MEGASAS_DEFAULT_CMD_PER_LUN             256
1073 #define MEGASAS_MAX_PD                          (MEGASAS_MAX_PD_CHANNELS * \
1074                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1075 #define MEGASAS_MAX_LD_IDS                      (MEGASAS_MAX_LD_CHANNELS * \
1076                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1077
1078 #define MEGASAS_MAX_SECTORS                    (2*1024)
1079 #define MEGASAS_MAX_SECTORS_IEEE                (2*128)
1080 #define MEGASAS_DBG_LVL                         1
1081
1082 #define MEGASAS_FW_BUSY                         1
1083
1084 #define VD_EXT_DEBUG 0
1085
1086 #define SCAN_PD_CHANNEL 0x1
1087 #define SCAN_VD_CHANNEL 0x2
1088
1089 enum MR_SCSI_CMD_TYPE {
1090         READ_WRITE_LDIO = 0,
1091         NON_READ_WRITE_LDIO = 1,
1092         READ_WRITE_SYSPDIO = 2,
1093         NON_READ_WRITE_SYSPDIO = 3,
1094 };
1095
1096 /* Frame Type */
1097 #define IO_FRAME                                0
1098 #define PTHRU_FRAME                             1
1099
1100 /*
1101  * When SCSI mid-layer calls driver's reset routine, driver waits for
1102  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1103  * that the driver cannot _actually_ abort or reset pending commands. While
1104  * it is waiting for the commands to complete, it prints a diagnostic message
1105  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1106  */
1107 #define MEGASAS_RESET_WAIT_TIME                 180
1108 #define MEGASAS_INTERNAL_CMD_WAIT_TIME          180
1109 #define MEGASAS_RESET_NOTICE_INTERVAL           5
1110 #define MEGASAS_IOCTL_CMD                       0
1111 #define MEGASAS_DEFAULT_CMD_TIMEOUT             90
1112 #define MEGASAS_THROTTLE_QUEUE_DEPTH            16
1113 #define MEGASAS_BLOCKED_CMD_TIMEOUT             60
1114 /*
1115  * FW reports the maximum of number of commands that it can accept (maximum
1116  * commands that can be outstanding) at any time. The driver must report a
1117  * lower number to the mid layer because it can issue a few internal commands
1118  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1119  * is shown below
1120  */
1121 #define MEGASAS_INT_CMDS                        32
1122 #define MEGASAS_SKINNY_INT_CMDS                 5
1123 #define MEGASAS_FUSION_INTERNAL_CMDS            5
1124 #define MEGASAS_FUSION_IOCTL_CMDS               3
1125 #define MEGASAS_MFI_IOCTL_CMDS                  27
1126
1127 #define MEGASAS_MAX_MSIX_QUEUES                 128
1128 /*
1129  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1130  * SGLs based on the size of dma_addr_t
1131  */
1132 #define IS_DMA64                                (sizeof(dma_addr_t) == 8)
1133
1134 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT                0x00000001
1135
1136 #define MFI_INTR_FLAG_REPLY_MESSAGE                     0x00000001
1137 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE             0x00000002
1138 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT       0x00000004
1139
1140 #define MFI_OB_INTR_STATUS_MASK                 0x00000002
1141 #define MFI_POLL_TIMEOUT_SECS                   60
1142 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF     (5 * HZ)
1143 #define MEGASAS_OCR_SETTLE_TIME_VF              (1000 * 30)
1144 #define MEGASAS_ROUTINE_WAIT_TIME_VF            300
1145 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
1146 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
1147 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          (0x00000001 | 0x00000004)
1148 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT      0x40000000
1149 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK        (0x00000001)
1150
1151 #define MFI_1068_PCSR_OFFSET                    0x84
1152 #define MFI_1068_FW_HANDSHAKE_OFFSET            0x64
1153 #define MFI_1068_FW_READY                       0xDDDD0000
1154
1155 #define MR_MAX_REPLY_QUEUES_OFFSET              0X0000001F
1156 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET          0X003FC000
1157 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
1158 #define MR_MAX_MSIX_REG_ARRAY                   16
1159 /*
1160 * register set for both 1068 and 1078 controllers
1161 * structure extended for 1078 registers
1162 */
1163
1164 struct megasas_register_set {
1165         u32     doorbell;                       /*0000h*/
1166         u32     fusion_seq_offset;              /*0004h*/
1167         u32     fusion_host_diag;               /*0008h*/
1168         u32     reserved_01;                    /*000Ch*/
1169
1170         u32     inbound_msg_0;                  /*0010h*/
1171         u32     inbound_msg_1;                  /*0014h*/
1172         u32     outbound_msg_0;                 /*0018h*/
1173         u32     outbound_msg_1;                 /*001Ch*/
1174
1175         u32     inbound_doorbell;               /*0020h*/
1176         u32     inbound_intr_status;            /*0024h*/
1177         u32     inbound_intr_mask;              /*0028h*/
1178
1179         u32     outbound_doorbell;              /*002Ch*/
1180         u32     outbound_intr_status;           /*0030h*/
1181         u32     outbound_intr_mask;             /*0034h*/
1182
1183         u32     reserved_1[2];                  /*0038h*/
1184
1185         u32     inbound_queue_port;             /*0040h*/
1186         u32     outbound_queue_port;            /*0044h*/
1187
1188         u32     reserved_2[9];                  /*0048h*/
1189         u32     reply_post_host_index;          /*006Ch*/
1190         u32     reserved_2_2[12];               /*0070h*/
1191
1192         u32     outbound_doorbell_clear;        /*00A0h*/
1193
1194         u32     reserved_3[3];                  /*00A4h*/
1195
1196         u32     outbound_scratch_pad ;          /*00B0h*/
1197         u32     outbound_scratch_pad_2;         /*00B4h*/
1198
1199         u32     reserved_4[2];                  /*00B8h*/
1200
1201         u32     inbound_low_queue_port ;        /*00C0h*/
1202
1203         u32     inbound_high_queue_port ;       /*00C4h*/
1204
1205         u32     reserved_5;                     /*00C8h*/
1206         u32     res_6[11];                      /*CCh*/
1207         u32     host_diag;
1208         u32     seq_offset;
1209         u32     index_registers[807];           /*00CCh*/
1210 } __attribute__ ((packed));
1211
1212 struct megasas_sge32 {
1213
1214         __le32 phys_addr;
1215         __le32 length;
1216
1217 } __attribute__ ((packed));
1218
1219 struct megasas_sge64 {
1220
1221         __le64 phys_addr;
1222         __le32 length;
1223
1224 } __attribute__ ((packed));
1225
1226 struct megasas_sge_skinny {
1227         __le64 phys_addr;
1228         __le32 length;
1229         __le32 flag;
1230 } __packed;
1231
1232 union megasas_sgl {
1233
1234         struct megasas_sge32 sge32[1];
1235         struct megasas_sge64 sge64[1];
1236         struct megasas_sge_skinny sge_skinny[1];
1237
1238 } __attribute__ ((packed));
1239
1240 struct megasas_header {
1241
1242         u8 cmd;                 /*00h */
1243         u8 sense_len;           /*01h */
1244         u8 cmd_status;          /*02h */
1245         u8 scsi_status;         /*03h */
1246
1247         u8 target_id;           /*04h */
1248         u8 lun;                 /*05h */
1249         u8 cdb_len;             /*06h */
1250         u8 sge_count;           /*07h */
1251
1252         __le32 context;         /*08h */
1253         __le32 pad_0;           /*0Ch */
1254
1255         __le16 flags;           /*10h */
1256         __le16 timeout;         /*12h */
1257         __le32 data_xferlen;    /*14h */
1258
1259 } __attribute__ ((packed));
1260
1261 union megasas_sgl_frame {
1262
1263         struct megasas_sge32 sge32[8];
1264         struct megasas_sge64 sge64[5];
1265
1266 } __attribute__ ((packed));
1267
1268 typedef union _MFI_CAPABILITIES {
1269         struct {
1270 #if   defined(__BIG_ENDIAN_BITFIELD)
1271                 u32     reserved:23;
1272                 u32     support_ext_io_size:1;
1273                 u32     support_ext_queue_depth:1;
1274                 u32     security_protocol_cmds_fw:1;
1275                 u32     support_core_affinity:1;
1276                 u32     support_ndrive_r1_lb:1;
1277                 u32     support_max_255lds:1;
1278                 u32     support_fastpath_wb:1;
1279                 u32     support_additional_msix:1;
1280                 u32     support_fp_remote_lun:1;
1281 #else
1282                 u32     support_fp_remote_lun:1;
1283                 u32     support_additional_msix:1;
1284                 u32     support_fastpath_wb:1;
1285                 u32     support_max_255lds:1;
1286                 u32     support_ndrive_r1_lb:1;
1287                 u32     support_core_affinity:1;
1288                 u32     security_protocol_cmds_fw:1;
1289                 u32     support_ext_queue_depth:1;
1290                 u32     support_ext_io_size:1;
1291                 u32     reserved:23;
1292 #endif
1293         } mfi_capabilities;
1294         __le32          reg;
1295 } MFI_CAPABILITIES;
1296
1297 struct megasas_init_frame {
1298
1299         u8 cmd;                 /*00h */
1300         u8 reserved_0;          /*01h */
1301         u8 cmd_status;          /*02h */
1302
1303         u8 reserved_1;          /*03h */
1304         MFI_CAPABILITIES driver_operations; /*04h*/
1305
1306         __le32 context;         /*08h */
1307         __le32 pad_0;           /*0Ch */
1308
1309         __le16 flags;           /*10h */
1310         __le16 reserved_3;              /*12h */
1311         __le32 data_xfer_len;   /*14h */
1312
1313         __le32 queue_info_new_phys_addr_lo;     /*18h */
1314         __le32 queue_info_new_phys_addr_hi;     /*1Ch */
1315         __le32 queue_info_old_phys_addr_lo;     /*20h */
1316         __le32 queue_info_old_phys_addr_hi;     /*24h */
1317         __le32 reserved_4[2];   /*28h */
1318         __le32 system_info_lo;      /*30h */
1319         __le32 system_info_hi;      /*34h */
1320         __le32 reserved_5[2];   /*38h */
1321
1322 } __attribute__ ((packed));
1323
1324 struct megasas_init_queue_info {
1325
1326         __le32 init_flags;              /*00h */
1327         __le32 reply_queue_entries;     /*04h */
1328
1329         __le32 reply_queue_start_phys_addr_lo;  /*08h */
1330         __le32 reply_queue_start_phys_addr_hi;  /*0Ch */
1331         __le32 producer_index_phys_addr_lo;     /*10h */
1332         __le32 producer_index_phys_addr_hi;     /*14h */
1333         __le32 consumer_index_phys_addr_lo;     /*18h */
1334         __le32 consumer_index_phys_addr_hi;     /*1Ch */
1335
1336 } __attribute__ ((packed));
1337
1338 struct megasas_io_frame {
1339
1340         u8 cmd;                 /*00h */
1341         u8 sense_len;           /*01h */
1342         u8 cmd_status;          /*02h */
1343         u8 scsi_status;         /*03h */
1344
1345         u8 target_id;           /*04h */
1346         u8 access_byte;         /*05h */
1347         u8 reserved_0;          /*06h */
1348         u8 sge_count;           /*07h */
1349
1350         __le32 context;         /*08h */
1351         __le32 pad_0;           /*0Ch */
1352
1353         __le16 flags;           /*10h */
1354         __le16 timeout;         /*12h */
1355         __le32 lba_count;       /*14h */
1356
1357         __le32 sense_buf_phys_addr_lo;  /*18h */
1358         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1359
1360         __le32 start_lba_lo;    /*20h */
1361         __le32 start_lba_hi;    /*24h */
1362
1363         union megasas_sgl sgl;  /*28h */
1364
1365 } __attribute__ ((packed));
1366
1367 struct megasas_pthru_frame {
1368
1369         u8 cmd;                 /*00h */
1370         u8 sense_len;           /*01h */
1371         u8 cmd_status;          /*02h */
1372         u8 scsi_status;         /*03h */
1373
1374         u8 target_id;           /*04h */
1375         u8 lun;                 /*05h */
1376         u8 cdb_len;             /*06h */
1377         u8 sge_count;           /*07h */
1378
1379         __le32 context;         /*08h */
1380         __le32 pad_0;           /*0Ch */
1381
1382         __le16 flags;           /*10h */
1383         __le16 timeout;         /*12h */
1384         __le32 data_xfer_len;   /*14h */
1385
1386         __le32 sense_buf_phys_addr_lo;  /*18h */
1387         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1388
1389         u8 cdb[16];             /*20h */
1390         union megasas_sgl sgl;  /*30h */
1391
1392 } __attribute__ ((packed));
1393
1394 struct megasas_dcmd_frame {
1395
1396         u8 cmd;                 /*00h */
1397         u8 reserved_0;          /*01h */
1398         u8 cmd_status;          /*02h */
1399         u8 reserved_1[4];       /*03h */
1400         u8 sge_count;           /*07h */
1401
1402         __le32 context;         /*08h */
1403         __le32 pad_0;           /*0Ch */
1404
1405         __le16 flags;           /*10h */
1406         __le16 timeout;         /*12h */
1407
1408         __le32 data_xfer_len;   /*14h */
1409         __le32 opcode;          /*18h */
1410
1411         union {                 /*1Ch */
1412                 u8 b[12];
1413                 __le16 s[6];
1414                 __le32 w[3];
1415         } mbox;
1416
1417         union megasas_sgl sgl;  /*28h */
1418
1419 } __attribute__ ((packed));
1420
1421 struct megasas_abort_frame {
1422
1423         u8 cmd;                 /*00h */
1424         u8 reserved_0;          /*01h */
1425         u8 cmd_status;          /*02h */
1426
1427         u8 reserved_1;          /*03h */
1428         __le32 reserved_2;      /*04h */
1429
1430         __le32 context;         /*08h */
1431         __le32 pad_0;           /*0Ch */
1432
1433         __le16 flags;           /*10h */
1434         __le16 reserved_3;      /*12h */
1435         __le32 reserved_4;      /*14h */
1436
1437         __le32 abort_context;   /*18h */
1438         __le32 pad_1;           /*1Ch */
1439
1440         __le32 abort_mfi_phys_addr_lo;  /*20h */
1441         __le32 abort_mfi_phys_addr_hi;  /*24h */
1442
1443         __le32 reserved_5[6];   /*28h */
1444
1445 } __attribute__ ((packed));
1446
1447 struct megasas_smp_frame {
1448
1449         u8 cmd;                 /*00h */
1450         u8 reserved_1;          /*01h */
1451         u8 cmd_status;          /*02h */
1452         u8 connection_status;   /*03h */
1453
1454         u8 reserved_2[3];       /*04h */
1455         u8 sge_count;           /*07h */
1456
1457         __le32 context;         /*08h */
1458         __le32 pad_0;           /*0Ch */
1459
1460         __le16 flags;           /*10h */
1461         __le16 timeout;         /*12h */
1462
1463         __le32 data_xfer_len;   /*14h */
1464         __le64 sas_addr;        /*18h */
1465
1466         union {
1467                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: req */
1468                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: req */
1469         } sgl;
1470
1471 } __attribute__ ((packed));
1472
1473 struct megasas_stp_frame {
1474
1475         u8 cmd;                 /*00h */
1476         u8 reserved_1;          /*01h */
1477         u8 cmd_status;          /*02h */
1478         u8 reserved_2;          /*03h */
1479
1480         u8 target_id;           /*04h */
1481         u8 reserved_3[2];       /*05h */
1482         u8 sge_count;           /*07h */
1483
1484         __le32 context;         /*08h */
1485         __le32 pad_0;           /*0Ch */
1486
1487         __le16 flags;           /*10h */
1488         __le16 timeout;         /*12h */
1489
1490         __le32 data_xfer_len;   /*14h */
1491
1492         __le16 fis[10];         /*18h */
1493         __le32 stp_flags;
1494
1495         union {
1496                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: data */
1497                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: data */
1498         } sgl;
1499
1500 } __attribute__ ((packed));
1501
1502 union megasas_frame {
1503
1504         struct megasas_header hdr;
1505         struct megasas_init_frame init;
1506         struct megasas_io_frame io;
1507         struct megasas_pthru_frame pthru;
1508         struct megasas_dcmd_frame dcmd;
1509         struct megasas_abort_frame abort;
1510         struct megasas_smp_frame smp;
1511         struct megasas_stp_frame stp;
1512
1513         u8 raw_bytes[64];
1514 };
1515
1516 struct megasas_cmd;
1517
1518 union megasas_evt_class_locale {
1519
1520         struct {
1521 #ifndef __BIG_ENDIAN_BITFIELD
1522                 u16 locale;
1523                 u8 reserved;
1524                 s8 class;
1525 #else
1526                 s8 class;
1527                 u8 reserved;
1528                 u16 locale;
1529 #endif
1530         } __attribute__ ((packed)) members;
1531
1532         u32 word;
1533
1534 } __attribute__ ((packed));
1535
1536 struct megasas_evt_log_info {
1537         __le32 newest_seq_num;
1538         __le32 oldest_seq_num;
1539         __le32 clear_seq_num;
1540         __le32 shutdown_seq_num;
1541         __le32 boot_seq_num;
1542
1543 } __attribute__ ((packed));
1544
1545 struct megasas_progress {
1546
1547         __le16 progress;
1548         __le16 elapsed_seconds;
1549
1550 } __attribute__ ((packed));
1551
1552 struct megasas_evtarg_ld {
1553
1554         u16 target_id;
1555         u8 ld_index;
1556         u8 reserved;
1557
1558 } __attribute__ ((packed));
1559
1560 struct megasas_evtarg_pd {
1561         u16 device_id;
1562         u8 encl_index;
1563         u8 slot_number;
1564
1565 } __attribute__ ((packed));
1566
1567 struct megasas_evt_detail {
1568
1569         __le32 seq_num;
1570         __le32 time_stamp;
1571         __le32 code;
1572         union megasas_evt_class_locale cl;
1573         u8 arg_type;
1574         u8 reserved1[15];
1575
1576         union {
1577                 struct {
1578                         struct megasas_evtarg_pd pd;
1579                         u8 cdb_length;
1580                         u8 sense_length;
1581                         u8 reserved[2];
1582                         u8 cdb[16];
1583                         u8 sense[64];
1584                 } __attribute__ ((packed)) cdbSense;
1585
1586                 struct megasas_evtarg_ld ld;
1587
1588                 struct {
1589                         struct megasas_evtarg_ld ld;
1590                         __le64 count;
1591                 } __attribute__ ((packed)) ld_count;
1592
1593                 struct {
1594                         __le64 lba;
1595                         struct megasas_evtarg_ld ld;
1596                 } __attribute__ ((packed)) ld_lba;
1597
1598                 struct {
1599                         struct megasas_evtarg_ld ld;
1600                         __le32 prevOwner;
1601                         __le32 newOwner;
1602                 } __attribute__ ((packed)) ld_owner;
1603
1604                 struct {
1605                         u64 ld_lba;
1606                         u64 pd_lba;
1607                         struct megasas_evtarg_ld ld;
1608                         struct megasas_evtarg_pd pd;
1609                 } __attribute__ ((packed)) ld_lba_pd_lba;
1610
1611                 struct {
1612                         struct megasas_evtarg_ld ld;
1613                         struct megasas_progress prog;
1614                 } __attribute__ ((packed)) ld_prog;
1615
1616                 struct {
1617                         struct megasas_evtarg_ld ld;
1618                         u32 prev_state;
1619                         u32 new_state;
1620                 } __attribute__ ((packed)) ld_state;
1621
1622                 struct {
1623                         u64 strip;
1624                         struct megasas_evtarg_ld ld;
1625                 } __attribute__ ((packed)) ld_strip;
1626
1627                 struct megasas_evtarg_pd pd;
1628
1629                 struct {
1630                         struct megasas_evtarg_pd pd;
1631                         u32 err;
1632                 } __attribute__ ((packed)) pd_err;
1633
1634                 struct {
1635                         u64 lba;
1636                         struct megasas_evtarg_pd pd;
1637                 } __attribute__ ((packed)) pd_lba;
1638
1639                 struct {
1640                         u64 lba;
1641                         struct megasas_evtarg_pd pd;
1642                         struct megasas_evtarg_ld ld;
1643                 } __attribute__ ((packed)) pd_lba_ld;
1644
1645                 struct {
1646                         struct megasas_evtarg_pd pd;
1647                         struct megasas_progress prog;
1648                 } __attribute__ ((packed)) pd_prog;
1649
1650                 struct {
1651                         struct megasas_evtarg_pd pd;
1652                         u32 prevState;
1653                         u32 newState;
1654                 } __attribute__ ((packed)) pd_state;
1655
1656                 struct {
1657                         u16 vendorId;
1658                         __le16 deviceId;
1659                         u16 subVendorId;
1660                         u16 subDeviceId;
1661                 } __attribute__ ((packed)) pci;
1662
1663                 u32 rate;
1664                 char str[96];
1665
1666                 struct {
1667                         u32 rtc;
1668                         u32 elapsedSeconds;
1669                 } __attribute__ ((packed)) time;
1670
1671                 struct {
1672                         u32 ecar;
1673                         u32 elog;
1674                         char str[64];
1675                 } __attribute__ ((packed)) ecc;
1676
1677                 u8 b[96];
1678                 __le16 s[48];
1679                 __le32 w[24];
1680                 __le64 d[12];
1681         } args;
1682
1683         char description[128];
1684
1685 } __attribute__ ((packed));
1686
1687 struct megasas_aen_event {
1688         struct delayed_work hotplug_work;
1689         struct megasas_instance *instance;
1690 };
1691
1692 struct megasas_irq_context {
1693         struct megasas_instance *instance;
1694         u32 MSIxIndex;
1695 };
1696
1697 struct MR_DRV_SYSTEM_INFO {
1698         u8      infoVersion;
1699         u8      systemIdLength;
1700         u16     reserved0;
1701         u8      systemId[64];
1702         u8      reserved[1980];
1703 };
1704
1705 struct megasas_instance {
1706
1707         __le32 *producer;
1708         dma_addr_t producer_h;
1709         __le32 *consumer;
1710         dma_addr_t consumer_h;
1711         struct MR_DRV_SYSTEM_INFO *system_info_buf;
1712         dma_addr_t system_info_h;
1713         struct MR_LD_VF_AFFILIATION *vf_affiliation;
1714         dma_addr_t vf_affiliation_h;
1715         struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
1716         dma_addr_t vf_affiliation_111_h;
1717         struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
1718         dma_addr_t hb_host_mem_h;
1719
1720         __le32 *reply_queue;
1721         dma_addr_t reply_queue_h;
1722
1723         u32 *crash_dump_buf;
1724         dma_addr_t crash_dump_h;
1725         void *crash_buf[MAX_CRASH_DUMP_SIZE];
1726         u32 crash_buf_pages;
1727         unsigned int    fw_crash_buffer_size;
1728         unsigned int    fw_crash_state;
1729         unsigned int    fw_crash_buffer_offset;
1730         u32 drv_buf_index;
1731         u32 drv_buf_alloc;
1732         u32 crash_dump_fw_support;
1733         u32 crash_dump_drv_support;
1734         u32 crash_dump_app_support;
1735         u32 secure_jbod_support;
1736         bool use_seqnum_jbod_fp;   /* Added for PD sequence */
1737         spinlock_t crashdump_lock;
1738
1739         struct megasas_register_set __iomem *reg_set;
1740         u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
1741         struct megasas_pd_list          pd_list[MEGASAS_MAX_PD];
1742         struct megasas_pd_list          local_pd_list[MEGASAS_MAX_PD];
1743         u8 ld_ids[MEGASAS_MAX_LD_IDS];
1744         s8 init_id;
1745
1746         u16 max_num_sge;
1747         u16 max_fw_cmds;
1748         u16 max_mfi_cmds;
1749         u16 max_scsi_cmds;
1750         u32 max_sectors_per_req;
1751         struct megasas_aen_event *ev;
1752
1753         struct megasas_cmd **cmd_list;
1754         struct list_head cmd_pool;
1755         /* used to sync fire the cmd to fw */
1756         spinlock_t mfi_pool_lock;
1757         /* used to sync fire the cmd to fw */
1758         spinlock_t hba_lock;
1759         /* used to synch producer, consumer ptrs in dpc */
1760         spinlock_t completion_lock;
1761         struct dma_pool *frame_dma_pool;
1762         struct dma_pool *sense_dma_pool;
1763
1764         struct megasas_evt_detail *evt_detail;
1765         dma_addr_t evt_detail_h;
1766         struct megasas_cmd *aen_cmd;
1767         struct mutex aen_mutex;
1768         struct semaphore ioctl_sem;
1769
1770         struct Scsi_Host *host;
1771
1772         wait_queue_head_t int_cmd_wait_q;
1773         wait_queue_head_t abort_cmd_wait_q;
1774
1775         struct pci_dev *pdev;
1776         u32 unique_id;
1777         u32 fw_support_ieee;
1778
1779         atomic_t fw_outstanding;
1780         atomic_t fw_reset_no_pci_access;
1781
1782         struct megasas_instance_template *instancet;
1783         struct tasklet_struct isr_tasklet;
1784         struct work_struct work_init;
1785         struct work_struct crash_init;
1786
1787         u8 flag;
1788         u8 unload;
1789         u8 flag_ieee;
1790         u8 issuepend_done;
1791         u8 disableOnlineCtrlReset;
1792         u8 UnevenSpanSupport;
1793
1794         u8 supportmax256vd;
1795         u8 allow_fw_scan;
1796         u16 fw_supported_vd_count;
1797         u16 fw_supported_pd_count;
1798
1799         u16 drv_supported_vd_count;
1800         u16 drv_supported_pd_count;
1801
1802         u8 adprecovery;
1803         unsigned long last_time;
1804         u32 mfiStatus;
1805         u32 last_seq_num;
1806
1807         struct list_head internal_reset_pending_q;
1808
1809         /* Ptr to hba specific information */
1810         void *ctrl_context;
1811         u32 ctrl_context_pages;
1812         struct megasas_ctrl_info *ctrl_info;
1813         unsigned int msix_vectors;
1814         struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1815         struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
1816         u64 map_id;
1817         u64 pd_seq_map_id;
1818         struct megasas_cmd *map_update_cmd;
1819         struct megasas_cmd *jbod_seq_cmd;
1820         unsigned long bar;
1821         long reset_flags;
1822         struct mutex reset_mutex;
1823         struct timer_list sriov_heartbeat_timer;
1824         char skip_heartbeat_timer_del;
1825         u8 requestorId;
1826         char PlasmaFW111;
1827         char mpio;
1828         u16 throttlequeuedepth;
1829         u8 mask_interrupts;
1830         u16 max_chain_frame_sz;
1831         u8 is_imr;
1832         bool dev_handle;
1833 };
1834 struct MR_LD_VF_MAP {
1835         u32 size;
1836         union MR_LD_REF ref;
1837         u8 ldVfCount;
1838         u8 reserved[6];
1839         u8 policy[1];
1840 };
1841
1842 struct MR_LD_VF_AFFILIATION {
1843         u32 size;
1844         u8 ldCount;
1845         u8 vfCount;
1846         u8 thisVf;
1847         u8 reserved[9];
1848         struct MR_LD_VF_MAP map[1];
1849 };
1850
1851 /* Plasma 1.11 FW backward compatibility structures */
1852 #define IOV_111_OFFSET 0x7CE
1853 #define MAX_VIRTUAL_FUNCTIONS 8
1854 #define MR_LD_ACCESS_HIDDEN 15
1855
1856 struct IOV_111 {
1857         u8 maxVFsSupported;
1858         u8 numVFsEnabled;
1859         u8 requestorId;
1860         u8 reserved[5];
1861 };
1862
1863 struct MR_LD_VF_MAP_111 {
1864         u8 targetId;
1865         u8 reserved[3];
1866         u8 policy[MAX_VIRTUAL_FUNCTIONS];
1867 };
1868
1869 struct MR_LD_VF_AFFILIATION_111 {
1870         u8 vdCount;
1871         u8 vfCount;
1872         u8 thisVf;
1873         u8 reserved[5];
1874         struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
1875 };
1876
1877 struct MR_CTRL_HB_HOST_MEM {
1878         struct {
1879                 u32 fwCounter;  /* Firmware heart beat counter */
1880                 struct {
1881                         u32 debugmode:1; /* 1=Firmware is in debug mode.
1882                                             Heart beat will not be updated. */
1883                         u32 reserved:31;
1884                 } debug;
1885                 u32 reserved_fw[6];
1886                 u32 driverCounter; /* Driver heart beat counter.  0x20 */
1887                 u32 reserved_driver[7];
1888         } HB;
1889         u8 pad[0x400-0x40];
1890 };
1891
1892 enum {
1893         MEGASAS_HBA_OPERATIONAL                 = 0,
1894         MEGASAS_ADPRESET_SM_INFAULT             = 1,
1895         MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS    = 2,
1896         MEGASAS_ADPRESET_SM_OPERATIONAL         = 3,
1897         MEGASAS_HW_CRITICAL_ERROR               = 4,
1898         MEGASAS_ADPRESET_SM_POLLING             = 5,
1899         MEGASAS_ADPRESET_INPROG_SIGN            = 0xDEADDEAD,
1900 };
1901
1902 struct megasas_instance_template {
1903         void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1904                 u32, struct megasas_register_set __iomem *);
1905
1906         void (*enable_intr)(struct megasas_instance *);
1907         void (*disable_intr)(struct megasas_instance *);
1908
1909         int (*clear_intr)(struct megasas_register_set __iomem *);
1910
1911         u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1912         int (*adp_reset)(struct megasas_instance *, \
1913                 struct megasas_register_set __iomem *);
1914         int (*check_reset)(struct megasas_instance *, \
1915                 struct megasas_register_set __iomem *);
1916         irqreturn_t (*service_isr)(int irq, void *devp);
1917         void (*tasklet)(unsigned long);
1918         u32 (*init_adapter)(struct megasas_instance *);
1919         u32 (*build_and_issue_cmd) (struct megasas_instance *,
1920                                     struct scsi_cmnd *);
1921         void (*issue_dcmd) (struct megasas_instance *instance,
1922                             struct megasas_cmd *cmd);
1923 };
1924
1925 #define MEGASAS_IS_LOGICAL(scp)                                         \
1926         ((scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
1927
1928 #define MEGASAS_DEV_INDEX(scp)                                          \
1929         (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) +   \
1930         scp->device->id)
1931
1932 #define MEGASAS_PD_INDEX(scp)                                           \
1933         ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) +         \
1934         scp->device->id)
1935
1936 struct megasas_cmd {
1937
1938         union megasas_frame *frame;
1939         dma_addr_t frame_phys_addr;
1940         u8 *sense;
1941         dma_addr_t sense_phys_addr;
1942
1943         u32 index;
1944         u8 sync_cmd;
1945         u8 cmd_status_drv;
1946         u8 abort_aen;
1947         u8 retry_for_fw_reset;
1948
1949
1950         struct list_head list;
1951         struct scsi_cmnd *scmd;
1952         u8 flags;
1953
1954         struct megasas_instance *instance;
1955         union {
1956                 struct {
1957                         u16 smid;
1958                         u16 resvd;
1959                 } context;
1960                 u32 frame_count;
1961         };
1962 };
1963
1964 #define MAX_MGMT_ADAPTERS               1024
1965 #define MAX_IOCTL_SGE                   16
1966
1967 struct megasas_iocpacket {
1968
1969         u16 host_no;
1970         u16 __pad1;
1971         u32 sgl_off;
1972         u32 sge_count;
1973         u32 sense_off;
1974         u32 sense_len;
1975         union {
1976                 u8 raw[128];
1977                 struct megasas_header hdr;
1978         } frame;
1979
1980         struct iovec sgl[MAX_IOCTL_SGE];
1981
1982 } __attribute__ ((packed));
1983
1984 struct megasas_aen {
1985         u16 host_no;
1986         u16 __pad1;
1987         u32 seq_num;
1988         u32 class_locale_word;
1989 } __attribute__ ((packed));
1990
1991 #ifdef CONFIG_COMPAT
1992 struct compat_megasas_iocpacket {
1993         u16 host_no;
1994         u16 __pad1;
1995         u32 sgl_off;
1996         u32 sge_count;
1997         u32 sense_off;
1998         u32 sense_len;
1999         union {
2000                 u8 raw[128];
2001                 struct megasas_header hdr;
2002         } frame;
2003         struct compat_iovec sgl[MAX_IOCTL_SGE];
2004 } __attribute__ ((packed));
2005
2006 #define MEGASAS_IOC_FIRMWARE32  _IOWR('M', 1, struct compat_megasas_iocpacket)
2007 #endif
2008
2009 #define MEGASAS_IOC_FIRMWARE    _IOWR('M', 1, struct megasas_iocpacket)
2010 #define MEGASAS_IOC_GET_AEN     _IOW('M', 3, struct megasas_aen)
2011
2012 struct megasas_mgmt_info {
2013
2014         u16 count;
2015         struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2016         int max_index;
2017 };
2018
2019 u8
2020 MR_BuildRaidContext(struct megasas_instance *instance,
2021                     struct IO_REQUEST_INFO *io_info,
2022                     struct RAID_CONTEXT *pRAID_Context,
2023                     struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2024 u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2025 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2026 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2027 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
2028 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
2029 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2030
2031 __le16 get_updated_dev_handle(struct megasas_instance *instance,
2032         struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info);
2033 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2034         struct LD_LOAD_BALANCE_INFO *lbInfo);
2035 int megasas_get_ctrl_info(struct megasas_instance *instance);
2036 /* PD sequence */
2037 int
2038 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
2039 int megasas_set_crash_dump_params(struct megasas_instance *instance,
2040         u8 crash_buf_state);
2041 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2042 void megasas_fusion_crash_dump_wq(struct work_struct *work);
2043
2044 void megasas_return_cmd_fusion(struct megasas_instance *instance,
2045         struct megasas_cmd_fusion *cmd);
2046 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2047         struct megasas_cmd *cmd, int timeout);
2048 void __megasas_return_cmd(struct megasas_instance *instance,
2049         struct megasas_cmd *cmd);
2050
2051 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2052         struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
2053 int megasas_cmd_type(struct scsi_cmnd *cmd);
2054 void megasas_setup_jbod_map(struct megasas_instance *instance);
2055
2056 #endif                          /*LSI_MEGARAID_SAS_H */