kernel/drivers/scsi/megaraid/megaraid_sas.h

   1 /*
   2  *  Linux MegaRAID driver for SAS based RAID controllers
   3  *
   4  *  Copyright (c) 2003-2013  LSI Corporation
   5  *  Copyright (c) 2013-2014  Avago Technologies
   6  *
   7  *  This program is free software; you can redistribute it and/or
   8  *  modify it under the terms of the GNU General Public License
   9  *  as published by the Free Software Foundation; either version 2
  10  *  of the License, or (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  FILE: megaraid_sas.h
  21  *
  22  *  Authors: Avago Technologies
  23  *           Kashyap Desai <kashyap.desai@avagotech.com>
  24  *           Sumit Saxena <sumit.saxena@avagotech.com>
  25  *
  26  *  Send feedback to: megaraidlinux.pdl@avagotech.com
  27  *
  28  *  Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
  29  *  San Jose, California 95131
  30  */
  31
  32 #ifndef LSI_MEGARAID_SAS_H
  33 #define LSI_MEGARAID_SAS_H
  34
  35 /*
  36  * MegaRAID SAS Driver meta data
  37  */
  38 #define MEGASAS_VERSION                         "06.806.08.00-rc1"
  39
  40 /*
  41  * Device IDs
  42  */
  43 #define PCI_DEVICE_ID_LSI_SAS1078R              0x0060
  44 #define PCI_DEVICE_ID_LSI_SAS1078DE             0x007C
  45 #define PCI_DEVICE_ID_LSI_VERDE_ZCR             0x0413
  46 #define PCI_DEVICE_ID_LSI_SAS1078GEN2           0x0078
  47 #define PCI_DEVICE_ID_LSI_SAS0079GEN2           0x0079
  48 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY         0x0073
  49 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY         0x0071
  50 #define PCI_DEVICE_ID_LSI_FUSION                0x005b
  51 #define PCI_DEVICE_ID_LSI_PLASMA                0x002f
  52 #define PCI_DEVICE_ID_LSI_INVADER               0x005d
  53 #define PCI_DEVICE_ID_LSI_FURY                  0x005f
  54
  55 /*
  56  * Intel HBA SSDIDs
  57  */
  58 #define MEGARAID_INTEL_RS3DC080_SSDID           0x9360
  59 #define MEGARAID_INTEL_RS3DC040_SSDID           0x9362
  60 #define MEGARAID_INTEL_RS3SC008_SSDID           0x9380
  61 #define MEGARAID_INTEL_RS3MC044_SSDID           0x9381
  62 #define MEGARAID_INTEL_RS3WC080_SSDID           0x9341
  63 #define MEGARAID_INTEL_RS3WC040_SSDID           0x9343
  64
  65 /*
  66  * Intel HBA branding
  67  */
  68 #define MEGARAID_INTEL_RS3DC080_BRANDING        \
  69         "Intel(R) RAID Controller RS3DC080"
  70 #define MEGARAID_INTEL_RS3DC040_BRANDING        \
  71         "Intel(R) RAID Controller RS3DC040"
  72 #define MEGARAID_INTEL_RS3SC008_BRANDING        \
  73         "Intel(R) RAID Controller RS3SC008"
  74 #define MEGARAID_INTEL_RS3MC044_BRANDING        \
  75         "Intel(R) RAID Controller RS3MC044"
  76 #define MEGARAID_INTEL_RS3WC080_BRANDING        \
  77         "Intel(R) RAID Controller RS3WC080"
  78 #define MEGARAID_INTEL_RS3WC040_BRANDING        \
  79         "Intel(R) RAID Controller RS3WC040"
  80
  81 /*
  82  * =====================================
  83  * MegaRAID SAS MFI firmware definitions
  84  * =====================================
  85  */
  86
  87 /*
  88  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
  89  * protocol between the software and firmware. Commands are issued using
  90  * "message frames"
  91  */
  92
  93 /*
  94  * FW posts its state in upper 4 bits of outbound_msg_0 register
  95  */
  96 #define MFI_STATE_MASK                          0xF0000000
  97 #define MFI_STATE_UNDEFINED                     0x00000000
  98 #define MFI_STATE_BB_INIT                       0x10000000
  99 #define MFI_STATE_FW_INIT                       0x40000000
 100 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
 101 #define MFI_STATE_FW_INIT_2                     0x70000000
 102 #define MFI_STATE_DEVICE_SCAN                   0x80000000
 103 #define MFI_STATE_BOOT_MESSAGE_PENDING          0x90000000
 104 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
 105 #define MFI_STATE_READY                         0xB0000000
 106 #define MFI_STATE_OPERATIONAL                   0xC0000000
 107 #define MFI_STATE_FAULT                         0xF0000000
 108 #define MFI_STATE_FORCE_OCR                     0x00000080
 109 #define MFI_STATE_DMADONE                       0x00000008
 110 #define MFI_STATE_CRASH_DUMP_DONE               0x00000004
 111 #define MFI_RESET_REQUIRED                      0x00000001
 112 #define MFI_RESET_ADAPTER                       0x00000002
 113 #define MEGAMFI_FRAME_SIZE                      64
 114
 115 /*
 116  * During FW init, clear pending cmds & reset state using inbound_msg_0
 117  *
 118  * ABORT        : Abort all pending cmds
 119  * READY        : Move from OPERATIONAL to READY state; discard queue info
 120  * MFIMODE      : Discard (possible) low MFA posted in 64-bit mode (??)
 121  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
 122  * HOTPLUG      : Resume from Hotplug
 123  * MFI_STOP_ADP : Send signal to FW to stop processing
 124  */
 125 #define WRITE_SEQUENCE_OFFSET           (0x0000000FC) /* I20 */
 126 #define HOST_DIAGNOSTIC_OFFSET          (0x000000F8)  /* I20 */
 127 #define DIAG_WRITE_ENABLE                       (0x00000080)
 128 #define DIAG_RESET_ADAPTER                      (0x00000004)
 129
 130 #define MFI_ADP_RESET                           0x00000040
 131 #define MFI_INIT_ABORT                          0x00000001
 132 #define MFI_INIT_READY                          0x00000002
 133 #define MFI_INIT_MFIMODE                        0x00000004
 134 #define MFI_INIT_CLEAR_HANDSHAKE                0x00000008
 135 #define MFI_INIT_HOTPLUG                        0x00000010
 136 #define MFI_STOP_ADP                            0x00000020
 137 #define MFI_RESET_FLAGS                         MFI_INIT_READY| \
 138                                                 MFI_INIT_MFIMODE| \
 139                                                 MFI_INIT_ABORT
 140
 141 /*
 142  * MFI frame flags
 143  */
 144 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
 145 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
 146 #define MFI_FRAME_SGL32                         0x0000
 147 #define MFI_FRAME_SGL64                         0x0002
 148 #define MFI_FRAME_SENSE32                       0x0000
 149 #define MFI_FRAME_SENSE64                       0x0004
 150 #define MFI_FRAME_DIR_NONE                      0x0000
 151 #define MFI_FRAME_DIR_WRITE                     0x0008
 152 #define MFI_FRAME_DIR_READ                      0x0010
 153 #define MFI_FRAME_DIR_BOTH                      0x0018
 154 #define MFI_FRAME_IEEE                          0x0020
 155
 156 /*
 157  * Definition for cmd_status
 158  */
 159 #define MFI_CMD_STATUS_POLL_MODE                0xFF
 160
 161 /*
 162  * MFI command opcodes
 163  */
 164 #define MFI_CMD_INIT                            0x00
 165 #define MFI_CMD_LD_READ                         0x01
 166 #define MFI_CMD_LD_WRITE                        0x02
 167 #define MFI_CMD_LD_SCSI_IO                      0x03
 168 #define MFI_CMD_PD_SCSI_IO                      0x04
 169 #define MFI_CMD_DCMD                            0x05
 170 #define MFI_CMD_ABORT                           0x06
 171 #define MFI_CMD_SMP                             0x07
 172 #define MFI_CMD_STP                             0x08
 173 #define MFI_CMD_INVALID                         0xff
 174
 175 #define MR_DCMD_CTRL_GET_INFO                   0x01010000
 176 #define MR_DCMD_LD_GET_LIST                     0x03010000
 177 #define MR_DCMD_LD_LIST_QUERY                   0x03010100
 178
 179 #define MR_DCMD_CTRL_CACHE_FLUSH                0x01101000
 180 #define MR_FLUSH_CTRL_CACHE                     0x01
 181 #define MR_FLUSH_DISK_CACHE                     0x02
 182
 183 #define MR_DCMD_CTRL_SHUTDOWN                   0x01050000
 184 #define MR_DCMD_HIBERNATE_SHUTDOWN              0x01060000
 185 #define MR_ENABLE_DRIVE_SPINDOWN                0x01
 186
 187 #define MR_DCMD_CTRL_EVENT_GET_INFO             0x01040100
 188 #define MR_DCMD_CTRL_EVENT_GET                  0x01040300
 189 #define MR_DCMD_CTRL_EVENT_WAIT                 0x01040500
 190 #define MR_DCMD_LD_GET_PROPERTIES               0x03030000
 191
 192 #define MR_DCMD_CLUSTER                         0x08000000
 193 #define MR_DCMD_CLUSTER_RESET_ALL               0x08010100
 194 #define MR_DCMD_CLUSTER_RESET_LD                0x08010200
 195 #define MR_DCMD_PD_LIST_QUERY                   0x02010100
 196
 197 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS      0x01190100
 198 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE        (0xF0010000 | 0x0600)
 199
 200 /*
 201  * Global functions
 202  */
 203 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
 204
 205
 206 /*
 207  * MFI command completion codes
 208  */
 209 enum MFI_STAT {
 210         MFI_STAT_OK = 0x00,
 211         MFI_STAT_INVALID_CMD = 0x01,
 212         MFI_STAT_INVALID_DCMD = 0x02,
 213         MFI_STAT_INVALID_PARAMETER = 0x03,
 214         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
 215         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
 216         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
 217         MFI_STAT_APP_IN_USE = 0x07,
 218         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
 219         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
 220         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
 221         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
 222         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
 223         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
 224         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
 225         MFI_STAT_FLASH_BUSY = 0x0f,
 226         MFI_STAT_FLASH_ERROR = 0x10,
 227         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
 228         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
 229         MFI_STAT_FLASH_NOT_OPEN = 0x13,
 230         MFI_STAT_FLASH_NOT_STARTED = 0x14,
 231         MFI_STAT_FLUSH_FAILED = 0x15,
 232         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
 233         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
 234         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
 235         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
 236         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
 237         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
 238         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
 239         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
 240         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
 241         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
 242         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
 243         MFI_STAT_MFC_HW_ERROR = 0x21,
 244         MFI_STAT_NO_HW_PRESENT = 0x22,
 245         MFI_STAT_NOT_FOUND = 0x23,
 246         MFI_STAT_NOT_IN_ENCL = 0x24,
 247         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
 248         MFI_STAT_PD_TYPE_WRONG = 0x26,
 249         MFI_STAT_PR_DISABLED = 0x27,
 250         MFI_STAT_ROW_INDEX_INVALID = 0x28,
 251         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
 252         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
 253         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
 254         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
 255         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
 256         MFI_STAT_SCSI_IO_FAILED = 0x2e,
 257         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
 258         MFI_STAT_SHUTDOWN_FAILED = 0x30,
 259         MFI_STAT_TIME_NOT_SET = 0x31,
 260         MFI_STAT_WRONG_STATE = 0x32,
 261         MFI_STAT_LD_OFFLINE = 0x33,
 262         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
 263         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
 264         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
 265         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
 266         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
 267         MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
 268
 269         MFI_STAT_INVALID_STATUS = 0xFF
 270 };
 271
 272 /*
 273  * Crash dump related defines
 274  */
 275 #define MAX_CRASH_DUMP_SIZE 512
 276 #define CRASH_DMA_BUF_SIZE  (1024 * 1024)
 277
 278 enum MR_FW_CRASH_DUMP_STATE {
 279         UNAVAILABLE = 0,
 280         AVAILABLE = 1,
 281         COPYING = 2,
 282         COPIED = 3,
 283         COPY_ERROR = 4,
 284 };
 285
 286 enum _MR_CRASH_BUF_STATUS {
 287         MR_CRASH_BUF_TURN_OFF = 0,
 288         MR_CRASH_BUF_TURN_ON = 1,
 289 };
 290
 291 /*
 292  * Number of mailbox bytes in DCMD message frame
 293  */
 294 #define MFI_MBOX_SIZE                           12
 295
 296 enum MR_EVT_CLASS {
 297
 298         MR_EVT_CLASS_DEBUG = -2,
 299         MR_EVT_CLASS_PROGRESS = -1,
 300         MR_EVT_CLASS_INFO = 0,
 301         MR_EVT_CLASS_WARNING = 1,
 302         MR_EVT_CLASS_CRITICAL = 2,
 303         MR_EVT_CLASS_FATAL = 3,
 304         MR_EVT_CLASS_DEAD = 4,
 305
 306 };
 307
 308 enum MR_EVT_LOCALE {
 309
 310         MR_EVT_LOCALE_LD = 0x0001,
 311         MR_EVT_LOCALE_PD = 0x0002,
 312         MR_EVT_LOCALE_ENCL = 0x0004,
 313         MR_EVT_LOCALE_BBU = 0x0008,
 314         MR_EVT_LOCALE_SAS = 0x0010,
 315         MR_EVT_LOCALE_CTRL = 0x0020,
 316         MR_EVT_LOCALE_CONFIG = 0x0040,
 317         MR_EVT_LOCALE_CLUSTER = 0x0080,
 318         MR_EVT_LOCALE_ALL = 0xffff,
 319
 320 };
 321
 322 enum MR_EVT_ARGS {
 323
 324         MR_EVT_ARGS_NONE,
 325         MR_EVT_ARGS_CDB_SENSE,
 326         MR_EVT_ARGS_LD,
 327         MR_EVT_ARGS_LD_COUNT,
 328         MR_EVT_ARGS_LD_LBA,
 329         MR_EVT_ARGS_LD_OWNER,
 330         MR_EVT_ARGS_LD_LBA_PD_LBA,
 331         MR_EVT_ARGS_LD_PROG,
 332         MR_EVT_ARGS_LD_STATE,
 333         MR_EVT_ARGS_LD_STRIP,
 334         MR_EVT_ARGS_PD,
 335         MR_EVT_ARGS_PD_ERR,
 336         MR_EVT_ARGS_PD_LBA,
 337         MR_EVT_ARGS_PD_LBA_LD,
 338         MR_EVT_ARGS_PD_PROG,
 339         MR_EVT_ARGS_PD_STATE,
 340         MR_EVT_ARGS_PCI,
 341         MR_EVT_ARGS_RATE,
 342         MR_EVT_ARGS_STR,
 343         MR_EVT_ARGS_TIME,
 344         MR_EVT_ARGS_ECC,
 345         MR_EVT_ARGS_LD_PROP,
 346         MR_EVT_ARGS_PD_SPARE,
 347         MR_EVT_ARGS_PD_INDEX,
 348         MR_EVT_ARGS_DIAG_PASS,
 349         MR_EVT_ARGS_DIAG_FAIL,
 350         MR_EVT_ARGS_PD_LBA_LBA,
 351         MR_EVT_ARGS_PORT_PHY,
 352         MR_EVT_ARGS_PD_MISSING,
 353         MR_EVT_ARGS_PD_ADDRESS,
 354         MR_EVT_ARGS_BITMAP,
 355         MR_EVT_ARGS_CONNECTOR,
 356         MR_EVT_ARGS_PD_PD,
 357         MR_EVT_ARGS_PD_FRU,
 358         MR_EVT_ARGS_PD_PATHINFO,
 359         MR_EVT_ARGS_PD_POWER_STATE,
 360         MR_EVT_ARGS_GENERIC,
 361 };
 362
 363 /*
 364  * define constants for device list query options
 365  */
 366 enum MR_PD_QUERY_TYPE {
 367         MR_PD_QUERY_TYPE_ALL                = 0,
 368         MR_PD_QUERY_TYPE_STATE              = 1,
 369         MR_PD_QUERY_TYPE_POWER_STATE        = 2,
 370         MR_PD_QUERY_TYPE_MEDIA_TYPE         = 3,
 371         MR_PD_QUERY_TYPE_SPEED              = 4,
 372         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST    = 5,
 373 };
 374
 375 enum MR_LD_QUERY_TYPE {
 376         MR_LD_QUERY_TYPE_ALL             = 0,
 377         MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
 378         MR_LD_QUERY_TYPE_USED_TGT_IDS    = 2,
 379         MR_LD_QUERY_TYPE_CLUSTER_ACCESS  = 3,
 380         MR_LD_QUERY_TYPE_CLUSTER_LOCALE  = 4,
 381 };
 382
 383
 384 #define MR_EVT_CFG_CLEARED                              0x0004
 385 #define MR_EVT_LD_STATE_CHANGE                          0x0051
 386 #define MR_EVT_PD_INSERTED                              0x005b
 387 #define MR_EVT_PD_REMOVED                               0x0070
 388 #define MR_EVT_LD_CREATED                               0x008a
 389 #define MR_EVT_LD_DELETED                               0x008b
 390 #define MR_EVT_FOREIGN_CFG_IMPORTED                     0x00db
 391 #define MR_EVT_LD_OFFLINE                               0x00fc
 392 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
 393
 394 enum MR_PD_STATE {
 395         MR_PD_STATE_UNCONFIGURED_GOOD   = 0x00,
 396         MR_PD_STATE_UNCONFIGURED_BAD    = 0x01,
 397         MR_PD_STATE_HOT_SPARE           = 0x02,
 398         MR_PD_STATE_OFFLINE             = 0x10,
 399         MR_PD_STATE_FAILED              = 0x11,
 400         MR_PD_STATE_REBUILD             = 0x14,
 401         MR_PD_STATE_ONLINE              = 0x18,
 402         MR_PD_STATE_COPYBACK            = 0x20,
 403         MR_PD_STATE_SYSTEM              = 0x40,
 404  };
 405
 406
 407  /*
 408  * defines the physical drive address structure
 409  */
 410 struct MR_PD_ADDRESS {
 411         u16     deviceId;
 412         u16     enclDeviceId;
 413
 414         union {
 415                 struct {
 416                         u8  enclIndex;
 417                         u8  slotNumber;
 418                 } mrPdAddress;
 419                 struct {
 420                         u8  enclPosition;
 421                         u8  enclConnectorIndex;
 422                 } mrEnclAddress;
 423         };
 424         u8      scsiDevType;
 425         union {
 426                 u8      connectedPortBitmap;
 427                 u8      connectedPortNumbers;
 428         };
 429         u64     sasAddr[2];
 430 } __packed;
 431
 432 /*
 433  * defines the physical drive list structure
 434  */
 435 struct MR_PD_LIST {
 436         u32             size;
 437         u32             count;
 438         struct MR_PD_ADDRESS   addr[1];
 439 } __packed;
 440
 441 struct megasas_pd_list {
 442         u16             tid;
 443         u8             driveType;
 444         u8             driveState;
 445 } __packed;
 446
 447  /*
 448  * defines the logical drive reference structure
 449  */
 450 union  MR_LD_REF {
 451         struct {
 452                 u8      targetId;
 453                 u8      reserved;
 454                 u16     seqNum;
 455         };
 456         u32     ref;
 457 } __packed;
 458
 459 /*
 460  * defines the logical drive list structure
 461  */
 462 struct MR_LD_LIST {
 463         u32     ldCount;
 464         u32     reserved;
 465         struct {
 466                 union MR_LD_REF   ref;
 467                 u8          state;
 468                 u8          reserved[3];
 469                 u64         size;
 470         } ldList[MAX_LOGICAL_DRIVES_EXT];
 471 } __packed;
 472
 473 struct MR_LD_TARGETID_LIST {
 474         u32     size;
 475         u32     count;
 476         u8      pad[3];
 477         u8      targetId[MAX_LOGICAL_DRIVES_EXT];
 478 };
 479
 480
 481 /*
 482  * SAS controller properties
 483  */
 484 struct megasas_ctrl_prop {
 485
 486         u16 seq_num;
 487         u16 pred_fail_poll_interval;
 488         u16 intr_throttle_count;
 489         u16 intr_throttle_timeouts;
 490         u8 rebuild_rate;
 491         u8 patrol_read_rate;
 492         u8 bgi_rate;
 493         u8 cc_rate;
 494         u8 recon_rate;
 495         u8 cache_flush_interval;
 496         u8 spinup_drv_count;
 497         u8 spinup_delay;
 498         u8 cluster_enable;
 499         u8 coercion_mode;
 500         u8 alarm_enable;
 501         u8 disable_auto_rebuild;
 502         u8 disable_battery_warn;
 503         u8 ecc_bucket_size;
 504         u16 ecc_bucket_leak_rate;
 505         u8 restore_hotspare_on_insertion;
 506         u8 expose_encl_devices;
 507         u8 maintainPdFailHistory;
 508         u8 disallowHostRequestReordering;
 509         u8 abortCCOnError;
 510         u8 loadBalanceMode;
 511         u8 disableAutoDetectBackplane;
 512
 513         u8 snapVDSpace;
 514
 515         /*
 516         * Add properties that can be controlled by
 517         * a bit in the following structure.
 518         */
 519         struct {
 520 #if   defined(__BIG_ENDIAN_BITFIELD)
 521                 u32     reserved:18;
 522                 u32     enableJBOD:1;
 523                 u32     disableSpinDownHS:1;
 524                 u32     allowBootWithPinnedCache:1;
 525                 u32     disableOnlineCtrlReset:1;
 526                 u32     enableSecretKeyControl:1;
 527                 u32     autoEnhancedImport:1;
 528                 u32     enableSpinDownUnconfigured:1;
 529                 u32     SSDPatrolReadEnabled:1;
 530                 u32     SSDSMARTerEnabled:1;
 531                 u32     disableNCQ:1;
 532                 u32     useFdeOnly:1;
 533                 u32     prCorrectUnconfiguredAreas:1;
 534                 u32     SMARTerEnabled:1;
 535                 u32     copyBackDisabled:1;
 536 #else
 537                 u32     copyBackDisabled:1;
 538                 u32     SMARTerEnabled:1;
 539                 u32     prCorrectUnconfiguredAreas:1;
 540                 u32     useFdeOnly:1;
 541                 u32     disableNCQ:1;
 542                 u32     SSDSMARTerEnabled:1;
 543                 u32     SSDPatrolReadEnabled:1;
 544                 u32     enableSpinDownUnconfigured:1;
 545                 u32     autoEnhancedImport:1;
 546                 u32     enableSecretKeyControl:1;
 547                 u32     disableOnlineCtrlReset:1;
 548                 u32     allowBootWithPinnedCache:1;
 549                 u32     disableSpinDownHS:1;
 550                 u32     enableJBOD:1;
 551                 u32     reserved:18;
 552 #endif
 553         } OnOffProperties;
 554         u8 autoSnapVDSpace;
 555         u8 viewSpace;
 556         u16 spinDownTime;
 557         u8  reserved[24];
 558 } __packed;
 559
 560 /*
 561  * SAS controller information
 562  */
 563 struct megasas_ctrl_info {
 564
 565         /*
 566          * PCI device information
 567          */
 568         struct {
 569
 570                 u16 vendor_id;
 571                 u16 device_id;
 572                 u16 sub_vendor_id;
 573                 u16 sub_device_id;
 574                 u8 reserved[24];
 575
 576         } __attribute__ ((packed)) pci;
 577
 578         /*
 579          * Host interface information
 580          */
 581         struct {
 582
 583                 u8 PCIX:1;
 584                 u8 PCIE:1;
 585                 u8 iSCSI:1;
 586                 u8 SAS_3G:1;
 587                 u8 SRIOV:1;
 588                 u8 reserved_0:3;
 589                 u8 reserved_1[6];
 590                 u8 port_count;
 591                 u64 port_addr[8];
 592
 593         } __attribute__ ((packed)) host_interface;
 594
 595         /*
 596          * Device (backend) interface information
 597          */
 598         struct {
 599
 600                 u8 SPI:1;
 601                 u8 SAS_3G:1;
 602                 u8 SATA_1_5G:1;
 603                 u8 SATA_3G:1;
 604                 u8 reserved_0:4;
 605                 u8 reserved_1[6];
 606                 u8 port_count;
 607                 u64 port_addr[8];
 608
 609         } __attribute__ ((packed)) device_interface;
 610
 611         /*
 612          * List of components residing in flash. All str are null terminated
 613          */
 614         u32 image_check_word;
 615         u32 image_component_count;
 616
 617         struct {
 618
 619                 char name[8];
 620                 char version[32];
 621                 char build_date[16];
 622                 char built_time[16];
 623
 624         } __attribute__ ((packed)) image_component[8];
 625
 626         /*
 627          * List of flash components that have been flashed on the card, but
 628          * are not in use, pending reset of the adapter. This list will be
 629          * empty if a flash operation has not occurred. All stings are null
 630          * terminated
 631          */
 632         u32 pending_image_component_count;
 633
 634         struct {
 635
 636                 char name[8];
 637                 char version[32];
 638                 char build_date[16];
 639                 char build_time[16];
 640
 641         } __attribute__ ((packed)) pending_image_component[8];
 642
 643         u8 max_arms;
 644         u8 max_spans;
 645         u8 max_arrays;
 646         u8 max_lds;
 647
 648         char product_name[80];
 649         char serial_no[32];
 650
 651         /*
 652          * Other physical/controller/operation information. Indicates the
 653          * presence of the hardware
 654          */
 655         struct {
 656
 657                 u32 bbu:1;
 658                 u32 alarm:1;
 659                 u32 nvram:1;
 660                 u32 uart:1;
 661                 u32 reserved:28;
 662
 663         } __attribute__ ((packed)) hw_present;
 664
 665         u32 current_fw_time;
 666
 667         /*
 668          * Maximum data transfer sizes
 669          */
 670         u16 max_concurrent_cmds;
 671         u16 max_sge_count;
 672         u32 max_request_size;
 673
 674         /*
 675          * Logical and physical device counts
 676          */
 677         u16 ld_present_count;
 678         u16 ld_degraded_count;
 679         u16 ld_offline_count;
 680
 681         u16 pd_present_count;
 682         u16 pd_disk_present_count;
 683         u16 pd_disk_pred_failure_count;
 684         u16 pd_disk_failed_count;
 685
 686         /*
 687          * Memory size information
 688          */
 689         u16 nvram_size;
 690         u16 memory_size;
 691         u16 flash_size;
 692
 693         /*
 694          * Error counters
 695          */
 696         u16 mem_correctable_error_count;
 697         u16 mem_uncorrectable_error_count;
 698
 699         /*
 700          * Cluster information
 701          */
 702         u8 cluster_permitted;
 703         u8 cluster_active;
 704
 705         /*
 706          * Additional max data transfer sizes
 707          */
 708         u16 max_strips_per_io;
 709
 710         /*
 711          * Controller capabilities structures
 712          */
 713         struct {
 714
 715                 u32 raid_level_0:1;
 716                 u32 raid_level_1:1;
 717                 u32 raid_level_5:1;
 718                 u32 raid_level_1E:1;
 719                 u32 raid_level_6:1;
 720                 u32 reserved:27;
 721
 722         } __attribute__ ((packed)) raid_levels;
 723
 724         struct {
 725
 726                 u32 rbld_rate:1;
 727                 u32 cc_rate:1;
 728                 u32 bgi_rate:1;
 729                 u32 recon_rate:1;
 730                 u32 patrol_rate:1;
 731                 u32 alarm_control:1;
 732                 u32 cluster_supported:1;
 733                 u32 bbu:1;
 734                 u32 spanning_allowed:1;
 735                 u32 dedicated_hotspares:1;
 736                 u32 revertible_hotspares:1;
 737                 u32 foreign_config_import:1;
 738                 u32 self_diagnostic:1;
 739                 u32 mixed_redundancy_arr:1;
 740                 u32 global_hot_spares:1;
 741                 u32 reserved:17;
 742
 743         } __attribute__ ((packed)) adapter_operations;
 744
 745         struct {
 746
 747                 u32 read_policy:1;
 748                 u32 write_policy:1;
 749                 u32 io_policy:1;
 750                 u32 access_policy:1;
 751                 u32 disk_cache_policy:1;
 752                 u32 reserved:27;
 753
 754         } __attribute__ ((packed)) ld_operations;
 755
 756         struct {
 757
 758                 u8 min;
 759                 u8 max;
 760                 u8 reserved[2];
 761
 762         } __attribute__ ((packed)) stripe_sz_ops;
 763
 764         struct {
 765
 766                 u32 force_online:1;
 767                 u32 force_offline:1;
 768                 u32 force_rebuild:1;
 769                 u32 reserved:29;
 770
 771         } __attribute__ ((packed)) pd_operations;
 772
 773         struct {
 774
 775                 u32 ctrl_supports_sas:1;
 776                 u32 ctrl_supports_sata:1;
 777                 u32 allow_mix_in_encl:1;
 778                 u32 allow_mix_in_ld:1;
 779                 u32 allow_sata_in_cluster:1;
 780                 u32 reserved:27;
 781
 782         } __attribute__ ((packed)) pd_mix_support;
 783
 784         /*
 785          * Define ECC single-bit-error bucket information
 786          */
 787         u8 ecc_bucket_count;
 788         u8 reserved_2[11];
 789
 790         /*
 791          * Include the controller properties (changeable items)
 792          */
 793         struct megasas_ctrl_prop properties;
 794
 795         /*
 796          * Define FW pkg version (set in envt v'bles on OEM basis)
 797          */
 798         char package_version[0x60];
 799
 800
 801         /*
 802         * If adapterOperations.supportMoreThan8Phys is set,
 803         * and deviceInterface.portCount is greater than 8,
 804         * SAS Addrs for first 8 ports shall be populated in
 805         * deviceInterface.portAddr, and the rest shall be
 806         * populated in deviceInterfacePortAddr2.
 807         */
 808         u64         deviceInterfacePortAddr2[8]; /*6a0h */
 809         u8          reserved3[128];              /*6e0h */
 810
 811         struct {                                /*760h */
 812                 u16 minPdRaidLevel_0:4;
 813                 u16 maxPdRaidLevel_0:12;
 814
 815                 u16 minPdRaidLevel_1:4;
 816                 u16 maxPdRaidLevel_1:12;
 817
 818                 u16 minPdRaidLevel_5:4;
 819                 u16 maxPdRaidLevel_5:12;
 820
 821                 u16 minPdRaidLevel_1E:4;
 822                 u16 maxPdRaidLevel_1E:12;
 823
 824                 u16 minPdRaidLevel_6:4;
 825                 u16 maxPdRaidLevel_6:12;
 826
 827                 u16 minPdRaidLevel_10:4;
 828                 u16 maxPdRaidLevel_10:12;
 829
 830                 u16 minPdRaidLevel_50:4;
 831                 u16 maxPdRaidLevel_50:12;
 832
 833                 u16 minPdRaidLevel_60:4;
 834                 u16 maxPdRaidLevel_60:12;
 835
 836                 u16 minPdRaidLevel_1E_RLQ0:4;
 837                 u16 maxPdRaidLevel_1E_RLQ0:12;
 838
 839                 u16 minPdRaidLevel_1E0_RLQ0:4;
 840                 u16 maxPdRaidLevel_1E0_RLQ0:12;
 841
 842                 u16 reserved[6];
 843         } pdsForRaidLevels;
 844
 845         u16 maxPds;                             /*780h */
 846         u16 maxDedHSPs;                         /*782h */
 847         u16 maxGlobalHSPs;                      /*784h */
 848         u16 ddfSize;                            /*786h */
 849         u8  maxLdsPerArray;                     /*788h */
 850         u8  partitionsInDDF;                    /*789h */
 851         u8  lockKeyBinding;                     /*78ah */
 852         u8  maxPITsPerLd;                       /*78bh */
 853         u8  maxViewsPerLd;                      /*78ch */
 854         u8  maxTargetId;                        /*78dh */
 855         u16 maxBvlVdSize;                       /*78eh */
 856
 857         u16 maxConfigurableSSCSize;             /*790h */
 858         u16 currentSSCsize;                     /*792h */
 859
 860         char    expanderFwVersion[12];          /*794h */
 861
 862         u16 PFKTrialTimeRemaining;              /*7A0h */
 863
 864         u16 cacheMemorySize;                    /*7A2h */
 865
 866         struct {                                /*7A4h */
 867 #if   defined(__BIG_ENDIAN_BITFIELD)
 868                 u32     reserved:5;
 869                 u32     activePassive:2;
 870                 u32     supportConfigAutoBalance:1;
 871                 u32     mpio:1;
 872                 u32     supportDataLDonSSCArray:1;
 873                 u32     supportPointInTimeProgress:1;
 874                 u32     supportUnevenSpans:1;
 875                 u32     dedicatedHotSparesLimited:1;
 876                 u32     headlessMode:1;
 877                 u32     supportEmulatedDrives:1;
 878                 u32     supportResetNow:1;
 879                 u32     realTimeScheduler:1;
 880                 u32     supportSSDPatrolRead:1;
 881                 u32     supportPerfTuning:1;
 882                 u32     disableOnlinePFKChange:1;
 883                 u32     supportJBOD:1;
 884                 u32     supportBootTimePFKChange:1;
 885                 u32     supportSetLinkSpeed:1;
 886                 u32     supportEmergencySpares:1;
 887                 u32     supportSuspendResumeBGops:1;
 888                 u32     blockSSDWriteCacheChange:1;
 889                 u32     supportShieldState:1;
 890                 u32     supportLdBBMInfo:1;
 891                 u32     supportLdPIType3:1;
 892                 u32     supportLdPIType2:1;
 893                 u32     supportLdPIType1:1;
 894                 u32     supportPIcontroller:1;
 895 #else
 896                 u32     supportPIcontroller:1;
 897                 u32     supportLdPIType1:1;
 898                 u32     supportLdPIType2:1;
 899                 u32     supportLdPIType3:1;
 900                 u32     supportLdBBMInfo:1;
 901                 u32     supportShieldState:1;
 902                 u32     blockSSDWriteCacheChange:1;
 903                 u32     supportSuspendResumeBGops:1;
 904                 u32     supportEmergencySpares:1;
 905                 u32     supportSetLinkSpeed:1;
 906                 u32     supportBootTimePFKChange:1;
 907                 u32     supportJBOD:1;
 908                 u32     disableOnlinePFKChange:1;
 909                 u32     supportPerfTuning:1;
 910                 u32     supportSSDPatrolRead:1;
 911                 u32     realTimeScheduler:1;
 912
 913                 u32     supportResetNow:1;
 914                 u32     supportEmulatedDrives:1;
 915                 u32     headlessMode:1;
 916                 u32     dedicatedHotSparesLimited:1;
 917
 918
 919                 u32     supportUnevenSpans:1;
 920                 u32     supportPointInTimeProgress:1;
 921                 u32     supportDataLDonSSCArray:1;
 922                 u32     mpio:1;
 923                 u32     supportConfigAutoBalance:1;
 924                 u32     activePassive:2;
 925                 u32     reserved:5;
 926 #endif
 927         } adapterOperations2;
 928
 929         u8  driverVersion[32];                  /*7A8h */
 930         u8  maxDAPdCountSpinup60;               /*7C8h */
 931         u8  temperatureROC;                     /*7C9h */
 932         u8  temperatureCtrl;                    /*7CAh */
 933         u8  reserved4;                          /*7CBh */
 934         u16 maxConfigurablePds;                 /*7CCh */
 935
 936
 937         u8  reserved5[2];                       /*0x7CDh */
 938
 939         /*
 940         * HA cluster information
 941         */
 942         struct {
 943 #if defined(__BIG_ENDIAN_BITFIELD)
 944                 u32     reserved:26;
 945                 u32     premiumFeatureMismatch:1;
 946                 u32     ctrlPropIncompatible:1;
 947                 u32     fwVersionMismatch:1;
 948                 u32     hwIncompatible:1;
 949                 u32     peerIsIncompatible:1;
 950                 u32     peerIsPresent:1;
 951 #else
 952                 u32     peerIsPresent:1;
 953                 u32     peerIsIncompatible:1;
 954                 u32     hwIncompatible:1;
 955                 u32     fwVersionMismatch:1;
 956                 u32     ctrlPropIncompatible:1;
 957                 u32     premiumFeatureMismatch:1;
 958                 u32     reserved:26;
 959 #endif
 960         } cluster;
 961
 962         char clusterId[16];                     /*7D4h */
 963         struct {
 964                 u8  maxVFsSupported;            /*0x7E4*/
 965                 u8  numVFsEnabled;              /*0x7E5*/
 966                 u8  requestorId;                /*0x7E6 0:PF, 1:VF1, 2:VF2*/
 967                 u8  reserved;                   /*0x7E7*/
 968         } iov;
 969
 970         struct {
 971 #if defined(__BIG_ENDIAN_BITFIELD)
 972                 u32     reserved:12;
 973                 u32     discardCacheDuringLDDelete:1;
 974                 u32     supportSecurityonJBOD:1;
 975                 u32     supportCacheBypassModes:1;
 976                 u32     supportDisableSESMonitoring:1;
 977                 u32     supportForceFlash:1;
 978                 u32     supportNVDRAM:1;
 979                 u32     supportDrvActivityLEDSetting:1;
 980                 u32     supportAllowedOpsforDrvRemoval:1;
 981                 u32     supportHOQRebuild:1;
 982                 u32     supportForceTo512e:1;
 983                 u32     supportNVCacheErase:1;
 984                 u32     supportDebugQueue:1;
 985                 u32     supportSwZone:1;
 986                 u32     supportCrashDump:1;
 987                 u32     supportMaxExtLDs:1;
 988                 u32     supportT10RebuildAssist:1;
 989                 u32     supportDisableImmediateIO:1;
 990                 u32     supportThermalPollInterval:1;
 991                 u32     supportPersonalityChange:2;
 992 #else
 993                 u32     supportPersonalityChange:2;
 994                 u32     supportThermalPollInterval:1;
 995                 u32     supportDisableImmediateIO:1;
 996                 u32     supportT10RebuildAssist:1;
 997                 u32     supportMaxExtLDs:1;
 998                 u32     supportCrashDump:1;
 999                 u32     supportSwZone:1;
1000                 u32     supportDebugQueue:1;
1001                 u32     supportNVCacheErase:1;
1002                 u32     supportForceTo512e:1;
1003                 u32     supportHOQRebuild:1;
1004                 u32     supportAllowedOpsforDrvRemoval:1;
1005                 u32     supportDrvActivityLEDSetting:1;
1006                 u32     supportNVDRAM:1;
1007                 u32     supportForceFlash:1;
1008                 u32     supportDisableSESMonitoring:1;
1009                 u32     supportCacheBypassModes:1;
1010                 u32     supportSecurityonJBOD:1;
1011                 u32     discardCacheDuringLDDelete:1;
1012                 u32     reserved:12;
1013 #endif
1014         } adapterOperations3;
1015
1016         u8          pad[0x800-0x7EC];
1017 } __packed;
1018
1019 /*
1020  * ===============================
1021  * MegaRAID SAS driver definitions
1022  * ===============================
1023  */
1024 #define MEGASAS_MAX_PD_CHANNELS                 2
1025 #define MEGASAS_MAX_LD_CHANNELS                 2
1026 #define MEGASAS_MAX_CHANNELS                    (MEGASAS_MAX_PD_CHANNELS + \
1027                                                 MEGASAS_MAX_LD_CHANNELS)
1028 #define MEGASAS_MAX_DEV_PER_CHANNEL             128
1029 #define MEGASAS_DEFAULT_INIT_ID                 -1
1030 #define MEGASAS_MAX_LUN                         8
1031 #define MEGASAS_DEFAULT_CMD_PER_LUN             256
1032 #define MEGASAS_MAX_PD                          (MEGASAS_MAX_PD_CHANNELS * \
1033                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1034 #define MEGASAS_MAX_LD_IDS                      (MEGASAS_MAX_LD_CHANNELS * \
1035                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1036
1037 #define MEGASAS_MAX_SECTORS                    (2*1024)
1038 #define MEGASAS_MAX_SECTORS_IEEE                (2*128)
1039 #define MEGASAS_DBG_LVL                         1
1040
1041 #define MEGASAS_FW_BUSY                         1
1042
1043 #define VD_EXT_DEBUG 0
1044
1045 enum MR_MFI_MPT_PTHR_FLAGS {
1046         MFI_MPT_DETACHED = 0,
1047         MFI_LIST_ADDED = 1,
1048         MFI_MPT_ATTACHED = 2,
1049 };
1050
1051 enum MR_SCSI_CMD_TYPE {
1052         READ_WRITE_LDIO = 0,
1053         NON_READ_WRITE_LDIO = 1,
1054         READ_WRITE_SYSPDIO = 2,
1055         NON_READ_WRITE_SYSPDIO = 3,
1056 };
1057
1058 /* Frame Type */
1059 #define IO_FRAME                                0
1060 #define PTHRU_FRAME                             1
1061
1062 /*
1063  * When SCSI mid-layer calls driver's reset routine, driver waits for
1064  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1065  * that the driver cannot _actually_ abort or reset pending commands. While
1066  * it is waiting for the commands to complete, it prints a diagnostic message
1067  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1068  */
1069 #define MEGASAS_RESET_WAIT_TIME                 180
1070 #define MEGASAS_INTERNAL_CMD_WAIT_TIME          180
1071 #define MEGASAS_RESET_NOTICE_INTERVAL           5
1072 #define MEGASAS_IOCTL_CMD                       0
1073 #define MEGASAS_DEFAULT_CMD_TIMEOUT             90
1074 #define MEGASAS_THROTTLE_QUEUE_DEPTH            16
1075 #define MEGASAS_BLOCKED_CMD_TIMEOUT             60
1076 /*
1077  * FW reports the maximum of number of commands that it can accept (maximum
1078  * commands that can be outstanding) at any time. The driver must report a
1079  * lower number to the mid layer because it can issue a few internal commands
1080  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1081  * is shown below
1082  */
1083 #define MEGASAS_INT_CMDS                        32
1084 #define MEGASAS_SKINNY_INT_CMDS                 5
1085 #define MEGASAS_FUSION_INTERNAL_CMDS            5
1086 #define MEGASAS_FUSION_IOCTL_CMDS               3
1087
1088 #define MEGASAS_MAX_MSIX_QUEUES                 128
1089 /*
1090  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1091  * SGLs based on the size of dma_addr_t
1092  */
1093 #define IS_DMA64                                (sizeof(dma_addr_t) == 8)
1094
1095 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT                0x00000001
1096
1097 #define MFI_INTR_FLAG_REPLY_MESSAGE                     0x00000001
1098 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE             0x00000002
1099 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT       0x00000004
1100
1101 #define MFI_OB_INTR_STATUS_MASK                 0x00000002
1102 #define MFI_POLL_TIMEOUT_SECS                   60
1103 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF     (5 * HZ)
1104 #define MEGASAS_OCR_SETTLE_TIME_VF              (1000 * 30)
1105 #define MEGASAS_ROUTINE_WAIT_TIME_VF            300
1106 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
1107 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
1108 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          (0x00000001 | 0x00000004)
1109 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT      0x40000000
1110 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK        (0x00000001)
1111
1112 #define MFI_1068_PCSR_OFFSET                    0x84
1113 #define MFI_1068_FW_HANDSHAKE_OFFSET            0x64
1114 #define MFI_1068_FW_READY                       0xDDDD0000
1115
1116 #define MR_MAX_REPLY_QUEUES_OFFSET              0X0000001F
1117 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET          0X003FC000
1118 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
1119 #define MR_MAX_MSIX_REG_ARRAY                   16
1120 /*
1121 * register set for both 1068 and 1078 controllers
1122 * structure extended for 1078 registers
1123 */
1124
1125 struct megasas_register_set {
1126         u32     doorbell;                       /*0000h*/
1127         u32     fusion_seq_offset;              /*0004h*/
1128         u32     fusion_host_diag;               /*0008h*/
1129         u32     reserved_01;                    /*000Ch*/
1130
1131         u32     inbound_msg_0;                  /*0010h*/
1132         u32     inbound_msg_1;                  /*0014h*/
1133         u32     outbound_msg_0;                 /*0018h*/
1134         u32     outbound_msg_1;                 /*001Ch*/
1135
1136         u32     inbound_doorbell;               /*0020h*/
1137         u32     inbound_intr_status;            /*0024h*/
1138         u32     inbound_intr_mask;              /*0028h*/
1139
1140         u32     outbound_doorbell;              /*002Ch*/
1141         u32     outbound_intr_status;           /*0030h*/
1142         u32     outbound_intr_mask;             /*0034h*/
1143
1144         u32     reserved_1[2];                  /*0038h*/
1145
1146         u32     inbound_queue_port;             /*0040h*/
1147         u32     outbound_queue_port;            /*0044h*/
1148
1149         u32     reserved_2[9];                  /*0048h*/
1150         u32     reply_post_host_index;          /*006Ch*/
1151         u32     reserved_2_2[12];               /*0070h*/
1152
1153         u32     outbound_doorbell_clear;        /*00A0h*/
1154
1155         u32     reserved_3[3];                  /*00A4h*/
1156
1157         u32     outbound_scratch_pad ;          /*00B0h*/
1158         u32     outbound_scratch_pad_2;         /*00B4h*/
1159
1160         u32     reserved_4[2];                  /*00B8h*/
1161
1162         u32     inbound_low_queue_port ;        /*00C0h*/
1163
1164         u32     inbound_high_queue_port ;       /*00C4h*/
1165
1166         u32     reserved_5;                     /*00C8h*/
1167         u32     res_6[11];                      /*CCh*/
1168         u32     host_diag;
1169         u32     seq_offset;
1170         u32     index_registers[807];           /*00CCh*/
1171 } __attribute__ ((packed));
1172
1173 struct megasas_sge32 {
1174
1175         u32 phys_addr;
1176         u32 length;
1177
1178 } __attribute__ ((packed));
1179
1180 struct megasas_sge64 {
1181
1182         u64 phys_addr;
1183         u32 length;
1184
1185 } __attribute__ ((packed));
1186
1187 struct megasas_sge_skinny {
1188         u64 phys_addr;
1189         u32 length;
1190         u32 flag;
1191 } __packed;
1192
1193 union megasas_sgl {
1194
1195         struct megasas_sge32 sge32[1];
1196         struct megasas_sge64 sge64[1];
1197         struct megasas_sge_skinny sge_skinny[1];
1198
1199 } __attribute__ ((packed));
1200
1201 struct megasas_header {
1202
1203         u8 cmd;                 /*00h */
1204         u8 sense_len;           /*01h */
1205         u8 cmd_status;          /*02h */
1206         u8 scsi_status;         /*03h */
1207
1208         u8 target_id;           /*04h */
1209         u8 lun;                 /*05h */
1210         u8 cdb_len;             /*06h */
1211         u8 sge_count;           /*07h */
1212
1213         u32 context;            /*08h */
1214         u32 pad_0;              /*0Ch */
1215
1216         u16 flags;              /*10h */
1217         u16 timeout;            /*12h */
1218         u32 data_xferlen;       /*14h */
1219
1220 } __attribute__ ((packed));
1221
1222 union megasas_sgl_frame {
1223
1224         struct megasas_sge32 sge32[8];
1225         struct megasas_sge64 sge64[5];
1226
1227 } __attribute__ ((packed));
1228
1229 typedef union _MFI_CAPABILITIES {
1230         struct {
1231 #if   defined(__BIG_ENDIAN_BITFIELD)
1232                 u32     reserved:25;
1233                 u32     security_protocol_cmds_fw:1;
1234                 u32     support_core_affinity:1;
1235                 u32     support_ndrive_r1_lb:1;
1236                 u32     support_max_255lds:1;
1237                 u32     support_fastpath_wb:1;
1238                 u32     support_additional_msix:1;
1239                 u32     support_fp_remote_lun:1;
1240 #else
1241                 u32     support_fp_remote_lun:1;
1242                 u32     support_additional_msix:1;
1243                 u32     support_fastpath_wb:1;
1244                 u32     support_max_255lds:1;
1245                 u32     support_ndrive_r1_lb:1;
1246                 u32     support_core_affinity:1;
1247                 u32     security_protocol_cmds_fw:1;
1248                 u32     reserved:25;
1249 #endif
1250         } mfi_capabilities;
1251         u32     reg;
1252 } MFI_CAPABILITIES;
1253
1254 struct megasas_init_frame {
1255
1256         u8 cmd;                 /*00h */
1257         u8 reserved_0;          /*01h */
1258         u8 cmd_status;          /*02h */
1259
1260         u8 reserved_1;          /*03h */
1261         MFI_CAPABILITIES driver_operations; /*04h*/
1262
1263         u32 context;            /*08h */
1264         u32 pad_0;              /*0Ch */
1265
1266         u16 flags;              /*10h */
1267         u16 reserved_3;         /*12h */
1268         u32 data_xfer_len;      /*14h */
1269
1270         u32 queue_info_new_phys_addr_lo;        /*18h */
1271         u32 queue_info_new_phys_addr_hi;        /*1Ch */
1272         u32 queue_info_old_phys_addr_lo;        /*20h */
1273         u32 queue_info_old_phys_addr_hi;        /*24h */
1274
1275         u32 reserved_4[6];      /*28h */
1276
1277 } __attribute__ ((packed));
1278
1279 struct megasas_init_queue_info {
1280
1281         u32 init_flags;         /*00h */
1282         u32 reply_queue_entries;        /*04h */
1283
1284         u32 reply_queue_start_phys_addr_lo;     /*08h */
1285         u32 reply_queue_start_phys_addr_hi;     /*0Ch */
1286         u32 producer_index_phys_addr_lo;        /*10h */
1287         u32 producer_index_phys_addr_hi;        /*14h */
1288         u32 consumer_index_phys_addr_lo;        /*18h */
1289         u32 consumer_index_phys_addr_hi;        /*1Ch */
1290
1291 } __attribute__ ((packed));
1292
1293 struct megasas_io_frame {
1294
1295         u8 cmd;                 /*00h */
1296         u8 sense_len;           /*01h */
1297         u8 cmd_status;          /*02h */
1298         u8 scsi_status;         /*03h */
1299
1300         u8 target_id;           /*04h */
1301         u8 access_byte;         /*05h */
1302         u8 reserved_0;          /*06h */
1303         u8 sge_count;           /*07h */
1304
1305         u32 context;            /*08h */
1306         u32 pad_0;              /*0Ch */
1307
1308         u16 flags;              /*10h */
1309         u16 timeout;            /*12h */
1310         u32 lba_count;          /*14h */
1311
1312         u32 sense_buf_phys_addr_lo;     /*18h */
1313         u32 sense_buf_phys_addr_hi;     /*1Ch */
1314
1315         u32 start_lba_lo;       /*20h */
1316         u32 start_lba_hi;       /*24h */
1317
1318         union megasas_sgl sgl;  /*28h */
1319
1320 } __attribute__ ((packed));
1321
1322 struct megasas_pthru_frame {
1323
1324         u8 cmd;                 /*00h */
1325         u8 sense_len;           /*01h */
1326         u8 cmd_status;          /*02h */
1327         u8 scsi_status;         /*03h */
1328
1329         u8 target_id;           /*04h */
1330         u8 lun;                 /*05h */
1331         u8 cdb_len;             /*06h */
1332         u8 sge_count;           /*07h */
1333
1334         u32 context;            /*08h */
1335         u32 pad_0;              /*0Ch */
1336
1337         u16 flags;              /*10h */
1338         u16 timeout;            /*12h */
1339         u32 data_xfer_len;      /*14h */
1340
1341         u32 sense_buf_phys_addr_lo;     /*18h */
1342         u32 sense_buf_phys_addr_hi;     /*1Ch */
1343
1344         u8 cdb[16];             /*20h */
1345         union megasas_sgl sgl;  /*30h */
1346
1347 } __attribute__ ((packed));
1348
1349 struct megasas_dcmd_frame {
1350
1351         u8 cmd;                 /*00h */
1352         u8 reserved_0;          /*01h */
1353         u8 cmd_status;          /*02h */
1354         u8 reserved_1[4];       /*03h */
1355         u8 sge_count;           /*07h */
1356
1357         u32 context;            /*08h */
1358         u32 pad_0;              /*0Ch */
1359
1360         u16 flags;              /*10h */
1361         u16 timeout;            /*12h */
1362
1363         u32 data_xfer_len;      /*14h */
1364         u32 opcode;             /*18h */
1365
1366         union {                 /*1Ch */
1367                 u8 b[12];
1368                 u16 s[6];
1369                 u32 w[3];
1370         } mbox;
1371
1372         union megasas_sgl sgl;  /*28h */
1373
1374 } __attribute__ ((packed));
1375
1376 struct megasas_abort_frame {
1377
1378         u8 cmd;                 /*00h */
1379         u8 reserved_0;          /*01h */
1380         u8 cmd_status;          /*02h */
1381
1382         u8 reserved_1;          /*03h */
1383         u32 reserved_2;         /*04h */
1384
1385         u32 context;            /*08h */
1386         u32 pad_0;              /*0Ch */
1387
1388         u16 flags;              /*10h */
1389         u16 reserved_3;         /*12h */
1390         u32 reserved_4;         /*14h */
1391
1392         u32 abort_context;      /*18h */
1393         u32 pad_1;              /*1Ch */
1394
1395         u32 abort_mfi_phys_addr_lo;     /*20h */
1396         u32 abort_mfi_phys_addr_hi;     /*24h */
1397
1398         u32 reserved_5[6];      /*28h */
1399
1400 } __attribute__ ((packed));
1401
1402 struct megasas_smp_frame {
1403
1404         u8 cmd;                 /*00h */
1405         u8 reserved_1;          /*01h */
1406         u8 cmd_status;          /*02h */
1407         u8 connection_status;   /*03h */
1408
1409         u8 reserved_2[3];       /*04h */
1410         u8 sge_count;           /*07h */
1411
1412         u32 context;            /*08h */
1413         u32 pad_0;              /*0Ch */
1414
1415         u16 flags;              /*10h */
1416         u16 timeout;            /*12h */
1417
1418         u32 data_xfer_len;      /*14h */
1419         u64 sas_addr;           /*18h */
1420
1421         union {
1422                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: req */
1423                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: req */
1424         } sgl;
1425
1426 } __attribute__ ((packed));
1427
1428 struct megasas_stp_frame {
1429
1430         u8 cmd;                 /*00h */
1431         u8 reserved_1;          /*01h */
1432         u8 cmd_status;          /*02h */
1433         u8 reserved_2;          /*03h */
1434
1435         u8 target_id;           /*04h */
1436         u8 reserved_3[2];       /*05h */
1437         u8 sge_count;           /*07h */
1438
1439         u32 context;            /*08h */
1440         u32 pad_0;              /*0Ch */
1441
1442         u16 flags;              /*10h */
1443         u16 timeout;            /*12h */
1444
1445         u32 data_xfer_len;      /*14h */
1446
1447         u16 fis[10];            /*18h */
1448         u32 stp_flags;
1449
1450         union {
1451                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: data */
1452                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: data */
1453         } sgl;
1454
1455 } __attribute__ ((packed));
1456
1457 union megasas_frame {
1458
1459         struct megasas_header hdr;
1460         struct megasas_init_frame init;
1461         struct megasas_io_frame io;
1462         struct megasas_pthru_frame pthru;
1463         struct megasas_dcmd_frame dcmd;
1464         struct megasas_abort_frame abort;
1465         struct megasas_smp_frame smp;
1466         struct megasas_stp_frame stp;
1467
1468         u8 raw_bytes[64];
1469 };
1470
1471 struct megasas_cmd;
1472
1473 union megasas_evt_class_locale {
1474
1475         struct {
1476 #ifndef __BIG_ENDIAN_BITFIELD
1477                 u16 locale;
1478                 u8 reserved;
1479                 s8 class;
1480 #else
1481                 s8 class;
1482                 u8 reserved;
1483                 u16 locale;
1484 #endif
1485         } __attribute__ ((packed)) members;
1486
1487         u32 word;
1488
1489 } __attribute__ ((packed));
1490
1491 struct megasas_evt_log_info {
1492         u32 newest_seq_num;
1493         u32 oldest_seq_num;
1494         u32 clear_seq_num;
1495         u32 shutdown_seq_num;
1496         u32 boot_seq_num;
1497
1498 } __attribute__ ((packed));
1499
1500 struct megasas_progress {
1501
1502         u16 progress;
1503         u16 elapsed_seconds;
1504
1505 } __attribute__ ((packed));
1506
1507 struct megasas_evtarg_ld {
1508
1509         u16 target_id;
1510         u8 ld_index;
1511         u8 reserved;
1512
1513 } __attribute__ ((packed));
1514
1515 struct megasas_evtarg_pd {
1516         u16 device_id;
1517         u8 encl_index;
1518         u8 slot_number;
1519
1520 } __attribute__ ((packed));
1521
1522 struct megasas_evt_detail {
1523
1524         u32 seq_num;
1525         u32 time_stamp;
1526         u32 code;
1527         union megasas_evt_class_locale cl;
1528         u8 arg_type;
1529         u8 reserved1[15];
1530
1531         union {
1532                 struct {
1533                         struct megasas_evtarg_pd pd;
1534                         u8 cdb_length;
1535                         u8 sense_length;
1536                         u8 reserved[2];
1537                         u8 cdb[16];
1538                         u8 sense[64];
1539                 } __attribute__ ((packed)) cdbSense;
1540
1541                 struct megasas_evtarg_ld ld;
1542
1543                 struct {
1544                         struct megasas_evtarg_ld ld;
1545                         u64 count;
1546                 } __attribute__ ((packed)) ld_count;
1547
1548                 struct {
1549                         u64 lba;
1550                         struct megasas_evtarg_ld ld;
1551                 } __attribute__ ((packed)) ld_lba;
1552
1553                 struct {
1554                         struct megasas_evtarg_ld ld;
1555                         u32 prevOwner;
1556                         u32 newOwner;
1557                 } __attribute__ ((packed)) ld_owner;
1558
1559                 struct {
1560                         u64 ld_lba;
1561                         u64 pd_lba;
1562                         struct megasas_evtarg_ld ld;
1563                         struct megasas_evtarg_pd pd;
1564                 } __attribute__ ((packed)) ld_lba_pd_lba;
1565
1566                 struct {
1567                         struct megasas_evtarg_ld ld;
1568                         struct megasas_progress prog;
1569                 } __attribute__ ((packed)) ld_prog;
1570
1571                 struct {
1572                         struct megasas_evtarg_ld ld;
1573                         u32 prev_state;
1574                         u32 new_state;
1575                 } __attribute__ ((packed)) ld_state;
1576
1577                 struct {
1578                         u64 strip;
1579                         struct megasas_evtarg_ld ld;
1580                 } __attribute__ ((packed)) ld_strip;
1581
1582                 struct megasas_evtarg_pd pd;
1583
1584                 struct {
1585                         struct megasas_evtarg_pd pd;
1586                         u32 err;
1587                 } __attribute__ ((packed)) pd_err;
1588
1589                 struct {
1590                         u64 lba;
1591                         struct megasas_evtarg_pd pd;
1592                 } __attribute__ ((packed)) pd_lba;
1593
1594                 struct {
1595                         u64 lba;
1596                         struct megasas_evtarg_pd pd;
1597                         struct megasas_evtarg_ld ld;
1598                 } __attribute__ ((packed)) pd_lba_ld;
1599
1600                 struct {
1601                         struct megasas_evtarg_pd pd;
1602                         struct megasas_progress prog;
1603                 } __attribute__ ((packed)) pd_prog;
1604
1605                 struct {
1606                         struct megasas_evtarg_pd pd;
1607                         u32 prevState;
1608                         u32 newState;
1609                 } __attribute__ ((packed)) pd_state;
1610
1611                 struct {
1612                         u16 vendorId;
1613                         u16 deviceId;
1614                         u16 subVendorId;
1615                         u16 subDeviceId;
1616                 } __attribute__ ((packed)) pci;
1617
1618                 u32 rate;
1619                 char str[96];
1620
1621                 struct {
1622                         u32 rtc;
1623                         u32 elapsedSeconds;
1624                 } __attribute__ ((packed)) time;
1625
1626                 struct {
1627                         u32 ecar;
1628                         u32 elog;
1629                         char str[64];
1630                 } __attribute__ ((packed)) ecc;
1631
1632                 u8 b[96];
1633                 u16 s[48];
1634                 u32 w[24];
1635                 u64 d[12];
1636         } args;
1637
1638         char description[128];
1639
1640 } __attribute__ ((packed));
1641
1642 struct megasas_aen_event {
1643         struct delayed_work hotplug_work;
1644         struct megasas_instance *instance;
1645 };
1646
1647 struct megasas_irq_context {
1648         struct megasas_instance *instance;
1649         u32 MSIxIndex;
1650 };
1651
1652 struct megasas_instance {
1653
1654         u32 *producer;
1655         dma_addr_t producer_h;
1656         u32 *consumer;
1657         dma_addr_t consumer_h;
1658         struct MR_LD_VF_AFFILIATION *vf_affiliation;
1659         dma_addr_t vf_affiliation_h;
1660         struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
1661         dma_addr_t vf_affiliation_111_h;
1662         struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
1663         dma_addr_t hb_host_mem_h;
1664
1665         u32 *reply_queue;
1666         dma_addr_t reply_queue_h;
1667
1668         u32 *crash_dump_buf;
1669         dma_addr_t crash_dump_h;
1670         void *crash_buf[MAX_CRASH_DUMP_SIZE];
1671         u32 crash_buf_pages;
1672         unsigned int    fw_crash_buffer_size;
1673         unsigned int    fw_crash_state;
1674         unsigned int    fw_crash_buffer_offset;
1675         u32 drv_buf_index;
1676         u32 drv_buf_alloc;
1677         u32 crash_dump_fw_support;
1678         u32 crash_dump_drv_support;
1679         u32 crash_dump_app_support;
1680         u32 secure_jbod_support;
1681         spinlock_t crashdump_lock;
1682
1683         struct megasas_register_set __iomem *reg_set;
1684         u32 *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
1685         struct megasas_pd_list          pd_list[MEGASAS_MAX_PD];
1686         struct megasas_pd_list          local_pd_list[MEGASAS_MAX_PD];
1687         u8 ld_ids[MEGASAS_MAX_LD_IDS];
1688         s8 init_id;
1689
1690         u16 max_num_sge;
1691         u16 max_fw_cmds;
1692         u16 max_mfi_cmds;
1693         u16 max_scsi_cmds;
1694         u32 max_sectors_per_req;
1695         struct megasas_aen_event *ev;
1696
1697         struct megasas_cmd **cmd_list;
1698         struct list_head cmd_pool;
1699         /* used to sync fire the cmd to fw */
1700         spinlock_t mfi_pool_lock;
1701         /* used to sync fire the cmd to fw */
1702         spinlock_t hba_lock;
1703         /* used to synch producer, consumer ptrs in dpc */
1704         spinlock_t completion_lock;
1705         struct dma_pool *frame_dma_pool;
1706         struct dma_pool *sense_dma_pool;
1707
1708         struct megasas_evt_detail *evt_detail;
1709         dma_addr_t evt_detail_h;
1710         struct megasas_cmd *aen_cmd;
1711         struct mutex aen_mutex;
1712         struct semaphore ioctl_sem;
1713
1714         struct Scsi_Host *host;
1715
1716         wait_queue_head_t int_cmd_wait_q;
1717         wait_queue_head_t abort_cmd_wait_q;
1718
1719         struct pci_dev *pdev;
1720         u32 unique_id;
1721         u32 fw_support_ieee;
1722
1723         atomic_t fw_outstanding;
1724         atomic_t fw_reset_no_pci_access;
1725
1726         struct megasas_instance_template *instancet;
1727         struct tasklet_struct isr_tasklet;
1728         struct work_struct work_init;
1729         struct work_struct crash_init;
1730
1731         u8 flag;
1732         u8 unload;
1733         u8 flag_ieee;
1734         u8 issuepend_done;
1735         u8 disableOnlineCtrlReset;
1736         u8 UnevenSpanSupport;
1737
1738         u8 supportmax256vd;
1739         u16 fw_supported_vd_count;
1740         u16 fw_supported_pd_count;
1741
1742         u16 drv_supported_vd_count;
1743         u16 drv_supported_pd_count;
1744
1745         u8 adprecovery;
1746         unsigned long last_time;
1747         u32 mfiStatus;
1748         u32 last_seq_num;
1749
1750         struct list_head internal_reset_pending_q;
1751
1752         /* Ptr to hba specific information */
1753         void *ctrl_context;
1754         u32 ctrl_context_pages;
1755         struct megasas_ctrl_info *ctrl_info;
1756         unsigned int msix_vectors;
1757         struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1758         struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
1759         u64 map_id;
1760         struct megasas_cmd *map_update_cmd;
1761         unsigned long bar;
1762         long reset_flags;
1763         struct mutex reset_mutex;
1764         struct timer_list sriov_heartbeat_timer;
1765         char skip_heartbeat_timer_del;
1766         u8 requestorId;
1767         char PlasmaFW111;
1768         char mpio;
1769         u16 throttlequeuedepth;
1770         u8 mask_interrupts;
1771         u8 is_imr;
1772 };
1773 struct MR_LD_VF_MAP {
1774         u32 size;
1775         union MR_LD_REF ref;
1776         u8 ldVfCount;
1777         u8 reserved[6];
1778         u8 policy[1];
1779 };
1780
1781 struct MR_LD_VF_AFFILIATION {
1782         u32 size;
1783         u8 ldCount;
1784         u8 vfCount;
1785         u8 thisVf;
1786         u8 reserved[9];
1787         struct MR_LD_VF_MAP map[1];
1788 };
1789
1790 /* Plasma 1.11 FW backward compatibility structures */
1791 #define IOV_111_OFFSET 0x7CE
1792 #define MAX_VIRTUAL_FUNCTIONS 8
1793 #define MR_LD_ACCESS_HIDDEN 15
1794
1795 struct IOV_111 {
1796         u8 maxVFsSupported;
1797         u8 numVFsEnabled;
1798         u8 requestorId;
1799         u8 reserved[5];
1800 };
1801
1802 struct MR_LD_VF_MAP_111 {
1803         u8 targetId;
1804         u8 reserved[3];
1805         u8 policy[MAX_VIRTUAL_FUNCTIONS];
1806 };
1807
1808 struct MR_LD_VF_AFFILIATION_111 {
1809         u8 vdCount;
1810         u8 vfCount;
1811         u8 thisVf;
1812         u8 reserved[5];
1813         struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
1814 };
1815
1816 struct MR_CTRL_HB_HOST_MEM {
1817         struct {
1818                 u32 fwCounter;  /* Firmware heart beat counter */
1819                 struct {
1820                         u32 debugmode:1; /* 1=Firmware is in debug mode.
1821                                             Heart beat will not be updated. */
1822                         u32 reserved:31;
1823                 } debug;
1824                 u32 reserved_fw[6];
1825                 u32 driverCounter; /* Driver heart beat counter.  0x20 */
1826                 u32 reserved_driver[7];
1827         } HB;
1828         u8 pad[0x400-0x40];
1829 };
1830
1831 enum {
1832         MEGASAS_HBA_OPERATIONAL                 = 0,
1833         MEGASAS_ADPRESET_SM_INFAULT             = 1,
1834         MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS    = 2,
1835         MEGASAS_ADPRESET_SM_OPERATIONAL         = 3,
1836         MEGASAS_HW_CRITICAL_ERROR               = 4,
1837         MEGASAS_ADPRESET_SM_POLLING             = 5,
1838         MEGASAS_ADPRESET_INPROG_SIGN            = 0xDEADDEAD,
1839 };
1840
1841 struct megasas_instance_template {
1842         void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1843                 u32, struct megasas_register_set __iomem *);
1844
1845         void (*enable_intr)(struct megasas_instance *);
1846         void (*disable_intr)(struct megasas_instance *);
1847
1848         int (*clear_intr)(struct megasas_register_set __iomem *);
1849
1850         u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1851         int (*adp_reset)(struct megasas_instance *, \
1852                 struct megasas_register_set __iomem *);
1853         int (*check_reset)(struct megasas_instance *, \
1854                 struct megasas_register_set __iomem *);
1855         irqreturn_t (*service_isr)(int irq, void *devp);
1856         void (*tasklet)(unsigned long);
1857         u32 (*init_adapter)(struct megasas_instance *);
1858         u32 (*build_and_issue_cmd) (struct megasas_instance *,
1859                                     struct scsi_cmnd *);
1860         void (*issue_dcmd) (struct megasas_instance *instance,
1861                             struct megasas_cmd *cmd);
1862 };
1863
1864 #define MEGASAS_IS_LOGICAL(scp)                                         \
1865         (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1866
1867 #define MEGASAS_DEV_INDEX(inst, scp)                                    \
1868         ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) +    \
1869         scp->device->id
1870
1871 struct megasas_cmd {
1872
1873         union megasas_frame *frame;
1874         dma_addr_t frame_phys_addr;
1875         u8 *sense;
1876         dma_addr_t sense_phys_addr;
1877
1878         u32 index;
1879         u8 sync_cmd;
1880         u8 cmd_status;
1881         u8 abort_aen;
1882         u8 retry_for_fw_reset;
1883
1884
1885         struct list_head list;
1886         struct scsi_cmnd *scmd;
1887
1888         void *mpt_pthr_cmd_blocked;
1889         atomic_t mfi_mpt_pthr;
1890         u8 is_wait_event;
1891
1892         struct megasas_instance *instance;
1893         union {
1894                 struct {
1895                         u16 smid;
1896                         u16 resvd;
1897                 } context;
1898                 u32 frame_count;
1899         };
1900 };
1901
1902 #define MAX_MGMT_ADAPTERS               1024
1903 #define MAX_IOCTL_SGE                   16
1904
1905 struct megasas_iocpacket {
1906
1907         u16 host_no;
1908         u16 __pad1;
1909         u32 sgl_off;
1910         u32 sge_count;
1911         u32 sense_off;
1912         u32 sense_len;
1913         union {
1914                 u8 raw[128];
1915                 struct megasas_header hdr;
1916         } frame;
1917
1918         struct iovec sgl[MAX_IOCTL_SGE];
1919
1920 } __attribute__ ((packed));
1921
1922 struct megasas_aen {
1923         u16 host_no;
1924         u16 __pad1;
1925         u32 seq_num;
1926         u32 class_locale_word;
1927 } __attribute__ ((packed));
1928
1929 #ifdef CONFIG_COMPAT
1930 struct compat_megasas_iocpacket {
1931         u16 host_no;
1932         u16 __pad1;
1933         u32 sgl_off;
1934         u32 sge_count;
1935         u32 sense_off;
1936         u32 sense_len;
1937         union {
1938                 u8 raw[128];
1939                 struct megasas_header hdr;
1940         } frame;
1941         struct compat_iovec sgl[MAX_IOCTL_SGE];
1942 } __attribute__ ((packed));
1943
1944 #define MEGASAS_IOC_FIRMWARE32  _IOWR('M', 1, struct compat_megasas_iocpacket)
1945 #endif
1946
1947 #define MEGASAS_IOC_FIRMWARE    _IOWR('M', 1, struct megasas_iocpacket)
1948 #define MEGASAS_IOC_GET_AEN     _IOW('M', 3, struct megasas_aen)
1949
1950 struct megasas_mgmt_info {
1951
1952         u16 count;
1953         struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1954         int max_index;
1955 };
1956
1957 u8
1958 MR_BuildRaidContext(struct megasas_instance *instance,
1959                     struct IO_REQUEST_INFO *io_info,
1960                     struct RAID_CONTEXT *pRAID_Context,
1961                     struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
1962 u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
1963 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1964 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
1965 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
1966 u16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
1967 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1968
1969 u16 get_updated_dev_handle(struct megasas_instance *instance,
1970         struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info);
1971 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
1972         struct LD_LOAD_BALANCE_INFO *lbInfo);
1973 int megasas_get_ctrl_info(struct megasas_instance *instance);
1974 int megasas_set_crash_dump_params(struct megasas_instance *instance,
1975         u8 crash_buf_state);
1976 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
1977 void megasas_fusion_crash_dump_wq(struct work_struct *work);
1978
1979 void megasas_return_cmd_fusion(struct megasas_instance *instance,
1980         struct megasas_cmd_fusion *cmd);
1981 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
1982         struct megasas_cmd *cmd, int timeout);
1983 void __megasas_return_cmd(struct megasas_instance *instance,
1984         struct megasas_cmd *cmd);
1985
1986 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
1987         struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
1988 int megasas_cmd_type(struct scsi_cmnd *cmd);
1989
1990 #endif                          /*LSI_MEGARAID_SAS_H */