kernel/drivers/rtc/rtc-omap.c

   1 /*
   2  * TI OMAP Real Time Clock interface for Linux
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
   6  *
   7  * Copyright (C) 2006 David Brownell (new RTC framework)
   8  * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/ioport.h>
  20 #include <linux/delay.h>
  21 #include <linux/rtc.h>
  22 #include <linux/bcd.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/io.h>
  28 #include <linux/clk.h>
  29
  30 /*
  31  * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
  32  * with century-range alarm matching, driven by the 32kHz clock.
  33  *
  34  * The main user-visible ways it differs from PC RTCs are by omitting
  35  * "don't care" alarm fields and sub-second periodic IRQs, and having
  36  * an autoadjust mechanism to calibrate to the true oscillator rate.
  37  *
  38  * Board-specific wiring options include using split power mode with
  39  * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
  40  * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
  41  * low power modes) for OMAP1 boards (OMAP-L138 has this built into
  42  * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
  43  */
  44
  45 /* RTC registers */
  46 #define OMAP_RTC_SECONDS_REG            0x00
  47 #define OMAP_RTC_MINUTES_REG            0x04
  48 #define OMAP_RTC_HOURS_REG              0x08
  49 #define OMAP_RTC_DAYS_REG               0x0C
  50 #define OMAP_RTC_MONTHS_REG             0x10
  51 #define OMAP_RTC_YEARS_REG              0x14
  52 #define OMAP_RTC_WEEKS_REG              0x18
  53
  54 #define OMAP_RTC_ALARM_SECONDS_REG      0x20
  55 #define OMAP_RTC_ALARM_MINUTES_REG      0x24
  56 #define OMAP_RTC_ALARM_HOURS_REG        0x28
  57 #define OMAP_RTC_ALARM_DAYS_REG         0x2c
  58 #define OMAP_RTC_ALARM_MONTHS_REG       0x30
  59 #define OMAP_RTC_ALARM_YEARS_REG        0x34
  60
  61 #define OMAP_RTC_CTRL_REG               0x40
  62 #define OMAP_RTC_STATUS_REG             0x44
  63 #define OMAP_RTC_INTERRUPTS_REG         0x48
  64
  65 #define OMAP_RTC_COMP_LSB_REG           0x4c
  66 #define OMAP_RTC_COMP_MSB_REG           0x50
  67 #define OMAP_RTC_OSC_REG                0x54
  68
  69 #define OMAP_RTC_KICK0_REG              0x6c
  70 #define OMAP_RTC_KICK1_REG              0x70
  71
  72 #define OMAP_RTC_IRQWAKEEN              0x7c
  73
  74 #define OMAP_RTC_ALARM2_SECONDS_REG     0x80
  75 #define OMAP_RTC_ALARM2_MINUTES_REG     0x84
  76 #define OMAP_RTC_ALARM2_HOURS_REG       0x88
  77 #define OMAP_RTC_ALARM2_DAYS_REG        0x8c
  78 #define OMAP_RTC_ALARM2_MONTHS_REG      0x90
  79 #define OMAP_RTC_ALARM2_YEARS_REG       0x94
  80
  81 #define OMAP_RTC_PMIC_REG               0x98
  82
  83 /* OMAP_RTC_CTRL_REG bit fields: */
  84 #define OMAP_RTC_CTRL_SPLIT             BIT(7)
  85 #define OMAP_RTC_CTRL_DISABLE           BIT(6)
  86 #define OMAP_RTC_CTRL_SET_32_COUNTER    BIT(5)
  87 #define OMAP_RTC_CTRL_TEST              BIT(4)
  88 #define OMAP_RTC_CTRL_MODE_12_24        BIT(3)
  89 #define OMAP_RTC_CTRL_AUTO_COMP         BIT(2)
  90 #define OMAP_RTC_CTRL_ROUND_30S         BIT(1)
  91 #define OMAP_RTC_CTRL_STOP              BIT(0)
  92
  93 /* OMAP_RTC_STATUS_REG bit fields: */
  94 #define OMAP_RTC_STATUS_POWER_UP        BIT(7)
  95 #define OMAP_RTC_STATUS_ALARM2          BIT(7)
  96 #define OMAP_RTC_STATUS_ALARM           BIT(6)
  97 #define OMAP_RTC_STATUS_1D_EVENT        BIT(5)
  98 #define OMAP_RTC_STATUS_1H_EVENT        BIT(4)
  99 #define OMAP_RTC_STATUS_1M_EVENT        BIT(3)
 100 #define OMAP_RTC_STATUS_1S_EVENT        BIT(2)
 101 #define OMAP_RTC_STATUS_RUN             BIT(1)
 102 #define OMAP_RTC_STATUS_BUSY            BIT(0)
 103
 104 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
 105 #define OMAP_RTC_INTERRUPTS_IT_ALARM2   BIT(4)
 106 #define OMAP_RTC_INTERRUPTS_IT_ALARM    BIT(3)
 107 #define OMAP_RTC_INTERRUPTS_IT_TIMER    BIT(2)
 108
 109 /* OMAP_RTC_OSC_REG bit fields: */
 110 #define OMAP_RTC_OSC_32KCLK_EN          BIT(6)
 111 #define OMAP_RTC_OSC_SEL_32KCLK_SRC     BIT(3)
 112 #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE  BIT(4)
 113
 114 /* OMAP_RTC_IRQWAKEEN bit fields: */
 115 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
 116
 117 /* OMAP_RTC_PMIC bit fields: */
 118 #define OMAP_RTC_PMIC_POWER_EN_EN       BIT(16)
 119
 120 /* OMAP_RTC_KICKER values */
 121 #define KICK0_VALUE                     0x83e70b13
 122 #define KICK1_VALUE                     0x95a4f1e0
 123
 124 struct omap_rtc;
 125
 126 struct omap_rtc_device_type {
 127         bool has_32kclk_en;
 128         bool has_irqwakeen;
 129         bool has_pmic_mode;
 130         bool has_power_up_reset;
 131         void (*lock)(struct omap_rtc *rtc);
 132         void (*unlock)(struct omap_rtc *rtc);
 133 };
 134
 135 struct omap_rtc {
 136         struct rtc_device *rtc;
 137         void __iomem *base;
 138         struct clk *clk;
 139         int irq_alarm;
 140         int irq_timer;
 141         u8 interrupts_reg;
 142         bool is_pmic_controller;
 143         bool has_ext_clk;
 144         const struct omap_rtc_device_type *type;
 145 };
 146
 147 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
 148 {
 149         return readb(rtc->base + reg);
 150 }
 151
 152 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
 153 {
 154         return readl(rtc->base + reg);
 155 }
 156
 157 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
 158 {
 159         writeb(val, rtc->base + reg);
 160 }
 161
 162 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
 163 {
 164         writel(val, rtc->base + reg);
 165 }
 166
 167 static void am3352_rtc_unlock(struct omap_rtc *rtc)
 168 {
 169         rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
 170         rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
 171 }
 172
 173 static void am3352_rtc_lock(struct omap_rtc *rtc)
 174 {
 175         rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
 176         rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
 177 }
 178
 179 static void default_rtc_unlock(struct omap_rtc *rtc)
 180 {
 181 }
 182
 183 static void default_rtc_lock(struct omap_rtc *rtc)
 184 {
 185 }
 186
 187 /*
 188  * We rely on the rtc framework to handle locking (rtc->ops_lock),
 189  * so the only other requirement is that register accesses which
 190  * require BUSY to be clear are made with IRQs locally disabled
 191  */
 192 static void rtc_wait_not_busy(struct omap_rtc *rtc)
 193 {
 194         int count;
 195         u8 status;
 196
 197         /* BUSY may stay active for 1/32768 second (~30 usec) */
 198         for (count = 0; count < 50; count++) {
 199                 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 200                 if (!(status & OMAP_RTC_STATUS_BUSY))
 201                         break;
 202                 udelay(1);
 203         }
 204         /* now we have ~15 usec to read/write various registers */
 205 }
 206
 207 static irqreturn_t rtc_irq(int irq, void *dev_id)
 208 {
 209         struct omap_rtc *rtc = dev_id;
 210         unsigned long events = 0;
 211         u8 irq_data;
 212
 213         irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 214
 215         /* alarm irq? */
 216         if (irq_data & OMAP_RTC_STATUS_ALARM) {
 217                 rtc->type->unlock(rtc);
 218                 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
 219                 rtc->type->lock(rtc);
 220                 events |= RTC_IRQF | RTC_AF;
 221         }
 222
 223         /* 1/sec periodic/update irq? */
 224         if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
 225                 events |= RTC_IRQF | RTC_UF;
 226
 227         rtc_update_irq(rtc->rtc, 1, events);
 228
 229         return IRQ_HANDLED;
 230 }
 231
 232 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 233 {
 234         struct omap_rtc *rtc = dev_get_drvdata(dev);
 235         u8 reg, irqwake_reg = 0;
 236
 237         local_irq_disable();
 238         rtc_wait_not_busy(rtc);
 239         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 240         if (rtc->type->has_irqwakeen)
 241                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
 242
 243         if (enabled) {
 244                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
 245                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 246         } else {
 247                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
 248                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 249         }
 250         rtc_wait_not_busy(rtc);
 251         rtc->type->unlock(rtc);
 252         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
 253         if (rtc->type->has_irqwakeen)
 254                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
 255         rtc->type->lock(rtc);
 256         local_irq_enable();
 257
 258         return 0;
 259 }
 260
 261 /* this hardware doesn't support "don't care" alarm fields */
 262 static int tm2bcd(struct rtc_time *tm)
 263 {
 264         if (rtc_valid_tm(tm) != 0)
 265                 return -EINVAL;
 266
 267         tm->tm_sec = bin2bcd(tm->tm_sec);
 268         tm->tm_min = bin2bcd(tm->tm_min);
 269         tm->tm_hour = bin2bcd(tm->tm_hour);
 270         tm->tm_mday = bin2bcd(tm->tm_mday);
 271
 272         tm->tm_mon = bin2bcd(tm->tm_mon + 1);
 273
 274         /* epoch == 1900 */
 275         if (tm->tm_year < 100 || tm->tm_year > 199)
 276                 return -EINVAL;
 277         tm->tm_year = bin2bcd(tm->tm_year - 100);
 278
 279         return 0;
 280 }
 281
 282 static void bcd2tm(struct rtc_time *tm)
 283 {
 284         tm->tm_sec = bcd2bin(tm->tm_sec);
 285         tm->tm_min = bcd2bin(tm->tm_min);
 286         tm->tm_hour = bcd2bin(tm->tm_hour);
 287         tm->tm_mday = bcd2bin(tm->tm_mday);
 288         tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
 289         /* epoch == 1900 */
 290         tm->tm_year = bcd2bin(tm->tm_year) + 100;
 291 }
 292
 293 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
 294 {
 295         tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
 296         tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
 297         tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
 298         tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
 299         tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
 300         tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
 301 }
 302
 303 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
 304 {
 305         struct omap_rtc *rtc = dev_get_drvdata(dev);
 306
 307         /* we don't report wday/yday/isdst ... */
 308         local_irq_disable();
 309         rtc_wait_not_busy(rtc);
 310         omap_rtc_read_time_raw(rtc, tm);
 311         local_irq_enable();
 312
 313         bcd2tm(tm);
 314
 315         return 0;
 316 }
 317
 318 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
 319 {
 320         struct omap_rtc *rtc = dev_get_drvdata(dev);
 321
 322         if (tm2bcd(tm) < 0)
 323                 return -EINVAL;
 324
 325         local_irq_disable();
 326         rtc_wait_not_busy(rtc);
 327
 328         rtc->type->unlock(rtc);
 329         rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
 330         rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
 331         rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
 332         rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
 333         rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
 334         rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
 335         rtc->type->lock(rtc);
 336
 337         local_irq_enable();
 338
 339         return 0;
 340 }
 341
 342 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
 343 {
 344         struct omap_rtc *rtc = dev_get_drvdata(dev);
 345         u8 interrupts;
 346
 347         local_irq_disable();
 348         rtc_wait_not_busy(rtc);
 349
 350         alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
 351         alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
 352         alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
 353         alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
 354         alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
 355         alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
 356
 357         local_irq_enable();
 358
 359         bcd2tm(&alm->time);
 360
 361         interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 362         alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
 363
 364         return 0;
 365 }
 366
 367 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
 368 {
 369         struct omap_rtc *rtc = dev_get_drvdata(dev);
 370         u8 reg, irqwake_reg = 0;
 371
 372         if (tm2bcd(&alm->time) < 0)
 373                 return -EINVAL;
 374
 375         local_irq_disable();
 376         rtc_wait_not_busy(rtc);
 377
 378         rtc->type->unlock(rtc);
 379         rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
 380         rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
 381         rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
 382         rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
 383         rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
 384         rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
 385
 386         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 387         if (rtc->type->has_irqwakeen)
 388                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
 389
 390         if (alm->enabled) {
 391                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
 392                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 393         } else {
 394                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
 395                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 396         }
 397         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
 398         if (rtc->type->has_irqwakeen)
 399                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
 400         rtc->type->lock(rtc);
 401
 402         local_irq_enable();
 403
 404         return 0;
 405 }
 406
 407 static struct omap_rtc *omap_rtc_power_off_rtc;
 408
 409 /*
 410  * omap_rtc_poweroff: RTC-controlled power off
 411  *
 412  * The RTC can be used to control an external PMIC via the pmic_power_en pin,
 413  * which can be configured to transition to OFF on ALARM2 events.
 414  *
 415  * Notes:
 416  * The two-second alarm offset is the shortest offset possible as the alarm
 417  * registers must be set before the next timer update and the offset
 418  * calculation is too heavy for everything to be done within a single access
 419  * period (~15 us).
 420  *
 421  * Called with local interrupts disabled.
 422  */
 423 static void omap_rtc_power_off(void)
 424 {
 425         struct omap_rtc *rtc = omap_rtc_power_off_rtc;
 426         struct rtc_time tm;
 427         unsigned long now;
 428         u32 val;
 429
 430         rtc->type->unlock(rtc);
 431         /* enable pmic_power_en control */
 432         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
 433         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
 434
 435         /* set alarm two seconds from now */
 436         omap_rtc_read_time_raw(rtc, &tm);
 437         bcd2tm(&tm);
 438         rtc_tm_to_time(&tm, &now);
 439         rtc_time_to_tm(now + 2, &tm);
 440
 441         if (tm2bcd(&tm) < 0) {
 442                 dev_err(&rtc->rtc->dev, "power off failed\n");
 443                 return;
 444         }
 445
 446         rtc_wait_not_busy(rtc);
 447
 448         rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
 449         rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
 450         rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
 451         rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
 452         rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
 453         rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
 454
 455         /*
 456          * enable ALARM2 interrupt
 457          *
 458          * NOTE: this fails on AM3352 if rtc_write (writeb) is used
 459          */
 460         val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 461         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
 462                         val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
 463         rtc->type->lock(rtc);
 464
 465         /*
 466          * Wait for alarm to trigger (within two seconds) and external PMIC to
 467          * power off the system. Add a 500 ms margin for external latencies
 468          * (e.g. debounce circuits).
 469          */
 470         mdelay(2500);
 471 }
 472
 473 static struct rtc_class_ops omap_rtc_ops = {
 474         .read_time      = omap_rtc_read_time,
 475         .set_time       = omap_rtc_set_time,
 476         .read_alarm     = omap_rtc_read_alarm,
 477         .set_alarm      = omap_rtc_set_alarm,
 478         .alarm_irq_enable = omap_rtc_alarm_irq_enable,
 479 };
 480
 481 static const struct omap_rtc_device_type omap_rtc_default_type = {
 482         .has_power_up_reset = true,
 483         .lock           = default_rtc_lock,
 484         .unlock         = default_rtc_unlock,
 485 };
 486
 487 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
 488         .has_32kclk_en  = true,
 489         .has_irqwakeen  = true,
 490         .has_pmic_mode  = true,
 491         .lock           = am3352_rtc_lock,
 492         .unlock         = am3352_rtc_unlock,
 493 };
 494
 495 static const struct omap_rtc_device_type omap_rtc_da830_type = {
 496         .lock           = am3352_rtc_lock,
 497         .unlock         = am3352_rtc_unlock,
 498 };
 499
 500 static const struct platform_device_id omap_rtc_id_table[] = {
 501         {
 502                 .name   = "omap_rtc",
 503                 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
 504         }, {
 505                 .name   = "am3352-rtc",
 506                 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
 507         }, {
 508                 .name   = "da830-rtc",
 509                 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
 510         }, {
 511                 /* sentinel */
 512         }
 513 };
 514 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
 515
 516 static const struct of_device_id omap_rtc_of_match[] = {
 517         {
 518                 .compatible     = "ti,am3352-rtc",
 519                 .data           = &omap_rtc_am3352_type,
 520         }, {
 521                 .compatible     = "ti,da830-rtc",
 522                 .data           = &omap_rtc_da830_type,
 523         }, {
 524                 /* sentinel */
 525         }
 526 };
 527 MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
 528
 529 static int omap_rtc_probe(struct platform_device *pdev)
 530 {
 531         struct omap_rtc *rtc;
 532         struct resource *res;
 533         u8 reg, mask, new_ctrl;
 534         const struct platform_device_id *id_entry;
 535         const struct of_device_id *of_id;
 536         int ret;
 537
 538         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
 539         if (!rtc)
 540                 return -ENOMEM;
 541
 542         of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
 543         if (of_id) {
 544                 rtc->type = of_id->data;
 545                 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
 546                                 of_property_read_bool(pdev->dev.of_node,
 547                                                 "system-power-controller");
 548         } else {
 549                 id_entry = platform_get_device_id(pdev);
 550                 rtc->type = (void *)id_entry->driver_data;
 551         }
 552
 553         rtc->irq_timer = platform_get_irq(pdev, 0);
 554         if (rtc->irq_timer <= 0)
 555                 return -ENOENT;
 556
 557         rtc->irq_alarm = platform_get_irq(pdev, 1);
 558         if (rtc->irq_alarm <= 0)
 559                 return -ENOENT;
 560
 561         rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
 562         if (!IS_ERR(rtc->clk))
 563                 rtc->has_ext_clk = true;
 564         else
 565                 rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
 566
 567         if (!IS_ERR(rtc->clk))
 568                 clk_prepare_enable(rtc->clk);
 569
 570         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 571         rtc->base = devm_ioremap_resource(&pdev->dev, res);
 572         if (IS_ERR(rtc->base))
 573                 return PTR_ERR(rtc->base);
 574
 575         platform_set_drvdata(pdev, rtc);
 576
 577         /* Enable the clock/module so that we can access the registers */
 578         pm_runtime_enable(&pdev->dev);
 579         pm_runtime_get_sync(&pdev->dev);
 580
 581         rtc->type->unlock(rtc);
 582
 583         /*
 584          * disable interrupts
 585          *
 586          * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
 587          */
 588         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 589
 590         /* enable RTC functional clock */
 591         if (rtc->type->has_32kclk_en) {
 592                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 593                 rtc_writel(rtc, OMAP_RTC_OSC_REG,
 594                                 reg | OMAP_RTC_OSC_32KCLK_EN);
 595         }
 596
 597         /* clear old status */
 598         reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 599
 600         mask = OMAP_RTC_STATUS_ALARM;
 601
 602         if (rtc->type->has_pmic_mode)
 603                 mask |= OMAP_RTC_STATUS_ALARM2;
 604
 605         if (rtc->type->has_power_up_reset) {
 606                 mask |= OMAP_RTC_STATUS_POWER_UP;
 607                 if (reg & OMAP_RTC_STATUS_POWER_UP)
 608                         dev_info(&pdev->dev, "RTC power up reset detected\n");
 609         }
 610
 611         if (reg & mask)
 612                 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
 613
 614         /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
 615         reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
 616         if (reg & OMAP_RTC_CTRL_STOP)
 617                 dev_info(&pdev->dev, "already running\n");
 618
 619         /* force to 24 hour mode */
 620         new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
 621         new_ctrl |= OMAP_RTC_CTRL_STOP;
 622
 623         /*
 624          * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
 625          *
 626          *  - Device wake-up capability setting should come through chip
 627          *    init logic. OMAP1 boards should initialize the "wakeup capable"
 628          *    flag in the platform device if the board is wired right for
 629          *    being woken up by RTC alarm. For OMAP-L138, this capability
 630          *    is built into the SoC by the "Deep Sleep" capability.
 631          *
 632          *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
 633          *    rather than nPWRON_RESET, should forcibly enable split
 634          *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
 635          *    is write-only, and always reads as zero...)
 636          */
 637
 638         if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
 639                 dev_info(&pdev->dev, "split power mode\n");
 640
 641         if (reg != new_ctrl)
 642                 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
 643
 644         /*
 645          * If we have the external clock then switch to it so we can keep
 646          * ticking across suspend.
 647          */
 648         if (rtc->has_ext_clk) {
 649                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 650                 reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
 651                 reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
 652                 rtc_writel(rtc, OMAP_RTC_OSC_REG, reg);
 653         }
 654
 655         rtc->type->lock(rtc);
 656
 657         device_init_wakeup(&pdev->dev, true);
 658
 659         rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
 660                         &omap_rtc_ops, THIS_MODULE);
 661         if (IS_ERR(rtc->rtc)) {
 662                 ret = PTR_ERR(rtc->rtc);
 663                 goto err;
 664         }
 665
 666         /* handle periodic and alarm irqs */
 667         ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
 668                         dev_name(&rtc->rtc->dev), rtc);
 669         if (ret)
 670                 goto err;
 671
 672         if (rtc->irq_timer != rtc->irq_alarm) {
 673                 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
 674                                 dev_name(&rtc->rtc->dev), rtc);
 675                 if (ret)
 676                         goto err;
 677         }
 678
 679         if (rtc->is_pmic_controller) {
 680                 if (!pm_power_off) {
 681                         omap_rtc_power_off_rtc = rtc;
 682                         pm_power_off = omap_rtc_power_off;
 683                 }
 684         }
 685
 686         return 0;
 687
 688 err:
 689         device_init_wakeup(&pdev->dev, false);
 690         rtc->type->lock(rtc);
 691         pm_runtime_put_sync(&pdev->dev);
 692         pm_runtime_disable(&pdev->dev);
 693
 694         return ret;
 695 }
 696
 697 static int __exit omap_rtc_remove(struct platform_device *pdev)
 698 {
 699         struct omap_rtc *rtc = platform_get_drvdata(pdev);
 700         u8 reg;
 701
 702         if (pm_power_off == omap_rtc_power_off &&
 703                         omap_rtc_power_off_rtc == rtc) {
 704                 pm_power_off = NULL;
 705                 omap_rtc_power_off_rtc = NULL;
 706         }
 707
 708         device_init_wakeup(&pdev->dev, 0);
 709
 710         if (!IS_ERR(rtc->clk))
 711                 clk_disable_unprepare(rtc->clk);
 712
 713         rtc->type->unlock(rtc);
 714         /* leave rtc running, but disable irqs */
 715         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 716
 717         if (rtc->has_ext_clk) {
 718                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 719                 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
 720                 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
 721         }
 722
 723         rtc->type->lock(rtc);
 724
 725         /* Disable the clock/module */
 726         pm_runtime_put_sync(&pdev->dev);
 727         pm_runtime_disable(&pdev->dev);
 728
 729         return 0;
 730 }
 731
 732 #ifdef CONFIG_PM_SLEEP
 733 static int omap_rtc_suspend(struct device *dev)
 734 {
 735         struct omap_rtc *rtc = dev_get_drvdata(dev);
 736
 737         rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 738
 739         rtc->type->unlock(rtc);
 740         /*
 741          * FIXME: the RTC alarm is not currently acting as a wakeup event
 742          * source on some platforms, and in fact this enable() call is just
 743          * saving a flag that's never used...
 744          */
 745         if (device_may_wakeup(dev))
 746                 enable_irq_wake(rtc->irq_alarm);
 747         else
 748                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 749         rtc->type->lock(rtc);
 750
 751         /* Disable the clock/module */
 752         pm_runtime_put_sync(dev);
 753
 754         return 0;
 755 }
 756
 757 static int omap_rtc_resume(struct device *dev)
 758 {
 759         struct omap_rtc *rtc = dev_get_drvdata(dev);
 760
 761         /* Enable the clock/module so that we can access the registers */
 762         pm_runtime_get_sync(dev);
 763
 764         rtc->type->unlock(rtc);
 765         if (device_may_wakeup(dev))
 766                 disable_irq_wake(rtc->irq_alarm);
 767         else
 768                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
 769         rtc->type->lock(rtc);
 770
 771         return 0;
 772 }
 773 #endif
 774
 775 static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume);
 776
 777 static void omap_rtc_shutdown(struct platform_device *pdev)
 778 {
 779         struct omap_rtc *rtc = platform_get_drvdata(pdev);
 780         u8 mask;
 781
 782         /*
 783          * Keep the ALARM interrupt enabled to allow the system to power up on
 784          * alarm events.
 785          */
 786         rtc->type->unlock(rtc);
 787         mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 788         mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
 789         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
 790         rtc->type->lock(rtc);
 791 }
 792
 793 static struct platform_driver omap_rtc_driver = {
 794         .probe          = omap_rtc_probe,
 795         .remove         = __exit_p(omap_rtc_remove),
 796         .shutdown       = omap_rtc_shutdown,
 797         .driver         = {
 798                 .name   = "omap_rtc",
 799                 .pm     = &omap_rtc_pm_ops,
 800                 .of_match_table = omap_rtc_of_match,
 801         },
 802         .id_table       = omap_rtc_id_table,
 803 };
 804
 805 module_platform_driver(omap_rtc_driver);
 806
 807 MODULE_ALIAS("platform:omap_rtc");
 808 MODULE_AUTHOR("George G. Davis (and others)");
 809 MODULE_LICENSE("GPL");