2 * Allwinner A31 SoCs pinctrl driver.
4 * Copyright (C) 2014 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
16 #include <linux/of_device.h>
17 #include <linux/pinctrl/pinctrl.h>
19 #include "pinctrl-sunxi.h"
21 static const struct sunxi_desc_pin sun6i_a31_pins[] = {
22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
26 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */
27 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
30 SUNXI_FUNCTION(0x0, "gpio_in"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
33 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */
34 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
35 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
36 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
37 SUNXI_FUNCTION(0x0, "gpio_in"),
38 SUNXI_FUNCTION(0x1, "gpio_out"),
39 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
40 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */
41 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
42 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
47 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */
48 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
49 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
54 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */
55 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
56 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
57 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
58 SUNXI_FUNCTION(0x0, "gpio_in"),
59 SUNXI_FUNCTION(0x1, "gpio_out"),
60 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
61 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */
62 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
63 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
65 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
68 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */
69 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
70 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
71 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
72 SUNXI_FUNCTION(0x0, "gpio_in"),
73 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
75 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */
76 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
77 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
82 SUNXI_FUNCTION(0x3, "lcd1"), /* D8 */
83 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
84 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
85 SUNXI_FUNCTION(0x0, "gpio_in"),
86 SUNXI_FUNCTION(0x1, "gpio_out"),
87 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
88 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */
89 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
90 SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
91 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
92 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
93 SUNXI_FUNCTION(0x0, "gpio_in"),
94 SUNXI_FUNCTION(0x1, "gpio_out"),
95 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
96 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */
97 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
98 SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
99 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
100 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
101 SUNXI_FUNCTION(0x0, "gpio_in"),
102 SUNXI_FUNCTION(0x1, "gpio_out"),
103 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
104 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */
105 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
106 SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
107 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
108 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
109 SUNXI_FUNCTION(0x0, "gpio_in"),
110 SUNXI_FUNCTION(0x1, "gpio_out"),
111 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
112 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */
113 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
114 SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
115 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
116 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
117 SUNXI_FUNCTION(0x0, "gpio_in"),
118 SUNXI_FUNCTION(0x1, "gpio_out"),
119 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
120 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */
121 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
122 SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
123 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
128 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */
129 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
130 SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
131 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
136 SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
137 SUNXI_FUNCTION(0x4, "clk_out_a"),
138 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
139 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
140 SUNXI_FUNCTION(0x0, "gpio_in"),
141 SUNXI_FUNCTION(0x1, "gpio_out"),
142 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
143 SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
144 SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
145 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
146 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
147 SUNXI_FUNCTION(0x0, "gpio_in"),
148 SUNXI_FUNCTION(0x1, "gpio_out"),
149 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
150 SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
151 SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
152 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
153 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
154 SUNXI_FUNCTION(0x0, "gpio_in"),
155 SUNXI_FUNCTION(0x1, "gpio_out"),
156 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
157 SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
158 SUNXI_FUNCTION(0x4, "clk_out_b"),
159 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
164 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */
165 SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
166 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
171 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */
172 SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
173 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
174 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
175 SUNXI_FUNCTION(0x0, "gpio_in"),
176 SUNXI_FUNCTION(0x1, "gpio_out"),
177 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
178 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */
179 SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
180 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
185 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */
186 SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
187 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
188 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
189 SUNXI_FUNCTION(0x0, "gpio_in"),
190 SUNXI_FUNCTION(0x1, "gpio_out"),
191 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
192 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */
193 SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
194 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
199 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */
200 SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
201 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
202 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
203 SUNXI_FUNCTION(0x0, "gpio_in"),
204 SUNXI_FUNCTION(0x1, "gpio_out"),
205 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
206 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */
207 SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
208 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
213 SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
214 SUNXI_FUNCTION(0x4, "clk_out_c"),
215 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
216 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
217 SUNXI_FUNCTION(0x0, "gpio_in"),
218 SUNXI_FUNCTION(0x1, "gpio_out"),
219 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
220 SUNXI_FUNCTION(0x3, "lcd1"), /* VSYNC */
221 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
223 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
224 SUNXI_FUNCTION(0x0, "gpio_in"),
225 SUNXI_FUNCTION(0x1, "gpio_out"),
226 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
227 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
228 SUNXI_FUNCTION(0x4, "csi"), /* MCLK1 */
229 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
230 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
231 SUNXI_FUNCTION(0x0, "gpio_in"),
232 SUNXI_FUNCTION(0x1, "gpio_out"),
233 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
234 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
235 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
236 SUNXI_FUNCTION(0x0, "gpio_in"),
237 SUNXI_FUNCTION(0x1, "gpio_out"),
238 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
239 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
240 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
241 SUNXI_FUNCTION(0x0, "gpio_in"),
242 SUNXI_FUNCTION(0x1, "gpio_out"),
243 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
244 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
245 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
246 SUNXI_FUNCTION(0x0, "gpio_in"),
247 SUNXI_FUNCTION(0x1, "gpio_out"),
248 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
249 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
250 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
255 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
256 SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
257 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
258 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
259 SUNXI_FUNCTION(0x0, "gpio_in"),
260 SUNXI_FUNCTION(0x1, "gpio_out"),
261 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
262 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
263 SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
264 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
269 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
271 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
272 SUNXI_FUNCTION(0x0, "gpio_in"),
273 SUNXI_FUNCTION(0x1, "gpio_out"),
274 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
275 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
276 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
277 SUNXI_FUNCTION(0x0, "gpio_in"),
278 SUNXI_FUNCTION(0x1, "gpio_out"),
279 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
280 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
281 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
282 SUNXI_FUNCTION(0x0, "gpio_in"),
283 SUNXI_FUNCTION(0x1, "gpio_out"),
284 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
285 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
286 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
287 SUNXI_FUNCTION(0x0, "gpio_in"),
288 SUNXI_FUNCTION(0x1, "gpio_out"),
289 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
290 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
291 SUNXI_FUNCTION(0x0, "gpio_in"),
292 SUNXI_FUNCTION(0x1, "gpio_out"),
293 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
294 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
295 SUNXI_FUNCTION(0x0, "gpio_in"),
296 SUNXI_FUNCTION(0x1, "gpio_out"),
297 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
298 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
299 SUNXI_FUNCTION(0x0, "gpio_in"),
300 SUNXI_FUNCTION(0x1, "gpio_out"),
301 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
302 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
303 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
304 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
305 SUNXI_FUNCTION(0x0, "gpio_in"),
306 SUNXI_FUNCTION(0x1, "gpio_out"),
307 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
308 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
309 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
310 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
311 SUNXI_FUNCTION(0x0, "gpio_in"),
312 SUNXI_FUNCTION(0x1, "gpio_out"),
313 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
314 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
315 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
316 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
317 SUNXI_FUNCTION(0x0, "gpio_in"),
318 SUNXI_FUNCTION(0x1, "gpio_out"),
319 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
320 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
321 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
326 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
327 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
332 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
333 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
334 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
335 SUNXI_FUNCTION(0x0, "gpio_in"),
336 SUNXI_FUNCTION(0x1, "gpio_out"),
337 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
338 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
339 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
340 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
341 SUNXI_FUNCTION(0x0, "gpio_in"),
342 SUNXI_FUNCTION(0x1, "gpio_out"),
343 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
344 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
345 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
346 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
347 SUNXI_FUNCTION(0x0, "gpio_in"),
348 SUNXI_FUNCTION(0x1, "gpio_out"),
349 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
350 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
351 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
352 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
353 SUNXI_FUNCTION(0x0, "gpio_in"),
354 SUNXI_FUNCTION(0x1, "gpio_out"),
355 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
356 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
357 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
358 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
359 SUNXI_FUNCTION(0x0, "gpio_in"),
360 SUNXI_FUNCTION(0x1, "gpio_out"),
361 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
362 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
363 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
364 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out"),
366 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
367 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
368 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
369 SUNXI_FUNCTION(0x0, "gpio_in"),
370 SUNXI_FUNCTION(0x1, "gpio_out"),
371 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
372 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
373 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
374 SUNXI_FUNCTION(0x0, "gpio_in"),
375 SUNXI_FUNCTION(0x1, "gpio_out"),
376 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
377 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
378 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
379 SUNXI_FUNCTION(0x0, "gpio_in"),
380 SUNXI_FUNCTION(0x1, "gpio_out"),
381 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
382 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
383 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
384 SUNXI_FUNCTION(0x0, "gpio_in"),
385 SUNXI_FUNCTION(0x1, "gpio_out"),
386 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
387 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
388 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
389 SUNXI_FUNCTION(0x0, "gpio_in"),
390 SUNXI_FUNCTION(0x1, "gpio_out"),
391 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
392 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
393 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
394 SUNXI_FUNCTION(0x0, "gpio_in"),
395 SUNXI_FUNCTION(0x1, "gpio_out"),
396 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
397 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
398 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
399 SUNXI_FUNCTION(0x0, "gpio_in"),
400 SUNXI_FUNCTION(0x1, "gpio_out"),
401 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
402 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
403 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
404 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
405 SUNXI_FUNCTION(0x0, "gpio_in"),
406 SUNXI_FUNCTION(0x1, "gpio_out"),
407 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
408 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
409 SUNXI_FUNCTION(0x0, "gpio_in"),
410 SUNXI_FUNCTION(0x1, "gpio_out"),
411 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
421 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
426 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
431 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
436 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
441 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
442 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
446 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
447 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
448 SUNXI_FUNCTION(0x0, "gpio_in"),
449 SUNXI_FUNCTION(0x1, "gpio_out"),
450 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
451 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
456 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
461 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
466 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
471 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
476 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
481 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
482 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
483 SUNXI_FUNCTION(0x0, "gpio_in"),
484 SUNXI_FUNCTION(0x1, "gpio_out"),
485 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
486 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
487 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
488 SUNXI_FUNCTION(0x0, "gpio_in"),
489 SUNXI_FUNCTION(0x1, "gpio_out"),
490 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
491 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
492 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
493 SUNXI_FUNCTION(0x0, "gpio_in"),
494 SUNXI_FUNCTION(0x1, "gpio_out"),
495 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
496 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
497 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
498 SUNXI_FUNCTION(0x0, "gpio_in"),
499 SUNXI_FUNCTION(0x1, "gpio_out"),
500 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
501 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
502 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
503 SUNXI_FUNCTION(0x0, "gpio_in"),
504 SUNXI_FUNCTION(0x1, "gpio_out"),
505 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
506 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
507 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
508 SUNXI_FUNCTION(0x0, "gpio_in"),
509 SUNXI_FUNCTION(0x1, "gpio_out"),
510 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
511 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
512 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
513 SUNXI_FUNCTION(0x0, "gpio_in"),
514 SUNXI_FUNCTION(0x1, "gpio_out"),
515 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
516 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
517 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
518 SUNXI_FUNCTION(0x0, "gpio_in"),
519 SUNXI_FUNCTION(0x1, "gpio_out"),
520 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
521 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
522 SUNXI_FUNCTION(0x0, "gpio_in"),
523 SUNXI_FUNCTION(0x1, "gpio_out"),
524 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
525 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
526 SUNXI_FUNCTION(0x0, "gpio_in"),
527 SUNXI_FUNCTION(0x1, "gpio_out"),
528 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
533 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
534 SUNXI_FUNCTION(0x0, "gpio_in"),
535 SUNXI_FUNCTION(0x1, "gpio_out"),
536 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
537 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
538 SUNXI_FUNCTION(0x0, "gpio_in"),
539 SUNXI_FUNCTION(0x1, "gpio_out"),
540 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
541 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
542 SUNXI_FUNCTION(0x0, "gpio_in"),
543 SUNXI_FUNCTION(0x1, "gpio_out"),
544 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
554 SUNXI_FUNCTION(0x3, "ts"), /* CLK */
555 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
556 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
557 SUNXI_FUNCTION(0x0, "gpio_in"),
558 SUNXI_FUNCTION(0x1, "gpio_out"),
559 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
560 SUNXI_FUNCTION(0x3, "ts"), /* ERR */
561 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
562 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
563 SUNXI_FUNCTION(0x0, "gpio_in"),
564 SUNXI_FUNCTION(0x1, "gpio_out"),
565 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
566 SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
567 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
568 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
569 SUNXI_FUNCTION(0x0, "gpio_in"),
570 SUNXI_FUNCTION(0x1, "gpio_out"),
571 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
572 SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
573 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
574 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
575 SUNXI_FUNCTION(0x0, "gpio_in"),
576 SUNXI_FUNCTION(0x1, "gpio_out"),
577 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
578 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
579 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
580 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
581 SUNXI_FUNCTION(0x0, "gpio_in"),
582 SUNXI_FUNCTION(0x1, "gpio_out"),
583 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
584 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
585 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
586 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
587 SUNXI_FUNCTION(0x0, "gpio_in"),
588 SUNXI_FUNCTION(0x1, "gpio_out"),
589 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
590 SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
591 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
592 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
593 SUNXI_FUNCTION(0x0, "gpio_in"),
594 SUNXI_FUNCTION(0x1, "gpio_out"),
595 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
596 SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
597 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
598 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
599 SUNXI_FUNCTION(0x0, "gpio_in"),
600 SUNXI_FUNCTION(0x1, "gpio_out"),
601 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
602 SUNXI_FUNCTION(0x3, "ts"), /* D0 */
603 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
604 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
605 SUNXI_FUNCTION(0x0, "gpio_in"),
606 SUNXI_FUNCTION(0x1, "gpio_out"),
607 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
608 SUNXI_FUNCTION(0x3, "ts"), /* D1 */
609 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
610 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
611 SUNXI_FUNCTION(0x0, "gpio_in"),
612 SUNXI_FUNCTION(0x1, "gpio_out"),
613 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
614 SUNXI_FUNCTION(0x3, "ts"), /* D2 */
615 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
616 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
617 SUNXI_FUNCTION(0x0, "gpio_in"),
618 SUNXI_FUNCTION(0x1, "gpio_out"),
619 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
620 SUNXI_FUNCTION(0x3, "ts"), /* D3 */
621 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
622 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
623 SUNXI_FUNCTION(0x0, "gpio_in"),
624 SUNXI_FUNCTION(0x1, "gpio_out"),
625 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
626 SUNXI_FUNCTION(0x3, "ts"), /* D4 */
627 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out"),
631 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
632 SUNXI_FUNCTION(0x3, "ts"), /* D5 */
633 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
634 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
635 SUNXI_FUNCTION(0x0, "gpio_in"),
636 SUNXI_FUNCTION(0x1, "gpio_out"),
637 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
638 SUNXI_FUNCTION(0x3, "ts"), /* D6 */
639 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
640 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
641 SUNXI_FUNCTION(0x0, "gpio_in"),
642 SUNXI_FUNCTION(0x1, "gpio_out"),
643 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
644 SUNXI_FUNCTION(0x3, "ts"), /* D7 */
645 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
646 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
647 SUNXI_FUNCTION(0x0, "gpio_in"),
648 SUNXI_FUNCTION(0x1, "gpio_out"),
649 SUNXI_FUNCTION(0x2, "csi"), /* MIPI CSI MCLK */
650 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
652 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
653 SUNXI_FUNCTION(0x0, "gpio_in"),
654 SUNXI_FUNCTION(0x1, "gpio_out"),
655 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
656 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
658 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
661 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
662 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
663 SUNXI_FUNCTION(0x0, "gpio_in"),
664 SUNXI_FUNCTION(0x1, "gpio_out"),
665 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
666 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
667 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
668 SUNXI_FUNCTION(0x0, "gpio_in"),
669 SUNXI_FUNCTION(0x1, "gpio_out"),
670 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
671 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
672 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
673 SUNXI_FUNCTION(0x0, "gpio_in"),
674 SUNXI_FUNCTION(0x1, "gpio_out"),
675 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
676 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
677 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
678 SUNXI_FUNCTION(0x0, "gpio_in"),
679 SUNXI_FUNCTION(0x1, "gpio_out"),
680 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
681 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
683 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
684 SUNXI_FUNCTION(0x0, "gpio_in"),
685 SUNXI_FUNCTION(0x1, "gpio_out"),
686 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
687 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
688 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
689 SUNXI_FUNCTION(0x0, "gpio_in"),
690 SUNXI_FUNCTION(0x1, "gpio_out"),
691 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
692 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
693 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
694 SUNXI_FUNCTION(0x0, "gpio_in"),
695 SUNXI_FUNCTION(0x1, "gpio_out"),
696 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
697 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
698 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
699 SUNXI_FUNCTION(0x0, "gpio_in"),
700 SUNXI_FUNCTION(0x1, "gpio_out"),
701 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
702 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
703 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
704 SUNXI_FUNCTION(0x0, "gpio_in"),
705 SUNXI_FUNCTION(0x1, "gpio_out"),
706 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
707 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
708 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
709 SUNXI_FUNCTION(0x0, "gpio_in"),
710 SUNXI_FUNCTION(0x1, "gpio_out"),
711 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
712 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
713 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
714 SUNXI_FUNCTION(0x0, "gpio_in"),
715 SUNXI_FUNCTION(0x1, "gpio_out"),
716 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
717 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
718 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
719 SUNXI_FUNCTION(0x0, "gpio_in"),
720 SUNXI_FUNCTION(0x1, "gpio_out"),
721 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
722 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
723 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
724 SUNXI_FUNCTION(0x0, "gpio_in"),
725 SUNXI_FUNCTION(0x1, "gpio_out"),
726 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
727 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
728 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
729 SUNXI_FUNCTION(0x0, "gpio_in"),
730 SUNXI_FUNCTION(0x1, "gpio_out"),
731 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
732 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
733 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
734 SUNXI_FUNCTION(0x0, "gpio_in"),
735 SUNXI_FUNCTION(0x1, "gpio_out"),
736 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
737 SUNXI_FUNCTION(0x3, "usb"), /* DP3 */
738 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
739 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
740 SUNXI_FUNCTION(0x0, "gpio_in"),
741 SUNXI_FUNCTION(0x1, "gpio_out"),
742 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
743 SUNXI_FUNCTION(0x3, "usb"), /* DM3 */
744 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
745 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
746 SUNXI_FUNCTION(0x0, "gpio_in"),
747 SUNXI_FUNCTION(0x1, "gpio_out"),
748 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
749 SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
750 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
751 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
752 SUNXI_FUNCTION(0x0, "gpio_in"),
753 SUNXI_FUNCTION(0x1, "gpio_out"),
754 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
755 SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
756 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
757 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
758 SUNXI_FUNCTION(0x0, "gpio_in"),
759 SUNXI_FUNCTION(0x1, "gpio_out"),
760 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
761 SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
762 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
763 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
764 SUNXI_FUNCTION(0x0, "gpio_in"),
765 SUNXI_FUNCTION(0x1, "gpio_out"),
766 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
767 SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
768 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
769 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
770 SUNXI_FUNCTION(0x0, "gpio_in"),
771 SUNXI_FUNCTION(0x1, "gpio_out"),
772 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
773 SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
774 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
775 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
776 SUNXI_FUNCTION(0x0, "gpio_in"),
777 SUNXI_FUNCTION(0x1, "gpio_out"),
778 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
779 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
780 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
781 SUNXI_FUNCTION(0x0, "gpio_in"),
782 SUNXI_FUNCTION(0x1, "gpio_out"),
783 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
784 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
786 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
787 SUNXI_FUNCTION(0x0, "gpio_in"),
788 SUNXI_FUNCTION(0x1, "gpio_out"),
789 SUNXI_FUNCTION(0x2, "nand1")), /* WE */
790 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
791 SUNXI_FUNCTION(0x0, "gpio_in"),
792 SUNXI_FUNCTION(0x1, "gpio_out"),
793 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
794 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
795 SUNXI_FUNCTION(0x0, "gpio_in"),
796 SUNXI_FUNCTION(0x1, "gpio_out"),
797 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
798 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
799 SUNXI_FUNCTION(0x0, "gpio_in"),
800 SUNXI_FUNCTION(0x1, "gpio_out"),
801 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
802 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
803 SUNXI_FUNCTION(0x0, "gpio_in"),
804 SUNXI_FUNCTION(0x1, "gpio_out"),
805 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
806 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
807 SUNXI_FUNCTION(0x0, "gpio_in"),
808 SUNXI_FUNCTION(0x1, "gpio_out"),
809 SUNXI_FUNCTION(0x2, "nand1")), /* RE */
810 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
811 SUNXI_FUNCTION(0x0, "gpio_in"),
812 SUNXI_FUNCTION(0x1, "gpio_out"),
813 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
814 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
815 SUNXI_FUNCTION(0x0, "gpio_in"),
816 SUNXI_FUNCTION(0x1, "gpio_out"),
817 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
818 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
819 SUNXI_FUNCTION(0x0, "gpio_in"),
820 SUNXI_FUNCTION(0x1, "gpio_out"),
821 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
822 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
823 SUNXI_FUNCTION(0x0, "gpio_in"),
824 SUNXI_FUNCTION(0x1, "gpio_out"),
825 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
826 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
827 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
828 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
829 SUNXI_FUNCTION(0x0, "gpio_in"),
830 SUNXI_FUNCTION(0x1, "gpio_out"),
831 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
832 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
833 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
834 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
835 SUNXI_FUNCTION(0x0, "gpio_in"),
836 SUNXI_FUNCTION(0x1, "gpio_out"),
837 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
838 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
839 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
840 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
841 SUNXI_FUNCTION(0x0, "gpio_in"),
842 SUNXI_FUNCTION(0x1, "gpio_out"),
843 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
844 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
845 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
846 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
847 SUNXI_FUNCTION(0x0, "gpio_in"),
848 SUNXI_FUNCTION(0x1, "gpio_out"),
849 SUNXI_FUNCTION(0x2, "pwm0")),
850 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
851 SUNXI_FUNCTION(0x0, "gpio_in"),
852 SUNXI_FUNCTION(0x1, "gpio_out"),
853 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
854 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
855 SUNXI_FUNCTION(0x0, "gpio_in"),
856 SUNXI_FUNCTION(0x1, "gpio_out"),
857 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
858 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
859 SUNXI_FUNCTION(0x0, "gpio_in"),
860 SUNXI_FUNCTION(0x1, "gpio_out"),
861 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
862 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
863 SUNXI_FUNCTION(0x0, "gpio_in"),
864 SUNXI_FUNCTION(0x1, "gpio_out"),
865 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
866 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
867 SUNXI_FUNCTION(0x0, "gpio_in"),
868 SUNXI_FUNCTION(0x1, "gpio_out"),
869 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
870 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
871 SUNXI_FUNCTION(0x0, "gpio_in"),
872 SUNXI_FUNCTION(0x1, "gpio_out"),
873 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
874 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
875 SUNXI_FUNCTION(0x0, "gpio_in"),
876 SUNXI_FUNCTION(0x1, "gpio_out"),
877 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
878 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
879 SUNXI_FUNCTION(0x0, "gpio_in"),
880 SUNXI_FUNCTION(0x1, "gpio_out"),
881 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
882 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
883 SUNXI_FUNCTION(0x0, "gpio_in"),
884 SUNXI_FUNCTION(0x1, "gpio_out")),
885 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
886 SUNXI_FUNCTION(0x0, "gpio_in"),
887 SUNXI_FUNCTION(0x1, "gpio_out")),
888 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
889 SUNXI_FUNCTION(0x0, "gpio_in"),
890 SUNXI_FUNCTION(0x1, "gpio_out")),
891 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
892 SUNXI_FUNCTION(0x0, "gpio_in"),
893 SUNXI_FUNCTION(0x1, "gpio_out")),
894 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
895 SUNXI_FUNCTION(0x0, "gpio_in"),
896 SUNXI_FUNCTION(0x1, "gpio_out")),
897 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
898 SUNXI_FUNCTION(0x0, "gpio_in"),
899 SUNXI_FUNCTION(0x1, "gpio_out")),
900 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out")),
903 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 29),
904 SUNXI_FUNCTION(0x0, "gpio_in"),
905 SUNXI_FUNCTION(0x1, "gpio_out"),
906 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
907 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 30),
908 SUNXI_FUNCTION(0x0, "gpio_in"),
909 SUNXI_FUNCTION(0x1, "gpio_out"),
910 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
913 static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
914 .pins = sun6i_a31_pins,
915 .npins = ARRAY_SIZE(sun6i_a31_pins),
919 static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
921 return sunxi_pinctrl_init(pdev,
922 &sun6i_a31_pinctrl_data);
925 static const struct of_device_id sun6i_a31_pinctrl_match[] = {
926 { .compatible = "allwinner,sun6i-a31-pinctrl", },
929 MODULE_DEVICE_TABLE(of, sun6i_a31_pinctrl_match);
931 static struct platform_driver sun6i_a31_pinctrl_driver = {
932 .probe = sun6i_a31_pinctrl_probe,
934 .name = "sun6i-a31-pinctrl",
935 .of_match_table = sun6i_a31_pinctrl_match,
938 module_platform_driver(sun6i_a31_pinctrl_driver);
940 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
941 MODULE_DESCRIPTION("Allwinner A31 pinctrl driver");
942 MODULE_LICENSE("GPL");
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