kernel/drivers/pinctrl/qcom/pinctrl-msm.c

   1 /*
   2  * Copyright (c) 2013, Sony Mobile Communications AB.
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/pinctrl/pinctrl.h>
  23 #include <linux/pinctrl/pinmux.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26 #include <linux/slab.h>
  27 #include <linux/gpio.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/reboot.h>
  31
  32 #include "../core.h"
  33 #include "../pinconf.h"
  34 #include "pinctrl-msm.h"
  35 #include "../pinctrl-utils.h"
  36
  37 #define MAX_NR_GPIO 300
  38 #define PS_HOLD_OFFSET 0x820
  39
  40 /**
  41  * struct msm_pinctrl - state for a pinctrl-msm device
  42  * @dev:            device handle.
  43  * @pctrl:          pinctrl handle.
  44  * @chip:           gpiochip handle.
  45  * @restart_nb:     restart notifier block.
  46  * @irq:            parent irq for the TLMM irq_chip.
  47  * @lock:           Spinlock to protect register resources as well
  48  *                  as msm_pinctrl data structures.
  49  * @enabled_irqs:   Bitmap of currently enabled irqs.
  50  * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
  51  *                  detection.
  52  * @soc;            Reference to soc_data of platform specific data.
  53  * @regs:           Base address for the TLMM register map.
  54  */
  55 struct msm_pinctrl {
  56         struct device *dev;
  57         struct pinctrl_dev *pctrl;
  58         struct gpio_chip chip;
  59         struct notifier_block restart_nb;
  60         int irq;
  61
  62         spinlock_t lock;
  63
  64         DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
  65         DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
  66
  67         const struct msm_pinctrl_soc_data *soc;
  68         void __iomem *regs;
  69 };
  70
  71 static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc)
  72 {
  73         return container_of(gc, struct msm_pinctrl, chip);
  74 }
  75
  76 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
  77 {
  78         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  79
  80         return pctrl->soc->ngroups;
  81 }
  82
  83 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
  84                                       unsigned group)
  85 {
  86         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  87
  88         return pctrl->soc->groups[group].name;
  89 }
  90
  91 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
  92                               unsigned group,
  93                               const unsigned **pins,
  94                               unsigned *num_pins)
  95 {
  96         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  97
  98         *pins = pctrl->soc->groups[group].pins;
  99         *num_pins = pctrl->soc->groups[group].npins;
 100         return 0;
 101 }
 102
 103 static const struct pinctrl_ops msm_pinctrl_ops = {
 104         .get_groups_count       = msm_get_groups_count,
 105         .get_group_name         = msm_get_group_name,
 106         .get_group_pins         = msm_get_group_pins,
 107         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 108         .dt_free_map            = pinctrl_utils_dt_free_map,
 109 };
 110
 111 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
 112 {
 113         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 114
 115         return pctrl->soc->nfunctions;
 116 }
 117
 118 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
 119                                          unsigned function)
 120 {
 121         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 122
 123         return pctrl->soc->functions[function].name;
 124 }
 125
 126 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
 127                                    unsigned function,
 128                                    const char * const **groups,
 129                                    unsigned * const num_groups)
 130 {
 131         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 132
 133         *groups = pctrl->soc->functions[function].groups;
 134         *num_groups = pctrl->soc->functions[function].ngroups;
 135         return 0;
 136 }
 137
 138 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 139                               unsigned function,
 140                               unsigned group)
 141 {
 142         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 143         const struct msm_pingroup *g;
 144         unsigned long flags;
 145         u32 val;
 146         int i;
 147
 148         g = &pctrl->soc->groups[group];
 149
 150         for (i = 0; i < g->nfuncs; i++) {
 151                 if (g->funcs[i] == function)
 152                         break;
 153         }
 154
 155         if (WARN_ON(i == g->nfuncs))
 156                 return -EINVAL;
 157
 158         spin_lock_irqsave(&pctrl->lock, flags);
 159
 160         val = readl(pctrl->regs + g->ctl_reg);
 161         val &= ~(0x7 << g->mux_bit);
 162         val |= i << g->mux_bit;
 163         writel(val, pctrl->regs + g->ctl_reg);
 164
 165         spin_unlock_irqrestore(&pctrl->lock, flags);
 166
 167         return 0;
 168 }
 169
 170 static const struct pinmux_ops msm_pinmux_ops = {
 171         .get_functions_count    = msm_get_functions_count,
 172         .get_function_name      = msm_get_function_name,
 173         .get_function_groups    = msm_get_function_groups,
 174         .set_mux                = msm_pinmux_set_mux,
 175 };
 176
 177 static int msm_config_reg(struct msm_pinctrl *pctrl,
 178                           const struct msm_pingroup *g,
 179                           unsigned param,
 180                           unsigned *mask,
 181                           unsigned *bit)
 182 {
 183         switch (param) {
 184         case PIN_CONFIG_BIAS_DISABLE:
 185         case PIN_CONFIG_BIAS_PULL_DOWN:
 186         case PIN_CONFIG_BIAS_BUS_HOLD:
 187         case PIN_CONFIG_BIAS_PULL_UP:
 188                 *bit = g->pull_bit;
 189                 *mask = 3;
 190                 break;
 191         case PIN_CONFIG_DRIVE_STRENGTH:
 192                 *bit = g->drv_bit;
 193                 *mask = 7;
 194                 break;
 195         case PIN_CONFIG_OUTPUT:
 196         case PIN_CONFIG_INPUT_ENABLE:
 197                 *bit = g->oe_bit;
 198                 *mask = 1;
 199                 break;
 200         default:
 201                 return -ENOTSUPP;
 202         }
 203
 204         return 0;
 205 }
 206
 207 #define MSM_NO_PULL     0
 208 #define MSM_PULL_DOWN   1
 209 #define MSM_KEEPER      2
 210 #define MSM_PULL_UP     3
 211
 212 static unsigned msm_regval_to_drive(u32 val)
 213 {
 214         return (val + 1) * 2;
 215 }
 216
 217 static int msm_config_group_get(struct pinctrl_dev *pctldev,
 218                                 unsigned int group,
 219                                 unsigned long *config)
 220 {
 221         const struct msm_pingroup *g;
 222         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 223         unsigned param = pinconf_to_config_param(*config);
 224         unsigned mask;
 225         unsigned arg;
 226         unsigned bit;
 227         int ret;
 228         u32 val;
 229
 230         g = &pctrl->soc->groups[group];
 231
 232         ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 233         if (ret < 0)
 234                 return ret;
 235
 236         val = readl(pctrl->regs + g->ctl_reg);
 237         arg = (val >> bit) & mask;
 238
 239         /* Convert register value to pinconf value */
 240         switch (param) {
 241         case PIN_CONFIG_BIAS_DISABLE:
 242                 arg = arg == MSM_NO_PULL;
 243                 break;
 244         case PIN_CONFIG_BIAS_PULL_DOWN:
 245                 arg = arg == MSM_PULL_DOWN;
 246                 break;
 247         case PIN_CONFIG_BIAS_BUS_HOLD:
 248                 arg = arg == MSM_KEEPER;
 249                 break;
 250         case PIN_CONFIG_BIAS_PULL_UP:
 251                 arg = arg == MSM_PULL_UP;
 252                 break;
 253         case PIN_CONFIG_DRIVE_STRENGTH:
 254                 arg = msm_regval_to_drive(arg);
 255                 break;
 256         case PIN_CONFIG_OUTPUT:
 257                 /* Pin is not output */
 258                 if (!arg)
 259                         return -EINVAL;
 260
 261                 val = readl(pctrl->regs + g->io_reg);
 262                 arg = !!(val & BIT(g->in_bit));
 263                 break;
 264         case PIN_CONFIG_INPUT_ENABLE:
 265                 /* Pin is output */
 266                 if (arg)
 267                         return -EINVAL;
 268                 arg = 1;
 269                 break;
 270         default:
 271                 return -ENOTSUPP;
 272         }
 273
 274         *config = pinconf_to_config_packed(param, arg);
 275
 276         return 0;
 277 }
 278
 279 static int msm_config_group_set(struct pinctrl_dev *pctldev,
 280                                 unsigned group,
 281                                 unsigned long *configs,
 282                                 unsigned num_configs)
 283 {
 284         const struct msm_pingroup *g;
 285         struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 286         unsigned long flags;
 287         unsigned param;
 288         unsigned mask;
 289         unsigned arg;
 290         unsigned bit;
 291         int ret;
 292         u32 val;
 293         int i;
 294
 295         g = &pctrl->soc->groups[group];
 296
 297         for (i = 0; i < num_configs; i++) {
 298                 param = pinconf_to_config_param(configs[i]);
 299                 arg = pinconf_to_config_argument(configs[i]);
 300
 301                 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 302                 if (ret < 0)
 303                         return ret;
 304
 305                 /* Convert pinconf values to register values */
 306                 switch (param) {
 307                 case PIN_CONFIG_BIAS_DISABLE:
 308                         arg = MSM_NO_PULL;
 309                         break;
 310                 case PIN_CONFIG_BIAS_PULL_DOWN:
 311                         arg = MSM_PULL_DOWN;
 312                         break;
 313                 case PIN_CONFIG_BIAS_BUS_HOLD:
 314                         arg = MSM_KEEPER;
 315                         break;
 316                 case PIN_CONFIG_BIAS_PULL_UP:
 317                         arg = MSM_PULL_UP;
 318                         break;
 319                 case PIN_CONFIG_DRIVE_STRENGTH:
 320                         /* Check for invalid values */
 321                         if (arg > 16 || arg < 2 || (arg % 2) != 0)
 322                                 arg = -1;
 323                         else
 324                                 arg = (arg / 2) - 1;
 325                         break;
 326                 case PIN_CONFIG_OUTPUT:
 327                         /* set output value */
 328                         spin_lock_irqsave(&pctrl->lock, flags);
 329                         val = readl(pctrl->regs + g->io_reg);
 330                         if (arg)
 331                                 val |= BIT(g->out_bit);
 332                         else
 333                                 val &= ~BIT(g->out_bit);
 334                         writel(val, pctrl->regs + g->io_reg);
 335                         spin_unlock_irqrestore(&pctrl->lock, flags);
 336
 337                         /* enable output */
 338                         arg = 1;
 339                         break;
 340                 case PIN_CONFIG_INPUT_ENABLE:
 341                         /* disable output */
 342                         arg = 0;
 343                         break;
 344                 default:
 345                         dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 346                                 param);
 347                         return -EINVAL;
 348                 }
 349
 350                 /* Range-check user-supplied value */
 351                 if (arg & ~mask) {
 352                         dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
 353                         return -EINVAL;
 354                 }
 355
 356                 spin_lock_irqsave(&pctrl->lock, flags);
 357                 val = readl(pctrl->regs + g->ctl_reg);
 358                 val &= ~(mask << bit);
 359                 val |= arg << bit;
 360                 writel(val, pctrl->regs + g->ctl_reg);
 361                 spin_unlock_irqrestore(&pctrl->lock, flags);
 362         }
 363
 364         return 0;
 365 }
 366
 367 static const struct pinconf_ops msm_pinconf_ops = {
 368         .is_generic             = true,
 369         .pin_config_group_get   = msm_config_group_get,
 370         .pin_config_group_set   = msm_config_group_set,
 371 };
 372
 373 static struct pinctrl_desc msm_pinctrl_desc = {
 374         .pctlops = &msm_pinctrl_ops,
 375         .pmxops = &msm_pinmux_ops,
 376         .confops = &msm_pinconf_ops,
 377         .owner = THIS_MODULE,
 378 };
 379
 380 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 381 {
 382         const struct msm_pingroup *g;
 383         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 384         unsigned long flags;
 385         u32 val;
 386
 387         g = &pctrl->soc->groups[offset];
 388
 389         spin_lock_irqsave(&pctrl->lock, flags);
 390
 391         val = readl(pctrl->regs + g->ctl_reg);
 392         val &= ~BIT(g->oe_bit);
 393         writel(val, pctrl->regs + g->ctl_reg);
 394
 395         spin_unlock_irqrestore(&pctrl->lock, flags);
 396
 397         return 0;
 398 }
 399
 400 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 401 {
 402         const struct msm_pingroup *g;
 403         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 404         unsigned long flags;
 405         u32 val;
 406
 407         g = &pctrl->soc->groups[offset];
 408
 409         spin_lock_irqsave(&pctrl->lock, flags);
 410
 411         val = readl(pctrl->regs + g->io_reg);
 412         if (value)
 413                 val |= BIT(g->out_bit);
 414         else
 415                 val &= ~BIT(g->out_bit);
 416         writel(val, pctrl->regs + g->io_reg);
 417
 418         val = readl(pctrl->regs + g->ctl_reg);
 419         val |= BIT(g->oe_bit);
 420         writel(val, pctrl->regs + g->ctl_reg);
 421
 422         spin_unlock_irqrestore(&pctrl->lock, flags);
 423
 424         return 0;
 425 }
 426
 427 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
 428 {
 429         const struct msm_pingroup *g;
 430         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 431         u32 val;
 432
 433         g = &pctrl->soc->groups[offset];
 434
 435         val = readl(pctrl->regs + g->io_reg);
 436         return !!(val & BIT(g->in_bit));
 437 }
 438
 439 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 440 {
 441         const struct msm_pingroup *g;
 442         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 443         unsigned long flags;
 444         u32 val;
 445
 446         g = &pctrl->soc->groups[offset];
 447
 448         spin_lock_irqsave(&pctrl->lock, flags);
 449
 450         val = readl(pctrl->regs + g->io_reg);
 451         if (value)
 452                 val |= BIT(g->out_bit);
 453         else
 454                 val &= ~BIT(g->out_bit);
 455         writel(val, pctrl->regs + g->io_reg);
 456
 457         spin_unlock_irqrestore(&pctrl->lock, flags);
 458 }
 459
 460 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
 461 {
 462         int gpio = chip->base + offset;
 463         return pinctrl_request_gpio(gpio);
 464 }
 465
 466 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
 467 {
 468         int gpio = chip->base + offset;
 469         return pinctrl_free_gpio(gpio);
 470 }
 471
 472 #ifdef CONFIG_DEBUG_FS
 473 #include <linux/seq_file.h>
 474
 475 static void msm_gpio_dbg_show_one(struct seq_file *s,
 476                                   struct pinctrl_dev *pctldev,
 477                                   struct gpio_chip *chip,
 478                                   unsigned offset,
 479                                   unsigned gpio)
 480 {
 481         const struct msm_pingroup *g;
 482         struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
 483         unsigned func;
 484         int is_out;
 485         int drive;
 486         int pull;
 487         u32 ctl_reg;
 488
 489         static const char * const pulls[] = {
 490                 "no pull",
 491                 "pull down",
 492                 "keeper",
 493                 "pull up"
 494         };
 495
 496         g = &pctrl->soc->groups[offset];
 497         ctl_reg = readl(pctrl->regs + g->ctl_reg);
 498
 499         is_out = !!(ctl_reg & BIT(g->oe_bit));
 500         func = (ctl_reg >> g->mux_bit) & 7;
 501         drive = (ctl_reg >> g->drv_bit) & 7;
 502         pull = (ctl_reg >> g->pull_bit) & 3;
 503
 504         seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 505         seq_printf(s, " %dmA", msm_regval_to_drive(drive));
 506         seq_printf(s, " %s", pulls[pull]);
 507 }
 508
 509 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 510 {
 511         unsigned gpio = chip->base;
 512         unsigned i;
 513
 514         for (i = 0; i < chip->ngpio; i++, gpio++) {
 515                 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 516                 seq_puts(s, "\n");
 517         }
 518 }
 519
 520 #else
 521 #define msm_gpio_dbg_show NULL
 522 #endif
 523
 524 static struct gpio_chip msm_gpio_template = {
 525         .direction_input  = msm_gpio_direction_input,
 526         .direction_output = msm_gpio_direction_output,
 527         .get              = msm_gpio_get,
 528         .set              = msm_gpio_set,
 529         .request          = msm_gpio_request,
 530         .free             = msm_gpio_free,
 531         .dbg_show         = msm_gpio_dbg_show,
 532 };
 533
 534 /* For dual-edge interrupts in software, since some hardware has no
 535  * such support:
 536  *
 537  * At appropriate moments, this function may be called to flip the polarity
 538  * settings of both-edge irq lines to try and catch the next edge.
 539  *
 540  * The attempt is considered successful if:
 541  * - the status bit goes high, indicating that an edge was caught, or
 542  * - the input value of the gpio doesn't change during the attempt.
 543  * If the value changes twice during the process, that would cause the first
 544  * test to fail but would force the second, as two opposite
 545  * transitions would cause a detection no matter the polarity setting.
 546  *
 547  * The do-loop tries to sledge-hammer closed the timing hole between
 548  * the initial value-read and the polarity-write - if the line value changes
 549  * during that window, an interrupt is lost, the new polarity setting is
 550  * incorrect, and the first success test will fail, causing a retry.
 551  *
 552  * Algorithm comes from Google's msmgpio driver.
 553  */
 554 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
 555                                           const struct msm_pingroup *g,
 556                                           struct irq_data *d)
 557 {
 558         int loop_limit = 100;
 559         unsigned val, val2, intstat;
 560         unsigned pol;
 561
 562         do {
 563                 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 564
 565                 pol = readl(pctrl->regs + g->intr_cfg_reg);
 566                 pol ^= BIT(g->intr_polarity_bit);
 567                 writel(pol, pctrl->regs + g->intr_cfg_reg);
 568
 569                 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
 570                 intstat = readl(pctrl->regs + g->intr_status_reg);
 571                 if (intstat || (val == val2))
 572                         return;
 573         } while (loop_limit-- > 0);
 574         dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
 575                 val, val2);
 576 }
 577
 578 static void msm_gpio_irq_mask(struct irq_data *d)
 579 {
 580         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 581         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 582         const struct msm_pingroup *g;
 583         unsigned long flags;
 584         u32 val;
 585
 586         g = &pctrl->soc->groups[d->hwirq];
 587
 588         spin_lock_irqsave(&pctrl->lock, flags);
 589
 590         val = readl(pctrl->regs + g->intr_cfg_reg);
 591         val &= ~BIT(g->intr_enable_bit);
 592         writel(val, pctrl->regs + g->intr_cfg_reg);
 593
 594         clear_bit(d->hwirq, pctrl->enabled_irqs);
 595
 596         spin_unlock_irqrestore(&pctrl->lock, flags);
 597 }
 598
 599 static void msm_gpio_irq_unmask(struct irq_data *d)
 600 {
 601         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 602         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 603         const struct msm_pingroup *g;
 604         unsigned long flags;
 605         u32 val;
 606
 607         g = &pctrl->soc->groups[d->hwirq];
 608
 609         spin_lock_irqsave(&pctrl->lock, flags);
 610
 611         val = readl(pctrl->regs + g->intr_status_reg);
 612         val &= ~BIT(g->intr_status_bit);
 613         writel(val, pctrl->regs + g->intr_status_reg);
 614
 615         val = readl(pctrl->regs + g->intr_cfg_reg);
 616         val |= BIT(g->intr_enable_bit);
 617         writel(val, pctrl->regs + g->intr_cfg_reg);
 618
 619         set_bit(d->hwirq, pctrl->enabled_irqs);
 620
 621         spin_unlock_irqrestore(&pctrl->lock, flags);
 622 }
 623
 624 static void msm_gpio_irq_ack(struct irq_data *d)
 625 {
 626         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 627         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 628         const struct msm_pingroup *g;
 629         unsigned long flags;
 630         u32 val;
 631
 632         g = &pctrl->soc->groups[d->hwirq];
 633
 634         spin_lock_irqsave(&pctrl->lock, flags);
 635
 636         val = readl(pctrl->regs + g->intr_status_reg);
 637         if (g->intr_ack_high)
 638                 val |= BIT(g->intr_status_bit);
 639         else
 640                 val &= ~BIT(g->intr_status_bit);
 641         writel(val, pctrl->regs + g->intr_status_reg);
 642
 643         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 644                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 645
 646         spin_unlock_irqrestore(&pctrl->lock, flags);
 647 }
 648
 649 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 650 {
 651         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 652         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 653         const struct msm_pingroup *g;
 654         unsigned long flags;
 655         u32 val;
 656
 657         g = &pctrl->soc->groups[d->hwirq];
 658
 659         spin_lock_irqsave(&pctrl->lock, flags);
 660
 661         /*
 662          * For hw without possibility of detecting both edges
 663          */
 664         if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
 665                 set_bit(d->hwirq, pctrl->dual_edge_irqs);
 666         else
 667                 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
 668
 669         /* Route interrupts to application cpu */
 670         val = readl(pctrl->regs + g->intr_target_reg);
 671         val &= ~(7 << g->intr_target_bit);
 672         val |= g->intr_target_kpss_val << g->intr_target_bit;
 673         writel(val, pctrl->regs + g->intr_target_reg);
 674
 675         /* Update configuration for gpio.
 676          * RAW_STATUS_EN is left on for all gpio irqs. Due to the
 677          * internal circuitry of TLMM, toggling the RAW_STATUS
 678          * could cause the INTR_STATUS to be set for EDGE interrupts.
 679          */
 680         val = readl(pctrl->regs + g->intr_cfg_reg);
 681         val |= BIT(g->intr_raw_status_bit);
 682         if (g->intr_detection_width == 2) {
 683                 val &= ~(3 << g->intr_detection_bit);
 684                 val &= ~(1 << g->intr_polarity_bit);
 685                 switch (type) {
 686                 case IRQ_TYPE_EDGE_RISING:
 687                         val |= 1 << g->intr_detection_bit;
 688                         val |= BIT(g->intr_polarity_bit);
 689                         break;
 690                 case IRQ_TYPE_EDGE_FALLING:
 691                         val |= 2 << g->intr_detection_bit;
 692                         val |= BIT(g->intr_polarity_bit);
 693                         break;
 694                 case IRQ_TYPE_EDGE_BOTH:
 695                         val |= 3 << g->intr_detection_bit;
 696                         val |= BIT(g->intr_polarity_bit);
 697                         break;
 698                 case IRQ_TYPE_LEVEL_LOW:
 699                         break;
 700                 case IRQ_TYPE_LEVEL_HIGH:
 701                         val |= BIT(g->intr_polarity_bit);
 702                         break;
 703                 }
 704         } else if (g->intr_detection_width == 1) {
 705                 val &= ~(1 << g->intr_detection_bit);
 706                 val &= ~(1 << g->intr_polarity_bit);
 707                 switch (type) {
 708                 case IRQ_TYPE_EDGE_RISING:
 709                         val |= BIT(g->intr_detection_bit);
 710                         val |= BIT(g->intr_polarity_bit);
 711                         break;
 712                 case IRQ_TYPE_EDGE_FALLING:
 713                         val |= BIT(g->intr_detection_bit);
 714                         break;
 715                 case IRQ_TYPE_EDGE_BOTH:
 716                         val |= BIT(g->intr_detection_bit);
 717                         val |= BIT(g->intr_polarity_bit);
 718                         break;
 719                 case IRQ_TYPE_LEVEL_LOW:
 720                         break;
 721                 case IRQ_TYPE_LEVEL_HIGH:
 722                         val |= BIT(g->intr_polarity_bit);
 723                         break;
 724                 }
 725         } else {
 726                 BUG();
 727         }
 728         writel(val, pctrl->regs + g->intr_cfg_reg);
 729
 730         if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 731                 msm_gpio_update_dual_edge_pos(pctrl, g, d);
 732
 733         spin_unlock_irqrestore(&pctrl->lock, flags);
 734
 735         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 736                 __irq_set_handler_locked(d->irq, handle_level_irq);
 737         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 738                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 739
 740         return 0;
 741 }
 742
 743 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 744 {
 745         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 746         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 747         unsigned long flags;
 748
 749         spin_lock_irqsave(&pctrl->lock, flags);
 750
 751         irq_set_irq_wake(pctrl->irq, on);
 752
 753         spin_unlock_irqrestore(&pctrl->lock, flags);
 754
 755         return 0;
 756 }
 757
 758 static struct irq_chip msm_gpio_irq_chip = {
 759         .name           = "msmgpio",
 760         .irq_mask       = msm_gpio_irq_mask,
 761         .irq_unmask     = msm_gpio_irq_unmask,
 762         .irq_ack        = msm_gpio_irq_ack,
 763         .irq_set_type   = msm_gpio_irq_set_type,
 764         .irq_set_wake   = msm_gpio_irq_set_wake,
 765 };
 766
 767 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 768 {
 769         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 770         const struct msm_pingroup *g;
 771         struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
 772         struct irq_chip *chip = irq_get_chip(irq);
 773         int irq_pin;
 774         int handled = 0;
 775         u32 val;
 776         int i;
 777
 778         chained_irq_enter(chip, desc);
 779
 780         /*
 781          * Each pin has it's own IRQ status register, so use
 782          * enabled_irq bitmap to limit the number of reads.
 783          */
 784         for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
 785                 g = &pctrl->soc->groups[i];
 786                 val = readl(pctrl->regs + g->intr_status_reg);
 787                 if (val & BIT(g->intr_status_bit)) {
 788                         irq_pin = irq_find_mapping(gc->irqdomain, i);
 789                         generic_handle_irq(irq_pin);
 790                         handled++;
 791                 }
 792         }
 793
 794         /* No interrupts were flagged */
 795         if (handled == 0)
 796                 handle_bad_irq(irq, desc);
 797
 798         chained_irq_exit(chip, desc);
 799 }
 800
 801 static int msm_gpio_init(struct msm_pinctrl *pctrl)
 802 {
 803         struct gpio_chip *chip;
 804         int ret;
 805         unsigned ngpio = pctrl->soc->ngpios;
 806
 807         if (WARN_ON(ngpio > MAX_NR_GPIO))
 808                 return -EINVAL;
 809
 810         chip = &pctrl->chip;
 811         chip->base = 0;
 812         chip->ngpio = ngpio;
 813         chip->label = dev_name(pctrl->dev);
 814         chip->dev = pctrl->dev;
 815         chip->owner = THIS_MODULE;
 816         chip->of_node = pctrl->dev->of_node;
 817
 818         ret = gpiochip_add(&pctrl->chip);
 819         if (ret) {
 820                 dev_err(pctrl->dev, "Failed register gpiochip\n");
 821                 return ret;
 822         }
 823
 824         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
 825         if (ret) {
 826                 dev_err(pctrl->dev, "Failed to add pin range\n");
 827                 gpiochip_remove(&pctrl->chip);
 828                 return ret;
 829         }
 830
 831         ret = gpiochip_irqchip_add(chip,
 832                                    &msm_gpio_irq_chip,
 833                                    0,
 834                                    handle_edge_irq,
 835                                    IRQ_TYPE_NONE);
 836         if (ret) {
 837                 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
 838                 gpiochip_remove(&pctrl->chip);
 839                 return -ENOSYS;
 840         }
 841
 842         gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
 843                                      msm_gpio_irq_handler);
 844
 845         return 0;
 846 }
 847
 848 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
 849                                void *data)
 850 {
 851         struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
 852
 853         writel(0, pctrl->regs + PS_HOLD_OFFSET);
 854         mdelay(1000);
 855         return NOTIFY_DONE;
 856 }
 857
 858 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
 859 {
 860         int i;
 861         const struct msm_function *func = pctrl->soc->functions;
 862
 863         for (i = 0; i < pctrl->soc->nfunctions; i++)
 864                 if (!strcmp(func[i].name, "ps_hold")) {
 865                         pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
 866                         pctrl->restart_nb.priority = 128;
 867                         if (register_restart_handler(&pctrl->restart_nb))
 868                                 dev_err(pctrl->dev,
 869                                         "failed to setup restart handler.\n");
 870                         break;
 871                 }
 872 }
 873
 874 int msm_pinctrl_probe(struct platform_device *pdev,
 875                       const struct msm_pinctrl_soc_data *soc_data)
 876 {
 877         struct msm_pinctrl *pctrl;
 878         struct resource *res;
 879         int ret;
 880
 881         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 882         if (!pctrl) {
 883                 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
 884                 return -ENOMEM;
 885         }
 886         pctrl->dev = &pdev->dev;
 887         pctrl->soc = soc_data;
 888         pctrl->chip = msm_gpio_template;
 889
 890         spin_lock_init(&pctrl->lock);
 891
 892         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 893         pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
 894         if (IS_ERR(pctrl->regs))
 895                 return PTR_ERR(pctrl->regs);
 896
 897         msm_pinctrl_setup_pm_reset(pctrl);
 898
 899         pctrl->irq = platform_get_irq(pdev, 0);
 900         if (pctrl->irq < 0) {
 901                 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
 902                 return pctrl->irq;
 903         }
 904
 905         msm_pinctrl_desc.name = dev_name(&pdev->dev);
 906         msm_pinctrl_desc.pins = pctrl->soc->pins;
 907         msm_pinctrl_desc.npins = pctrl->soc->npins;
 908         pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
 909         if (!pctrl->pctrl) {
 910                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 911                 return -ENODEV;
 912         }
 913
 914         ret = msm_gpio_init(pctrl);
 915         if (ret) {
 916                 pinctrl_unregister(pctrl->pctrl);
 917                 return ret;
 918         }
 919
 920         platform_set_drvdata(pdev, pctrl);
 921
 922         dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
 923
 924         return 0;
 925 }
 926 EXPORT_SYMBOL(msm_pinctrl_probe);
 927
 928 int msm_pinctrl_remove(struct platform_device *pdev)
 929 {
 930         struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
 931
 932         gpiochip_remove(&pctrl->chip);
 933         pinctrl_unregister(pctrl->pctrl);
 934
 935         unregister_restart_handler(&pctrl->restart_nb);
 936
 937         return 0;
 938 }
 939 EXPORT_SYMBOL(msm_pinctrl_remove);
 940