kernel/drivers/pinctrl/pinctrl-amd.c

   1 /*
   2  * GPIO driver for AMD
   3  *
   4  * Copyright (c) 2014,2015 AMD Corporation.
   5  * Authors: Ken Xue <Ken.Xue@amd.com>
   6  *      Wu, Jeff <Jeff.Wu@amd.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/bug.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/compiler.h>
  19 #include <linux/types.h>
  20 #include <linux/errno.h>
  21 #include <linux/log2.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio.h>
  24 #include <linux/slab.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/mutex.h>
  27 #include <linux/acpi.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/list.h>
  31 #include <linux/bitops.h>
  32 #include <linux/pinctrl/pinconf.h>
  33 #include <linux/pinctrl/pinconf-generic.h>
  34
  35 #include "pinctrl-utils.h"
  36 #include "pinctrl-amd.h"
  37
  38 static inline struct amd_gpio *to_amd_gpio(struct gpio_chip *gc)
  39 {
  40         return container_of(gc, struct amd_gpio, gc);
  41 }
  42
  43 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  44 {
  45         unsigned long flags;
  46         u32 pin_reg;
  47         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
  48
  49         spin_lock_irqsave(&gpio_dev->lock, flags);
  50         pin_reg = readl(gpio_dev->base + offset * 4);
  51         /*
  52          * Suppose BIOS or Bootloader sets specific debounce for the
  53          * GPIO. if not, set debounce to be  2.75ms and remove glitch.
  54         */
  55         if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
  56                 pin_reg |= 0xf;
  57                 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
  58                 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
  59                 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
  60         }
  61
  62         pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
  63         writel(pin_reg, gpio_dev->base + offset * 4);
  64         spin_unlock_irqrestore(&gpio_dev->lock, flags);
  65
  66         return 0;
  67 }
  68
  69 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
  70                 int value)
  71 {
  72         u32 pin_reg;
  73         unsigned long flags;
  74         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
  75
  76         spin_lock_irqsave(&gpio_dev->lock, flags);
  77         pin_reg = readl(gpio_dev->base + offset * 4);
  78         pin_reg |= BIT(OUTPUT_ENABLE_OFF);
  79         if (value)
  80                 pin_reg |= BIT(OUTPUT_VALUE_OFF);
  81         else
  82                 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
  83         writel(pin_reg, gpio_dev->base + offset * 4);
  84         spin_unlock_irqrestore(&gpio_dev->lock, flags);
  85
  86         return 0;
  87 }
  88
  89 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
  90 {
  91         u32 pin_reg;
  92         unsigned long flags;
  93         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
  94
  95         spin_lock_irqsave(&gpio_dev->lock, flags);
  96         pin_reg = readl(gpio_dev->base + offset * 4);
  97         spin_unlock_irqrestore(&gpio_dev->lock, flags);
  98
  99         return !!(pin_reg & BIT(PIN_STS_OFF));
 100 }
 101
 102 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
 103 {
 104         u32 pin_reg;
 105         unsigned long flags;
 106         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 107
 108         spin_lock_irqsave(&gpio_dev->lock, flags);
 109         pin_reg = readl(gpio_dev->base + offset * 4);
 110         if (value)
 111                 pin_reg |= BIT(OUTPUT_VALUE_OFF);
 112         else
 113                 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
 114         writel(pin_reg, gpio_dev->base + offset * 4);
 115         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 116 }
 117
 118 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
 119                 unsigned debounce)
 120 {
 121         u32 time;
 122         u32 pin_reg;
 123         int ret = 0;
 124         unsigned long flags;
 125         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 126
 127         spin_lock_irqsave(&gpio_dev->lock, flags);
 128         pin_reg = readl(gpio_dev->base + offset * 4);
 129
 130         if (debounce) {
 131                 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
 132                 pin_reg &= ~DB_TMR_OUT_MASK;
 133                 /*
 134                 Debounce        Debounce        Timer   Max
 135                 TmrLarge        TmrOutUnit      Unit    Debounce
 136                                                         Time
 137                 0       0       61 usec (2 RtcClk)      976 usec
 138                 0       1       244 usec (8 RtcClk)     3.9 msec
 139                 1       0       15.6 msec (512 RtcClk)  250 msec
 140                 1       1       62.5 msec (2048 RtcClk) 1 sec
 141                 */
 142
 143                 if (debounce < 61) {
 144                         pin_reg |= 1;
 145                         pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 146                         pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 147                 } else if (debounce < 976) {
 148                         time = debounce / 61;
 149                         pin_reg |= time & DB_TMR_OUT_MASK;
 150                         pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 151                         pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 152                 } else if (debounce < 3900) {
 153                         time = debounce / 244;
 154                         pin_reg |= time & DB_TMR_OUT_MASK;
 155                         pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
 156                         pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 157                 } else if (debounce < 250000) {
 158                         time = debounce / 15600;
 159                         pin_reg |= time & DB_TMR_OUT_MASK;
 160                         pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 161                         pin_reg |= BIT(DB_TMR_LARGE_OFF);
 162                 } else if (debounce < 1000000) {
 163                         time = debounce / 62500;
 164                         pin_reg |= time & DB_TMR_OUT_MASK;
 165                         pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
 166                         pin_reg |= BIT(DB_TMR_LARGE_OFF);
 167                 } else {
 168                         pin_reg &= ~DB_CNTRl_MASK;
 169                         ret = -EINVAL;
 170                 }
 171         } else {
 172                 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 173                 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 174                 pin_reg &= ~DB_TMR_OUT_MASK;
 175                 pin_reg &= ~DB_CNTRl_MASK;
 176         }
 177         writel(pin_reg, gpio_dev->base + offset * 4);
 178         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 179
 180         return ret;
 181 }
 182
 183 #ifdef CONFIG_DEBUG_FS
 184 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
 185 {
 186         u32 pin_reg;
 187         unsigned long flags;
 188         unsigned int bank, i, pin_num;
 189         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 190
 191         char *level_trig;
 192         char *active_level;
 193         char *interrupt_enable;
 194         char *interrupt_mask;
 195         char *wake_cntrl0;
 196         char *wake_cntrl1;
 197         char *wake_cntrl2;
 198         char *pin_sts;
 199         char *pull_up_sel;
 200         char *pull_up_enable;
 201         char *pull_down_enable;
 202         char *output_value;
 203         char *output_enable;
 204
 205         for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
 206                 seq_printf(s, "GPIO bank%d\t", bank);
 207
 208                 switch (bank) {
 209                 case 0:
 210                         i = 0;
 211                         pin_num = AMD_GPIO_PINS_BANK0;
 212                         break;
 213                 case 1:
 214                         i = 64;
 215                         pin_num = AMD_GPIO_PINS_BANK1 + i;
 216                         break;
 217                 case 2:
 218                         i = 128;
 219                         pin_num = AMD_GPIO_PINS_BANK2 + i;
 220                         break;
 221                 }
 222
 223                 for (; i < pin_num; i++) {
 224                         seq_printf(s, "pin%d\t", i);
 225                         spin_lock_irqsave(&gpio_dev->lock, flags);
 226                         pin_reg = readl(gpio_dev->base + i * 4);
 227                         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 228
 229                         if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
 230                                 interrupt_enable = "interrupt is enabled|";
 231
 232                                 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
 233                                 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
 234                                         active_level = "Active low|";
 235                                 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
 236                                 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
 237                                         active_level = "Active high|";
 238                                 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
 239                                         && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
 240                                         active_level = "Active on both|";
 241                                 else
 242                                         active_level = "Unknow Active level|";
 243
 244                                 if (pin_reg & BIT(LEVEL_TRIG_OFF))
 245                                         level_trig = "Level trigger|";
 246                                 else
 247                                         level_trig = "Edge trigger|";
 248
 249                         } else {
 250                                 interrupt_enable =
 251                                         "interrupt is disabled|";
 252                                 active_level = " ";
 253                                 level_trig = " ";
 254                         }
 255
 256                         if (pin_reg & BIT(INTERRUPT_MASK_OFF))
 257                                 interrupt_mask =
 258                                         "interrupt is unmasked|";
 259                         else
 260                                 interrupt_mask =
 261                                         "interrupt is masked|";
 262
 263                         if (pin_reg & BIT(WAKE_CNTRL_OFF))
 264                                 wake_cntrl0 = "enable wakeup in S0i3 state|";
 265                         else
 266                                 wake_cntrl0 = "disable wakeup in S0i3 state|";
 267
 268                         if (pin_reg & BIT(WAKE_CNTRL_OFF))
 269                                 wake_cntrl1 = "enable wakeup in S3 state|";
 270                         else
 271                                 wake_cntrl1 = "disable wakeup in S3 state|";
 272
 273                         if (pin_reg & BIT(WAKE_CNTRL_OFF))
 274                                 wake_cntrl2 = "enable wakeup in S4/S5 state|";
 275                         else
 276                                 wake_cntrl2 = "disable wakeup in S4/S5 state|";
 277
 278                         if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
 279                                 pull_up_enable = "pull-up is enabled|";
 280                                 if (pin_reg & BIT(PULL_UP_SEL_OFF))
 281                                         pull_up_sel = "8k pull-up|";
 282                                 else
 283                                         pull_up_sel = "4k pull-up|";
 284                         } else {
 285                                 pull_up_enable = "pull-up is disabled|";
 286                                 pull_up_sel = " ";
 287                         }
 288
 289                         if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
 290                                 pull_down_enable = "pull-down is enabled|";
 291                         else
 292                                 pull_down_enable = "Pull-down is disabled|";
 293
 294                         if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
 295                                 pin_sts = " ";
 296                                 output_enable = "output is enabled|";
 297                                 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
 298                                         output_value = "output is high|";
 299                                 else
 300                                         output_value = "output is low|";
 301                         } else {
 302                                 output_enable = "output is disabled|";
 303                                 output_value = " ";
 304
 305                                 if (pin_reg & BIT(PIN_STS_OFF))
 306                                         pin_sts = "input is high|";
 307                                 else
 308                                         pin_sts = "input is low|";
 309                         }
 310
 311                         seq_printf(s, "%s %s %s %s %s %s\n"
 312                                 " %s %s %s %s %s %s %s 0x%x\n",
 313                                 level_trig, active_level, interrupt_enable,
 314                                 interrupt_mask, wake_cntrl0, wake_cntrl1,
 315                                 wake_cntrl2, pin_sts, pull_up_sel,
 316                                 pull_up_enable, pull_down_enable,
 317                                 output_value, output_enable, pin_reg);
 318                 }
 319         }
 320 }
 321 #else
 322 #define amd_gpio_dbg_show NULL
 323 #endif
 324
 325 static void amd_gpio_irq_enable(struct irq_data *d)
 326 {
 327         u32 pin_reg;
 328         unsigned long flags;
 329         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 330         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 331
 332         spin_lock_irqsave(&gpio_dev->lock, flags);
 333         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 334         /*
 335                 Suppose BIOS or Bootloader sets specific debounce for the
 336                 GPIO. if not, set debounce to be  2.75ms.
 337         */
 338         if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
 339                 pin_reg |= 0xf;
 340                 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
 341                 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 342         }
 343         pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
 344         pin_reg |= BIT(INTERRUPT_MASK_OFF);
 345         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 346         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 347 }
 348
 349 static void amd_gpio_irq_disable(struct irq_data *d)
 350 {
 351         u32 pin_reg;
 352         unsigned long flags;
 353         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 354         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 355
 356         spin_lock_irqsave(&gpio_dev->lock, flags);
 357         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 358         pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
 359         pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
 360         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 361         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 362 }
 363
 364 static void amd_gpio_irq_mask(struct irq_data *d)
 365 {
 366         u32 pin_reg;
 367         unsigned long flags;
 368         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 369         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 370
 371         spin_lock_irqsave(&gpio_dev->lock, flags);
 372         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 373         pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
 374         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 375         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 376 }
 377
 378 static void amd_gpio_irq_unmask(struct irq_data *d)
 379 {
 380         u32 pin_reg;
 381         unsigned long flags;
 382         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 383         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 384
 385         spin_lock_irqsave(&gpio_dev->lock, flags);
 386         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 387         pin_reg |= BIT(INTERRUPT_MASK_OFF);
 388         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 389         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 390 }
 391
 392 static void amd_gpio_irq_eoi(struct irq_data *d)
 393 {
 394         u32 reg;
 395         unsigned long flags;
 396         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 397         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 398
 399         spin_lock_irqsave(&gpio_dev->lock, flags);
 400         reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
 401         reg |= EOI_MASK;
 402         writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
 403         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 404 }
 405
 406 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 407 {
 408         int ret = 0;
 409         u32 pin_reg;
 410         unsigned long flags;
 411         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 412         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 413
 414         spin_lock_irqsave(&gpio_dev->lock, flags);
 415         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 416
 417         switch (type & IRQ_TYPE_SENSE_MASK) {
 418         case IRQ_TYPE_EDGE_RISING:
 419                 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
 420                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 421                 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
 422                 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
 423                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 424                 break;
 425
 426         case IRQ_TYPE_EDGE_FALLING:
 427                 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
 428                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 429                 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
 430                 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
 431                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 432                 break;
 433
 434         case IRQ_TYPE_EDGE_BOTH:
 435                 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
 436                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 437                 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
 438                 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
 439                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 440                 break;
 441
 442         case IRQ_TYPE_LEVEL_HIGH:
 443                 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
 444                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 445                 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
 446                 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
 447                 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
 448                 __irq_set_handler_locked(d->irq, handle_level_irq);
 449                 break;
 450
 451         case IRQ_TYPE_LEVEL_LOW:
 452                 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
 453                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 454                 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
 455                 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
 456                 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
 457                 __irq_set_handler_locked(d->irq, handle_level_irq);
 458                 break;
 459
 460         case IRQ_TYPE_NONE:
 461                 break;
 462
 463         default:
 464                 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
 465                 ret = -EINVAL;
 466         }
 467
 468         pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
 469         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 470         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 471
 472         return ret;
 473 }
 474
 475 static void amd_irq_ack(struct irq_data *d)
 476 {
 477         /*
 478          * based on HW design,there is no need to ack HW
 479          * before handle current irq. But this routine is
 480          * necessary for handle_edge_irq
 481         */
 482 }
 483
 484 static struct irq_chip amd_gpio_irqchip = {
 485         .name         = "amd_gpio",
 486         .irq_ack      = amd_irq_ack,
 487         .irq_enable   = amd_gpio_irq_enable,
 488         .irq_disable  = amd_gpio_irq_disable,
 489         .irq_mask     = amd_gpio_irq_mask,
 490         .irq_unmask   = amd_gpio_irq_unmask,
 491         .irq_eoi      = amd_gpio_irq_eoi,
 492         .irq_set_type = amd_gpio_irq_set_type,
 493 };
 494
 495 static void amd_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 496 {
 497         u32 i;
 498         u32 off;
 499         u32 reg;
 500         u32 pin_reg;
 501         u64 reg64;
 502         int handled = 0;
 503         unsigned long flags;
 504         struct irq_chip *chip = irq_get_chip(irq);
 505         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 506         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 507
 508         chained_irq_enter(chip, desc);
 509         /*enable GPIO interrupt again*/
 510         spin_lock_irqsave(&gpio_dev->lock, flags);
 511         reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
 512         reg64 = reg;
 513         reg64 = reg64 << 32;
 514
 515         reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
 516         reg64 |= reg;
 517         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 518
 519         /*
 520          * first 46 bits indicates interrupt status.
 521          * one bit represents four interrupt sources.
 522         */
 523         for (off = 0; off < 46 ; off++) {
 524                 if (reg64 & BIT(off)) {
 525                         for (i = 0; i < 4; i++) {
 526                                 pin_reg = readl(gpio_dev->base +
 527                                                 (off * 4 + i) * 4);
 528                                 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
 529                                         (pin_reg & BIT(WAKE_STS_OFF))) {
 530                                         irq = irq_find_mapping(gc->irqdomain,
 531                                                                 off * 4 + i);
 532                                         generic_handle_irq(irq);
 533                                         writel(pin_reg,
 534                                                 gpio_dev->base
 535                                                 + (off * 4 + i) * 4);
 536                                         handled++;
 537                                 }
 538                         }
 539                 }
 540         }
 541
 542         if (handled == 0)
 543                 handle_bad_irq(irq, desc);
 544
 545         spin_lock_irqsave(&gpio_dev->lock, flags);
 546         reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
 547         reg |= EOI_MASK;
 548         writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
 549         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 550
 551         chained_irq_exit(chip, desc);
 552 }
 553
 554 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
 555 {
 556         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 557
 558         return gpio_dev->ngroups;
 559 }
 560
 561 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
 562                                       unsigned group)
 563 {
 564         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 565
 566         return gpio_dev->groups[group].name;
 567 }
 568
 569 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
 570                               unsigned group,
 571                               const unsigned **pins,
 572                               unsigned *num_pins)
 573 {
 574         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 575
 576         *pins = gpio_dev->groups[group].pins;
 577         *num_pins = gpio_dev->groups[group].npins;
 578         return 0;
 579 }
 580
 581 static const struct pinctrl_ops amd_pinctrl_ops = {
 582         .get_groups_count       = amd_get_groups_count,
 583         .get_group_name         = amd_get_group_name,
 584         .get_group_pins         = amd_get_group_pins,
 585 #ifdef CONFIG_OF
 586         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 587         .dt_free_map            = pinctrl_utils_dt_free_map,
 588 #endif
 589 };
 590
 591 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
 592                           unsigned int pin,
 593                           unsigned long *config)
 594 {
 595         u32 pin_reg;
 596         unsigned arg;
 597         unsigned long flags;
 598         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 599         enum pin_config_param param = pinconf_to_config_param(*config);
 600
 601         spin_lock_irqsave(&gpio_dev->lock, flags);
 602         pin_reg = readl(gpio_dev->base + pin*4);
 603         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 604         switch (param) {
 605         case PIN_CONFIG_INPUT_DEBOUNCE:
 606                 arg = pin_reg & DB_TMR_OUT_MASK;
 607                 break;
 608
 609         case PIN_CONFIG_BIAS_PULL_DOWN:
 610                 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
 611                 break;
 612
 613         case PIN_CONFIG_BIAS_PULL_UP:
 614                 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
 615                 break;
 616
 617         case PIN_CONFIG_DRIVE_STRENGTH:
 618                 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
 619                 break;
 620
 621         default:
 622                 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
 623                         param);
 624                 return -ENOTSUPP;
 625         }
 626
 627         *config = pinconf_to_config_packed(param, arg);
 628
 629         return 0;
 630 }
 631
 632 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 633                                 unsigned long *configs, unsigned num_configs)
 634 {
 635         int i;
 636         u32 arg;
 637         int ret = 0;
 638         u32 pin_reg;
 639         unsigned long flags;
 640         enum pin_config_param param;
 641         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 642
 643         spin_lock_irqsave(&gpio_dev->lock, flags);
 644         for (i = 0; i < num_configs; i++) {
 645                 param = pinconf_to_config_param(configs[i]);
 646                 arg = pinconf_to_config_argument(configs[i]);
 647                 pin_reg = readl(gpio_dev->base + pin*4);
 648
 649                 switch (param) {
 650                 case PIN_CONFIG_INPUT_DEBOUNCE:
 651                         pin_reg &= ~DB_TMR_OUT_MASK;
 652                         pin_reg |= arg & DB_TMR_OUT_MASK;
 653                         break;
 654
 655                 case PIN_CONFIG_BIAS_PULL_DOWN:
 656                         pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
 657                         pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
 658                         break;
 659
 660                 case PIN_CONFIG_BIAS_PULL_UP:
 661                         pin_reg &= ~BIT(PULL_UP_SEL_OFF);
 662                         pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
 663                         pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
 664                         pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
 665                         break;
 666
 667                 case PIN_CONFIG_DRIVE_STRENGTH:
 668                         pin_reg &= ~(DRV_STRENGTH_SEL_MASK
 669                                         << DRV_STRENGTH_SEL_OFF);
 670                         pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
 671                                         << DRV_STRENGTH_SEL_OFF;
 672                         break;
 673
 674                 default:
 675                         dev_err(&gpio_dev->pdev->dev,
 676                                 "Invalid config param %04x\n", param);
 677                         ret = -ENOTSUPP;
 678                 }
 679
 680                 writel(pin_reg, gpio_dev->base + pin*4);
 681         }
 682         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 683
 684         return ret;
 685 }
 686
 687 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
 688                                 unsigned int group,
 689                                 unsigned long *config)
 690 {
 691         const unsigned *pins;
 692         unsigned npins;
 693         int ret;
 694
 695         ret = amd_get_group_pins(pctldev, group, &pins, &npins);
 696         if (ret)
 697                 return ret;
 698
 699         if (amd_pinconf_get(pctldev, pins[0], config))
 700                         return -ENOTSUPP;
 701
 702         return 0;
 703 }
 704
 705 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
 706                                 unsigned group, unsigned long *configs,
 707                                 unsigned num_configs)
 708 {
 709         const unsigned *pins;
 710         unsigned npins;
 711         int i, ret;
 712
 713         ret = amd_get_group_pins(pctldev, group, &pins, &npins);
 714         if (ret)
 715                 return ret;
 716         for (i = 0; i < npins; i++) {
 717                 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
 718                         return -ENOTSUPP;
 719         }
 720         return 0;
 721 }
 722
 723 static const struct pinconf_ops amd_pinconf_ops = {
 724         .pin_config_get         = amd_pinconf_get,
 725         .pin_config_set         = amd_pinconf_set,
 726         .pin_config_group_get = amd_pinconf_group_get,
 727         .pin_config_group_set = amd_pinconf_group_set,
 728 };
 729
 730 static struct pinctrl_desc amd_pinctrl_desc = {
 731         .pins   = kerncz_pins,
 732         .npins = ARRAY_SIZE(kerncz_pins),
 733         .pctlops = &amd_pinctrl_ops,
 734         .confops = &amd_pinconf_ops,
 735         .owner = THIS_MODULE,
 736 };
 737
 738 static int amd_gpio_probe(struct platform_device *pdev)
 739 {
 740         int ret = 0;
 741         int irq_base;
 742         struct resource *res;
 743         struct amd_gpio *gpio_dev;
 744
 745         gpio_dev = devm_kzalloc(&pdev->dev,
 746                                 sizeof(struct amd_gpio), GFP_KERNEL);
 747         if (!gpio_dev)
 748                 return -ENOMEM;
 749
 750         spin_lock_init(&gpio_dev->lock);
 751
 752         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 753         if (!res) {
 754                 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
 755                 return -EINVAL;
 756         }
 757
 758         gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
 759                                                 resource_size(res));
 760         if (IS_ERR(gpio_dev->base))
 761                 return PTR_ERR(gpio_dev->base);
 762
 763         irq_base = platform_get_irq(pdev, 0);
 764         if (irq_base < 0) {
 765                 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
 766                 return -EINVAL;
 767         }
 768
 769         gpio_dev->pdev = pdev;
 770         gpio_dev->gc.direction_input    = amd_gpio_direction_input;
 771         gpio_dev->gc.direction_output   = amd_gpio_direction_output;
 772         gpio_dev->gc.get                        = amd_gpio_get_value;
 773         gpio_dev->gc.set                        = amd_gpio_set_value;
 774         gpio_dev->gc.set_debounce       = amd_gpio_set_debounce;
 775         gpio_dev->gc.dbg_show           = amd_gpio_dbg_show;
 776
 777         gpio_dev->gc.base                       = 0;
 778         gpio_dev->gc.label                      = pdev->name;
 779         gpio_dev->gc.owner                      = THIS_MODULE;
 780         gpio_dev->gc.dev                        = &pdev->dev;
 781         gpio_dev->gc.ngpio                      = TOTAL_NUMBER_OF_PINS;
 782 #if defined(CONFIG_OF_GPIO)
 783         gpio_dev->gc.of_node                    = pdev->dev.of_node;
 784 #endif
 785
 786         gpio_dev->groups = kerncz_groups;
 787         gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
 788
 789         amd_pinctrl_desc.name = dev_name(&pdev->dev);
 790         gpio_dev->pctrl = pinctrl_register(&amd_pinctrl_desc,
 791                                         &pdev->dev, gpio_dev);
 792         if (!gpio_dev->pctrl) {
 793                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 794                 return -ENODEV;
 795         }
 796
 797         ret = gpiochip_add(&gpio_dev->gc);
 798         if (ret)
 799                 goto out1;
 800
 801         ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
 802                                 0, 0, TOTAL_NUMBER_OF_PINS);
 803         if (ret) {
 804                 dev_err(&pdev->dev, "Failed to add pin range\n");
 805                 goto out2;
 806         }
 807
 808         ret = gpiochip_irqchip_add(&gpio_dev->gc,
 809                                 &amd_gpio_irqchip,
 810                                 0,
 811                                 handle_simple_irq,
 812                                 IRQ_TYPE_NONE);
 813         if (ret) {
 814                 dev_err(&pdev->dev, "could not add irqchip\n");
 815                 ret = -ENODEV;
 816                 goto out2;
 817         }
 818
 819         gpiochip_set_chained_irqchip(&gpio_dev->gc,
 820                                  &amd_gpio_irqchip,
 821                                  irq_base,
 822                                  amd_gpio_irq_handler);
 823
 824         platform_set_drvdata(pdev, gpio_dev);
 825
 826         dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
 827         return ret;
 828
 829 out2:
 830         gpiochip_remove(&gpio_dev->gc);
 831
 832 out1:
 833         pinctrl_unregister(gpio_dev->pctrl);
 834         return ret;
 835 }
 836
 837 static int amd_gpio_remove(struct platform_device *pdev)
 838 {
 839         struct amd_gpio *gpio_dev;
 840
 841         gpio_dev = platform_get_drvdata(pdev);
 842
 843         gpiochip_remove(&gpio_dev->gc);
 844         pinctrl_unregister(gpio_dev->pctrl);
 845
 846         return 0;
 847 }
 848
 849 static const struct acpi_device_id amd_gpio_acpi_match[] = {
 850         { "AMD0030", 0 },
 851         { },
 852 };
 853 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
 854
 855 static struct platform_driver amd_gpio_driver = {
 856         .driver         = {
 857                 .name   = "amd_gpio",
 858                 .owner  = THIS_MODULE,
 859                 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
 860         },
 861         .probe          = amd_gpio_probe,
 862         .remove         = amd_gpio_remove,
 863 };
 864
 865 module_platform_driver(amd_gpio_driver);
 866
 867 MODULE_LICENSE("GPL v2");
 868 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
 869 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");