kernel/drivers/pinctrl/pinctrl-amd.c

   1 /*
   2  * GPIO driver for AMD
   3  *
   4  * Copyright (c) 2014,2015 AMD Corporation.
   5  * Authors: Ken Xue <Ken.Xue@amd.com>
   6  *      Wu, Jeff <Jeff.Wu@amd.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/bug.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/compiler.h>
  19 #include <linux/types.h>
  20 #include <linux/errno.h>
  21 #include <linux/log2.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio.h>
  24 #include <linux/slab.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/mutex.h>
  27 #include <linux/acpi.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/list.h>
  31 #include <linux/bitops.h>
  32 #include <linux/pinctrl/pinconf.h>
  33 #include <linux/pinctrl/pinconf-generic.h>
  34
  35 #include "pinctrl-utils.h"
  36 #include "pinctrl-amd.h"
  37
  38 static inline struct amd_gpio *to_amd_gpio(struct gpio_chip *gc)
  39 {
  40         return container_of(gc, struct amd_gpio, gc);
  41 }
  42
  43 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  44 {
  45         unsigned long flags;
  46         u32 pin_reg;
  47         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
  48
  49         spin_lock_irqsave(&gpio_dev->lock, flags);
  50         pin_reg = readl(gpio_dev->base + offset * 4);
  51         pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
  52         writel(pin_reg, gpio_dev->base + offset * 4);
  53         spin_unlock_irqrestore(&gpio_dev->lock, flags);
  54
  55         return 0;
  56 }
  57
  58 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
  59                 int value)
  60 {
  61         u32 pin_reg;
  62         unsigned long flags;
  63         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
  64
  65         spin_lock_irqsave(&gpio_dev->lock, flags);
  66         pin_reg = readl(gpio_dev->base + offset * 4);
  67         pin_reg |= BIT(OUTPUT_ENABLE_OFF);
  68         if (value)
  69                 pin_reg |= BIT(OUTPUT_VALUE_OFF);
  70         else
  71                 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
  72         writel(pin_reg, gpio_dev->base + offset * 4);
  73         spin_unlock_irqrestore(&gpio_dev->lock, flags);
  74
  75         return 0;
  76 }
  77
  78 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
  79 {
  80         u32 pin_reg;
  81         unsigned long flags;
  82         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
  83
  84         spin_lock_irqsave(&gpio_dev->lock, flags);
  85         pin_reg = readl(gpio_dev->base + offset * 4);
  86         spin_unlock_irqrestore(&gpio_dev->lock, flags);
  87
  88         return !!(pin_reg & BIT(PIN_STS_OFF));
  89 }
  90
  91 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
  92 {
  93         u32 pin_reg;
  94         unsigned long flags;
  95         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
  96
  97         spin_lock_irqsave(&gpio_dev->lock, flags);
  98         pin_reg = readl(gpio_dev->base + offset * 4);
  99         if (value)
 100                 pin_reg |= BIT(OUTPUT_VALUE_OFF);
 101         else
 102                 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
 103         writel(pin_reg, gpio_dev->base + offset * 4);
 104         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 105 }
 106
 107 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
 108                 unsigned debounce)
 109 {
 110         u32 time;
 111         u32 pin_reg;
 112         int ret = 0;
 113         unsigned long flags;
 114         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 115
 116         spin_lock_irqsave(&gpio_dev->lock, flags);
 117         pin_reg = readl(gpio_dev->base + offset * 4);
 118
 119         if (debounce) {
 120                 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
 121                 pin_reg &= ~DB_TMR_OUT_MASK;
 122                 /*
 123                 Debounce        Debounce        Timer   Max
 124                 TmrLarge        TmrOutUnit      Unit    Debounce
 125                                                         Time
 126                 0       0       61 usec (2 RtcClk)      976 usec
 127                 0       1       244 usec (8 RtcClk)     3.9 msec
 128                 1       0       15.6 msec (512 RtcClk)  250 msec
 129                 1       1       62.5 msec (2048 RtcClk) 1 sec
 130                 */
 131
 132                 if (debounce < 61) {
 133                         pin_reg |= 1;
 134                         pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 135                         pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 136                 } else if (debounce < 976) {
 137                         time = debounce / 61;
 138                         pin_reg |= time & DB_TMR_OUT_MASK;
 139                         pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 140                         pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 141                 } else if (debounce < 3900) {
 142                         time = debounce / 244;
 143                         pin_reg |= time & DB_TMR_OUT_MASK;
 144                         pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
 145                         pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 146                 } else if (debounce < 250000) {
 147                         time = debounce / 15600;
 148                         pin_reg |= time & DB_TMR_OUT_MASK;
 149                         pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 150                         pin_reg |= BIT(DB_TMR_LARGE_OFF);
 151                 } else if (debounce < 1000000) {
 152                         time = debounce / 62500;
 153                         pin_reg |= time & DB_TMR_OUT_MASK;
 154                         pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
 155                         pin_reg |= BIT(DB_TMR_LARGE_OFF);
 156                 } else {
 157                         pin_reg &= ~DB_CNTRl_MASK;
 158                         ret = -EINVAL;
 159                 }
 160         } else {
 161                 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 162                 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 163                 pin_reg &= ~DB_TMR_OUT_MASK;
 164                 pin_reg &= ~DB_CNTRl_MASK;
 165         }
 166         writel(pin_reg, gpio_dev->base + offset * 4);
 167         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 168
 169         return ret;
 170 }
 171
 172 #ifdef CONFIG_DEBUG_FS
 173 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
 174 {
 175         u32 pin_reg;
 176         unsigned long flags;
 177         unsigned int bank, i, pin_num;
 178         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 179
 180         char *level_trig;
 181         char *active_level;
 182         char *interrupt_enable;
 183         char *interrupt_mask;
 184         char *wake_cntrl0;
 185         char *wake_cntrl1;
 186         char *wake_cntrl2;
 187         char *pin_sts;
 188         char *pull_up_sel;
 189         char *pull_up_enable;
 190         char *pull_down_enable;
 191         char *output_value;
 192         char *output_enable;
 193
 194         for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
 195                 seq_printf(s, "GPIO bank%d\t", bank);
 196
 197                 switch (bank) {
 198                 case 0:
 199                         i = 0;
 200                         pin_num = AMD_GPIO_PINS_BANK0;
 201                         break;
 202                 case 1:
 203                         i = 64;
 204                         pin_num = AMD_GPIO_PINS_BANK1 + i;
 205                         break;
 206                 case 2:
 207                         i = 128;
 208                         pin_num = AMD_GPIO_PINS_BANK2 + i;
 209                         break;
 210                 }
 211
 212                 for (; i < pin_num; i++) {
 213                         seq_printf(s, "pin%d\t", i);
 214                         spin_lock_irqsave(&gpio_dev->lock, flags);
 215                         pin_reg = readl(gpio_dev->base + i * 4);
 216                         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 217
 218                         if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
 219                                 interrupt_enable = "interrupt is enabled|";
 220
 221                                 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
 222                                 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
 223                                         active_level = "Active low|";
 224                                 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
 225                                 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
 226                                         active_level = "Active high|";
 227                                 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
 228                                         && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
 229                                         active_level = "Active on both|";
 230                                 else
 231                                         active_level = "Unknow Active level|";
 232
 233                                 if (pin_reg & BIT(LEVEL_TRIG_OFF))
 234                                         level_trig = "Level trigger|";
 235                                 else
 236                                         level_trig = "Edge trigger|";
 237
 238                         } else {
 239                                 interrupt_enable =
 240                                         "interrupt is disabled|";
 241                                 active_level = " ";
 242                                 level_trig = " ";
 243                         }
 244
 245                         if (pin_reg & BIT(INTERRUPT_MASK_OFF))
 246                                 interrupt_mask =
 247                                         "interrupt is unmasked|";
 248                         else
 249                                 interrupt_mask =
 250                                         "interrupt is masked|";
 251
 252                         if (pin_reg & BIT(WAKE_CNTRL_OFF))
 253                                 wake_cntrl0 = "enable wakeup in S0i3 state|";
 254                         else
 255                                 wake_cntrl0 = "disable wakeup in S0i3 state|";
 256
 257                         if (pin_reg & BIT(WAKE_CNTRL_OFF))
 258                                 wake_cntrl1 = "enable wakeup in S3 state|";
 259                         else
 260                                 wake_cntrl1 = "disable wakeup in S3 state|";
 261
 262                         if (pin_reg & BIT(WAKE_CNTRL_OFF))
 263                                 wake_cntrl2 = "enable wakeup in S4/S5 state|";
 264                         else
 265                                 wake_cntrl2 = "disable wakeup in S4/S5 state|";
 266
 267                         if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
 268                                 pull_up_enable = "pull-up is enabled|";
 269                                 if (pin_reg & BIT(PULL_UP_SEL_OFF))
 270                                         pull_up_sel = "8k pull-up|";
 271                                 else
 272                                         pull_up_sel = "4k pull-up|";
 273                         } else {
 274                                 pull_up_enable = "pull-up is disabled|";
 275                                 pull_up_sel = " ";
 276                         }
 277
 278                         if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
 279                                 pull_down_enable = "pull-down is enabled|";
 280                         else
 281                                 pull_down_enable = "Pull-down is disabled|";
 282
 283                         if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
 284                                 pin_sts = " ";
 285                                 output_enable = "output is enabled|";
 286                                 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
 287                                         output_value = "output is high|";
 288                                 else
 289                                         output_value = "output is low|";
 290                         } else {
 291                                 output_enable = "output is disabled|";
 292                                 output_value = " ";
 293
 294                                 if (pin_reg & BIT(PIN_STS_OFF))
 295                                         pin_sts = "input is high|";
 296                                 else
 297                                         pin_sts = "input is low|";
 298                         }
 299
 300                         seq_printf(s, "%s %s %s %s %s %s\n"
 301                                 " %s %s %s %s %s %s %s 0x%x\n",
 302                                 level_trig, active_level, interrupt_enable,
 303                                 interrupt_mask, wake_cntrl0, wake_cntrl1,
 304                                 wake_cntrl2, pin_sts, pull_up_sel,
 305                                 pull_up_enable, pull_down_enable,
 306                                 output_value, output_enable, pin_reg);
 307                 }
 308         }
 309 }
 310 #else
 311 #define amd_gpio_dbg_show NULL
 312 #endif
 313
 314 static void amd_gpio_irq_enable(struct irq_data *d)
 315 {
 316         u32 pin_reg;
 317         unsigned long flags;
 318         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 319         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 320
 321         spin_lock_irqsave(&gpio_dev->lock, flags);
 322         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 323         pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
 324         pin_reg |= BIT(INTERRUPT_MASK_OFF);
 325         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 326         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 327 }
 328
 329 static void amd_gpio_irq_disable(struct irq_data *d)
 330 {
 331         u32 pin_reg;
 332         unsigned long flags;
 333         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 334         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 335
 336         spin_lock_irqsave(&gpio_dev->lock, flags);
 337         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 338         pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
 339         pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
 340         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 341         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 342 }
 343
 344 static void amd_gpio_irq_mask(struct irq_data *d)
 345 {
 346         u32 pin_reg;
 347         unsigned long flags;
 348         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 349         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 350
 351         spin_lock_irqsave(&gpio_dev->lock, flags);
 352         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 353         pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
 354         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 355         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 356 }
 357
 358 static void amd_gpio_irq_unmask(struct irq_data *d)
 359 {
 360         u32 pin_reg;
 361         unsigned long flags;
 362         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 363         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 364
 365         spin_lock_irqsave(&gpio_dev->lock, flags);
 366         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 367         pin_reg |= BIT(INTERRUPT_MASK_OFF);
 368         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 369         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 370 }
 371
 372 static void amd_gpio_irq_eoi(struct irq_data *d)
 373 {
 374         u32 reg;
 375         unsigned long flags;
 376         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 377         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 378
 379         spin_lock_irqsave(&gpio_dev->lock, flags);
 380         reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
 381         reg |= EOI_MASK;
 382         writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
 383         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 384 }
 385
 386 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 387 {
 388         int ret = 0;
 389         u32 pin_reg;
 390         unsigned long flags;
 391         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 392         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 393
 394         spin_lock_irqsave(&gpio_dev->lock, flags);
 395         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
 396
 397         switch (type & IRQ_TYPE_SENSE_MASK) {
 398         case IRQ_TYPE_EDGE_RISING:
 399                 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
 400                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 401                 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
 402                 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
 403                 irq_set_handler_locked(d, handle_edge_irq);
 404                 break;
 405
 406         case IRQ_TYPE_EDGE_FALLING:
 407                 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
 408                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 409                 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
 410                 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
 411                 irq_set_handler_locked(d, handle_edge_irq);
 412                 break;
 413
 414         case IRQ_TYPE_EDGE_BOTH:
 415                 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
 416                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 417                 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
 418                 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
 419                 irq_set_handler_locked(d, handle_edge_irq);
 420                 break;
 421
 422         case IRQ_TYPE_LEVEL_HIGH:
 423                 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
 424                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 425                 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
 426                 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
 427                 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
 428                 irq_set_handler_locked(d, handle_level_irq);
 429                 break;
 430
 431         case IRQ_TYPE_LEVEL_LOW:
 432                 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
 433                 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
 434                 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
 435                 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
 436                 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
 437                 irq_set_handler_locked(d, handle_level_irq);
 438                 break;
 439
 440         case IRQ_TYPE_NONE:
 441                 break;
 442
 443         default:
 444                 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
 445                 ret = -EINVAL;
 446         }
 447
 448         pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
 449         writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
 450         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 451
 452         return ret;
 453 }
 454
 455 static void amd_irq_ack(struct irq_data *d)
 456 {
 457         /*
 458          * based on HW design,there is no need to ack HW
 459          * before handle current irq. But this routine is
 460          * necessary for handle_edge_irq
 461         */
 462 }
 463
 464 static struct irq_chip amd_gpio_irqchip = {
 465         .name         = "amd_gpio",
 466         .irq_ack      = amd_irq_ack,
 467         .irq_enable   = amd_gpio_irq_enable,
 468         .irq_disable  = amd_gpio_irq_disable,
 469         .irq_mask     = amd_gpio_irq_mask,
 470         .irq_unmask   = amd_gpio_irq_unmask,
 471         .irq_eoi      = amd_gpio_irq_eoi,
 472         .irq_set_type = amd_gpio_irq_set_type,
 473 };
 474
 475 static void amd_gpio_irq_handler(struct irq_desc *desc)
 476 {
 477         u32 i;
 478         u32 off;
 479         u32 reg;
 480         u32 pin_reg;
 481         u64 reg64;
 482         int handled = 0;
 483         unsigned int irq;
 484         unsigned long flags;
 485         struct irq_chip *chip = irq_desc_get_chip(desc);
 486         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 487         struct amd_gpio *gpio_dev = to_amd_gpio(gc);
 488
 489         chained_irq_enter(chip, desc);
 490         /*enable GPIO interrupt again*/
 491         spin_lock_irqsave(&gpio_dev->lock, flags);
 492         reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
 493         reg64 = reg;
 494         reg64 = reg64 << 32;
 495
 496         reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
 497         reg64 |= reg;
 498         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 499
 500         /*
 501          * first 46 bits indicates interrupt status.
 502          * one bit represents four interrupt sources.
 503         */
 504         for (off = 0; off < 46 ; off++) {
 505                 if (reg64 & BIT(off)) {
 506                         for (i = 0; i < 4; i++) {
 507                                 pin_reg = readl(gpio_dev->base +
 508                                                 (off * 4 + i) * 4);
 509                                 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
 510                                         (pin_reg & BIT(WAKE_STS_OFF))) {
 511                                         irq = irq_find_mapping(gc->irqdomain,
 512                                                                 off * 4 + i);
 513                                         generic_handle_irq(irq);
 514                                         writel(pin_reg,
 515                                                 gpio_dev->base
 516                                                 + (off * 4 + i) * 4);
 517                                         handled++;
 518                                 }
 519                         }
 520                 }
 521         }
 522
 523         if (handled == 0)
 524                 handle_bad_irq(desc);
 525
 526         spin_lock_irqsave(&gpio_dev->lock, flags);
 527         reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
 528         reg |= EOI_MASK;
 529         writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
 530         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 531
 532         chained_irq_exit(chip, desc);
 533 }
 534
 535 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
 536 {
 537         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 538
 539         return gpio_dev->ngroups;
 540 }
 541
 542 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
 543                                       unsigned group)
 544 {
 545         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 546
 547         return gpio_dev->groups[group].name;
 548 }
 549
 550 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
 551                               unsigned group,
 552                               const unsigned **pins,
 553                               unsigned *num_pins)
 554 {
 555         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 556
 557         *pins = gpio_dev->groups[group].pins;
 558         *num_pins = gpio_dev->groups[group].npins;
 559         return 0;
 560 }
 561
 562 static const struct pinctrl_ops amd_pinctrl_ops = {
 563         .get_groups_count       = amd_get_groups_count,
 564         .get_group_name         = amd_get_group_name,
 565         .get_group_pins         = amd_get_group_pins,
 566 #ifdef CONFIG_OF
 567         .dt_node_to_map         = pinconf_generic_dt_node_to_map_group,
 568         .dt_free_map            = pinctrl_utils_dt_free_map,
 569 #endif
 570 };
 571
 572 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
 573                           unsigned int pin,
 574                           unsigned long *config)
 575 {
 576         u32 pin_reg;
 577         unsigned arg;
 578         unsigned long flags;
 579         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 580         enum pin_config_param param = pinconf_to_config_param(*config);
 581
 582         spin_lock_irqsave(&gpio_dev->lock, flags);
 583         pin_reg = readl(gpio_dev->base + pin*4);
 584         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 585         switch (param) {
 586         case PIN_CONFIG_INPUT_DEBOUNCE:
 587                 arg = pin_reg & DB_TMR_OUT_MASK;
 588                 break;
 589
 590         case PIN_CONFIG_BIAS_PULL_DOWN:
 591                 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
 592                 break;
 593
 594         case PIN_CONFIG_BIAS_PULL_UP:
 595                 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
 596                 break;
 597
 598         case PIN_CONFIG_DRIVE_STRENGTH:
 599                 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
 600                 break;
 601
 602         default:
 603                 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
 604                         param);
 605                 return -ENOTSUPP;
 606         }
 607
 608         *config = pinconf_to_config_packed(param, arg);
 609
 610         return 0;
 611 }
 612
 613 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 614                                 unsigned long *configs, unsigned num_configs)
 615 {
 616         int i;
 617         u32 arg;
 618         int ret = 0;
 619         u32 pin_reg;
 620         unsigned long flags;
 621         enum pin_config_param param;
 622         struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
 623
 624         spin_lock_irqsave(&gpio_dev->lock, flags);
 625         for (i = 0; i < num_configs; i++) {
 626                 param = pinconf_to_config_param(configs[i]);
 627                 arg = pinconf_to_config_argument(configs[i]);
 628                 pin_reg = readl(gpio_dev->base + pin*4);
 629
 630                 switch (param) {
 631                 case PIN_CONFIG_INPUT_DEBOUNCE:
 632                         pin_reg &= ~DB_TMR_OUT_MASK;
 633                         pin_reg |= arg & DB_TMR_OUT_MASK;
 634                         break;
 635
 636                 case PIN_CONFIG_BIAS_PULL_DOWN:
 637                         pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
 638                         pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
 639                         break;
 640
 641                 case PIN_CONFIG_BIAS_PULL_UP:
 642                         pin_reg &= ~BIT(PULL_UP_SEL_OFF);
 643                         pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
 644                         pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
 645                         pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
 646                         break;
 647
 648                 case PIN_CONFIG_DRIVE_STRENGTH:
 649                         pin_reg &= ~(DRV_STRENGTH_SEL_MASK
 650                                         << DRV_STRENGTH_SEL_OFF);
 651                         pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
 652                                         << DRV_STRENGTH_SEL_OFF;
 653                         break;
 654
 655                 default:
 656                         dev_err(&gpio_dev->pdev->dev,
 657                                 "Invalid config param %04x\n", param);
 658                         ret = -ENOTSUPP;
 659                 }
 660
 661                 writel(pin_reg, gpio_dev->base + pin*4);
 662         }
 663         spin_unlock_irqrestore(&gpio_dev->lock, flags);
 664
 665         return ret;
 666 }
 667
 668 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
 669                                 unsigned int group,
 670                                 unsigned long *config)
 671 {
 672         const unsigned *pins;
 673         unsigned npins;
 674         int ret;
 675
 676         ret = amd_get_group_pins(pctldev, group, &pins, &npins);
 677         if (ret)
 678                 return ret;
 679
 680         if (amd_pinconf_get(pctldev, pins[0], config))
 681                         return -ENOTSUPP;
 682
 683         return 0;
 684 }
 685
 686 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
 687                                 unsigned group, unsigned long *configs,
 688                                 unsigned num_configs)
 689 {
 690         const unsigned *pins;
 691         unsigned npins;
 692         int i, ret;
 693
 694         ret = amd_get_group_pins(pctldev, group, &pins, &npins);
 695         if (ret)
 696                 return ret;
 697         for (i = 0; i < npins; i++) {
 698                 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
 699                         return -ENOTSUPP;
 700         }
 701         return 0;
 702 }
 703
 704 static const struct pinconf_ops amd_pinconf_ops = {
 705         .pin_config_get         = amd_pinconf_get,
 706         .pin_config_set         = amd_pinconf_set,
 707         .pin_config_group_get = amd_pinconf_group_get,
 708         .pin_config_group_set = amd_pinconf_group_set,
 709 };
 710
 711 static struct pinctrl_desc amd_pinctrl_desc = {
 712         .pins   = kerncz_pins,
 713         .npins = ARRAY_SIZE(kerncz_pins),
 714         .pctlops = &amd_pinctrl_ops,
 715         .confops = &amd_pinconf_ops,
 716         .owner = THIS_MODULE,
 717 };
 718
 719 static int amd_gpio_probe(struct platform_device *pdev)
 720 {
 721         int ret = 0;
 722         int irq_base;
 723         struct resource *res;
 724         struct amd_gpio *gpio_dev;
 725
 726         gpio_dev = devm_kzalloc(&pdev->dev,
 727                                 sizeof(struct amd_gpio), GFP_KERNEL);
 728         if (!gpio_dev)
 729                 return -ENOMEM;
 730
 731         spin_lock_init(&gpio_dev->lock);
 732
 733         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 734         if (!res) {
 735                 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
 736                 return -EINVAL;
 737         }
 738
 739         gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
 740                                                 resource_size(res));
 741         if (IS_ERR(gpio_dev->base))
 742                 return PTR_ERR(gpio_dev->base);
 743
 744         irq_base = platform_get_irq(pdev, 0);
 745         if (irq_base < 0) {
 746                 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
 747                 return -EINVAL;
 748         }
 749
 750         gpio_dev->pdev = pdev;
 751         gpio_dev->gc.direction_input    = amd_gpio_direction_input;
 752         gpio_dev->gc.direction_output   = amd_gpio_direction_output;
 753         gpio_dev->gc.get                        = amd_gpio_get_value;
 754         gpio_dev->gc.set                        = amd_gpio_set_value;
 755         gpio_dev->gc.set_debounce       = amd_gpio_set_debounce;
 756         gpio_dev->gc.dbg_show           = amd_gpio_dbg_show;
 757
 758         gpio_dev->gc.base                       = 0;
 759         gpio_dev->gc.label                      = pdev->name;
 760         gpio_dev->gc.owner                      = THIS_MODULE;
 761         gpio_dev->gc.dev                        = &pdev->dev;
 762         gpio_dev->gc.ngpio                      = TOTAL_NUMBER_OF_PINS;
 763 #if defined(CONFIG_OF_GPIO)
 764         gpio_dev->gc.of_node                    = pdev->dev.of_node;
 765 #endif
 766
 767         gpio_dev->groups = kerncz_groups;
 768         gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
 769
 770         amd_pinctrl_desc.name = dev_name(&pdev->dev);
 771         gpio_dev->pctrl = pinctrl_register(&amd_pinctrl_desc,
 772                                         &pdev->dev, gpio_dev);
 773         if (IS_ERR(gpio_dev->pctrl)) {
 774                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 775                 return PTR_ERR(gpio_dev->pctrl);
 776         }
 777
 778         ret = gpiochip_add(&gpio_dev->gc);
 779         if (ret)
 780                 goto out1;
 781
 782         ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
 783                                 0, 0, TOTAL_NUMBER_OF_PINS);
 784         if (ret) {
 785                 dev_err(&pdev->dev, "Failed to add pin range\n");
 786                 goto out2;
 787         }
 788
 789         ret = gpiochip_irqchip_add(&gpio_dev->gc,
 790                                 &amd_gpio_irqchip,
 791                                 0,
 792                                 handle_simple_irq,
 793                                 IRQ_TYPE_NONE);
 794         if (ret) {
 795                 dev_err(&pdev->dev, "could not add irqchip\n");
 796                 ret = -ENODEV;
 797                 goto out2;
 798         }
 799
 800         gpiochip_set_chained_irqchip(&gpio_dev->gc,
 801                                  &amd_gpio_irqchip,
 802                                  irq_base,
 803                                  amd_gpio_irq_handler);
 804
 805         platform_set_drvdata(pdev, gpio_dev);
 806
 807         dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
 808         return ret;
 809
 810 out2:
 811         gpiochip_remove(&gpio_dev->gc);
 812
 813 out1:
 814         pinctrl_unregister(gpio_dev->pctrl);
 815         return ret;
 816 }
 817
 818 static int amd_gpio_remove(struct platform_device *pdev)
 819 {
 820         struct amd_gpio *gpio_dev;
 821
 822         gpio_dev = platform_get_drvdata(pdev);
 823
 824         gpiochip_remove(&gpio_dev->gc);
 825         pinctrl_unregister(gpio_dev->pctrl);
 826
 827         return 0;
 828 }
 829
 830 static const struct acpi_device_id amd_gpio_acpi_match[] = {
 831         { "AMD0030", 0 },
 832         { },
 833 };
 834 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
 835
 836 static struct platform_driver amd_gpio_driver = {
 837         .driver         = {
 838                 .name   = "amd_gpio",
 839                 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
 840         },
 841         .probe          = amd_gpio_probe,
 842         .remove         = amd_gpio_remove,
 843 };
 844
 845 module_platform_driver(amd_gpio_driver);
 846
 847 MODULE_LICENSE("GPL v2");
 848 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
 849 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");