kernel/drivers/pinctrl/intel/pinctrl-cherryview.c

   1 /*
   2  * Cherryview/Braswell pinctrl driver
   3  *
   4  * Copyright (C) 2014, Intel Corporation
   5  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *
   7  * This driver is based on the original Cherryview GPIO driver by
   8  *   Ning Li <ning.li@intel.com>
   9  *   Alan Cox <alan@linux.intel.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/types.h>
  20 #include <linux/gpio.h>
  21 #include <linux/gpio/driver.h>
  22 #include <linux/acpi.h>
  23 #include <linux/pinctrl/pinctrl.h>
  24 #include <linux/pinctrl/pinmux.h>
  25 #include <linux/pinctrl/pinconf.h>
  26 #include <linux/pinctrl/pinconf-generic.h>
  27 #include <linux/platform_device.h>
  28
  29 #define CHV_INTSTAT                     0x300
  30 #define CHV_INTMASK                     0x380
  31
  32 #define FAMILY_PAD_REGS_OFF             0x4400
  33 #define FAMILY_PAD_REGS_SIZE            0x400
  34 #define MAX_FAMILY_PAD_GPIO_NO          15
  35 #define GPIO_REGS_SIZE                  8
  36
  37 #define CHV_PADCTRL0                    0x000
  38 #define CHV_PADCTRL0_INTSEL_SHIFT       28
  39 #define CHV_PADCTRL0_INTSEL_MASK        (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
  40 #define CHV_PADCTRL0_TERM_UP            BIT(23)
  41 #define CHV_PADCTRL0_TERM_SHIFT         20
  42 #define CHV_PADCTRL0_TERM_MASK          (7 << CHV_PADCTRL0_TERM_SHIFT)
  43 #define CHV_PADCTRL0_TERM_20K           1
  44 #define CHV_PADCTRL0_TERM_5K            2
  45 #define CHV_PADCTRL0_TERM_1K            4
  46 #define CHV_PADCTRL0_PMODE_SHIFT        16
  47 #define CHV_PADCTRL0_PMODE_MASK         (0xf << CHV_PADCTRL0_PMODE_SHIFT)
  48 #define CHV_PADCTRL0_GPIOEN             BIT(15)
  49 #define CHV_PADCTRL0_GPIOCFG_SHIFT      8
  50 #define CHV_PADCTRL0_GPIOCFG_MASK       (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
  51 #define CHV_PADCTRL0_GPIOCFG_GPIO       0
  52 #define CHV_PADCTRL0_GPIOCFG_GPO        1
  53 #define CHV_PADCTRL0_GPIOCFG_GPI        2
  54 #define CHV_PADCTRL0_GPIOCFG_HIZ        3
  55 #define CHV_PADCTRL0_GPIOTXSTATE        BIT(1)
  56 #define CHV_PADCTRL0_GPIORXSTATE        BIT(0)
  57
  58 #define CHV_PADCTRL1                    0x004
  59 #define CHV_PADCTRL1_CFGLOCK            BIT(31)
  60 #define CHV_PADCTRL1_INVRXTX_SHIFT      4
  61 #define CHV_PADCTRL1_INVRXTX_MASK       (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
  62 #define CHV_PADCTRL1_INVRXTX_TXENABLE   (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
  63 #define CHV_PADCTRL1_ODEN               BIT(3)
  64 #define CHV_PADCTRL1_INVRXTX_RXDATA     (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
  65 #define CHV_PADCTRL1_INTWAKECFG_MASK    7
  66 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
  67 #define CHV_PADCTRL1_INTWAKECFG_RISING  2
  68 #define CHV_PADCTRL1_INTWAKECFG_BOTH    3
  69 #define CHV_PADCTRL1_INTWAKECFG_LEVEL   4
  70
  71 /**
  72  * struct chv_alternate_function - A per group or per pin alternate function
  73  * @pin: Pin number (only used in per pin configs)
  74  * @mode: Mode the pin should be set in
  75  * @invert_oe: Invert OE for this pin
  76  */
  77 struct chv_alternate_function {
  78         unsigned pin;
  79         u8 mode;
  80         bool invert_oe;
  81 };
  82
  83 /**
  84  * struct chv_pincgroup - describes a CHV pin group
  85  * @name: Name of the group
  86  * @pins: An array of pins in this group
  87  * @npins: Number of pins in this group
  88  * @altfunc: Alternate function applied to all pins in this group
  89  * @overrides: Alternate function override per pin or %NULL if not used
  90  * @noverrides: Number of per pin alternate function overrides if
  91  *              @overrides != NULL.
  92  */
  93 struct chv_pingroup {
  94         const char *name;
  95         const unsigned *pins;
  96         size_t npins;
  97         struct chv_alternate_function altfunc;
  98         const struct chv_alternate_function *overrides;
  99         size_t noverrides;
 100 };
 101
 102 /**
 103  * struct chv_function - A CHV pinmux function
 104  * @name: Name of the function
 105  * @groups: An array of groups for this function
 106  * @ngroups: Number of groups in @groups
 107  */
 108 struct chv_function {
 109         const char *name;
 110         const char * const *groups;
 111         size_t ngroups;
 112 };
 113
 114 /**
 115  * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
 116  * @base: Start pin number
 117  * @npins: Number of pins in this range
 118  */
 119 struct chv_gpio_pinrange {
 120         unsigned base;
 121         unsigned npins;
 122 };
 123
 124 /**
 125  * struct chv_community - A community specific configuration
 126  * @uid: ACPI _UID used to match the community
 127  * @pins: All pins in this community
 128  * @npins: Number of pins
 129  * @groups: All groups in this community
 130  * @ngroups: Number of groups
 131  * @functions: All functions in this community
 132  * @nfunctions: Number of functions
 133  * @ngpios: Number of GPIOs in this community
 134  * @gpio_ranges: An array of GPIO ranges in this community
 135  * @ngpio_ranges: Number of GPIO ranges
 136  * @ngpios: Total number of GPIOs in this community
 137  */
 138 struct chv_community {
 139         const char *uid;
 140         const struct pinctrl_pin_desc *pins;
 141         size_t npins;
 142         const struct chv_pingroup *groups;
 143         size_t ngroups;
 144         const struct chv_function *functions;
 145         size_t nfunctions;
 146         const struct chv_gpio_pinrange *gpio_ranges;
 147         size_t ngpio_ranges;
 148         size_t ngpios;
 149 };
 150
 151 struct chv_pin_context {
 152         u32 padctrl0;
 153         u32 padctrl1;
 154 };
 155
 156 /**
 157  * struct chv_pinctrl - CHV pinctrl private structure
 158  * @dev: Pointer to the parent device
 159  * @pctldesc: Pin controller description
 160  * @pctldev: Pointer to the pin controller device
 161  * @chip: GPIO chip in this pin controller
 162  * @regs: MMIO registers
 163  * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
 164  *              offset (in GPIO number space)
 165  * @community: Community this pinctrl instance represents
 166  *
 167  * The first group in @groups is expected to contain all pins that can be
 168  * used as GPIOs.
 169  */
 170 struct chv_pinctrl {
 171         struct device *dev;
 172         struct pinctrl_desc pctldesc;
 173         struct pinctrl_dev *pctldev;
 174         struct gpio_chip chip;
 175         void __iomem *regs;
 176         unsigned intr_lines[16];
 177         const struct chv_community *community;
 178         u32 saved_intmask;
 179         struct chv_pin_context *saved_pin_context;
 180 };
 181
 182 #define gpiochip_to_pinctrl(c) container_of(c, struct chv_pinctrl, chip)
 183
 184 #define ALTERNATE_FUNCTION(p, m, i)             \
 185         {                                       \
 186                 .pin = (p),                     \
 187                 .mode = (m),                    \
 188                 .invert_oe = (i),               \
 189         }
 190
 191 #define PIN_GROUP(n, p, m, i)                   \
 192         {                                       \
 193                 .name = (n),                    \
 194                 .pins = (p),                    \
 195                 .npins = ARRAY_SIZE((p)),       \
 196                 .altfunc.mode = (m),            \
 197                 .altfunc.invert_oe = (i),       \
 198         }
 199
 200 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o)  \
 201         {                                       \
 202                 .name = (n),                    \
 203                 .pins = (p),                    \
 204                 .npins = ARRAY_SIZE((p)),       \
 205                 .altfunc.mode = (m),            \
 206                 .altfunc.invert_oe = (i),       \
 207                 .overrides = (o),               \
 208                 .noverrides = ARRAY_SIZE((o)),  \
 209         }
 210
 211 #define FUNCTION(n, g)                          \
 212         {                                       \
 213                 .name = (n),                    \
 214                 .groups = (g),                  \
 215                 .ngroups = ARRAY_SIZE((g)),     \
 216         }
 217
 218 #define GPIO_PINRANGE(start, end)               \
 219         {                                       \
 220                 .base = (start),                \
 221                 .npins = (end) - (start) + 1,   \
 222         }
 223
 224 static const struct pinctrl_pin_desc southwest_pins[] = {
 225         PINCTRL_PIN(0, "FST_SPI_D2"),
 226         PINCTRL_PIN(1, "FST_SPI_D0"),
 227         PINCTRL_PIN(2, "FST_SPI_CLK"),
 228         PINCTRL_PIN(3, "FST_SPI_D3"),
 229         PINCTRL_PIN(4, "FST_SPI_CS1_B"),
 230         PINCTRL_PIN(5, "FST_SPI_D1"),
 231         PINCTRL_PIN(6, "FST_SPI_CS0_B"),
 232         PINCTRL_PIN(7, "FST_SPI_CS2_B"),
 233
 234         PINCTRL_PIN(15, "UART1_RTS_B"),
 235         PINCTRL_PIN(16, "UART1_RXD"),
 236         PINCTRL_PIN(17, "UART2_RXD"),
 237         PINCTRL_PIN(18, "UART1_CTS_B"),
 238         PINCTRL_PIN(19, "UART2_RTS_B"),
 239         PINCTRL_PIN(20, "UART1_TXD"),
 240         PINCTRL_PIN(21, "UART2_TXD"),
 241         PINCTRL_PIN(22, "UART2_CTS_B"),
 242
 243         PINCTRL_PIN(30, "MF_HDA_CLK"),
 244         PINCTRL_PIN(31, "MF_HDA_RSTB"),
 245         PINCTRL_PIN(32, "MF_HDA_SDIO"),
 246         PINCTRL_PIN(33, "MF_HDA_SDO"),
 247         PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
 248         PINCTRL_PIN(35, "MF_HDA_SYNC"),
 249         PINCTRL_PIN(36, "MF_HDA_SDI1"),
 250         PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
 251
 252         PINCTRL_PIN(45, "I2C5_SDA"),
 253         PINCTRL_PIN(46, "I2C4_SDA"),
 254         PINCTRL_PIN(47, "I2C6_SDA"),
 255         PINCTRL_PIN(48, "I2C5_SCL"),
 256         PINCTRL_PIN(49, "I2C_NFC_SDA"),
 257         PINCTRL_PIN(50, "I2C4_SCL"),
 258         PINCTRL_PIN(51, "I2C6_SCL"),
 259         PINCTRL_PIN(52, "I2C_NFC_SCL"),
 260
 261         PINCTRL_PIN(60, "I2C1_SDA"),
 262         PINCTRL_PIN(61, "I2C0_SDA"),
 263         PINCTRL_PIN(62, "I2C2_SDA"),
 264         PINCTRL_PIN(63, "I2C1_SCL"),
 265         PINCTRL_PIN(64, "I2C3_SDA"),
 266         PINCTRL_PIN(65, "I2C0_SCL"),
 267         PINCTRL_PIN(66, "I2C2_SCL"),
 268         PINCTRL_PIN(67, "I2C3_SCL"),
 269
 270         PINCTRL_PIN(75, "SATA_GP0"),
 271         PINCTRL_PIN(76, "SATA_GP1"),
 272         PINCTRL_PIN(77, "SATA_LEDN"),
 273         PINCTRL_PIN(78, "SATA_GP2"),
 274         PINCTRL_PIN(79, "MF_SMB_ALERTB"),
 275         PINCTRL_PIN(80, "SATA_GP3"),
 276         PINCTRL_PIN(81, "MF_SMB_CLK"),
 277         PINCTRL_PIN(82, "MF_SMB_DATA"),
 278
 279         PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
 280         PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
 281         PINCTRL_PIN(92, "GP_SSP_2_CLK"),
 282         PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
 283         PINCTRL_PIN(94, "GP_SSP_2_RXD"),
 284         PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
 285         PINCTRL_PIN(96, "GP_SSP_2_FS"),
 286         PINCTRL_PIN(97, "GP_SSP_2_TXD"),
 287 };
 288
 289 static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 290 static const unsigned southwest_uart0_pins[] = { 16, 20 };
 291 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
 292 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
 293 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
 294 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
 295 static const unsigned southwest_lpe_pins[] = {
 296         30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
 297 };
 298 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
 299 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
 300 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
 301 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
 302 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
 303 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
 304 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
 305 static const unsigned southwest_smbus_pins[] = { 79, 81, 82 };
 306 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
 307
 308 /* LPE I2S TXD pins need to have invert_oe set */
 309 static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
 310         ALTERNATE_FUNCTION(30, 1, true),
 311         ALTERNATE_FUNCTION(34, 1, true),
 312         ALTERNATE_FUNCTION(97, 1, true),
 313 };
 314
 315 /*
 316  * Two spi3 chipselects are available in different mode than the main spi3
 317  * functionality, which is using mode 1.
 318  */
 319 static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
 320         ALTERNATE_FUNCTION(76, 3, false),
 321         ALTERNATE_FUNCTION(80, 3, false),
 322 };
 323
 324 static const struct chv_pingroup southwest_groups[] = {
 325         PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false),
 326         PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false),
 327         PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false),
 328         PIN_GROUP("hda_grp", southwest_hda_pins, 2, false),
 329         PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true),
 330         PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true),
 331         PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true),
 332         PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true),
 333         PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true),
 334         PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true),
 335         PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true),
 336         PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
 337
 338         PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
 339                                 southwest_lpe_altfuncs),
 340         PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
 341                                 southwest_spi3_altfuncs),
 342 };
 343
 344 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
 345 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
 346 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
 347 static const char * const southwest_hda_groups[] = { "hda_grp" };
 348 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
 349 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
 350 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
 351 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
 352 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
 353 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
 354 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
 355 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
 356 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
 357 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
 358
 359 /*
 360  * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
 361  * enabled only as GPIOs.
 362  */
 363 static const struct chv_function southwest_functions[] = {
 364         FUNCTION("uart0", southwest_uart0_groups),
 365         FUNCTION("uart1", southwest_uart1_groups),
 366         FUNCTION("uart2", southwest_uart2_groups),
 367         FUNCTION("hda", southwest_hda_groups),
 368         FUNCTION("lpe", southwest_lpe_groups),
 369         FUNCTION("i2c0", southwest_i2c0_groups),
 370         FUNCTION("i2c1", southwest_i2c1_groups),
 371         FUNCTION("i2c2", southwest_i2c2_groups),
 372         FUNCTION("i2c3", southwest_i2c3_groups),
 373         FUNCTION("i2c4", southwest_i2c4_groups),
 374         FUNCTION("i2c5", southwest_i2c5_groups),
 375         FUNCTION("i2c6", southwest_i2c6_groups),
 376         FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
 377         FUNCTION("spi3", southwest_spi3_groups),
 378 };
 379
 380 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
 381         GPIO_PINRANGE(0, 7),
 382         GPIO_PINRANGE(15, 22),
 383         GPIO_PINRANGE(30, 37),
 384         GPIO_PINRANGE(45, 52),
 385         GPIO_PINRANGE(60, 67),
 386         GPIO_PINRANGE(75, 82),
 387         GPIO_PINRANGE(90, 97),
 388 };
 389
 390 static const struct chv_community southwest_community = {
 391         .uid = "1",
 392         .pins = southwest_pins,
 393         .npins = ARRAY_SIZE(southwest_pins),
 394         .groups = southwest_groups,
 395         .ngroups = ARRAY_SIZE(southwest_groups),
 396         .functions = southwest_functions,
 397         .nfunctions = ARRAY_SIZE(southwest_functions),
 398         .gpio_ranges = southwest_gpio_ranges,
 399         .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
 400         .ngpios = ARRAY_SIZE(southwest_pins),
 401 };
 402
 403 static const struct pinctrl_pin_desc north_pins[] = {
 404         PINCTRL_PIN(0, "GPIO_DFX_0"),
 405         PINCTRL_PIN(1, "GPIO_DFX_3"),
 406         PINCTRL_PIN(2, "GPIO_DFX_7"),
 407         PINCTRL_PIN(3, "GPIO_DFX_1"),
 408         PINCTRL_PIN(4, "GPIO_DFX_5"),
 409         PINCTRL_PIN(5, "GPIO_DFX_4"),
 410         PINCTRL_PIN(6, "GPIO_DFX_8"),
 411         PINCTRL_PIN(7, "GPIO_DFX_2"),
 412         PINCTRL_PIN(8, "GPIO_DFX_6"),
 413
 414         PINCTRL_PIN(15, "GPIO_SUS0"),
 415         PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
 416         PINCTRL_PIN(17, "GPIO_SUS3"),
 417         PINCTRL_PIN(18, "GPIO_SUS7"),
 418         PINCTRL_PIN(19, "GPIO_SUS1"),
 419         PINCTRL_PIN(20, "GPIO_SUS5"),
 420         PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
 421         PINCTRL_PIN(22, "GPIO_SUS4"),
 422         PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
 423         PINCTRL_PIN(24, "GPIO_SUS2"),
 424         PINCTRL_PIN(25, "GPIO_SUS6"),
 425         PINCTRL_PIN(26, "CX_PREQ_B"),
 426         PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
 427
 428         PINCTRL_PIN(30, "TRST_B"),
 429         PINCTRL_PIN(31, "TCK"),
 430         PINCTRL_PIN(32, "PROCHOT_B"),
 431         PINCTRL_PIN(33, "SVIDO_DATA"),
 432         PINCTRL_PIN(34, "TMS"),
 433         PINCTRL_PIN(35, "CX_PRDY_B_2"),
 434         PINCTRL_PIN(36, "TDO_2"),
 435         PINCTRL_PIN(37, "CX_PRDY_B"),
 436         PINCTRL_PIN(38, "SVIDO_ALERT_B"),
 437         PINCTRL_PIN(39, "TDO"),
 438         PINCTRL_PIN(40, "SVIDO_CLK"),
 439         PINCTRL_PIN(41, "TDI"),
 440
 441         PINCTRL_PIN(45, "GP_CAMERASB_05"),
 442         PINCTRL_PIN(46, "GP_CAMERASB_02"),
 443         PINCTRL_PIN(47, "GP_CAMERASB_08"),
 444         PINCTRL_PIN(48, "GP_CAMERASB_00"),
 445         PINCTRL_PIN(49, "GP_CAMERASB_06"),
 446         PINCTRL_PIN(50, "GP_CAMERASB_10"),
 447         PINCTRL_PIN(51, "GP_CAMERASB_03"),
 448         PINCTRL_PIN(52, "GP_CAMERASB_09"),
 449         PINCTRL_PIN(53, "GP_CAMERASB_01"),
 450         PINCTRL_PIN(54, "GP_CAMERASB_07"),
 451         PINCTRL_PIN(55, "GP_CAMERASB_11"),
 452         PINCTRL_PIN(56, "GP_CAMERASB_04"),
 453
 454         PINCTRL_PIN(60, "PANEL0_BKLTEN"),
 455         PINCTRL_PIN(61, "HV_DDI0_HPD"),
 456         PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
 457         PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
 458         PINCTRL_PIN(64, "HV_DDI1_HPD"),
 459         PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
 460         PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
 461         PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
 462         PINCTRL_PIN(68, "HV_DDI2_HPD"),
 463         PINCTRL_PIN(69, "PANEL1_VDDEN"),
 464         PINCTRL_PIN(70, "PANEL1_BKLTEN"),
 465         PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
 466         PINCTRL_PIN(72, "PANEL0_VDDEN"),
 467 };
 468
 469 static const struct chv_gpio_pinrange north_gpio_ranges[] = {
 470         GPIO_PINRANGE(0, 8),
 471         GPIO_PINRANGE(15, 27),
 472         GPIO_PINRANGE(30, 41),
 473         GPIO_PINRANGE(45, 56),
 474         GPIO_PINRANGE(60, 72),
 475 };
 476
 477 static const struct chv_community north_community = {
 478         .uid = "2",
 479         .pins = north_pins,
 480         .npins = ARRAY_SIZE(north_pins),
 481         .gpio_ranges = north_gpio_ranges,
 482         .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
 483         .ngpios = ARRAY_SIZE(north_pins),
 484 };
 485
 486 static const struct pinctrl_pin_desc east_pins[] = {
 487         PINCTRL_PIN(0, "PMU_SLP_S3_B"),
 488         PINCTRL_PIN(1, "PMU_BATLOW_B"),
 489         PINCTRL_PIN(2, "SUS_STAT_B"),
 490         PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
 491         PINCTRL_PIN(4, "PMU_AC_PRESENT"),
 492         PINCTRL_PIN(5, "PMU_PLTRST_B"),
 493         PINCTRL_PIN(6, "PMU_SUSCLK"),
 494         PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
 495         PINCTRL_PIN(8, "PMU_PWRBTN_B"),
 496         PINCTRL_PIN(9, "PMU_SLP_S4_B"),
 497         PINCTRL_PIN(10, "PMU_WAKE_B"),
 498         PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
 499
 500         PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
 501         PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
 502         PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
 503         PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
 504         PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
 505         PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
 506         PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
 507         PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
 508         PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
 509         PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
 510         PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
 511         PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
 512 };
 513
 514 static const struct chv_gpio_pinrange east_gpio_ranges[] = {
 515         GPIO_PINRANGE(0, 11),
 516         GPIO_PINRANGE(15, 26),
 517 };
 518
 519 static const struct chv_community east_community = {
 520         .uid = "3",
 521         .pins = east_pins,
 522         .npins = ARRAY_SIZE(east_pins),
 523         .gpio_ranges = east_gpio_ranges,
 524         .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
 525         .ngpios = ARRAY_SIZE(east_pins),
 526 };
 527
 528 static const struct pinctrl_pin_desc southeast_pins[] = {
 529         PINCTRL_PIN(0, "MF_PLT_CLK0"),
 530         PINCTRL_PIN(1, "PWM1"),
 531         PINCTRL_PIN(2, "MF_PLT_CLK1"),
 532         PINCTRL_PIN(3, "MF_PLT_CLK4"),
 533         PINCTRL_PIN(4, "MF_PLT_CLK3"),
 534         PINCTRL_PIN(5, "PWM0"),
 535         PINCTRL_PIN(6, "MF_PLT_CLK5"),
 536         PINCTRL_PIN(7, "MF_PLT_CLK2"),
 537
 538         PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
 539         PINCTRL_PIN(16, "SDMMC1_CLK"),
 540         PINCTRL_PIN(17, "SDMMC1_D0"),
 541         PINCTRL_PIN(18, "SDMMC2_D1"),
 542         PINCTRL_PIN(19, "SDMMC2_CLK"),
 543         PINCTRL_PIN(20, "SDMMC1_D2"),
 544         PINCTRL_PIN(21, "SDMMC2_D2"),
 545         PINCTRL_PIN(22, "SDMMC2_CMD"),
 546         PINCTRL_PIN(23, "SDMMC1_CMD"),
 547         PINCTRL_PIN(24, "SDMMC1_D1"),
 548         PINCTRL_PIN(25, "SDMMC2_D0"),
 549         PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
 550
 551         PINCTRL_PIN(30, "SDMMC3_D1"),
 552         PINCTRL_PIN(31, "SDMMC3_CLK"),
 553         PINCTRL_PIN(32, "SDMMC3_D3"),
 554         PINCTRL_PIN(33, "SDMMC3_D2"),
 555         PINCTRL_PIN(34, "SDMMC3_CMD"),
 556         PINCTRL_PIN(35, "SDMMC3_D0"),
 557
 558         PINCTRL_PIN(45, "MF_LPC_AD2"),
 559         PINCTRL_PIN(46, "LPC_CLKRUNB"),
 560         PINCTRL_PIN(47, "MF_LPC_AD0"),
 561         PINCTRL_PIN(48, "LPC_FRAMEB"),
 562         PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
 563         PINCTRL_PIN(50, "MF_LPC_AD3"),
 564         PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
 565         PINCTRL_PIN(52, "MF_LPC_AD1"),
 566
 567         PINCTRL_PIN(60, "SPI1_MISO"),
 568         PINCTRL_PIN(61, "SPI1_CSO_B"),
 569         PINCTRL_PIN(62, "SPI1_CLK"),
 570         PINCTRL_PIN(63, "MMC1_D6"),
 571         PINCTRL_PIN(64, "SPI1_MOSI"),
 572         PINCTRL_PIN(65, "MMC1_D5"),
 573         PINCTRL_PIN(66, "SPI1_CS1_B"),
 574         PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
 575         PINCTRL_PIN(68, "MMC1_D7"),
 576         PINCTRL_PIN(69, "MMC1_RCLK"),
 577
 578         PINCTRL_PIN(75, "USB_OC1_B"),
 579         PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
 580         PINCTRL_PIN(77, "GPIO_ALERT"),
 581         PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
 582         PINCTRL_PIN(79, "ILB_SERIRQ"),
 583         PINCTRL_PIN(80, "USB_OC0_B"),
 584         PINCTRL_PIN(81, "SDMMC3_CD_B"),
 585         PINCTRL_PIN(82, "SPKR"),
 586         PINCTRL_PIN(83, "SUSPWRDNACK"),
 587         PINCTRL_PIN(84, "SPARE_PIN"),
 588         PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
 589 };
 590
 591 static const unsigned southeast_pwm0_pins[] = { 5 };
 592 static const unsigned southeast_pwm1_pins[] = { 1 };
 593 static const unsigned southeast_sdmmc1_pins[] = {
 594         16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
 595 };
 596 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
 597 static const unsigned southeast_sdmmc3_pins[] = {
 598         30, 31, 32, 33, 34, 35, 78, 81, 85,
 599 };
 600 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
 601 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
 602
 603 static const struct chv_pingroup southeast_groups[] = {
 604         PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false),
 605         PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false),
 606         PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
 607         PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
 608         PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
 609         PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false),
 610         PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false),
 611 };
 612
 613 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
 614 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
 615 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
 616 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
 617 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
 618 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
 619 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
 620
 621 static const struct chv_function southeast_functions[] = {
 622         FUNCTION("pwm0", southeast_pwm0_groups),
 623         FUNCTION("pwm1", southeast_pwm1_groups),
 624         FUNCTION("sdmmc1", southeast_sdmmc1_groups),
 625         FUNCTION("sdmmc2", southeast_sdmmc2_groups),
 626         FUNCTION("sdmmc3", southeast_sdmmc3_groups),
 627         FUNCTION("spi1", southeast_spi1_groups),
 628         FUNCTION("spi2", southeast_spi2_groups),
 629 };
 630
 631 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
 632         GPIO_PINRANGE(0, 7),
 633         GPIO_PINRANGE(15, 26),
 634         GPIO_PINRANGE(30, 35),
 635         GPIO_PINRANGE(45, 52),
 636         GPIO_PINRANGE(60, 69),
 637         GPIO_PINRANGE(75, 85),
 638 };
 639
 640 static const struct chv_community southeast_community = {
 641         .uid = "4",
 642         .pins = southeast_pins,
 643         .npins = ARRAY_SIZE(southeast_pins),
 644         .groups = southeast_groups,
 645         .ngroups = ARRAY_SIZE(southeast_groups),
 646         .functions = southeast_functions,
 647         .nfunctions = ARRAY_SIZE(southeast_functions),
 648         .gpio_ranges = southeast_gpio_ranges,
 649         .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
 650         .ngpios = ARRAY_SIZE(southeast_pins),
 651 };
 652
 653 static const struct chv_community *chv_communities[] = {
 654         &southwest_community,
 655         &north_community,
 656         &east_community,
 657         &southeast_community,
 658 };
 659
 660 /*
 661  * Lock to serialize register accesses
 662  *
 663  * Due to a silicon issue, a shared lock must be used to prevent
 664  * concurrent accesses across the 4 GPIO controllers.
 665  *
 666  * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
 667  * errata #CHT34, for further information.
 668  */
 669 static DEFINE_RAW_SPINLOCK(chv_lock);
 670
 671 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset,
 672                                 unsigned reg)
 673 {
 674         unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
 675         unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
 676
 677         offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
 678                  GPIO_REGS_SIZE * pad_no;
 679
 680         return pctrl->regs + offset + reg;
 681 }
 682
 683 static void chv_writel(u32 value, void __iomem *reg)
 684 {
 685         writel(value, reg);
 686         /* simple readback to confirm the bus transferring done */
 687         readl(reg);
 688 }
 689
 690 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
 691 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset)
 692 {
 693         void __iomem *reg;
 694
 695         reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
 696         return readl(reg) & CHV_PADCTRL1_CFGLOCK;
 697 }
 698
 699 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
 700 {
 701         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 702
 703         return pctrl->community->ngroups;
 704 }
 705
 706 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
 707                                       unsigned group)
 708 {
 709         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 710
 711         return pctrl->community->groups[group].name;
 712 }
 713
 714 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 715                               const unsigned **pins, unsigned *npins)
 716 {
 717         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 718
 719         *pins = pctrl->community->groups[group].pins;
 720         *npins = pctrl->community->groups[group].npins;
 721         return 0;
 722 }
 723
 724 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 725                              unsigned offset)
 726 {
 727         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 728         unsigned long flags;
 729         u32 ctrl0, ctrl1;
 730         bool locked;
 731
 732         raw_spin_lock_irqsave(&chv_lock, flags);
 733
 734         ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
 735         ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
 736         locked = chv_pad_locked(pctrl, offset);
 737
 738         raw_spin_unlock_irqrestore(&chv_lock, flags);
 739
 740         if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
 741                 seq_puts(s, "GPIO ");
 742         } else {
 743                 u32 mode;
 744
 745                 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
 746                 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
 747
 748                 seq_printf(s, "mode %d ", mode);
 749         }
 750
 751         seq_printf(s, "ctrl0 0x%08x ctrl1 0x%08x", ctrl0, ctrl1);
 752
 753         if (locked)
 754                 seq_puts(s, " [LOCKED]");
 755 }
 756
 757 static const struct pinctrl_ops chv_pinctrl_ops = {
 758         .get_groups_count = chv_get_groups_count,
 759         .get_group_name = chv_get_group_name,
 760         .get_group_pins = chv_get_group_pins,
 761         .pin_dbg_show = chv_pin_dbg_show,
 762 };
 763
 764 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
 765 {
 766         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 767
 768         return pctrl->community->nfunctions;
 769 }
 770
 771 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
 772                                          unsigned function)
 773 {
 774         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 775
 776         return pctrl->community->functions[function].name;
 777 }
 778
 779 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
 780                                    unsigned function,
 781                                    const char * const **groups,
 782                                    unsigned * const ngroups)
 783 {
 784         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 785
 786         *groups = pctrl->community->functions[function].groups;
 787         *ngroups = pctrl->community->functions[function].ngroups;
 788         return 0;
 789 }
 790
 791 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 792                               unsigned group)
 793 {
 794         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 795         const struct chv_pingroup *grp;
 796         unsigned long flags;
 797         int i;
 798
 799         grp = &pctrl->community->groups[group];
 800
 801         raw_spin_lock_irqsave(&chv_lock, flags);
 802
 803         /* Check first that the pad is not locked */
 804         for (i = 0; i < grp->npins; i++) {
 805                 if (chv_pad_locked(pctrl, grp->pins[i])) {
 806                         dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
 807                                  grp->pins[i]);
 808                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 809                         return -EBUSY;
 810                 }
 811         }
 812
 813         for (i = 0; i < grp->npins; i++) {
 814                 const struct chv_alternate_function *altfunc = &grp->altfunc;
 815                 int pin = grp->pins[i];
 816                 void __iomem *reg;
 817                 u32 value;
 818
 819                 /* Check if there is pin-specific config */
 820                 if (grp->overrides) {
 821                         int j;
 822
 823                         for (j = 0; j < grp->noverrides; j++) {
 824                                 if (grp->overrides[j].pin == pin) {
 825                                         altfunc = &grp->overrides[j];
 826                                         break;
 827                                 }
 828                         }
 829                 }
 830
 831                 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
 832                 value = readl(reg);
 833                 /* Disable GPIO mode */
 834                 value &= ~CHV_PADCTRL0_GPIOEN;
 835                 /* Set to desired mode */
 836                 value &= ~CHV_PADCTRL0_PMODE_MASK;
 837                 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
 838                 chv_writel(value, reg);
 839
 840                 /* Update for invert_oe */
 841                 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
 842                 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
 843                 if (altfunc->invert_oe)
 844                         value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
 845                 chv_writel(value, reg);
 846
 847                 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
 848                         pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
 849         }
 850
 851         raw_spin_unlock_irqrestore(&chv_lock, flags);
 852
 853         return 0;
 854 }
 855
 856 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
 857                                    struct pinctrl_gpio_range *range,
 858                                    unsigned offset)
 859 {
 860         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 861         unsigned long flags;
 862         void __iomem *reg;
 863         u32 value;
 864
 865         raw_spin_lock_irqsave(&chv_lock, flags);
 866
 867         if (chv_pad_locked(pctrl, offset)) {
 868                 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
 869                 if (!(value & CHV_PADCTRL0_GPIOEN)) {
 870                         /* Locked so cannot enable */
 871                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 872                         return -EBUSY;
 873                 }
 874         } else {
 875                 int i;
 876
 877                 /* Reset the interrupt mapping */
 878                 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
 879                         if (pctrl->intr_lines[i] == offset) {
 880                                 pctrl->intr_lines[i] = 0;
 881                                 break;
 882                         }
 883                 }
 884
 885                 /* Disable interrupt generation */
 886                 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
 887                 value = readl(reg);
 888                 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
 889                 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
 890                 chv_writel(value, reg);
 891
 892                 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
 893                 value = readl(reg);
 894
 895                 /*
 896                  * If the pin is in HiZ mode (both TX and RX buffers are
 897                  * disabled) we turn it to be input now.
 898                  */
 899                 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
 900                      (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
 901                         value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
 902                         value |= CHV_PADCTRL0_GPIOCFG_GPI <<
 903                                 CHV_PADCTRL0_GPIOCFG_SHIFT;
 904                 }
 905
 906                 /* Switch to a GPIO mode */
 907                 value |= CHV_PADCTRL0_GPIOEN;
 908                 chv_writel(value, reg);
 909         }
 910
 911         raw_spin_unlock_irqrestore(&chv_lock, flags);
 912
 913         return 0;
 914 }
 915
 916 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
 917                                   struct pinctrl_gpio_range *range,
 918                                   unsigned offset)
 919 {
 920         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 921         unsigned long flags;
 922         void __iomem *reg;
 923         u32 value;
 924
 925         raw_spin_lock_irqsave(&chv_lock, flags);
 926
 927         reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
 928         value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
 929         chv_writel(value, reg);
 930
 931         raw_spin_unlock_irqrestore(&chv_lock, flags);
 932 }
 933
 934 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
 935                                   struct pinctrl_gpio_range *range,
 936                                   unsigned offset, bool input)
 937 {
 938         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 939         void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
 940         unsigned long flags;
 941         u32 ctrl0;
 942
 943         raw_spin_lock_irqsave(&chv_lock, flags);
 944
 945         ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
 946         if (input)
 947                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
 948         else
 949                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
 950         chv_writel(ctrl0, reg);
 951
 952         raw_spin_unlock_irqrestore(&chv_lock, flags);
 953
 954         return 0;
 955 }
 956
 957 static const struct pinmux_ops chv_pinmux_ops = {
 958         .get_functions_count = chv_get_functions_count,
 959         .get_function_name = chv_get_function_name,
 960         .get_function_groups = chv_get_function_groups,
 961         .set_mux = chv_pinmux_set_mux,
 962         .gpio_request_enable = chv_gpio_request_enable,
 963         .gpio_disable_free = chv_gpio_disable_free,
 964         .gpio_set_direction = chv_gpio_set_direction,
 965 };
 966
 967 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
 968                           unsigned long *config)
 969 {
 970         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 971         enum pin_config_param param = pinconf_to_config_param(*config);
 972         unsigned long flags;
 973         u32 ctrl0, ctrl1;
 974         u16 arg = 0;
 975         u32 term;
 976
 977         raw_spin_lock_irqsave(&chv_lock, flags);
 978         ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
 979         ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
 980         raw_spin_unlock_irqrestore(&chv_lock, flags);
 981
 982         term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
 983
 984         switch (param) {
 985         case PIN_CONFIG_BIAS_DISABLE:
 986                 if (term)
 987                         return -EINVAL;
 988                 break;
 989
 990         case PIN_CONFIG_BIAS_PULL_UP:
 991                 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
 992                         return -EINVAL;
 993
 994                 switch (term) {
 995                 case CHV_PADCTRL0_TERM_20K:
 996                         arg = 20000;
 997                         break;
 998                 case CHV_PADCTRL0_TERM_5K:
 999                         arg = 5000;
1000                         break;
1001                 case CHV_PADCTRL0_TERM_1K:
1002                         arg = 1000;
1003                         break;
1004                 }
1005
1006                 break;
1007
1008         case PIN_CONFIG_BIAS_PULL_DOWN:
1009                 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1010                         return -EINVAL;
1011
1012                 switch (term) {
1013                 case CHV_PADCTRL0_TERM_20K:
1014                         arg = 20000;
1015                         break;
1016                 case CHV_PADCTRL0_TERM_5K:
1017                         arg = 5000;
1018                         break;
1019                 }
1020
1021                 break;
1022
1023         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1024                 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1025                         return -EINVAL;
1026                 break;
1027
1028         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1029                 u32 cfg;
1030
1031                 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1032                 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1033                 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1034                         return -EINVAL;
1035
1036                 break;
1037         }
1038
1039         default:
1040                 return -ENOTSUPP;
1041         }
1042
1043         *config = pinconf_to_config_packed(param, arg);
1044         return 0;
1045 }
1046
1047 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
1048                                enum pin_config_param param, u16 arg)
1049 {
1050         void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1051         unsigned long flags;
1052         u32 ctrl0, pull;
1053
1054         raw_spin_lock_irqsave(&chv_lock, flags);
1055         ctrl0 = readl(reg);
1056
1057         switch (param) {
1058         case PIN_CONFIG_BIAS_DISABLE:
1059                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1060                 break;
1061
1062         case PIN_CONFIG_BIAS_PULL_UP:
1063                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1064
1065                 switch (arg) {
1066                 case 1000:
1067                         /* For 1k there is only pull up */
1068                         pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1069                         break;
1070                 case 5000:
1071                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1072                         break;
1073                 case 20000:
1074                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1075                         break;
1076                 default:
1077                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1078                         return -EINVAL;
1079                 }
1080
1081                 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1082                 break;
1083
1084         case PIN_CONFIG_BIAS_PULL_DOWN:
1085                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1086
1087                 switch (arg) {
1088                 case 5000:
1089                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1090                         break;
1091                 case 20000:
1092                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1093                         break;
1094                 default:
1095                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1096                         return -EINVAL;
1097                 }
1098
1099                 ctrl0 |= pull;
1100                 break;
1101
1102         default:
1103                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1104                 return -EINVAL;
1105         }
1106
1107         chv_writel(ctrl0, reg);
1108         raw_spin_unlock_irqrestore(&chv_lock, flags);
1109
1110         return 0;
1111 }
1112
1113 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1114                           unsigned long *configs, unsigned nconfigs)
1115 {
1116         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1117         enum pin_config_param param;
1118         int i, ret;
1119         u16 arg;
1120
1121         if (chv_pad_locked(pctrl, pin))
1122                 return -EBUSY;
1123
1124         for (i = 0; i < nconfigs; i++) {
1125                 param = pinconf_to_config_param(configs[i]);
1126                 arg = pinconf_to_config_argument(configs[i]);
1127
1128                 switch (param) {
1129                 case PIN_CONFIG_BIAS_DISABLE:
1130                 case PIN_CONFIG_BIAS_PULL_UP:
1131                 case PIN_CONFIG_BIAS_PULL_DOWN:
1132                         ret = chv_config_set_pull(pctrl, pin, param, arg);
1133                         if (ret)
1134                                 return ret;
1135                         break;
1136
1137                 default:
1138                         return -ENOTSUPP;
1139                 }
1140
1141                 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1142                         param, arg);
1143         }
1144
1145         return 0;
1146 }
1147
1148 static const struct pinconf_ops chv_pinconf_ops = {
1149         .is_generic = true,
1150         .pin_config_set = chv_config_set,
1151         .pin_config_get = chv_config_get,
1152 };
1153
1154 static struct pinctrl_desc chv_pinctrl_desc = {
1155         .pctlops = &chv_pinctrl_ops,
1156         .pmxops = &chv_pinmux_ops,
1157         .confops = &chv_pinconf_ops,
1158         .owner = THIS_MODULE,
1159 };
1160
1161 static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl,
1162                                        unsigned offset)
1163 {
1164         return pctrl->community->pins[offset].number;
1165 }
1166
1167 static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
1168 {
1169         struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
1170         int pin = chv_gpio_offset_to_pin(pctrl, offset);
1171         unsigned long flags;
1172         u32 ctrl0, cfg;
1173
1174         raw_spin_lock_irqsave(&chv_lock, flags);
1175         ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1176         raw_spin_unlock_irqrestore(&chv_lock, flags);
1177
1178         cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1179         cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1180
1181         if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1182                 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1183         return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1184 }
1185
1186 static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1187 {
1188         struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
1189         unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1190         unsigned long flags;
1191         void __iomem *reg;
1192         u32 ctrl0;
1193
1194         raw_spin_lock_irqsave(&chv_lock, flags);
1195
1196         reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1197         ctrl0 = readl(reg);
1198
1199         if (value)
1200                 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1201         else
1202                 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1203
1204         chv_writel(ctrl0, reg);
1205
1206         raw_spin_unlock_irqrestore(&chv_lock, flags);
1207 }
1208
1209 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1210 {
1211         struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
1212         unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1213         u32 ctrl0, direction;
1214         unsigned long flags;
1215
1216         raw_spin_lock_irqsave(&chv_lock, flags);
1217         ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1218         raw_spin_unlock_irqrestore(&chv_lock, flags);
1219
1220         direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1221         direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1222
1223         return direction != CHV_PADCTRL0_GPIOCFG_GPO;
1224 }
1225
1226 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1227 {
1228         return pinctrl_gpio_direction_input(chip->base + offset);
1229 }
1230
1231 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1232                                      int value)
1233 {
1234         chv_gpio_set(chip, offset, value);
1235         return pinctrl_gpio_direction_output(chip->base + offset);
1236 }
1237
1238 static const struct gpio_chip chv_gpio_chip = {
1239         .owner = THIS_MODULE,
1240         .request = gpiochip_generic_request,
1241         .free = gpiochip_generic_free,
1242         .get_direction = chv_gpio_get_direction,
1243         .direction_input = chv_gpio_direction_input,
1244         .direction_output = chv_gpio_direction_output,
1245         .get = chv_gpio_get,
1246         .set = chv_gpio_set,
1247 };
1248
1249 static void chv_gpio_irq_ack(struct irq_data *d)
1250 {
1251         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1252         struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
1253         int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1254         u32 intr_line;
1255
1256         raw_spin_lock(&chv_lock);
1257
1258         intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1259         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1260         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1261         chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1262
1263         raw_spin_unlock(&chv_lock);
1264 }
1265
1266 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1267 {
1268         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1269         struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
1270         int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1271         u32 value, intr_line;
1272         unsigned long flags;
1273
1274         raw_spin_lock_irqsave(&chv_lock, flags);
1275
1276         intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1277         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1278         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1279
1280         value = readl(pctrl->regs + CHV_INTMASK);
1281         if (mask)
1282                 value &= ~BIT(intr_line);
1283         else
1284                 value |= BIT(intr_line);
1285         chv_writel(value, pctrl->regs + CHV_INTMASK);
1286
1287         raw_spin_unlock_irqrestore(&chv_lock, flags);
1288 }
1289
1290 static void chv_gpio_irq_mask(struct irq_data *d)
1291 {
1292         chv_gpio_irq_mask_unmask(d, true);
1293 }
1294
1295 static void chv_gpio_irq_unmask(struct irq_data *d)
1296 {
1297         chv_gpio_irq_mask_unmask(d, false);
1298 }
1299
1300 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1301 {
1302         /*
1303          * Check if the interrupt has been requested with 0 as triggering
1304          * type. In that case it is assumed that the current values
1305          * programmed to the hardware are used (e.g BIOS configured
1306          * defaults).
1307          *
1308          * In that case ->irq_set_type() will never be called so we need to
1309          * read back the values from hardware now, set correct flow handler
1310          * and update mappings before the interrupt is being used.
1311          */
1312         if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1313                 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1314                 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
1315                 unsigned offset = irqd_to_hwirq(d);
1316                 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1317                 irq_flow_handler_t handler;
1318                 unsigned long flags;
1319                 u32 intsel, value;
1320
1321                 raw_spin_lock_irqsave(&chv_lock, flags);
1322                 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1323                 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1324                 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1325
1326                 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1327                 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1328                         handler = handle_level_irq;
1329                 else
1330                         handler = handle_edge_irq;
1331
1332                 if (!pctrl->intr_lines[intsel]) {
1333                         irq_set_handler_locked(d, handler);
1334                         pctrl->intr_lines[intsel] = offset;
1335                 }
1336                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1337         }
1338
1339         chv_gpio_irq_unmask(d);
1340         return 0;
1341 }
1342
1343 static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1344 {
1345         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1346         struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
1347         unsigned offset = irqd_to_hwirq(d);
1348         int pin = chv_gpio_offset_to_pin(pctrl, offset);
1349         unsigned long flags;
1350         u32 value;
1351
1352         raw_spin_lock_irqsave(&chv_lock, flags);
1353
1354         /*
1355          * Pins which can be used as shared interrupt are configured in
1356          * BIOS. Driver trusts BIOS configurations and assigns different
1357          * handler according to the irq type.
1358          *
1359          * Driver needs to save the mapping between each pin and
1360          * its interrupt line.
1361          * 1. If the pin cfg is locked in BIOS:
1362          *      Trust BIOS has programmed IntWakeCfg bits correctly,
1363          *      driver just needs to save the mapping.
1364          * 2. If the pin cfg is not locked in BIOS:
1365          *      Driver programs the IntWakeCfg bits and save the mapping.
1366          */
1367         if (!chv_pad_locked(pctrl, pin)) {
1368                 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1369
1370                 value = readl(reg);
1371                 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1372                 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1373
1374                 if (type & IRQ_TYPE_EDGE_BOTH) {
1375                         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1376                                 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1377                         else if (type & IRQ_TYPE_EDGE_RISING)
1378                                 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1379                         else if (type & IRQ_TYPE_EDGE_FALLING)
1380                                 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1381                 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1382                         value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1383                         if (type & IRQ_TYPE_LEVEL_LOW)
1384                                 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1385                 }
1386
1387                 chv_writel(value, reg);
1388         }
1389
1390         value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1391         value &= CHV_PADCTRL0_INTSEL_MASK;
1392         value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1393
1394         pctrl->intr_lines[value] = offset;
1395
1396         if (type & IRQ_TYPE_EDGE_BOTH)
1397                 irq_set_handler_locked(d, handle_edge_irq);
1398         else if (type & IRQ_TYPE_LEVEL_MASK)
1399                 irq_set_handler_locked(d, handle_level_irq);
1400
1401         raw_spin_unlock_irqrestore(&chv_lock, flags);
1402
1403         return 0;
1404 }
1405
1406 static struct irq_chip chv_gpio_irqchip = {
1407         .name = "chv-gpio",
1408         .irq_startup = chv_gpio_irq_startup,
1409         .irq_ack = chv_gpio_irq_ack,
1410         .irq_mask = chv_gpio_irq_mask,
1411         .irq_unmask = chv_gpio_irq_unmask,
1412         .irq_set_type = chv_gpio_irq_type,
1413         .flags = IRQCHIP_SKIP_SET_WAKE,
1414 };
1415
1416 static void chv_gpio_irq_handler(struct irq_desc *desc)
1417 {
1418         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1419         struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
1420         struct irq_chip *chip = irq_desc_get_chip(desc);
1421         unsigned long pending;
1422         u32 intr_line;
1423
1424         chained_irq_enter(chip, desc);
1425
1426         pending = readl(pctrl->regs + CHV_INTSTAT);
1427         for_each_set_bit(intr_line, &pending, 16) {
1428                 unsigned irq, offset;
1429
1430                 offset = pctrl->intr_lines[intr_line];
1431                 irq = irq_find_mapping(gc->irqdomain, offset);
1432                 generic_handle_irq(irq);
1433         }
1434
1435         chained_irq_exit(chip, desc);
1436 }
1437
1438 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1439 {
1440         const struct chv_gpio_pinrange *range;
1441         struct gpio_chip *chip = &pctrl->chip;
1442         int ret, i, offset;
1443
1444         *chip = chv_gpio_chip;
1445
1446         chip->ngpio = pctrl->community->ngpios;
1447         chip->label = dev_name(pctrl->dev);
1448         chip->dev = pctrl->dev;
1449         chip->base = -1;
1450
1451         ret = gpiochip_add(chip);
1452         if (ret) {
1453                 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1454                 return ret;
1455         }
1456
1457         for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) {
1458                 range = &pctrl->community->gpio_ranges[i];
1459                 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset,
1460                                              range->base, range->npins);
1461                 if (ret) {
1462                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1463                         goto fail;
1464                 }
1465
1466                 offset += range->npins;
1467         }
1468
1469         /* Mask and clear all interrupts */
1470         chv_writel(0, pctrl->regs + CHV_INTMASK);
1471         chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1472
1473         ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
1474                                    handle_simple_irq, IRQ_TYPE_NONE);
1475         if (ret) {
1476                 dev_err(pctrl->dev, "failed to add IRQ chip\n");
1477                 goto fail;
1478         }
1479
1480         gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,
1481                                      chv_gpio_irq_handler);
1482         return 0;
1483
1484 fail:
1485         gpiochip_remove(chip);
1486
1487         return ret;
1488 }
1489
1490 static int chv_pinctrl_probe(struct platform_device *pdev)
1491 {
1492         struct chv_pinctrl *pctrl;
1493         struct acpi_device *adev;
1494         struct resource *res;
1495         int ret, irq, i;
1496
1497         adev = ACPI_COMPANION(&pdev->dev);
1498         if (!adev)
1499                 return -ENODEV;
1500
1501         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1502         if (!pctrl)
1503                 return -ENOMEM;
1504
1505         for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1506                 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1507                         pctrl->community = chv_communities[i];
1508                         break;
1509                 }
1510         if (i == ARRAY_SIZE(chv_communities))
1511                 return -ENODEV;
1512
1513         pctrl->dev = &pdev->dev;
1514
1515 #ifdef CONFIG_PM_SLEEP
1516         pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1517                 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1518                 GFP_KERNEL);
1519         if (!pctrl->saved_pin_context)
1520                 return -ENOMEM;
1521 #endif
1522
1523         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1524         pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1525         if (IS_ERR(pctrl->regs))
1526                 return PTR_ERR(pctrl->regs);
1527
1528         irq = platform_get_irq(pdev, 0);
1529         if (irq < 0) {
1530                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1531                 return irq;
1532         }
1533
1534         pctrl->pctldesc = chv_pinctrl_desc;
1535         pctrl->pctldesc.name = dev_name(&pdev->dev);
1536         pctrl->pctldesc.pins = pctrl->community->pins;
1537         pctrl->pctldesc.npins = pctrl->community->npins;
1538
1539         pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl);
1540         if (IS_ERR(pctrl->pctldev)) {
1541                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1542                 return PTR_ERR(pctrl->pctldev);
1543         }
1544
1545         ret = chv_gpio_probe(pctrl, irq);
1546         if (ret) {
1547                 pinctrl_unregister(pctrl->pctldev);
1548                 return ret;
1549         }
1550
1551         platform_set_drvdata(pdev, pctrl);
1552
1553         return 0;
1554 }
1555
1556 static int chv_pinctrl_remove(struct platform_device *pdev)
1557 {
1558         struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1559
1560         gpiochip_remove(&pctrl->chip);
1561         pinctrl_unregister(pctrl->pctldev);
1562
1563         return 0;
1564 }
1565
1566 #ifdef CONFIG_PM_SLEEP
1567 static int chv_pinctrl_suspend_noirq(struct device *dev)
1568 {
1569         struct platform_device *pdev = to_platform_device(dev);
1570         struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1571         unsigned long flags;
1572         int i;
1573
1574         raw_spin_lock_irqsave(&chv_lock, flags);
1575
1576         pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1577
1578         for (i = 0; i < pctrl->community->npins; i++) {
1579                 const struct pinctrl_pin_desc *desc;
1580                 struct chv_pin_context *ctx;
1581                 void __iomem *reg;
1582
1583                 desc = &pctrl->community->pins[i];
1584                 if (chv_pad_locked(pctrl, desc->number))
1585                         continue;
1586
1587                 ctx = &pctrl->saved_pin_context[i];
1588
1589                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1590                 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1591
1592                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1593                 ctx->padctrl1 = readl(reg);
1594         }
1595
1596         raw_spin_unlock_irqrestore(&chv_lock, flags);
1597
1598         return 0;
1599 }
1600
1601 static int chv_pinctrl_resume_noirq(struct device *dev)
1602 {
1603         struct platform_device *pdev = to_platform_device(dev);
1604         struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1605         unsigned long flags;
1606         int i;
1607
1608         raw_spin_lock_irqsave(&chv_lock, flags);
1609
1610         /*
1611          * Mask all interrupts before restoring per-pin configuration
1612          * registers because we don't know in which state BIOS left them
1613          * upon exiting suspend.
1614          */
1615         chv_writel(0, pctrl->regs + CHV_INTMASK);
1616
1617         for (i = 0; i < pctrl->community->npins; i++) {
1618                 const struct pinctrl_pin_desc *desc;
1619                 const struct chv_pin_context *ctx;
1620                 void __iomem *reg;
1621                 u32 val;
1622
1623                 desc = &pctrl->community->pins[i];
1624                 if (chv_pad_locked(pctrl, desc->number))
1625                         continue;
1626
1627                 ctx = &pctrl->saved_pin_context[i];
1628
1629                 /* Only restore if our saved state differs from the current */
1630                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1631                 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1632                 if (ctx->padctrl0 != val) {
1633                         chv_writel(ctx->padctrl0, reg);
1634                         dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1635                                 desc->number, readl(reg));
1636                 }
1637
1638                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1639                 val = readl(reg);
1640                 if (ctx->padctrl1 != val) {
1641                         chv_writel(ctx->padctrl1, reg);
1642                         dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1643                                 desc->number, readl(reg));
1644                 }
1645         }
1646
1647         /*
1648          * Now that all pins are restored to known state, we can restore
1649          * the interrupt mask register as well.
1650          */
1651         chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1652         chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1653
1654         raw_spin_unlock_irqrestore(&chv_lock, flags);
1655
1656         return 0;
1657 }
1658 #endif
1659
1660 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1661         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1662                                       chv_pinctrl_resume_noirq)
1663 };
1664
1665 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1666         { "INT33FF" },
1667         { }
1668 };
1669 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1670
1671 static struct platform_driver chv_pinctrl_driver = {
1672         .probe = chv_pinctrl_probe,
1673         .remove = chv_pinctrl_remove,
1674         .driver = {
1675                 .name = "cherryview-pinctrl",
1676                 .pm = &chv_pinctrl_pm_ops,
1677                 .acpi_match_table = chv_pinctrl_acpi_match,
1678         },
1679 };
1680
1681 static int __init chv_pinctrl_init(void)
1682 {
1683         return platform_driver_register(&chv_pinctrl_driver);
1684 }
1685 subsys_initcall(chv_pinctrl_init);
1686
1687 static void __exit chv_pinctrl_exit(void)
1688 {
1689         platform_driver_unregister(&chv_pinctrl_driver);
1690 }
1691 module_exit(chv_pinctrl_exit);
1692
1693 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1694 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1695 MODULE_LICENSE("GPL v2");