kernel/drivers/phy/phy-ti-pipe3.c

   1 /*
   2  * phy-ti-pipe3 - PIPE3 PHY driver.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Author: Kishon Vijay Abraham I <kishon@ti.com>
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/of.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/io.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/delay.h>
  29 #include <linux/phy/omap_control_phy.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/mfd/syscon.h>
  32 #include <linux/regmap.h>
  33
  34 #define PLL_STATUS              0x00000004
  35 #define PLL_GO                  0x00000008
  36 #define PLL_CONFIGURATION1      0x0000000C
  37 #define PLL_CONFIGURATION2      0x00000010
  38 #define PLL_CONFIGURATION3      0x00000014
  39 #define PLL_CONFIGURATION4      0x00000020
  40
  41 #define PLL_REGM_MASK           0x001FFE00
  42 #define PLL_REGM_SHIFT          0x9
  43 #define PLL_REGM_F_MASK         0x0003FFFF
  44 #define PLL_REGM_F_SHIFT        0x0
  45 #define PLL_REGN_MASK           0x000001FE
  46 #define PLL_REGN_SHIFT          0x1
  47 #define PLL_SELFREQDCO_MASK     0x0000000E
  48 #define PLL_SELFREQDCO_SHIFT    0x1
  49 #define PLL_SD_MASK             0x0003FC00
  50 #define PLL_SD_SHIFT            10
  51 #define SET_PLL_GO              0x1
  52 #define PLL_LDOPWDN             BIT(15)
  53 #define PLL_TICOPWDN            BIT(16)
  54 #define PLL_LOCK                0x2
  55 #define PLL_IDLE                0x1
  56
  57 #define SATA_PLL_SOFT_RESET     BIT(18)
  58
  59 /*
  60  * This is an Empirical value that works, need to confirm the actual
  61  * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
  62  * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
  63  */
  64 #define PLL_IDLE_TIME   100     /* in milliseconds */
  65 #define PLL_LOCK_TIME   100     /* in milliseconds */
  66
  67 struct pipe3_dpll_params {
  68         u16     m;
  69         u8      n;
  70         u8      freq:3;
  71         u8      sd;
  72         u32     mf;
  73 };
  74
  75 struct pipe3_dpll_map {
  76         unsigned long rate;
  77         struct pipe3_dpll_params params;
  78 };
  79
  80 struct ti_pipe3 {
  81         void __iomem            *pll_ctrl_base;
  82         struct device           *dev;
  83         struct device           *control_dev;
  84         struct clk              *wkupclk;
  85         struct clk              *sys_clk;
  86         struct clk              *refclk;
  87         struct clk              *div_clk;
  88         struct pipe3_dpll_map   *dpll_map;
  89         struct regmap           *dpll_reset_syscon; /* ctrl. reg. acces */
  90         unsigned int            dpll_reset_reg; /* reg. index within syscon */
  91         bool                    sata_refclk_enabled;
  92 };
  93
  94 static struct pipe3_dpll_map dpll_map_usb[] = {
  95         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
  96         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
  97         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
  98         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
  99         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
 100         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
 101         { },                                    /* Terminator */
 102 };
 103
 104 static struct pipe3_dpll_map dpll_map_sata[] = {
 105         {12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
 106         {16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
 107         {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
 108         {20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
 109         {26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
 110         {38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
 111         { },                                    /* Terminator */
 112 };
 113
 114 static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
 115 {
 116         return __raw_readl(addr + offset);
 117 }
 118
 119 static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
 120         u32 data)
 121 {
 122         __raw_writel(data, addr + offset);
 123 }
 124
 125 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
 126 {
 127         unsigned long rate;
 128         struct pipe3_dpll_map *dpll_map = phy->dpll_map;
 129
 130         rate = clk_get_rate(phy->sys_clk);
 131
 132         for (; dpll_map->rate; dpll_map++) {
 133                 if (rate == dpll_map->rate)
 134                         return &dpll_map->params;
 135         }
 136
 137         dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
 138
 139         return NULL;
 140 }
 141
 142 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
 143 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
 144
 145 static int ti_pipe3_power_off(struct phy *x)
 146 {
 147         struct ti_pipe3 *phy = phy_get_drvdata(x);
 148
 149         omap_control_phy_power(phy->control_dev, 0);
 150
 151         return 0;
 152 }
 153
 154 static int ti_pipe3_power_on(struct phy *x)
 155 {
 156         struct ti_pipe3 *phy = phy_get_drvdata(x);
 157
 158         omap_control_phy_power(phy->control_dev, 1);
 159
 160         return 0;
 161 }
 162
 163 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
 164 {
 165         u32             val;
 166         unsigned long   timeout;
 167
 168         timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
 169         do {
 170                 cpu_relax();
 171                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 172                 if (val & PLL_LOCK)
 173                         return 0;
 174         } while (!time_after(jiffies, timeout));
 175
 176         dev_err(phy->dev, "DPLL failed to lock\n");
 177         return -EBUSY;
 178 }
 179
 180 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
 181 {
 182         u32                     val;
 183         struct pipe3_dpll_params *dpll_params;
 184
 185         dpll_params = ti_pipe3_get_dpll_params(phy);
 186         if (!dpll_params)
 187                 return -EINVAL;
 188
 189         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 190         val &= ~PLL_REGN_MASK;
 191         val |= dpll_params->n << PLL_REGN_SHIFT;
 192         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 193
 194         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 195         val &= ~PLL_SELFREQDCO_MASK;
 196         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 197         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 198
 199         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 200         val &= ~PLL_REGM_MASK;
 201         val |= dpll_params->m << PLL_REGM_SHIFT;
 202         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 203
 204         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
 205         val &= ~PLL_REGM_F_MASK;
 206         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 207         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
 208
 209         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
 210         val &= ~PLL_SD_MASK;
 211         val |= dpll_params->sd << PLL_SD_SHIFT;
 212         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
 213
 214         ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 215
 216         return ti_pipe3_dpll_wait_lock(phy);
 217 }
 218
 219 static int ti_pipe3_init(struct phy *x)
 220 {
 221         struct ti_pipe3 *phy = phy_get_drvdata(x);
 222         u32 val;
 223         int ret = 0;
 224
 225         ti_pipe3_enable_clocks(phy);
 226         /*
 227          * Set pcie_pcs register to 0x96 for proper functioning of phy
 228          * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
 229          * 18-1804.
 230          */
 231         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
 232                 omap_control_pcie_pcs(phy->control_dev, 0x96);
 233                 return 0;
 234         }
 235
 236         /* Bring it out of IDLE if it is IDLE */
 237         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 238         if (val & PLL_IDLE) {
 239                 val &= ~PLL_IDLE;
 240                 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 241                 ret = ti_pipe3_dpll_wait_lock(phy);
 242         }
 243
 244         /* Program the DPLL only if not locked */
 245         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 246         if (!(val & PLL_LOCK))
 247                 if (ti_pipe3_dpll_program(phy))
 248                         return -EINVAL;
 249
 250         return ret;
 251 }
 252
 253 static int ti_pipe3_exit(struct phy *x)
 254 {
 255         struct ti_pipe3 *phy = phy_get_drvdata(x);
 256         u32 val;
 257         unsigned long timeout;
 258
 259         /* If dpll_reset_syscon is not present we wont power down SATA DPLL
 260          * due to Errata i783
 261          */
 262         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") &&
 263             !phy->dpll_reset_syscon)
 264                 return 0;
 265
 266         /* PCIe doesn't have internal DPLL */
 267         if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
 268                 /* Put DPLL in IDLE mode */
 269                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 270                 val |= PLL_IDLE;
 271                 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 272
 273                 /* wait for LDO and Oscillator to power down */
 274                 timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
 275                 do {
 276                         cpu_relax();
 277                         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 278                         if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 279                                 break;
 280                 } while (!time_after(jiffies, timeout));
 281
 282                 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 283                         dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
 284                                 val);
 285                         return -EBUSY;
 286                 }
 287         }
 288
 289         /* i783: SATA needs control bit toggle after PLL unlock */
 290         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata")) {
 291                 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 292                                    SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
 293                 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 294                                    SATA_PLL_SOFT_RESET, 0);
 295         }
 296
 297         ti_pipe3_disable_clocks(phy);
 298
 299         return 0;
 300 }
 301 static const struct phy_ops ops = {
 302         .init           = ti_pipe3_init,
 303         .exit           = ti_pipe3_exit,
 304         .power_on       = ti_pipe3_power_on,
 305         .power_off      = ti_pipe3_power_off,
 306         .owner          = THIS_MODULE,
 307 };
 308
 309 static const struct of_device_id ti_pipe3_id_table[];
 310
 311 static int ti_pipe3_probe(struct platform_device *pdev)
 312 {
 313         struct ti_pipe3 *phy;
 314         struct phy *generic_phy;
 315         struct phy_provider *phy_provider;
 316         struct resource *res;
 317         struct device_node *node = pdev->dev.of_node;
 318         struct device_node *control_node;
 319         struct platform_device *control_pdev;
 320         const struct of_device_id *match;
 321         struct clk *clk;
 322
 323         phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
 324         if (!phy)
 325                 return -ENOMEM;
 326
 327         phy->dev                = &pdev->dev;
 328
 329         if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 330                 match = of_match_device(ti_pipe3_id_table, &pdev->dev);
 331                 if (!match)
 332                         return -EINVAL;
 333
 334                 phy->dpll_map = (struct pipe3_dpll_map *)match->data;
 335                 if (!phy->dpll_map) {
 336                         dev_err(&pdev->dev, "no DPLL data\n");
 337                         return -EINVAL;
 338                 }
 339
 340                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 341                                                    "pll_ctrl");
 342                 phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
 343                 if (IS_ERR(phy->pll_ctrl_base))
 344                         return PTR_ERR(phy->pll_ctrl_base);
 345
 346                 phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
 347                 if (IS_ERR(phy->sys_clk)) {
 348                         dev_err(&pdev->dev, "unable to get sysclk\n");
 349                         return -EINVAL;
 350                 }
 351         }
 352
 353         phy->refclk = devm_clk_get(phy->dev, "refclk");
 354         if (IS_ERR(phy->refclk)) {
 355                 dev_err(&pdev->dev, "unable to get refclk\n");
 356                 /* older DTBs have missing refclk in SATA PHY
 357                  * so don't bail out in case of SATA PHY.
 358                  */
 359                 if (!of_device_is_compatible(node, "ti,phy-pipe3-sata"))
 360                         return PTR_ERR(phy->refclk);
 361         }
 362
 363         if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
 364                 phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
 365                 if (IS_ERR(phy->wkupclk)) {
 366                         dev_err(&pdev->dev, "unable to get wkupclk\n");
 367                         return PTR_ERR(phy->wkupclk);
 368                 }
 369         } else {
 370                 phy->wkupclk = ERR_PTR(-ENODEV);
 371                 phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
 372                                                         "syscon-pllreset");
 373                 if (IS_ERR(phy->dpll_reset_syscon)) {
 374                         dev_info(&pdev->dev,
 375                                  "can't get syscon-pllreset, sata dpll won't idle\n");
 376                         phy->dpll_reset_syscon = NULL;
 377                 } else {
 378                         if (of_property_read_u32_index(node,
 379                                                        "syscon-pllreset", 1,
 380                                                        &phy->dpll_reset_reg)) {
 381                                 dev_err(&pdev->dev,
 382                                         "couldn't get pllreset reg. offset\n");
 383                                 return -EINVAL;
 384                         }
 385                 }
 386         }
 387
 388         if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 389
 390                 clk = devm_clk_get(phy->dev, "dpll_ref");
 391                 if (IS_ERR(clk)) {
 392                         dev_err(&pdev->dev, "unable to get dpll ref clk\n");
 393                         return PTR_ERR(clk);
 394                 }
 395                 clk_set_rate(clk, 1500000000);
 396
 397                 clk = devm_clk_get(phy->dev, "dpll_ref_m2");
 398                 if (IS_ERR(clk)) {
 399                         dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
 400                         return PTR_ERR(clk);
 401                 }
 402                 clk_set_rate(clk, 100000000);
 403
 404                 clk = devm_clk_get(phy->dev, "phy-div");
 405                 if (IS_ERR(clk)) {
 406                         dev_err(&pdev->dev, "unable to get phy-div clk\n");
 407                         return PTR_ERR(clk);
 408                 }
 409                 clk_set_rate(clk, 100000000);
 410
 411                 phy->div_clk = devm_clk_get(phy->dev, "div-clk");
 412                 if (IS_ERR(phy->div_clk)) {
 413                         dev_err(&pdev->dev, "unable to get div-clk\n");
 414                         return PTR_ERR(phy->div_clk);
 415                 }
 416         } else {
 417                 phy->div_clk = ERR_PTR(-ENODEV);
 418         }
 419
 420         control_node = of_parse_phandle(node, "ctrl-module", 0);
 421         if (!control_node) {
 422                 dev_err(&pdev->dev, "Failed to get control device phandle\n");
 423                 return -EINVAL;
 424         }
 425
 426         control_pdev = of_find_device_by_node(control_node);
 427         if (!control_pdev) {
 428                 dev_err(&pdev->dev, "Failed to get control device\n");
 429                 return -EINVAL;
 430         }
 431
 432         phy->control_dev = &control_pdev->dev;
 433
 434         omap_control_phy_power(phy->control_dev, 0);
 435
 436         platform_set_drvdata(pdev, phy);
 437         pm_runtime_enable(phy->dev);
 438
 439         /*
 440          * Prevent auto-disable of refclk for SATA PHY due to Errata i783
 441          */
 442         if (of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
 443                 if (!IS_ERR(phy->refclk)) {
 444                         clk_prepare_enable(phy->refclk);
 445                         phy->sata_refclk_enabled = true;
 446                 }
 447         }
 448
 449         generic_phy = devm_phy_create(phy->dev, NULL, &ops);
 450         if (IS_ERR(generic_phy))
 451                 return PTR_ERR(generic_phy);
 452
 453         phy_set_drvdata(generic_phy, phy);
 454         phy_provider = devm_of_phy_provider_register(phy->dev,
 455                         of_phy_simple_xlate);
 456         if (IS_ERR(phy_provider))
 457                 return PTR_ERR(phy_provider);
 458
 459         return 0;
 460 }
 461
 462 static int ti_pipe3_remove(struct platform_device *pdev)
 463 {
 464         pm_runtime_disable(&pdev->dev);
 465
 466         return 0;
 467 }
 468
 469 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
 470 {
 471         int ret = 0;
 472
 473         if (!IS_ERR(phy->refclk)) {
 474                 ret = clk_prepare_enable(phy->refclk);
 475                 if (ret) {
 476                         dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
 477                         return ret;
 478                 }
 479         }
 480
 481         if (!IS_ERR(phy->wkupclk)) {
 482                 ret = clk_prepare_enable(phy->wkupclk);
 483                 if (ret) {
 484                         dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
 485                         goto disable_refclk;
 486                 }
 487         }
 488
 489         if (!IS_ERR(phy->div_clk)) {
 490                 ret = clk_prepare_enable(phy->div_clk);
 491                 if (ret) {
 492                         dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
 493                         goto disable_wkupclk;
 494                 }
 495         }
 496
 497         return 0;
 498
 499 disable_wkupclk:
 500         if (!IS_ERR(phy->wkupclk))
 501                 clk_disable_unprepare(phy->wkupclk);
 502
 503 disable_refclk:
 504         if (!IS_ERR(phy->refclk))
 505                 clk_disable_unprepare(phy->refclk);
 506
 507         return ret;
 508 }
 509
 510 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
 511 {
 512         if (!IS_ERR(phy->wkupclk))
 513                 clk_disable_unprepare(phy->wkupclk);
 514         if (!IS_ERR(phy->refclk)) {
 515                 clk_disable_unprepare(phy->refclk);
 516                 /*
 517                  * SATA refclk needs an additional disable as we left it
 518                  * on in probe to avoid Errata i783
 519                  */
 520                 if (phy->sata_refclk_enabled) {
 521                         clk_disable_unprepare(phy->refclk);
 522                         phy->sata_refclk_enabled = false;
 523                 }
 524         }
 525
 526         if (!IS_ERR(phy->div_clk))
 527                 clk_disable_unprepare(phy->div_clk);
 528 }
 529
 530 static const struct of_device_id ti_pipe3_id_table[] = {
 531         {
 532                 .compatible = "ti,phy-usb3",
 533                 .data = dpll_map_usb,
 534         },
 535         {
 536                 .compatible = "ti,omap-usb3",
 537                 .data = dpll_map_usb,
 538         },
 539         {
 540                 .compatible = "ti,phy-pipe3-sata",
 541                 .data = dpll_map_sata,
 542         },
 543         {
 544                 .compatible = "ti,phy-pipe3-pcie",
 545         },
 546         {}
 547 };
 548 MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
 549
 550 static struct platform_driver ti_pipe3_driver = {
 551         .probe          = ti_pipe3_probe,
 552         .remove         = ti_pipe3_remove,
 553         .driver         = {
 554                 .name   = "ti-pipe3",
 555                 .of_match_table = ti_pipe3_id_table,
 556         },
 557 };
 558
 559 module_platform_driver(ti_pipe3_driver);
 560
 561 MODULE_ALIAS("platform:ti_pipe3");
 562 MODULE_AUTHOR("Texas Instruments Inc.");
 563 MODULE_DESCRIPTION("TI PIPE3 phy driver");
 564 MODULE_LICENSE("GPL v2");