2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/acpi.h>
21 #include <linux/kallsyms.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
32 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
37 static void quirk_mmio_always_on(struct pci_dev *dev)
39 dev->mmio_always_on = 1;
41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
44 /* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
48 static void quirk_mellanox_tavor(struct pci_dev *dev)
50 dev->broken_parity_status = 1; /* This device gives false positives */
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
55 /* Deal with broken BIOSes that neglect to enable passive release,
56 which can cause problems in combination with the 82441FX/PPro MTRRs */
57 static void quirk_passive_release(struct pci_dev *dev)
59 struct pci_dev *d = NULL;
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
65 pci_read_config_byte(d, 0x82, &dlc);
67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
69 pci_write_config_byte(d, 0x82, dlc);
73 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
76 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
78 ask them for me please -- Alan
80 This appears to be BIOS not version dependent. So presumably there is a
83 static void quirk_isa_dma_hangs(struct pci_dev *dev)
85 if (!isa_dma_bridge_buggy) {
86 isa_dma_bridge_buggy = 1;
87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
106 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
111 pci_read_config_dword(dev, 0x40, &pmbase);
112 pmbase = pmbase & 0xff80;
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
123 * Chipsets where PCI->PCI transfers vanish or hang
125 static void quirk_nopcipci(struct pci_dev *dev)
127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
129 pci_pci_problems |= PCIPCI_FAIL;
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
135 static void quirk_nopciamd(struct pci_dev *dev)
138 pci_read_config_byte(dev, 0x08, &rev);
141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
142 pci_pci_problems |= PCIAGP_FAIL;
145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
148 * Triton requires workarounds to be used by the drivers
150 static void quirk_triton(struct pci_dev *dev)
152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
154 pci_pci_problems |= PCIPCI_TRITON;
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
166 * and http://www.georgebreese.com/net/software/#PCI
167 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
168 * the info on which Mr Breese based his work.
170 * Updated based on further information from the site and also on
171 * information provided by VIA
173 static void quirk_vialatency(struct pci_dev *dev)
177 /* Ok we have a potential problem chipset here. Now see if we have
178 a buggy southbridge */
180 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
182 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
183 /* Check for buggy part revisions */
184 if (p->revision < 0x40 || p->revision > 0x42)
187 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
188 if (p == NULL) /* No problem parts */
190 /* Check for buggy part revisions */
191 if (p->revision < 0x10 || p->revision > 0x12)
196 * Ok we have the problem. Now set the PCI master grant to
197 * occur every master grant. The apparent bug is that under high
198 * PCI load (quite common in Linux of course) you can get data
199 * loss when the CPU is held off the bus for 3 bus master requests
200 * This happens to include the IDE controllers....
202 * VIA only apply this fix when an SB Live! is present but under
203 * both Linux and Windows this isn't enough, and we have seen
204 * corruption without SB Live! but with things like 3 UDMA IDE
205 * controllers. So we ignore that bit of the VIA recommendation..
208 pci_read_config_byte(dev, 0x76, &busarb);
209 /* Set bit 4 and bi 5 of byte 76 to 0x01
210 "Master priority rotation on every PCI master grant */
213 pci_write_config_byte(dev, 0x76, busarb);
214 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
221 /* Must restore this on a resume from RAM */
222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
227 * VIA Apollo VP3 needs ETBF on BT848/878
229 static void quirk_viaetbf(struct pci_dev *dev)
231 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
232 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
233 pci_pci_problems |= PCIPCI_VIAETBF;
236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
238 static void quirk_vsfx(struct pci_dev *dev)
240 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
242 pci_pci_problems |= PCIPCI_VSFX;
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
248 * Ali Magik requires workarounds to be used by the drivers
249 * that DMA to AGP space. Latency must be set to 0xA and triton
250 * workaround applied too
251 * [Info kindly provided by ALi]
253 static void quirk_alimagik(struct pci_dev *dev)
255 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
256 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
257 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
264 * Natoma has some interesting boundary conditions with Zoran stuff
267 static void quirk_natoma(struct pci_dev *dev)
269 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
270 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
271 pci_pci_problems |= PCIPCI_NATOMA;
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
282 * This chip can cause PCI parity errors if config register 0xA0 is read
283 * while DMAs are occurring.
285 static void quirk_citrine(struct pci_dev *dev)
287 dev->cfg_size = 0xA0;
289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
291 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
292 static void quirk_extend_bar_to_page(struct pci_dev *dev)
296 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
297 struct resource *r = &dev->resource[i];
299 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
300 r->end = PAGE_SIZE - 1;
302 r->flags |= IORESOURCE_UNSET;
303 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
311 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
312 * If it's needed, re-allocate the region.
314 static void quirk_s3_64M(struct pci_dev *dev)
316 struct resource *r = &dev->resource[0];
318 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
319 r->flags |= IORESOURCE_UNSET;
324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
327 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
331 struct pci_bus_region bus_region;
332 struct resource *res = dev->resource + pos;
334 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
339 res->name = pci_name(dev);
340 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
342 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
343 region &= ~(size - 1);
345 /* Convert from PCI bus to resource space */
346 bus_region.start = region;
347 bus_region.end = region + size - 1;
348 pcibios_bus_to_resource(dev->bus, res, &bus_region);
350 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
351 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
355 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
356 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
357 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
358 * (which conflicts w/ BAR1's memory range).
360 * CS553x's ISA PCI BARs may also be read-only (ref:
361 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
363 static void quirk_cs5536_vsa(struct pci_dev *dev)
365 static char *name = "CS5536 ISA bridge";
367 if (pci_resource_len(dev, 0) != 8) {
368 quirk_io(dev, 0, 8, name); /* SMB */
369 quirk_io(dev, 1, 256, name); /* GPIO */
370 quirk_io(dev, 2, 64, name); /* MFGPT */
371 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
377 static void quirk_io_region(struct pci_dev *dev, int port,
378 unsigned size, int nr, const char *name)
381 struct pci_bus_region bus_region;
382 struct resource *res = dev->resource + nr;
384 pci_read_config_word(dev, port, ®ion);
385 region &= ~(size - 1);
390 res->name = pci_name(dev);
391 res->flags = IORESOURCE_IO;
393 /* Convert from PCI bus to resource space */
394 bus_region.start = region;
395 bus_region.end = region + size - 1;
396 pcibios_bus_to_resource(dev->bus, res, &bus_region);
398 if (!pci_claim_resource(dev, nr))
399 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
403 * ATI Northbridge setups MCE the processor if you even
404 * read somewhere between 0x3b0->0x3bb or read 0x3d3
406 static void quirk_ati_exploding_mce(struct pci_dev *dev)
408 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
409 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
410 request_region(0x3b0, 0x0C, "RadeonIGP");
411 request_region(0x3d3, 0x01, "RadeonIGP");
413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
416 * In the AMD NL platform, this device ([1022:7912]) has a class code of
417 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
419 * But the dwc3 driver is a more specific driver for this device, and we'd
420 * prefer to use it instead of xhci. To prevent xhci from claiming the
421 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
422 * defines as "USB device (not host controller)". The dwc3 driver can then
423 * claim it based on its Vendor and Device ID.
425 static void quirk_amd_nl_class(struct pci_dev *pdev)
428 * Use 'USB Device' (0x0c03fe) instead of PCI header provided
430 pdev->class = 0x0c03fe;
432 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
436 * Let's make the southbridge information explicit instead
437 * of having to worry about people probing the ACPI areas,
438 * for example.. (Yes, it happens, and if you read the wrong
439 * ACPI register it will put the machine to sleep with no
440 * way of waking it up again. Bummer).
442 * ALI M7101: Two IO regions pointed to by words at
443 * 0xE0 (64 bytes of ACPI registers)
444 * 0xE2 (32 bytes of SMB registers)
446 static void quirk_ali7101_acpi(struct pci_dev *dev)
448 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
449 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
451 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
453 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
456 u32 mask, size, base;
458 pci_read_config_dword(dev, port, &devres);
459 if ((devres & enable) != enable)
461 mask = (devres >> 16) & 15;
462 base = devres & 0xffff;
465 unsigned bit = size >> 1;
466 if ((bit & mask) == bit)
471 * For now we only print it out. Eventually we'll want to
472 * reserve it (at least if it's in the 0x1000+ range), but
473 * let's get enough confirmation reports first.
476 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
480 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
483 u32 mask, size, base;
485 pci_read_config_dword(dev, port, &devres);
486 if ((devres & enable) != enable)
488 base = devres & 0xffff0000;
489 mask = (devres & 0x3f) << 16;
492 unsigned bit = size >> 1;
493 if ((bit & mask) == bit)
498 * For now we only print it out. Eventually we'll want to
499 * reserve it, but let's get enough confirmation reports first.
502 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
507 * PIIX4 ACPI: Two IO regions pointed to by longwords at
508 * 0x40 (64 bytes of ACPI registers)
509 * 0x90 (16 bytes of SMB registers)
510 * and a few strange programmable PIIX4 device resources.
512 static void quirk_piix4_acpi(struct pci_dev *dev)
516 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
517 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
519 /* Device resource A has enables for some of the other ones */
520 pci_read_config_dword(dev, 0x5c, &res_a);
522 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
523 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
525 /* Device resource D is just bitfields for static resources */
527 /* Device 12 enabled? */
528 if (res_a & (1 << 29)) {
529 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
530 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
532 /* Device 13 enabled? */
533 if (res_a & (1 << 30)) {
534 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
535 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
537 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
538 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
540 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
541 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
543 #define ICH_PMBASE 0x40
544 #define ICH_ACPI_CNTL 0x44
545 #define ICH4_ACPI_EN 0x10
546 #define ICH6_ACPI_EN 0x80
547 #define ICH4_GPIOBASE 0x58
548 #define ICH4_GPIO_CNTL 0x5c
549 #define ICH4_GPIO_EN 0x10
550 #define ICH6_GPIOBASE 0x48
551 #define ICH6_GPIO_CNTL 0x4c
552 #define ICH6_GPIO_EN 0x10
555 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
556 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
557 * 0x58 (64 bytes of GPIO I/O space)
559 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
564 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
565 * with low legacy (and fixed) ports. We don't know the decoding
566 * priority and can't tell whether the legacy device or the one created
567 * here is really at that address. This happens on boards with broken
571 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
572 if (enable & ICH4_ACPI_EN)
573 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
574 "ICH4 ACPI/GPIO/TCO");
576 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
577 if (enable & ICH4_GPIO_EN)
578 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
582 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
584 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
585 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
588 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
589 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
592 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
596 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
597 if (enable & ICH6_ACPI_EN)
598 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
599 "ICH6 ACPI/GPIO/TCO");
601 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
602 if (enable & ICH6_GPIO_EN)
603 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
607 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
612 pci_read_config_dword(dev, reg, &val);
620 * This is not correct. It is 16, 32 or 64 bytes depending on
621 * register D31:F0:ADh bits 5:4.
623 * But this gets us at least _part_ of it.
631 /* Just print it out for now. We should reserve it after more debugging */
632 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
635 static void quirk_ich6_lpc(struct pci_dev *dev)
637 /* Shared ACPI/GPIO decode with all ICH6+ */
638 ich6_lpc_acpi_gpio(dev);
640 /* ICH6-specific generic IO decode */
641 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
642 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
647 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
652 pci_read_config_dword(dev, reg, &val);
659 * IO base in bits 15:2, mask in bits 23:18, both
663 mask = (val >> 16) & 0xfc;
666 /* Just print it out for now. We should reserve it after more debugging */
667 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
670 /* ICH7-10 has the same common LPC generic IO decode registers */
671 static void quirk_ich7_lpc(struct pci_dev *dev)
673 /* We share the common ACPI/GPIO decode with ICH6 */
674 ich6_lpc_acpi_gpio(dev);
676 /* And have 4 ICH7+ generic decodes */
677 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
678 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
679 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
680 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
682 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
683 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
684 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
685 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
686 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
687 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
688 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
689 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
690 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
691 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
692 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
693 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
694 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
697 * VIA ACPI: One IO region pointed to by longword at
698 * 0x48 or 0x20 (256 bytes of ACPI registers)
700 static void quirk_vt82c586_acpi(struct pci_dev *dev)
702 if (dev->revision & 0x10)
703 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
709 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
710 * 0x48 (256 bytes of ACPI registers)
711 * 0x70 (128 bytes of hardware monitoring register)
712 * 0x90 (16 bytes of SMB registers)
714 static void quirk_vt82c686_acpi(struct pci_dev *dev)
716 quirk_vt82c586_acpi(dev);
718 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
721 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
723 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
726 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
727 * 0x88 (128 bytes of power management registers)
728 * 0xd0 (16 bytes of SMB registers)
730 static void quirk_vt8235_acpi(struct pci_dev *dev)
732 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
733 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
738 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
739 * Disable fast back-to-back on the secondary bus segment
741 static void quirk_xio2000a(struct pci_dev *dev)
743 struct pci_dev *pdev;
746 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
747 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
748 pci_read_config_word(pdev, PCI_COMMAND, &command);
749 if (command & PCI_COMMAND_FAST_BACK)
750 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
753 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
756 #ifdef CONFIG_X86_IO_APIC
758 #include <asm/io_apic.h>
761 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
762 * devices to the external APIC.
764 * TODO: When we have device-specific interrupt routers,
765 * this code will go away from quirks.
767 static void quirk_via_ioapic(struct pci_dev *dev)
772 tmp = 0; /* nothing routed to external APIC */
774 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
776 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
777 tmp == 0 ? "Disa" : "Ena");
779 /* Offset 0x58: External APIC IRQ output control */
780 pci_write_config_byte(dev, 0x58, tmp);
782 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
783 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
786 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
787 * This leads to doubled level interrupt rates.
788 * Set this bit to get rid of cycle wastage.
789 * Otherwise uncritical.
791 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
794 #define BYPASS_APIC_DEASSERT 8
796 pci_read_config_byte(dev, 0x5B, &misc_control2);
797 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
798 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
799 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
803 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
806 * The AMD io apic can hang the box when an apic irq is masked.
807 * We check all revs >= B0 (yet not in the pre production!) as the bug
808 * is currently marked NoFix
810 * We have multiple reports of hangs with this chipset that went away with
811 * noapic specified. For the moment we assume it's the erratum. We may be wrong
812 * of course. However the advice is demonstrably good even if so..
814 static void quirk_amd_ioapic(struct pci_dev *dev)
816 if (dev->revision >= 0x02) {
817 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
818 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
821 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
823 static void quirk_ioapic_rmw(struct pci_dev *dev)
825 if (dev->devfn == 0 && dev->bus->number == 0)
828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
829 #endif /* CONFIG_X86_IO_APIC */
832 * Some settings of MMRBC can lead to data corruption so block changes.
833 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
835 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
837 if (dev->subordinate && dev->revision <= 0x12) {
838 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
840 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
843 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
846 * FIXME: it is questionable that quirk_via_acpi
847 * is needed. It shows up as an ISA bridge, and does not
848 * support the PCI_INTERRUPT_LINE register at all. Therefore
849 * it seems like setting the pci_dev's 'irq' to the
850 * value of the ACPI SCI interrupt is only done for convenience.
853 static void quirk_via_acpi(struct pci_dev *d)
856 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
859 pci_read_config_byte(d, 0x42, &irq);
861 if (irq && (irq != 2))
864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
869 * VIA bridges which have VLink
872 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
874 static void quirk_via_bridge(struct pci_dev *dev)
876 /* See what bridge we have and find the device ranges */
877 switch (dev->device) {
878 case PCI_DEVICE_ID_VIA_82C686:
879 /* The VT82C686 is special, it attaches to PCI and can have
880 any device number. All its subdevices are functions of
881 that single device. */
882 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
883 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
885 case PCI_DEVICE_ID_VIA_8237:
886 case PCI_DEVICE_ID_VIA_8237A:
887 via_vlink_dev_lo = 15;
889 case PCI_DEVICE_ID_VIA_8235:
890 via_vlink_dev_lo = 16;
892 case PCI_DEVICE_ID_VIA_8231:
893 case PCI_DEVICE_ID_VIA_8233_0:
894 case PCI_DEVICE_ID_VIA_8233A:
895 case PCI_DEVICE_ID_VIA_8233C_0:
896 via_vlink_dev_lo = 17;
900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
910 * quirk_via_vlink - VIA VLink IRQ number update
913 * If the device we are dealing with is on a PIC IRQ we need to
914 * ensure that the IRQ line register which usually is not relevant
915 * for PCI cards, is actually written so that interrupts get sent
916 * to the right place.
917 * We only do this on systems where a VIA south bridge was detected,
918 * and only for VIA devices on the motherboard (see quirk_via_bridge
922 static void quirk_via_vlink(struct pci_dev *dev)
926 /* Check if we have VLink at all */
927 if (via_vlink_dev_lo == -1)
932 /* Don't quirk interrupts outside the legacy IRQ range */
933 if (!new_irq || new_irq > 15)
936 /* Internal device ? */
937 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
938 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
941 /* This is an internal VLink device on a PIC interrupt. The BIOS
942 ought to have set this but may not have, so we redo it */
944 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
945 if (new_irq != irq) {
946 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
948 udelay(15); /* unknown if delay really needed */
949 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
952 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
955 * VIA VT82C598 has its device ID settable and many BIOSes
956 * set it to the ID of VT82C597 for backward compatibility.
957 * We need to switch it off to be able to recognize the real
960 static void quirk_vt82c598_id(struct pci_dev *dev)
962 pci_write_config_byte(dev, 0xfc, 0);
963 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
965 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
968 * CardBus controllers have a legacy base address that enables them
969 * to respond as i82365 pcmcia controllers. We don't want them to
970 * do this even if the Linux CardBus driver is not loaded, because
971 * the Linux i82365 driver does not (and should not) handle CardBus.
973 static void quirk_cardbus_legacy(struct pci_dev *dev)
975 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
977 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
978 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
979 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
980 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
983 * Following the PCI ordering rules is optional on the AMD762. I'm not
984 * sure what the designers were smoking but let's not inhale...
986 * To be fair to AMD, it follows the spec by default, its BIOS people
989 static void quirk_amd_ordering(struct pci_dev *dev)
992 pci_read_config_dword(dev, 0x4C, &pcic);
993 if ((pcic & 6) != 6) {
995 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
996 pci_write_config_dword(dev, 0x4C, pcic);
997 pci_read_config_dword(dev, 0x84, &pcic);
998 pcic |= (1 << 23); /* Required in this mode */
999 pci_write_config_dword(dev, 0x84, pcic);
1002 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1003 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1006 * DreamWorks provided workaround for Dunord I-3000 problem
1008 * This card decodes and responds to addresses not apparently
1009 * assigned to it. We force a larger allocation to ensure that
1010 * nothing gets put too close to it.
1012 static void quirk_dunord(struct pci_dev *dev)
1014 struct resource *r = &dev->resource[1];
1016 r->flags |= IORESOURCE_UNSET;
1020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1023 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1024 * is subtractive decoding (transparent), and does indicate this
1025 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1028 static void quirk_transparent_bridge(struct pci_dev *dev)
1030 dev->transparent = 1;
1032 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1033 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1036 * Common misconfiguration of the MediaGX/Geode PCI master that will
1037 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1038 * datasheets found at http://www.national.com/analog for info on what
1039 * these bits do. <christer@weinigel.se>
1041 static void quirk_mediagx_master(struct pci_dev *dev)
1045 pci_read_config_byte(dev, 0x41, ®);
1048 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1050 pci_write_config_byte(dev, 0x41, reg);
1053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1054 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1057 * Ensure C0 rev restreaming is off. This is normally done by
1058 * the BIOS but in the odd case it is not the results are corruption
1059 * hence the presence of a Linux check
1061 static void quirk_disable_pxb(struct pci_dev *pdev)
1065 if (pdev->revision != 0x04) /* Only C0 requires this */
1067 pci_read_config_word(pdev, 0x40, &config);
1068 if (config & (1<<6)) {
1070 pci_write_config_word(pdev, 0x40, config);
1071 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1075 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1077 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1079 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1082 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1084 pci_read_config_byte(pdev, 0x40, &tmp);
1085 pci_write_config_byte(pdev, 0x40, tmp|1);
1086 pci_write_config_byte(pdev, 0x9, 1);
1087 pci_write_config_byte(pdev, 0xa, 6);
1088 pci_write_config_byte(pdev, 0x40, tmp);
1090 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1091 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1095 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1097 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1099 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1101 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1104 * Serverworks CSB5 IDE does not fully support native mode
1106 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1109 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1113 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1114 /* PCI layer will sort out resources */
1117 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1120 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1122 static void quirk_ide_samemode(struct pci_dev *pdev)
1126 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1128 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1129 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1132 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1135 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1138 * Some ATA devices break if put into D3
1141 static void quirk_no_ata_d3(struct pci_dev *pdev)
1143 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1145 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1146 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1147 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1148 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1149 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1150 /* ALi loses some register settings that we cannot then restore */
1151 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1152 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1153 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1154 occur when mode detecting */
1155 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1156 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1158 /* This was originally an Alpha specific thing, but it really fits here.
1159 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1161 static void quirk_eisa_bridge(struct pci_dev *dev)
1163 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1169 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1170 * is not activated. The myth is that Asus said that they do not want the
1171 * users to be irritated by just another PCI Device in the Win98 device
1172 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1173 * package 2.7.0 for details)
1175 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1176 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1177 * becomes necessary to do this tweak in two steps -- the chosen trigger
1178 * is either the Host bridge (preferred) or on-board VGA controller.
1180 * Note that we used to unhide the SMBus that way on Toshiba laptops
1181 * (Satellite A40 and Tecra M2) but then found that the thermal management
1182 * was done by SMM code, which could cause unsynchronized concurrent
1183 * accesses to the SMBus registers, with potentially bad effects. Thus you
1184 * should be very careful when adding new entries: if SMM is accessing the
1185 * Intel SMBus, this is a very good reason to leave it hidden.
1187 * Likewise, many recent laptops use ACPI for thermal management. If the
1188 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1189 * natively, and keeping the SMBus hidden is the right thing to do. If you
1190 * are about to add an entry in the table below, please first disassemble
1191 * the DSDT and double-check that there is no code accessing the SMBus.
1193 static int asus_hides_smbus;
1195 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1197 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1198 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1199 switch (dev->subsystem_device) {
1200 case 0x8025: /* P4B-LX */
1201 case 0x8070: /* P4B */
1202 case 0x8088: /* P4B533 */
1203 case 0x1626: /* L3C notebook */
1204 asus_hides_smbus = 1;
1206 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1207 switch (dev->subsystem_device) {
1208 case 0x80b1: /* P4GE-V */
1209 case 0x80b2: /* P4PE */
1210 case 0x8093: /* P4B533-V */
1211 asus_hides_smbus = 1;
1213 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1214 switch (dev->subsystem_device) {
1215 case 0x8030: /* P4T533 */
1216 asus_hides_smbus = 1;
1218 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1219 switch (dev->subsystem_device) {
1220 case 0x8070: /* P4G8X Deluxe */
1221 asus_hides_smbus = 1;
1223 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1224 switch (dev->subsystem_device) {
1225 case 0x80c9: /* PU-DLS */
1226 asus_hides_smbus = 1;
1228 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1229 switch (dev->subsystem_device) {
1230 case 0x1751: /* M2N notebook */
1231 case 0x1821: /* M5N notebook */
1232 case 0x1897: /* A6L notebook */
1233 asus_hides_smbus = 1;
1235 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1236 switch (dev->subsystem_device) {
1237 case 0x184b: /* W1N notebook */
1238 case 0x186a: /* M6Ne notebook */
1239 asus_hides_smbus = 1;
1241 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1242 switch (dev->subsystem_device) {
1243 case 0x80f2: /* P4P800-X */
1244 asus_hides_smbus = 1;
1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1247 switch (dev->subsystem_device) {
1248 case 0x1882: /* M6V notebook */
1249 case 0x1977: /* A6VA notebook */
1250 asus_hides_smbus = 1;
1252 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1253 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1254 switch (dev->subsystem_device) {
1255 case 0x088C: /* HP Compaq nc8000 */
1256 case 0x0890: /* HP Compaq nc6000 */
1257 asus_hides_smbus = 1;
1259 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1260 switch (dev->subsystem_device) {
1261 case 0x12bc: /* HP D330L */
1262 case 0x12bd: /* HP D530 */
1263 case 0x006a: /* HP Compaq nx9500 */
1264 asus_hides_smbus = 1;
1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1267 switch (dev->subsystem_device) {
1268 case 0x12bf: /* HP xw4100 */
1269 asus_hides_smbus = 1;
1271 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1272 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1273 switch (dev->subsystem_device) {
1274 case 0xC00C: /* Samsung P35 notebook */
1275 asus_hides_smbus = 1;
1277 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1278 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1279 switch (dev->subsystem_device) {
1280 case 0x0058: /* Compaq Evo N620c */
1281 asus_hides_smbus = 1;
1283 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1284 switch (dev->subsystem_device) {
1285 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1286 /* Motherboard doesn't have Host bridge
1287 * subvendor/subdevice IDs, therefore checking
1288 * its on-board VGA controller */
1289 asus_hides_smbus = 1;
1291 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1292 switch (dev->subsystem_device) {
1293 case 0x00b8: /* Compaq Evo D510 CMT */
1294 case 0x00b9: /* Compaq Evo D510 SFF */
1295 case 0x00ba: /* Compaq Evo D510 USDT */
1296 /* Motherboard doesn't have Host bridge
1297 * subvendor/subdevice IDs and on-board VGA
1298 * controller is disabled if an AGP card is
1299 * inserted, therefore checking USB UHCI
1301 asus_hides_smbus = 1;
1303 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1304 switch (dev->subsystem_device) {
1305 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1306 /* Motherboard doesn't have host bridge
1307 * subvendor/subdevice IDs, therefore checking
1308 * its on-board VGA controller */
1309 asus_hides_smbus = 1;
1313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1328 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1332 if (likely(!asus_hides_smbus))
1335 pci_read_config_word(dev, 0xF2, &val);
1337 pci_write_config_word(dev, 0xF2, val & (~0x8));
1338 pci_read_config_word(dev, 0xF2, &val);
1340 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1343 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1353 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1354 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1355 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1356 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1357 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1358 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1359 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1361 /* It appears we just have one such device. If not, we have a warning */
1362 static void __iomem *asus_rcba_base;
1363 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1367 if (likely(!asus_hides_smbus))
1369 WARN_ON(asus_rcba_base);
1371 pci_read_config_dword(dev, 0xF0, &rcba);
1372 /* use bits 31:14, 16 kB aligned */
1373 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1374 if (asus_rcba_base == NULL)
1378 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1382 if (likely(!asus_hides_smbus || !asus_rcba_base))
1384 /* read the Function Disable register, dword mode only */
1385 val = readl(asus_rcba_base + 0x3418);
1386 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1389 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1391 if (likely(!asus_hides_smbus || !asus_rcba_base))
1393 iounmap(asus_rcba_base);
1394 asus_rcba_base = NULL;
1395 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1398 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1400 asus_hides_smbus_lpc_ich6_suspend(dev);
1401 asus_hides_smbus_lpc_ich6_resume_early(dev);
1402 asus_hides_smbus_lpc_ich6_resume(dev);
1404 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1405 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1406 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1407 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1410 * SiS 96x south bridge: BIOS typically hides SMBus device...
1412 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1415 pci_read_config_byte(dev, 0x77, &val);
1417 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1418 pci_write_config_byte(dev, 0x77, val & ~0x10);
1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1425 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1426 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1427 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1428 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1431 * ... This is further complicated by the fact that some SiS96x south
1432 * bridges pretend to be 85C503/5513 instead. In that case see if we
1433 * spotted a compatible north bridge to make sure.
1434 * (pci_find_device doesn't work yet)
1436 * We can also enable the sis96x bit in the discovery register..
1438 #define SIS_DETECT_REGISTER 0x40
1440 static void quirk_sis_503(struct pci_dev *dev)
1445 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1446 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1447 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1448 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1449 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1454 * Ok, it now shows up as a 96x.. run the 96x quirk by
1455 * hand in case it has already been processed.
1456 * (depends on link order, which is apparently not guaranteed)
1458 dev->device = devid;
1459 quirk_sis_96x_smbus(dev);
1461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1462 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1466 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1467 * and MC97 modem controller are disabled when a second PCI soundcard is
1468 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1471 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1474 int asus_hides_ac97 = 0;
1476 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1477 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1478 asus_hides_ac97 = 1;
1481 if (!asus_hides_ac97)
1484 pci_read_config_byte(dev, 0x50, &val);
1486 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1487 pci_read_config_byte(dev, 0x50, &val);
1489 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1492 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1496 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1498 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1501 * If we are using libata we can drive this chip properly but must
1502 * do this early on to make the additional device appear during
1505 static void quirk_jmicron_ata(struct pci_dev *pdev)
1507 u32 conf1, conf5, class;
1510 /* Only poke fn 0 */
1511 if (PCI_FUNC(pdev->devfn))
1514 pci_read_config_dword(pdev, 0x40, &conf1);
1515 pci_read_config_dword(pdev, 0x80, &conf5);
1517 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1518 conf5 &= ~(1 << 24); /* Clear bit 24 */
1520 switch (pdev->device) {
1521 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1522 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1523 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1524 /* The controller should be in single function ahci mode */
1525 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1528 case PCI_DEVICE_ID_JMICRON_JMB365:
1529 case PCI_DEVICE_ID_JMICRON_JMB366:
1530 /* Redirect IDE second PATA port to the right spot */
1533 case PCI_DEVICE_ID_JMICRON_JMB361:
1534 case PCI_DEVICE_ID_JMICRON_JMB363:
1535 case PCI_DEVICE_ID_JMICRON_JMB369:
1536 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1537 /* Set the class codes correctly and then direct IDE 0 */
1538 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1541 case PCI_DEVICE_ID_JMICRON_JMB368:
1542 /* The controller should be in single function IDE mode */
1543 conf1 |= 0x00C00000; /* Set 22, 23 */
1547 pci_write_config_dword(pdev, 0x40, conf1);
1548 pci_write_config_dword(pdev, 0x80, conf5);
1550 /* Update pdev accordingly */
1551 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1552 pdev->hdr_type = hdr & 0x7f;
1553 pdev->multifunction = !!(hdr & 0x80);
1555 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1556 pdev->class = class >> 8;
1558 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1559 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1560 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1561 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1562 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1563 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1564 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1565 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1566 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1567 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1568 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1569 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1570 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1571 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1572 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1573 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1574 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1575 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1579 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1581 if (dev->multifunction) {
1582 device_disable_async_suspend(&dev->dev);
1583 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1586 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1587 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1591 #ifdef CONFIG_X86_IO_APIC
1592 static void quirk_alder_ioapic(struct pci_dev *pdev)
1596 if ((pdev->class >> 8) != 0xff00)
1599 /* the first BAR is the location of the IO APIC...we must
1600 * not touch this (and it's already covered by the fixmap), so
1601 * forcibly insert it into the resource tree */
1602 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1603 insert_resource(&iomem_resource, &pdev->resource[0]);
1605 /* The next five BARs all seem to be rubbish, so just clean
1607 for (i = 1; i < 6; i++)
1608 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1613 static void quirk_pcie_mch(struct pci_dev *pdev)
1618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1624 * It's possible for the MSI to get corrupted if shpc and acpi
1625 * are used together on certain PXH-based systems.
1627 static void quirk_pcie_pxh(struct pci_dev *dev)
1631 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1633 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1634 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1635 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1636 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1637 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1640 * Some Intel PCI Express chipsets have trouble with downstream
1641 * device power management.
1643 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1645 pci_pm_d3_delay = 120;
1649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1657 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1660 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1662 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1663 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1664 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1671 #ifdef CONFIG_X86_IO_APIC
1673 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1674 * remap the original interrupt in the linux kernel to the boot interrupt, so
1675 * that a PCI device's interrupt handler is installed on the boot interrupt
1678 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1680 if (noioapicquirk || noioapicreroute)
1683 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1684 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1685 dev->vendor, dev->device);
1687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1691 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1692 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1695 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1696 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1697 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1698 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1699 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1700 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1701 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1702 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1705 * On some chipsets we can disable the generation of legacy INTx boot
1710 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1711 * 300641-004US, section 5.7.3.
1713 #define INTEL_6300_IOAPIC_ABAR 0x40
1714 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1716 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1718 u16 pci_config_word;
1723 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1724 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1725 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1727 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1728 dev->vendor, dev->device);
1730 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1731 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1734 * disable boot interrupts on HT-1000
1736 #define BC_HT1000_FEATURE_REG 0x64
1737 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1738 #define BC_HT1000_MAP_IDX 0xC00
1739 #define BC_HT1000_MAP_DATA 0xC01
1741 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1743 u32 pci_config_dword;
1749 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1750 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1751 BC_HT1000_PIC_REGS_ENABLE);
1753 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1754 outb(irq, BC_HT1000_MAP_IDX);
1755 outb(0x00, BC_HT1000_MAP_DATA);
1758 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1760 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1761 dev->vendor, dev->device);
1763 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1764 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1767 * disable boot interrupts on AMD and ATI chipsets
1770 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1771 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1772 * (due to an erratum).
1774 #define AMD_813X_MISC 0x40
1775 #define AMD_813X_NOIOAMODE (1<<0)
1776 #define AMD_813X_REV_B1 0x12
1777 #define AMD_813X_REV_B2 0x13
1779 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1781 u32 pci_config_dword;
1785 if ((dev->revision == AMD_813X_REV_B1) ||
1786 (dev->revision == AMD_813X_REV_B2))
1789 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1790 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1791 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1793 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1794 dev->vendor, dev->device);
1796 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1797 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1798 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1799 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1801 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1803 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1805 u16 pci_config_word;
1810 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1811 if (!pci_config_word) {
1812 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1813 dev->vendor, dev->device);
1816 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1817 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1818 dev->vendor, dev->device);
1820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1821 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1822 #endif /* CONFIG_X86_IO_APIC */
1825 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1826 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1827 * Re-allocate the region if needed...
1829 static void quirk_tc86c001_ide(struct pci_dev *dev)
1831 struct resource *r = &dev->resource[0];
1833 if (r->start & 0x8) {
1834 r->flags |= IORESOURCE_UNSET;
1839 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1840 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1841 quirk_tc86c001_ide);
1844 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1845 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1846 * being read correctly if bit 7 of the base address is set.
1847 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1848 * Re-allocate the regions to a 256-byte boundary if necessary.
1850 static void quirk_plx_pci9050(struct pci_dev *dev)
1854 /* Fixed in revision 2 (PCI 9052). */
1855 if (dev->revision >= 2)
1857 for (bar = 0; bar <= 1; bar++)
1858 if (pci_resource_len(dev, bar) == 0x80 &&
1859 (pci_resource_start(dev, bar) & 0x80)) {
1860 struct resource *r = &dev->resource[bar];
1861 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1863 r->flags |= IORESOURCE_UNSET;
1868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1871 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1872 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1873 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1874 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1876 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1879 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1880 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1882 static void quirk_netmos(struct pci_dev *dev)
1884 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1885 unsigned int num_serial = dev->subsystem_device & 0xf;
1888 * These Netmos parts are multiport serial devices with optional
1889 * parallel ports. Even when parallel ports are present, they
1890 * are identified as class SERIAL, which means the serial driver
1891 * will claim them. To prevent this, mark them as class OTHER.
1892 * These combo devices should be claimed by parport_serial.
1894 * The subdevice ID is of the form 0x00PS, where <P> is the number
1895 * of parallel ports and <S> is the number of serial ports.
1897 switch (dev->device) {
1898 case PCI_DEVICE_ID_NETMOS_9835:
1899 /* Well, this rule doesn't hold for the following 9835 device */
1900 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1901 dev->subsystem_device == 0x0299)
1903 case PCI_DEVICE_ID_NETMOS_9735:
1904 case PCI_DEVICE_ID_NETMOS_9745:
1905 case PCI_DEVICE_ID_NETMOS_9845:
1906 case PCI_DEVICE_ID_NETMOS_9855:
1908 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1909 dev->device, num_parallel, num_serial);
1910 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1911 (dev->class & 0xff);
1915 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1916 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1918 static void quirk_f0_vpd_link(struct pci_dev *dev)
1920 if (!dev->multifunction || !PCI_FUNC(dev->devfn))
1922 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1924 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1925 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1927 static void quirk_e100_interrupt(struct pci_dev *dev)
1933 switch (dev->device) {
1934 /* PCI IDs taken from drivers/net/e100.c */
1936 case 0x1030 ... 0x1034:
1937 case 0x1038 ... 0x103E:
1938 case 0x1050 ... 0x1057:
1940 case 0x1064 ... 0x106B:
1941 case 0x1091 ... 0x1095:
1954 * Some firmware hands off the e100 with interrupts enabled,
1955 * which can cause a flood of interrupts if packets are
1956 * received before the driver attaches to the device. So
1957 * disable all e100 interrupts here. The driver will
1958 * re-enable them when it's ready.
1960 pci_read_config_word(dev, PCI_COMMAND, &command);
1962 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1966 * Check that the device is in the D0 power state. If it's not,
1967 * there is no point to look any further.
1970 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1971 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1975 /* Convert from PCI bus to resource space. */
1976 csr = ioremap(pci_resource_start(dev, 0), 8);
1978 dev_warn(&dev->dev, "Can't map e100 registers\n");
1982 cmd_hi = readb(csr + 3);
1984 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
1990 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1991 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
1994 * The 82575 and 82598 may experience data corruption issues when transitioning
1995 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1997 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
1999 dev_info(&dev->dev, "Disabling L0s\n");
2000 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2002 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2004 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2007 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2010 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2011 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2012 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2013 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2017 static void fixup_rev1_53c810(struct pci_dev *dev)
2019 /* rev 1 ncr53c810 chips don't set the class at all which means
2020 * they don't get their resources remapped. Fix that here.
2023 if (dev->class == PCI_CLASS_NOT_DEFINED) {
2024 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
2025 dev->class = PCI_CLASS_STORAGE_SCSI;
2028 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2030 /* Enable 1k I/O space granularity on the Intel P64H2 */
2031 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2035 pci_read_config_word(dev, 0x40, &en1k);
2038 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2039 dev->io_window_1k = 1;
2042 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2044 /* Under some circumstances, AER is not linked with extended capabilities.
2045 * Force it to be linked by setting the corresponding control bit in the
2048 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2051 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2053 pci_write_config_byte(dev, 0xf41, b | 0x20);
2054 dev_info(&dev->dev, "Linking AER extended capability\n");
2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2059 quirk_nvidia_ck804_pcie_aer_ext_cap);
2060 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2061 quirk_nvidia_ck804_pcie_aer_ext_cap);
2063 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2066 * Disable PCI Bus Parking and PCI Master read caching on CX700
2067 * which causes unspecified timing errors with a VT6212L on the PCI
2068 * bus leading to USB2.0 packet loss.
2070 * This quirk is only enabled if a second (on the external PCI bus)
2071 * VT6212L is found -- the CX700 core itself also contains a USB
2072 * host controller with the same PCI ID as the VT6212L.
2075 /* Count VT6212L instances */
2076 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2077 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2080 /* p should contain the first (internal) VT6212L -- see if we have
2081 an external one by searching again */
2082 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2087 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2089 /* Turn off PCI Bus Parking */
2090 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2092 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2096 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2098 /* Turn off PCI Master read caching */
2099 pci_write_config_byte(dev, 0x72, 0x0);
2101 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2102 pci_write_config_byte(dev, 0x75, 0x1);
2104 /* Disable "Read FIFO Timer" */
2105 pci_write_config_byte(dev, 0x77, 0x0);
2107 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2114 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2115 * VPD end tag will hang the device. This problem was initially
2116 * observed when a vpd entry was created in sysfs
2117 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2118 * will dump 32k of data. Reading a full 32k will cause an access
2119 * beyond the VPD end tag causing the device to hang. Once the device
2120 * is hung, the bnx2 driver will not be able to reset the device.
2121 * We believe that it is legal to read beyond the end tag and
2122 * therefore the solution is to limit the read/write length.
2124 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2127 * Only disable the VPD capability for 5706, 5706S, 5708,
2128 * 5708S and 5709 rev. A
2130 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2131 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2132 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2133 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2134 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2135 (dev->revision & 0xf0) == 0x0)) {
2137 dev->vpd->len = 0x80;
2141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2142 PCI_DEVICE_ID_NX2_5706,
2143 quirk_brcm_570x_limit_vpd);
2144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2145 PCI_DEVICE_ID_NX2_5706S,
2146 quirk_brcm_570x_limit_vpd);
2147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2148 PCI_DEVICE_ID_NX2_5708,
2149 quirk_brcm_570x_limit_vpd);
2150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2151 PCI_DEVICE_ID_NX2_5708S,
2152 quirk_brcm_570x_limit_vpd);
2153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2154 PCI_DEVICE_ID_NX2_5709,
2155 quirk_brcm_570x_limit_vpd);
2156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2157 PCI_DEVICE_ID_NX2_5709S,
2158 quirk_brcm_570x_limit_vpd);
2160 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2164 pci_read_config_dword(dev, 0xf4, &rev);
2166 /* Only CAP the MRRS if the device is a 5719 A0 */
2167 if (rev == 0x05719000) {
2168 int readrq = pcie_get_readrq(dev);
2170 pcie_set_readrq(dev, 2048);
2174 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2175 PCI_DEVICE_ID_TIGON3_5719,
2176 quirk_brcm_5719_limit_mrrs);
2178 /* Originally in EDAC sources for i82875P:
2179 * Intel tells BIOS developers to hide device 6 which
2180 * configures the overflow device access containing
2181 * the DRBs - this is where we expose device 6.
2182 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2184 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2188 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2189 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2190 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2194 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2195 quirk_unhide_mch_dev6);
2196 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2197 quirk_unhide_mch_dev6);
2199 #ifdef CONFIG_TILEPRO
2201 * The Tilera TILEmpower tilepro platform needs to set the link speed
2202 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2203 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2204 * capability register of the PEX8624 PCIe switch. The switch
2205 * supports link speed auto negotiation, but falsely sets
2206 * the link speed to 5GT/s.
2208 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2210 if (tile_plx_gen1) {
2211 pci_write_config_dword(dev, 0x98, 0x1);
2215 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2216 #endif /* CONFIG_TILEPRO */
2218 #ifdef CONFIG_PCI_MSI
2219 /* Some chipsets do not support MSI. We cannot easily rely on setting
2220 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2221 * some other buses controlled by the chipset even if Linux is not
2222 * aware of it. Instead of setting the flag on all buses in the
2223 * machine, simply disable MSI globally.
2225 static void quirk_disable_all_msi(struct pci_dev *dev)
2228 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2238 /* Disable MSI on chipsets that are known to not support it */
2239 static void quirk_disable_msi(struct pci_dev *dev)
2241 if (dev->subordinate) {
2242 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2243 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2251 * The APC bridge device in AMD 780 family northbridges has some random
2252 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2253 * we use the possible vendor/device IDs of the host bridge for the
2254 * declared quirk, and search for the APC bridge by slot number.
2256 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2258 struct pci_dev *apc_bridge;
2260 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2262 if (apc_bridge->device == 0x9602)
2263 quirk_disable_msi(apc_bridge);
2264 pci_dev_put(apc_bridge);
2267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2270 /* Go through the list of Hypertransport capabilities and
2271 * return 1 if a HT MSI capability is found and enabled */
2272 static int msi_ht_cap_enabled(struct pci_dev *dev)
2276 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2277 while (pos && ttl--) {
2280 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2282 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2283 flags & HT_MSI_FLAGS_ENABLE ?
2284 "enabled" : "disabled");
2285 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2288 pos = pci_find_next_ht_capability(dev, pos,
2289 HT_CAPTYPE_MSI_MAPPING);
2294 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2295 static void quirk_msi_ht_cap(struct pci_dev *dev)
2297 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2298 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2299 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2305 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2306 * MSI are supported if the MSI capability set in any of these mappings.
2308 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2310 struct pci_dev *pdev;
2312 if (!dev->subordinate)
2315 /* check HT MSI cap on this chipset and the root one.
2316 * a single one having MSI is enough to be sure that MSI are supported.
2318 pdev = pci_get_slot(dev->bus, 0);
2321 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2322 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2323 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2328 quirk_nvidia_ck804_msi_ht_cap);
2330 /* Force enable MSI mapping capability on HT bridges */
2331 static void ht_enable_msi_mapping(struct pci_dev *dev)
2335 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2336 while (pos && ttl--) {
2339 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2341 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2343 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2344 flags | HT_MSI_FLAGS_ENABLE);
2346 pos = pci_find_next_ht_capability(dev, pos,
2347 HT_CAPTYPE_MSI_MAPPING);
2350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2351 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2352 ht_enable_msi_mapping);
2354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2355 ht_enable_msi_mapping);
2357 /* The P5N32-SLI motherboards from Asus have a problem with msi
2358 * for the MCP55 NIC. It is not yet determined whether the msi problem
2359 * also affects other devices. As for now, turn off msi for this device.
2361 static void nvenet_msi_disable(struct pci_dev *dev)
2363 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2366 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2367 strstr(board_name, "P5N32-E SLI"))) {
2368 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2372 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2373 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2374 nvenet_msi_disable);
2377 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2378 * config register. This register controls the routing of legacy
2379 * interrupts from devices that route through the MCP55. If this register
2380 * is misprogrammed, interrupts are only sent to the BSP, unlike
2381 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2382 * having this register set properly prevents kdump from booting up
2383 * properly, so let's make sure that we have it set correctly.
2384 * Note that this is an undocumented register.
2386 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2390 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2393 pci_read_config_dword(dev, 0x74, &cfg);
2395 if (cfg & ((1 << 2) | (1 << 15))) {
2396 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2397 cfg &= ~((1 << 2) | (1 << 15));
2398 pci_write_config_dword(dev, 0x74, cfg);
2402 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2403 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2404 nvbridge_check_legacy_irq_routing);
2406 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2407 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2408 nvbridge_check_legacy_irq_routing);
2410 static int ht_check_msi_mapping(struct pci_dev *dev)
2415 /* check if there is HT MSI cap or enabled on this device */
2416 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2417 while (pos && ttl--) {
2422 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2424 if (flags & HT_MSI_FLAGS_ENABLE) {
2431 pos = pci_find_next_ht_capability(dev, pos,
2432 HT_CAPTYPE_MSI_MAPPING);
2438 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2440 struct pci_dev *dev;
2445 dev_no = host_bridge->devfn >> 3;
2446 for (i = dev_no + 1; i < 0x20; i++) {
2447 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2451 /* found next host bridge ?*/
2452 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2458 if (ht_check_msi_mapping(dev)) {
2469 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2470 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2472 static int is_end_of_ht_chain(struct pci_dev *dev)
2478 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2483 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2485 ctrl_off = ((flags >> 10) & 1) ?
2486 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2487 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2489 if (ctrl & (1 << 6))
2496 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2498 struct pci_dev *host_bridge;
2503 dev_no = dev->devfn >> 3;
2504 for (i = dev_no; i >= 0; i--) {
2505 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2509 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2514 pci_dev_put(host_bridge);
2520 /* don't enable end_device/host_bridge with leaf directly here */
2521 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2522 host_bridge_with_leaf(host_bridge))
2525 /* root did that ! */
2526 if (msi_ht_cap_enabled(host_bridge))
2529 ht_enable_msi_mapping(dev);
2532 pci_dev_put(host_bridge);
2535 static void ht_disable_msi_mapping(struct pci_dev *dev)
2539 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2540 while (pos && ttl--) {
2543 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2545 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2547 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2548 flags & ~HT_MSI_FLAGS_ENABLE);
2550 pos = pci_find_next_ht_capability(dev, pos,
2551 HT_CAPTYPE_MSI_MAPPING);
2555 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2557 struct pci_dev *host_bridge;
2561 if (!pci_msi_enabled())
2564 /* check if there is HT MSI cap or enabled on this device */
2565 found = ht_check_msi_mapping(dev);
2572 * HT MSI mapping should be disabled on devices that are below
2573 * a non-Hypertransport host bridge. Locate the host bridge...
2575 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2576 if (host_bridge == NULL) {
2577 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2581 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2583 /* Host bridge is to HT */
2585 /* it is not enabled, try to enable it */
2587 ht_enable_msi_mapping(dev);
2589 nv_ht_enable_msi_mapping(dev);
2594 /* HT MSI is not enabled */
2598 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2599 ht_disable_msi_mapping(dev);
2602 pci_dev_put(host_bridge);
2605 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2607 return __nv_msi_ht_cap_quirk(dev, 1);
2610 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2612 return __nv_msi_ht_cap_quirk(dev, 0);
2615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2616 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2619 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2621 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2623 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2625 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2629 /* SB700 MSI issue will be fixed at HW level from revision A21,
2630 * we need check PCI REVISION ID of SMBus controller to get SB700
2633 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2638 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2639 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2642 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2644 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2645 if (dev->revision < 0x18) {
2646 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2647 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2651 PCI_DEVICE_ID_TIGON3_5780,
2652 quirk_msi_intx_disable_bug);
2653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2654 PCI_DEVICE_ID_TIGON3_5780S,
2655 quirk_msi_intx_disable_bug);
2656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2657 PCI_DEVICE_ID_TIGON3_5714,
2658 quirk_msi_intx_disable_bug);
2659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2660 PCI_DEVICE_ID_TIGON3_5714S,
2661 quirk_msi_intx_disable_bug);
2662 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2663 PCI_DEVICE_ID_TIGON3_5715,
2664 quirk_msi_intx_disable_bug);
2665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2666 PCI_DEVICE_ID_TIGON3_5715S,
2667 quirk_msi_intx_disable_bug);
2669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2670 quirk_msi_intx_disable_ati_bug);
2671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2672 quirk_msi_intx_disable_ati_bug);
2673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2674 quirk_msi_intx_disable_ati_bug);
2675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2676 quirk_msi_intx_disable_ati_bug);
2677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2678 quirk_msi_intx_disable_ati_bug);
2680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2681 quirk_msi_intx_disable_bug);
2682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2683 quirk_msi_intx_disable_bug);
2684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2685 quirk_msi_intx_disable_bug);
2687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2688 quirk_msi_intx_disable_bug);
2689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2690 quirk_msi_intx_disable_bug);
2691 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2692 quirk_msi_intx_disable_bug);
2693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2694 quirk_msi_intx_disable_bug);
2695 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2696 quirk_msi_intx_disable_bug);
2697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2698 quirk_msi_intx_disable_bug);
2699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2700 quirk_msi_intx_disable_qca_bug);
2701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2702 quirk_msi_intx_disable_qca_bug);
2703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2704 quirk_msi_intx_disable_qca_bug);
2705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2706 quirk_msi_intx_disable_qca_bug);
2707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2708 quirk_msi_intx_disable_qca_bug);
2709 #endif /* CONFIG_PCI_MSI */
2711 /* Allow manual resource allocation for PCI hotplug bridges
2712 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2713 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2714 * kernel fails to allocate resources when hotplug device is
2715 * inserted and PCI bus is rescanned.
2717 static void quirk_hotplug_bridge(struct pci_dev *dev)
2719 dev->is_hotplug_bridge = 1;
2722 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2725 * This is a quirk for the Ricoh MMC controller found as a part of
2726 * some mulifunction chips.
2728 * This is very similar and based on the ricoh_mmc driver written by
2729 * Philip Langdale. Thank you for these magic sequences.
2731 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2732 * and one or both of cardbus or firewire.
2734 * It happens that they implement SD and MMC
2735 * support as separate controllers (and PCI functions). The linux SDHCI
2736 * driver supports MMC cards but the chip detects MMC cards in hardware
2737 * and directs them to the MMC controller - so the SDHCI driver never sees
2740 * To get around this, we must disable the useless MMC controller.
2741 * At that point, the SDHCI controller will start seeing them
2742 * It seems to be the case that the relevant PCI registers to deactivate the
2743 * MMC controller live on PCI function 0, which might be the cardbus controller
2744 * or the firewire controller, depending on the particular chip in question
2746 * This has to be done early, because as soon as we disable the MMC controller
2747 * other pci functions shift up one level, e.g. function #2 becomes function
2748 * #1, and this will confuse the pci core.
2751 #ifdef CONFIG_MMC_RICOH_MMC
2752 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2754 /* disable via cardbus interface */
2759 /* disable must be done via function #0 */
2760 if (PCI_FUNC(dev->devfn))
2763 pci_read_config_byte(dev, 0xB7, &disable);
2767 pci_read_config_byte(dev, 0x8E, &write_enable);
2768 pci_write_config_byte(dev, 0x8E, 0xAA);
2769 pci_read_config_byte(dev, 0x8D, &write_target);
2770 pci_write_config_byte(dev, 0x8D, 0xB7);
2771 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2772 pci_write_config_byte(dev, 0x8E, write_enable);
2773 pci_write_config_byte(dev, 0x8D, write_target);
2775 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2776 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2778 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2779 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2781 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2783 /* disable via firewire interface */
2787 /* disable must be done via function #0 */
2788 if (PCI_FUNC(dev->devfn))
2791 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2792 * certain types of SD/MMC cards. Lowering the SD base
2793 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2795 * 0x150 - SD2.0 mode enable for changing base clock
2796 * frequency to 50Mhz
2797 * 0xe1 - Base clock frequency
2798 * 0x32 - 50Mhz new clock frequency
2799 * 0xf9 - Key register for 0x150
2800 * 0xfc - key register for 0xe1
2802 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2803 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2804 pci_write_config_byte(dev, 0xf9, 0xfc);
2805 pci_write_config_byte(dev, 0x150, 0x10);
2806 pci_write_config_byte(dev, 0xf9, 0x00);
2807 pci_write_config_byte(dev, 0xfc, 0x01);
2808 pci_write_config_byte(dev, 0xe1, 0x32);
2809 pci_write_config_byte(dev, 0xfc, 0x00);
2811 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2814 pci_read_config_byte(dev, 0xCB, &disable);
2819 pci_read_config_byte(dev, 0xCA, &write_enable);
2820 pci_write_config_byte(dev, 0xCA, 0x57);
2821 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2822 pci_write_config_byte(dev, 0xCA, write_enable);
2824 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2825 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2828 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2829 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2830 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2831 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2832 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2833 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2834 #endif /*CONFIG_MMC_RICOH_MMC*/
2836 #ifdef CONFIG_DMAR_TABLE
2837 #define VTUNCERRMSK_REG 0x1ac
2838 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2840 * This is a quirk for masking vt-d spec defined errors to platform error
2841 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2842 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2843 * on the RAS config settings of the platform) when a vt-d fault happens.
2844 * The resulting SMI caused the system to hang.
2846 * VT-d spec related errors are already handled by the VT-d OS code, so no
2847 * need to report the same error through other channels.
2849 static void vtd_mask_spec_errors(struct pci_dev *dev)
2853 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2854 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2856 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2857 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2860 static void fixup_ti816x_class(struct pci_dev *dev)
2862 u32 class = dev->class;
2864 /* TI 816x devices do not have class code set when in PCIe boot mode */
2865 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2866 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2869 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2870 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
2872 /* Some PCIe devices do not work reliably with the claimed maximum
2873 * payload size supported.
2875 static void fixup_mpss_256(struct pci_dev *dev)
2877 dev->pcie_mpss = 1; /* 256 bytes */
2879 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2880 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2882 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2884 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2886 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2887 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2888 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2889 * until all of the devices are discovered and buses walked, read completion
2890 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2891 * it is possible to hotplug a device with MPS of 256B.
2893 static void quirk_intel_mc_errata(struct pci_dev *dev)
2898 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2901 /* Intel errata specifies bits to change but does not say what they are.
2902 * Keeping them magical until such time as the registers and values can
2905 err = pci_read_config_word(dev, 0x48, &rcc);
2907 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
2911 if (!(rcc & (1 << 10)))
2916 err = pci_write_config_word(dev, 0x48, rcc);
2918 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
2922 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
2924 /* Intel 5000 series memory controllers and ports 2-7 */
2925 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2926 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2927 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2928 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2929 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2930 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2931 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2932 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2938 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2939 /* Intel 5100 series memory controllers and ports 2-7 */
2940 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2941 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2942 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2943 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2944 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2945 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2947 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2948 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2949 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2950 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2954 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
2955 * work around this, query the size it should be configured to by the device and
2956 * modify the resource end to correspond to this new size.
2958 static void quirk_intel_ntb(struct pci_dev *dev)
2963 rc = pci_read_config_byte(dev, 0x00D0, &val);
2967 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
2969 rc = pci_read_config_byte(dev, 0x00D1, &val);
2973 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
2975 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
2976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
2978 static ktime_t fixup_debug_start(struct pci_dev *dev,
2979 void (*fn)(struct pci_dev *dev))
2981 ktime_t calltime = ktime_set(0, 0);
2983 dev_dbg(&dev->dev, "calling %pF\n", fn);
2984 if (initcall_debug) {
2985 pr_debug("calling %pF @ %i for %s\n",
2986 fn, task_pid_nr(current), dev_name(&dev->dev));
2987 calltime = ktime_get();
2993 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2994 void (*fn)(struct pci_dev *dev))
2996 ktime_t delta, rettime;
2997 unsigned long long duration;
2999 if (initcall_debug) {
3000 rettime = ktime_get();
3001 delta = ktime_sub(rettime, calltime);
3002 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3003 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3004 fn, duration, dev_name(&dev->dev));
3009 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3010 * even though no one is handling them (f.e. i915 driver is never loaded).
3011 * Additionally the interrupt destination is not set up properly
3012 * and the interrupt ends up -somewhere-.
3014 * These spurious interrupts are "sticky" and the kernel disables
3015 * the (shared) interrupt line after 100.000+ generated interrupts.
3017 * Fix it by disabling the still enabled interrupts.
3018 * This resolves crashes often seen on monitor unplug.
3020 #define I915_DEIER_REG 0x4400c
3021 static void disable_igfx_irq(struct pci_dev *dev)
3023 void __iomem *regs = pci_iomap(dev, 0, 0);
3025 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3029 /* Check if any interrupt line is still enabled */
3030 if (readl(regs + I915_DEIER_REG) != 0) {
3031 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3033 writel(0, regs + I915_DEIER_REG);
3036 pci_iounmap(dev, regs);
3038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3043 * PCI devices which are on Intel chips can skip the 10ms delay
3044 * before entering D3 mode.
3046 static void quirk_remove_d3_delay(struct pci_dev *dev)
3050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3051 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3057 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3066 * Some devices may pass our check in pci_intx_mask_supported if
3067 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3068 * support this feature.
3070 static void quirk_broken_intx_masking(struct pci_dev *dev)
3072 dev->broken_intx_masking = 1;
3074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
3075 quirk_broken_intx_masking);
3076 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3077 quirk_broken_intx_masking);
3079 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3080 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3082 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169,
3085 quirk_broken_intx_masking);
3086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3087 quirk_broken_intx_masking);
3089 static void quirk_no_bus_reset(struct pci_dev *dev)
3091 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3095 * Atheros AR93xx chips do not behave after a bus reset. The device will
3096 * throw a Link Down error on AER-capable systems and regardless of AER,
3097 * config space of the device is never accessible again and typically
3098 * causes the system to hang or reset when access is attempted.
3099 * http://www.spinics.net/lists/linux-pci/msg34797.html
3101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3103 static void quirk_no_pm_reset(struct pci_dev *dev)
3106 * We can't do a bus reset on root bus devices, but an ineffective
3107 * PM reset may be better than nothing.
3109 if (!pci_is_root_bus(dev->bus))
3110 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3114 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3115 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3116 * to have no effect on the device: it retains the framebuffer contents and
3117 * monitor sync. Advertising this support makes other layers, like VFIO,
3118 * assume pci_reset_function() is viable for this device. Mark it as
3119 * unavailable to skip it when testing reset methods.
3121 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3122 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3126 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3128 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3129 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3130 * be present after resume if a device was plugged in before suspend.
3132 * The thunderbolt controller consists of a pcie switch with downstream
3133 * bridges leading to the NHI and to the tunnel pci bridges.
3135 * This quirk cuts power to the whole chip. Therefore we have to apply it
3136 * during suspend_noirq of the upstream bridge.
3138 * Power is automagically restored before resume. No action is needed.
3140 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3142 acpi_handle bridge, SXIO, SXFP, SXLV;
3144 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3146 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3148 bridge = ACPI_HANDLE(&dev->dev);
3152 * SXIO and SXLV are present only on machines requiring this quirk.
3153 * TB bridges in external devices might have the same device id as those
3154 * on the host, but they will not have the associated ACPI methods. This
3155 * implicitly checks that we are at the right bridge.
3157 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3158 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3159 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3161 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3163 /* magic sequence */
3164 acpi_execute_simple_method(SXIO, NULL, 1);
3165 acpi_execute_simple_method(SXFP, NULL, 0);
3167 acpi_execute_simple_method(SXLV, NULL, 0);
3168 acpi_execute_simple_method(SXIO, NULL, 0);
3169 acpi_execute_simple_method(SXLV, NULL, 0);
3171 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 0x1547,
3172 quirk_apple_poweroff_thunderbolt);
3175 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3177 * During suspend the thunderbolt controller is reset and all pci
3178 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3179 * during resume. We have to manually wait for the NHI since there is
3180 * no parent child relationship between the NHI and the tunneled
3183 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3185 struct pci_dev *sibling = NULL;
3186 struct pci_dev *nhi = NULL;
3188 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3190 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3193 * Find the NHI and confirm that we are a bridge on the tb host
3194 * controller and not on a tb endpoint.
3196 sibling = pci_get_slot(dev->bus, 0x0);
3198 goto out; /* we are the downstream bridge to the NHI */
3199 if (!sibling || !sibling->subordinate)
3201 nhi = pci_get_slot(sibling->subordinate, 0x0);
3204 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3205 || (nhi->device != 0x1547 && nhi->device != 0x156c)
3206 || nhi->subsystem_vendor != 0x2222
3207 || nhi->subsystem_device != 0x1111)
3209 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3210 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3213 pci_dev_put(sibling);
3215 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x1547,
3216 quirk_apple_wait_for_thunderbolt);
3217 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x156d,
3218 quirk_apple_wait_for_thunderbolt);
3221 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3222 struct pci_fixup *end)
3226 for (; f < end; f++)
3227 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3228 f->class == (u32) PCI_ANY_ID) &&
3229 (f->vendor == dev->vendor ||
3230 f->vendor == (u16) PCI_ANY_ID) &&
3231 (f->device == dev->device ||
3232 f->device == (u16) PCI_ANY_ID)) {
3233 calltime = fixup_debug_start(dev, f->hook);
3235 fixup_debug_report(dev, calltime, f->hook);
3239 extern struct pci_fixup __start_pci_fixups_early[];
3240 extern struct pci_fixup __end_pci_fixups_early[];
3241 extern struct pci_fixup __start_pci_fixups_header[];
3242 extern struct pci_fixup __end_pci_fixups_header[];
3243 extern struct pci_fixup __start_pci_fixups_final[];
3244 extern struct pci_fixup __end_pci_fixups_final[];
3245 extern struct pci_fixup __start_pci_fixups_enable[];
3246 extern struct pci_fixup __end_pci_fixups_enable[];
3247 extern struct pci_fixup __start_pci_fixups_resume[];
3248 extern struct pci_fixup __end_pci_fixups_resume[];
3249 extern struct pci_fixup __start_pci_fixups_resume_early[];
3250 extern struct pci_fixup __end_pci_fixups_resume_early[];
3251 extern struct pci_fixup __start_pci_fixups_suspend[];
3252 extern struct pci_fixup __end_pci_fixups_suspend[];
3253 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3254 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3256 static bool pci_apply_fixup_final_quirks;
3258 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3260 struct pci_fixup *start, *end;
3263 case pci_fixup_early:
3264 start = __start_pci_fixups_early;
3265 end = __end_pci_fixups_early;
3268 case pci_fixup_header:
3269 start = __start_pci_fixups_header;
3270 end = __end_pci_fixups_header;
3273 case pci_fixup_final:
3274 if (!pci_apply_fixup_final_quirks)
3276 start = __start_pci_fixups_final;
3277 end = __end_pci_fixups_final;
3280 case pci_fixup_enable:
3281 start = __start_pci_fixups_enable;
3282 end = __end_pci_fixups_enable;
3285 case pci_fixup_resume:
3286 start = __start_pci_fixups_resume;
3287 end = __end_pci_fixups_resume;
3290 case pci_fixup_resume_early:
3291 start = __start_pci_fixups_resume_early;
3292 end = __end_pci_fixups_resume_early;
3295 case pci_fixup_suspend:
3296 start = __start_pci_fixups_suspend;
3297 end = __end_pci_fixups_suspend;
3300 case pci_fixup_suspend_late:
3301 start = __start_pci_fixups_suspend_late;
3302 end = __end_pci_fixups_suspend_late;
3306 /* stupid compiler warning, you would think with an enum... */
3309 pci_do_fixups(dev, start, end);
3311 EXPORT_SYMBOL(pci_fixup_device);
3314 static int __init pci_apply_final_quirks(void)
3316 struct pci_dev *dev = NULL;
3320 if (pci_cache_line_size)
3321 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3322 pci_cache_line_size << 2);
3324 pci_apply_fixup_final_quirks = true;
3325 for_each_pci_dev(dev) {
3326 pci_fixup_device(pci_fixup_final, dev);
3328 * If arch hasn't set it explicitly yet, use the CLS
3329 * value shared by all PCI devices. If there's a
3330 * mismatch, fall back to the default value.
3332 if (!pci_cache_line_size) {
3333 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3336 if (!tmp || cls == tmp)
3339 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3341 pci_dfl_cache_line_size << 2);
3342 pci_cache_line_size = pci_dfl_cache_line_size;
3346 if (!pci_cache_line_size) {
3347 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3348 cls << 2, pci_dfl_cache_line_size << 2);
3349 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3355 fs_initcall_sync(pci_apply_final_quirks);
3358 * Followings are device-specific reset methods which can be used to
3359 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3362 static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3366 /* only implement PCI_CLASS_SERIAL_USB at present */
3367 if (dev->class == PCI_CLASS_SERIAL_USB) {
3368 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3375 pci_write_config_byte(dev, pos + 0x4, 1);
3384 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3387 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3389 * The 82599 supports FLR on VFs, but FLR support is reported only
3390 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3391 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3397 if (!pci_wait_for_pending_transaction(dev))
3398 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3400 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3407 #include "../gpu/drm/i915/i915_reg.h"
3408 #define MSG_CTL 0x45010
3409 #define NSDE_PWR_STATE 0xd0100
3410 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3412 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3414 void __iomem *mmio_base;
3415 unsigned long timeout;
3421 mmio_base = pci_iomap(dev, 0, 0);
3425 iowrite32(0x00000002, mmio_base + MSG_CTL);
3428 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3429 * driver loaded sets the right bits. However, this's a reset and
3430 * the bits have been set by i915 previously, so we clobber
3431 * SOUTH_CHICKEN2 register directly here.
3433 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3435 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3436 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3438 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3440 val = ioread32(mmio_base + PCH_PP_STATUS);
3441 if ((val & 0xb0000000) == 0)
3442 goto reset_complete;
3444 } while (time_before(jiffies, timeout));
3445 dev_warn(&dev->dev, "timeout during reset\n");
3448 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3450 pci_iounmap(dev, mmio_base);
3455 * Device-specific reset method for Chelsio T4-based adapters.
3457 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3463 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3464 * that we have no device-specific reset method.
3466 if ((dev->device & 0xf000) != 0x4000)
3470 * If this is the "probe" phase, return 0 indicating that we can
3471 * reset this device.
3477 * T4 can wedge if there are DMAs in flight within the chip and Bus
3478 * Master has been disabled. We need to have it on till the Function
3479 * Level Reset completes. (BUS_MASTER is disabled in
3480 * pci_reset_function()).
3482 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3483 pci_write_config_word(dev, PCI_COMMAND,
3484 old_command | PCI_COMMAND_MASTER);
3487 * Perform the actual device function reset, saving and restoring
3488 * configuration information around the reset.
3490 pci_save_state(dev);
3493 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3494 * are disabled when an MSI-X interrupt message needs to be delivered.
3495 * So we briefly re-enable MSI-X interrupts for the duration of the
3496 * FLR. The pci_restore_state() below will restore the original
3499 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3500 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3501 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3503 PCI_MSIX_FLAGS_ENABLE |
3504 PCI_MSIX_FLAGS_MASKALL);
3507 * Start of pcie_flr() code sequence. This reset code is a copy of
3508 * the guts of pcie_flr() because that's not an exported function.
3511 if (!pci_wait_for_pending_transaction(dev))
3512 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3514 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3518 * End of pcie_flr() code sequence.
3522 * Restore the configuration information (BAR values, etc.) including
3523 * the original PCI Configuration Space Command word, and return
3526 pci_restore_state(dev);
3527 pci_write_config_word(dev, PCI_COMMAND, old_command);
3531 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3532 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3533 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3535 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3536 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3537 reset_intel_82599_sfp_virtfn },
3538 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3540 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3542 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3543 reset_intel_generic_dev },
3544 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3545 reset_chelsio_generic_dev },
3550 * These device-specific reset methods are here rather than in a driver
3551 * because when a host assigns a device to a guest VM, the host may need
3552 * to reset the device but probably doesn't have a driver for it.
3554 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3556 const struct pci_dev_reset_methods *i;
3558 for (i = pci_dev_reset_methods; i->reset; i++) {
3559 if ((i->vendor == dev->vendor ||
3560 i->vendor == (u16)PCI_ANY_ID) &&
3561 (i->device == dev->device ||
3562 i->device == (u16)PCI_ANY_ID))
3563 return i->reset(dev, probe);
3569 static void quirk_dma_func0_alias(struct pci_dev *dev)
3571 if (PCI_FUNC(dev->devfn) != 0) {
3572 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
3573 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3578 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3580 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3582 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3585 static void quirk_dma_func1_alias(struct pci_dev *dev)
3587 if (PCI_FUNC(dev->devfn) != 1) {
3588 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1);
3589 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3594 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3595 * SKUs function 1 is present and is a legacy IDE controller, in other
3596 * SKUs this function is not present, making this a ghost requester.
3597 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3600 quirk_dma_func1_alias);
3601 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3603 quirk_dma_func1_alias);
3604 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3605 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3606 quirk_dma_func1_alias);
3607 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3608 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3609 quirk_dma_func1_alias);
3610 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3612 quirk_dma_func1_alias);
3613 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3615 quirk_dma_func1_alias);
3616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3617 quirk_dma_func1_alias);
3618 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3620 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3621 quirk_dma_func1_alias);
3624 * Some devices DMA with the wrong devfn, not just the wrong function.
3625 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3626 * the alias is "fixed" and independent of the device devfn.
3628 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3629 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3630 * single device on the secondary bus. In reality, the single exposed
3631 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3632 * that provides a bridge to the internal bus of the I/O processor. The
3633 * controller supports private devices, which can be hidden from PCI config
3634 * space. In the case of the Adaptec 3405, a private device at 01.0
3635 * appears to be the DMA engine, which therefore needs to become a DMA
3636 * alias for the device.
3638 static const struct pci_device_id fixed_dma_alias_tbl[] = {
3639 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3640 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3641 .driver_data = PCI_DEVFN(1, 0) },
3645 static void quirk_fixed_dma_alias(struct pci_dev *dev)
3647 const struct pci_device_id *id;
3649 id = pci_match_id(fixed_dma_alias_tbl, dev);
3651 dev->dma_alias_devfn = id->driver_data;
3652 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3653 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
3654 PCI_SLOT(dev->dma_alias_devfn),
3655 PCI_FUNC(dev->dma_alias_devfn));
3659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3662 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3663 * using the wrong DMA alias for the device. Some of these devices can be
3664 * used as either forward or reverse bridges, so we need to test whether the
3665 * device is operating in the correct mode. We could probably apply this
3666 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3667 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3668 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3670 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3672 if (!pci_is_root_bus(pdev->bus) &&
3673 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3674 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3675 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3676 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3678 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3679 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3680 quirk_use_pcie_bridge_dma_alias);
3681 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3682 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3683 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3684 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3685 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3686 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3689 * AMD has indicated that the devices below do not support peer-to-peer
3690 * in any system where they are found in the southbridge with an AMD
3691 * IOMMU in the system. Multifunction devices that do not support
3692 * peer-to-peer between functions can claim to support a subset of ACS.
3693 * Such devices effectively enable request redirect (RR) and completion
3694 * redirect (CR) since all transactions are redirected to the upstream
3697 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3698 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3699 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3701 * 1002:4385 SBx00 SMBus Controller
3702 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3703 * 1002:4383 SBx00 Azalia (Intel HDA)
3704 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3705 * 1002:4384 SBx00 PCI to PCI Bridge
3706 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
3708 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
3710 * 1022:780f [AMD] FCH PCI Bridge
3711 * 1022:7809 [AMD] FCH USB OHCI Controller
3713 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3716 struct acpi_table_header *header = NULL;
3719 /* Targeting multifunction devices on the SB (appears on root bus) */
3720 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3723 /* The IVRS table describes the AMD IOMMU */
3724 status = acpi_get_table("IVRS", 0, &header);
3725 if (ACPI_FAILURE(status))
3728 /* Filter out flags not applicable to multifunction */
3729 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3731 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3738 * Many Intel PCH root ports do provide ACS-like features to disable peer
3739 * transactions and validate bus numbers in requests, but do not provide an
3740 * actual PCIe ACS capability. This is the list of device IDs known to fall
3741 * into that category as provided by Intel in Red Hat bugzilla 1037684.
3743 static const u16 pci_quirk_intel_pch_acs_ids[] = {
3745 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
3746 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
3747 /* Cougarpoint PCH */
3748 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
3749 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
3750 /* Pantherpoint PCH */
3751 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
3752 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
3753 /* Lynxpoint-H PCH */
3754 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
3755 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
3756 /* Lynxpoint-LP PCH */
3757 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
3758 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
3760 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
3761 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
3762 /* Patsburg (X79) PCH */
3763 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
3764 /* Wellsburg (X99) PCH */
3765 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
3766 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
3769 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
3773 /* Filter out a few obvious non-matches first */
3774 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
3777 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
3778 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
3784 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
3786 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
3788 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
3789 INTEL_PCH_ACS_FLAGS : 0;
3791 if (!pci_quirk_intel_pch_acs_match(dev))
3794 return acs_flags & ~flags ? 0 : 1;
3797 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
3800 * SV, TB, and UF are not relevant to multifunction endpoints.
3802 * Multifunction devices are only required to implement RR, CR, and DT
3803 * in their ACS capability if they support peer-to-peer transactions.
3804 * Devices matching this quirk have been verified by the vendor to not
3805 * perform peer-to-peer with other functions, allowing us to mask out
3806 * these bits as if they were unimplemented in the ACS capability.
3808 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
3809 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
3811 return acs_flags ? 0 : 1;
3814 static const struct pci_dev_acs_enabled {
3817 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3818 } pci_dev_acs_enabled[] = {
3819 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
3820 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
3821 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
3822 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3823 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3824 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
3825 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
3826 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
3827 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
3828 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
3829 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
3830 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
3831 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
3832 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
3833 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
3834 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
3835 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
3836 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
3837 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
3838 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
3839 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
3840 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
3841 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
3842 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
3843 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
3844 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
3845 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
3846 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
3847 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
3848 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
3850 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
3851 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
3852 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
3853 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
3854 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
3855 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
3856 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
3858 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
3859 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
3860 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
3861 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
3862 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
3863 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
3864 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
3865 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
3867 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
3868 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
3869 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
3871 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
3872 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
3873 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
3874 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
3875 /* 82571 (Quads omitted due to non-ACS switch) */
3876 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
3877 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
3878 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
3879 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
3880 /* Intel PCH root ports */
3881 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
3882 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
3883 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
3887 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3889 const struct pci_dev_acs_enabled *i;
3893 * Allow devices that do not expose standard PCIe ACS capabilities
3894 * or control to indicate their support here. Multi-function express
3895 * devices which do not allow internal peer-to-peer between functions,
3896 * but do not implement PCIe ACS may wish to return true here.
3898 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3899 if ((i->vendor == dev->vendor ||
3900 i->vendor == (u16)PCI_ANY_ID) &&
3901 (i->device == dev->device ||
3902 i->device == (u16)PCI_ANY_ID)) {
3903 ret = i->acs_enabled(dev, acs_flags);
3912 /* Config space offset of Root Complex Base Address register */
3913 #define INTEL_LPC_RCBA_REG 0xf0
3914 /* 31:14 RCBA address */
3915 #define INTEL_LPC_RCBA_MASK 0xffffc000
3917 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
3919 /* Backbone Scratch Pad Register */
3920 #define INTEL_BSPR_REG 0x1104
3921 /* Backbone Peer Non-Posted Disable */
3922 #define INTEL_BSPR_REG_BPNPD (1 << 8)
3923 /* Backbone Peer Posted Disable */
3924 #define INTEL_BSPR_REG_BPPD (1 << 9)
3926 /* Upstream Peer Decode Configuration Register */
3927 #define INTEL_UPDCR_REG 0x1114
3928 /* 5:0 Peer Decode Enable bits */
3929 #define INTEL_UPDCR_REG_MASK 0x3f
3931 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
3933 u32 rcba, bspr, updcr;
3934 void __iomem *rcba_mem;
3937 * Read the RCBA register from the LPC (D31:F0). PCH root ports
3938 * are D28:F* and therefore get probed before LPC, thus we can't
3939 * use pci_get_slot/pci_read_config_dword here.
3941 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
3942 INTEL_LPC_RCBA_REG, &rcba);
3943 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
3946 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
3947 PAGE_ALIGN(INTEL_UPDCR_REG));
3952 * The BSPR can disallow peer cycles, but it's set by soft strap and
3953 * therefore read-only. If both posted and non-posted peer cycles are
3954 * disallowed, we're ok. If either are allowed, then we need to use
3955 * the UPDCR to disable peer decodes for each port. This provides the
3956 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
3958 bspr = readl(rcba_mem + INTEL_BSPR_REG);
3959 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
3960 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
3961 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
3962 if (updcr & INTEL_UPDCR_REG_MASK) {
3963 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
3964 updcr &= ~INTEL_UPDCR_REG_MASK;
3965 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
3973 /* Miscellaneous Port Configuration register */
3974 #define INTEL_MPC_REG 0xd8
3975 /* MPC: Invalid Receive Bus Number Check Enable */
3976 #define INTEL_MPC_REG_IRBNCE (1 << 26)
3978 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
3983 * When enabled, the IRBNCE bit of the MPC register enables the
3984 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
3985 * ensures that requester IDs fall within the bus number range
3986 * of the bridge. Enable if not already.
3988 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
3989 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
3990 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
3991 mpc |= INTEL_MPC_REG_IRBNCE;
3992 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
3996 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
3998 if (!pci_quirk_intel_pch_acs_match(dev))
4001 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4002 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4006 pci_quirk_enable_intel_rp_mpc_acs(dev);
4008 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4010 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4015 static const struct pci_dev_enable_acs {
4018 int (*enable_acs)(struct pci_dev *dev);
4019 } pci_dev_enable_acs[] = {
4020 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4024 void pci_dev_specific_enable_acs(struct pci_dev *dev)
4026 const struct pci_dev_enable_acs *i;
4029 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4030 if ((i->vendor == dev->vendor ||
4031 i->vendor == (u16)PCI_ANY_ID) &&
4032 (i->device == dev->device ||
4033 i->device == (u16)PCI_ANY_ID)) {
4034 ret = i->enable_acs(dev);