kernel/drivers/net/wireless/rtlwifi/rtl8723be/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "../rtl8723com/phy_common.h"
  37 #include "dm.h"
  38 #include "../rtl8723com/dm_common.h"
  39 #include "fw.h"
  40 #include "../rtl8723com/fw_common.h"
  41 #include "led.h"
  42 #include "hw.h"
  43 #include "../pwrseqcmd.h"
  44 #include "pwrseq.h"
  45 #include "../btcoexist/rtl_btc.h"
  46
  47 #define LLT_CONFIG      5
  48
  49 static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
  50 {
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  53         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  54         unsigned long flags;
  55
  56         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  57         while (skb_queue_len(&ring->queue)) {
  58                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  59                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  60
  61                 pci_unmap_single(rtlpci->pdev,
  62                                  rtlpriv->cfg->ops->get_desc(
  63                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
  64                                  skb->len, PCI_DMA_TODEVICE);
  65                 kfree_skb(skb);
  66                 ring->idx = (ring->idx + 1) % ring->entries;
  67         }
  68         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  69 }
  70
  71 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  72                                         u8 set_bits, u8 clear_bits)
  73 {
  74         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  75         struct rtl_priv *rtlpriv = rtl_priv(hw);
  76
  77         rtlpci->reg_bcn_ctrl_val |= set_bits;
  78         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  79
  80         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  81 }
  82
  83 static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw)
  84 {
  85         struct rtl_priv *rtlpriv = rtl_priv(hw);
  86         u8 tmp1byte;
  87
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  89         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  91         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  92         tmp1byte &= ~(BIT(0));
  93         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  94 }
  95
  96 static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw)
  97 {
  98         struct rtl_priv *rtlpriv = rtl_priv(hw);
  99         u8 tmp1byte;
 100
 101         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 102         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 103         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 104         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 105         tmp1byte |= BIT(1);
 106         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 107 }
 108
 109 static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw)
 110 {
 111         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1));
 112 }
 113
 114 static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw)
 115 {
 116         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0);
 117 }
 118
 119 static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
 120                                        bool b_need_turn_off_ckk)
 121 {
 122         struct rtl_priv *rtlpriv = rtl_priv(hw);
 123         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 124         bool b_support_remote_wake_up;
 125         u32 count = 0, isr_regaddr, content;
 126         bool b_schedule_timer = b_need_turn_off_ckk;
 127         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 128                                       (u8 *)(&b_support_remote_wake_up));
 129
 130         if (!rtlhal->fw_ready)
 131                 return;
 132         if (!rtlpriv->psc.fw_current_inpsmode)
 133                 return;
 134
 135         while (1) {
 136                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 137                 if (rtlhal->fw_clk_change_in_progress) {
 138                         while (rtlhal->fw_clk_change_in_progress) {
 139                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 140                                 count++;
 141                                 udelay(100);
 142                                 if (count > 1000)
 143                                         return;
 144                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 145                         }
 146                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 147                 } else {
 148                         rtlhal->fw_clk_change_in_progress = false;
 149                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 150                         break;
 151                 }
 152         }
 153
 154         if (IS_IN_LOW_POWER_STATE(rtlhal->fw_ps_state)) {
 155                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 156                                               (u8 *)(&rpwm_val));
 157                 if (FW_PS_IS_ACK(rpwm_val)) {
 158                         isr_regaddr = REG_HISR;
 159                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 160                         while (!(content & IMR_CPWM) && (count < 500)) {
 161                                 udelay(50);
 162                                 count++;
 163                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 164                         }
 165
 166                         if (content & IMR_CPWM) {
 167                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 168                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON;
 169                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 170                                          "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
 171                                          rtlhal->fw_ps_state);
 172                         }
 173                 }
 174
 175                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 176                 rtlhal->fw_clk_change_in_progress = false;
 177                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 178                 if (b_schedule_timer)
 179                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 180                                   jiffies + MSECS(10));
 181         } else  {
 182                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 183                 rtlhal->fw_clk_change_in_progress = false;
 184                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 185         }
 186 }
 187
 188 static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
 189 {
 190         struct rtl_priv *rtlpriv = rtl_priv(hw);
 191         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 192         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 193         struct rtl8192_tx_ring *ring;
 194         enum rf_pwrstate rtstate;
 195         bool b_schedule_timer = false;
 196         u8 queue;
 197
 198         if (!rtlhal->fw_ready)
 199                 return;
 200         if (!rtlpriv->psc.fw_current_inpsmode)
 201                 return;
 202         if (!rtlhal->allow_sw_to_change_hwclc)
 203                 return;
 204         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 205         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 206                 return;
 207
 208         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 209                 ring = &rtlpci->tx_ring[queue];
 210                 if (skb_queue_len(&ring->queue)) {
 211                         b_schedule_timer = true;
 212                         break;
 213                 }
 214         }
 215
 216         if (b_schedule_timer) {
 217                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 218                           jiffies + MSECS(10));
 219                 return;
 220         }
 221
 222         if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
 223                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 224                 if (!rtlhal->fw_clk_change_in_progress) {
 225                         rtlhal->fw_clk_change_in_progress = true;
 226                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 227                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 228                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 229                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 230                                                       (u8 *)(&rpwm_val));
 231                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 232                         rtlhal->fw_clk_change_in_progress = false;
 233                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 234                 } else {
 235                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 236                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 237                                   jiffies + MSECS(10));
 238                 }
 239         }
 240
 241 }
 242
 243 static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 244 {
 245         u8 rpwm_val = 0;
 246         rpwm_val |= (FW_PS_STATE_RF_OFF | FW_PS_ACK);
 247         _rtl8723be_set_fw_clock_on(hw, rpwm_val, true);
 248 }
 249
 250 static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw)
 251 {
 252         struct rtl_priv *rtlpriv = rtl_priv(hw);
 253         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 254         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 255         bool fw_current_inps = false;
 256         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 257
 258         if (ppsc->low_power_enable) {
 259                 rpwm_val = (FW_PS_STATE_ALL_ON | FW_PS_ACK);/* RF on */
 260                 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false);
 261                 rtlhal->allow_sw_to_change_hwclc = false;
 262                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 263                                               (u8 *)(&fw_pwrmode));
 264                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 265                                               (u8 *)(&fw_current_inps));
 266         } else {
 267                 rpwm_val = FW_PS_STATE_ALL_ON;  /* RF on */
 268                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 269                                               (u8 *)(&rpwm_val));
 270                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 271                                               (u8 *)(&fw_pwrmode));
 272                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 273                                               (u8 *)(&fw_current_inps));
 274         }
 275
 276 }
 277
 278 static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
 279 {
 280         struct rtl_priv *rtlpriv = rtl_priv(hw);
 281         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 282         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 283         bool fw_current_inps = true;
 284         u8 rpwm_val;
 285
 286         if (ppsc->low_power_enable) {
 287                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR;  /* RF off */
 288                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 289                                               (u8 *)(&fw_current_inps));
 290                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 291                                               (u8 *)(&ppsc->fwctrl_psmode));
 292                 rtlhal->allow_sw_to_change_hwclc = true;
 293                 _rtl8723be_set_fw_clock_off(hw, rpwm_val);
 294         } else {
 295                 rpwm_val = FW_PS_STATE_RF_OFF;  /* RF off */
 296                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 297                                               (u8 *)(&fw_current_inps));
 298                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 299                                               (u8 *)(&ppsc->fwctrl_psmode));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 301                                               (u8 *)(&rpwm_val));
 302         }
 303
 304 }
 305
 306 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 307 {
 308         struct rtl_priv *rtlpriv = rtl_priv(hw);
 309         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 310         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 311
 312         switch (variable) {
 313         case HW_VAR_RCR:
 314                 *((u32 *)(val)) = rtlpci->receive_config;
 315                 break;
 316         case HW_VAR_RF_STATE:
 317                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 318                 break;
 319         case HW_VAR_FWLPS_RF_ON:{
 320                 enum rf_pwrstate rfState;
 321                 u32 val_rcr;
 322
 323                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 324                                               (u8 *)(&rfState));
 325                 if (rfState == ERFOFF) {
 326                         *((bool *)(val)) = true;
 327                 } else {
 328                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 329                         val_rcr &= 0x00070000;
 330                         if (val_rcr)
 331                                 *((bool *)(val)) = false;
 332                         else
 333                                 *((bool *)(val)) = true;
 334                 }
 335                 }
 336                 break;
 337         case HW_VAR_FW_PSMODE_STATUS:
 338                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 339                 break;
 340         case HW_VAR_CORRECT_TSF:{
 341                 u64 tsf;
 342                 u32 *ptsf_low = (u32 *)&tsf;
 343                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 344
 345                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 346                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 347
 348                 *((u64 *)(val)) = tsf;
 349                 }
 350                 break;
 351         default:
 352                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 353                          "switch case not process %x\n", variable);
 354                 break;
 355         }
 356 }
 357
 358 static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw)
 359 {
 360         struct rtl_priv *rtlpriv = rtl_priv(hw);
 361         u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 362         u8 count = 0, dlbcn_count = 0;
 363         bool b_recover = false;
 364
 365         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 366         rtl_write_byte(rtlpriv, REG_CR + 1,
 367                        (tmp_regcr | BIT(0)));
 368
 369         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
 370         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
 371
 372         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 373         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
 374         if (tmp_reg422 & BIT(6))
 375                 b_recover = true;
 376
 377         do {
 378                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 379                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 380                                (bcnvalid_reg | BIT(0)));
 381                 _rtl8723be_return_beacon_queue_skb(hw);
 382
 383                 rtl8723be_set_fw_rsvdpagepkt(hw, 0);
 384                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 385                 count = 0;
 386                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 387                         count++;
 388                         udelay(10);
 389                         bcnvalid_reg = rtl_read_byte(rtlpriv,
 390                                                      REG_TDECTRL + 2);
 391                 }
 392                 dlbcn_count++;
 393         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 394
 395         if (bcnvalid_reg & BIT(0))
 396                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
 397
 398         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
 399         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
 400
 401         if (b_recover)
 402                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 403
 404         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 405         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
 406 }
 407
 408 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 409 {
 410         struct rtl_priv *rtlpriv = rtl_priv(hw);
 411         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 412         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 413         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 414         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 415         u8 idx;
 416
 417         switch (variable) {
 418         case HW_VAR_ETHER_ADDR:
 419                 for (idx = 0; idx < ETH_ALEN; idx++)
 420                         rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
 421                 break;
 422         case HW_VAR_BASIC_RATE:{
 423                 u16 b_rate_cfg = ((u16 *)val)[0];
 424                 u8 rate_index = 0;
 425                 b_rate_cfg = b_rate_cfg & 0x15f;
 426                 b_rate_cfg |= 0x01;
 427                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 428                 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
 429                 while (b_rate_cfg > 0x1) {
 430                         b_rate_cfg = (b_rate_cfg >> 1);
 431                         rate_index++;
 432                 }
 433                 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
 434                 }
 435                 break;
 436         case HW_VAR_BSSID:
 437                 for (idx = 0; idx < ETH_ALEN; idx++)
 438                         rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
 439
 440                 break;
 441         case HW_VAR_SIFS:
 442                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 443                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 444
 445                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 446                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 447
 448                 if (!mac->ht_enable)
 449                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
 450                 else
 451                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 452                                        *((u16 *)val));
 453                 break;
 454         case HW_VAR_SLOT_TIME:{
 455                 u8 e_aci;
 456
 457                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 458                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 459
 460                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 461
 462                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 463                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 464                                                       (u8 *)(&e_aci));
 465                 }
 466                 }
 467                 break;
 468         case HW_VAR_ACK_PREAMBLE:{
 469                 u8 reg_tmp;
 470                 u8 short_preamble = (bool)(*(u8 *)val);
 471                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2);
 472                 if (short_preamble) {
 473                         reg_tmp |= 0x02;
 474                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 475                 } else {
 476                         reg_tmp &= 0xFD;
 477                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 478                 }
 479                 }
 480                 break;
 481         case HW_VAR_WPA_CONFIG:
 482                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 483                 break;
 484         case HW_VAR_AMPDU_MIN_SPACE:{
 485                 u8 min_spacing_to_set;
 486                 u8 sec_min_space;
 487
 488                 min_spacing_to_set = *((u8 *)val);
 489                 if (min_spacing_to_set <= 7) {
 490                         sec_min_space = 0;
 491
 492                         if (min_spacing_to_set < sec_min_space)
 493                                 min_spacing_to_set = sec_min_space;
 494
 495                         mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
 496                                               min_spacing_to_set);
 497
 498                         *val = min_spacing_to_set;
 499
 500                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 501                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 502                                   mac->min_space_cfg);
 503
 504                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 505                                        mac->min_space_cfg);
 506                 }
 507                 }
 508                 break;
 509         case HW_VAR_SHORTGI_DENSITY:{
 510                 u8 density_to_set;
 511
 512                 density_to_set = *((u8 *)val);
 513                 mac->min_space_cfg |= (density_to_set << 3);
 514
 515                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 516                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 517                           mac->min_space_cfg);
 518
 519                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 520                                mac->min_space_cfg);
 521                 }
 522                 break;
 523         case HW_VAR_AMPDU_FACTOR:{
 524                 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
 525                 u8 factor_toset;
 526                 u8 *p_regtoset = NULL;
 527                 u8 index = 0;
 528
 529                 p_regtoset = regtoset_normal;
 530
 531                 factor_toset = *((u8 *)val);
 532                 if (factor_toset <= 3) {
 533                         factor_toset = (1 << (factor_toset + 2));
 534                         if (factor_toset > 0xf)
 535                                 factor_toset = 0xf;
 536
 537                         for (index = 0; index < 4; index++) {
 538                                 if ((p_regtoset[index] & 0xf0) >
 539                                     (factor_toset << 4))
 540                                         p_regtoset[index] =
 541                                                 (p_regtoset[index] & 0x0f) |
 542                                                 (factor_toset << 4);
 543
 544                                 if ((p_regtoset[index] & 0x0f) > factor_toset)
 545                                         p_regtoset[index] =
 546                                                 (p_regtoset[index] & 0xf0) |
 547                                                 (factor_toset);
 548
 549                                 rtl_write_byte(rtlpriv,
 550                                                (REG_AGGLEN_LMT + index),
 551                                                p_regtoset[index]);
 552
 553                         }
 554
 555                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 556                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 557                                   factor_toset);
 558                 }
 559                 }
 560                 break;
 561         case HW_VAR_AC_PARAM:{
 562                 u8 e_aci = *((u8 *)val);
 563                 rtl8723_dm_init_edca_turbo(hw);
 564
 565                 if (rtlpci->acm_method != EACMWAY2_SW)
 566                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 567                                                       (u8 *)(&e_aci));
 568                 }
 569                 break;
 570         case HW_VAR_ACM_CTRL:{
 571                 u8 e_aci = *((u8 *)val);
 572                 union aci_aifsn *p_aci_aifsn =
 573                                 (union aci_aifsn *)(&(mac->ac[0].aifs));
 574                 u8 acm = p_aci_aifsn->f.acm;
 575                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 576
 577                 acm_ctrl =
 578                     acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 579
 580                 if (acm) {
 581                         switch (e_aci) {
 582                         case AC0_BE:
 583                                 acm_ctrl |= ACMHW_BEQEN;
 584                                 break;
 585                         case AC2_VI:
 586                                 acm_ctrl |= ACMHW_VIQEN;
 587                                 break;
 588                         case AC3_VO:
 589                                 acm_ctrl |= ACMHW_VOQEN;
 590                                 break;
 591                         default:
 592                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 593                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 594                                          acm);
 595                                 break;
 596                         }
 597                 } else {
 598                         switch (e_aci) {
 599                         case AC0_BE:
 600                                 acm_ctrl &= (~ACMHW_BEQEN);
 601                                 break;
 602                         case AC2_VI:
 603                                 acm_ctrl &= (~ACMHW_VIQEN);
 604                                 break;
 605                         case AC3_VO:
 606                                 acm_ctrl &= (~ACMHW_VOQEN);
 607                                 break;
 608                         default:
 609                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 610                                          "switch case not process\n");
 611                                 break;
 612                         }
 613                 }
 614
 615                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 616                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 617                          acm_ctrl);
 618                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 619                 }
 620                 break;
 621         case HW_VAR_RCR:
 622                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 623                 rtlpci->receive_config = ((u32 *)(val))[0];
 624                 break;
 625         case HW_VAR_RETRY_LIMIT:{
 626                 u8 retry_limit = ((u8 *)(val))[0];
 627
 628                 rtl_write_word(rtlpriv, REG_RL,
 629                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 630                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 631                 }
 632                 break;
 633         case HW_VAR_DUAL_TSF_RST:
 634                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 635                 break;
 636         case HW_VAR_EFUSE_BYTES:
 637                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 638                 break;
 639         case HW_VAR_EFUSE_USAGE:
 640                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 641                 break;
 642         case HW_VAR_IO_CMD:
 643                 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val));
 644                 break;
 645         case HW_VAR_SET_RPWM:{
 646                 u8 rpwm_val;
 647
 648                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 649                 udelay(1);
 650
 651                 if (rpwm_val & BIT(7)) {
 652                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
 653                 } else {
 654                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 655                                        ((*(u8 *)val) | BIT(7)));
 656                 }
 657                 }
 658                 break;
 659         case HW_VAR_H2C_FW_PWRMODE:
 660                 rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 661                 break;
 662         case HW_VAR_FW_PSMODE_STATUS:
 663                 ppsc->fw_current_inpsmode = *((bool *)val);
 664                 break;
 665         case HW_VAR_RESUME_CLK_ON:
 666                 _rtl8723be_set_fw_ps_rf_on(hw);
 667                 break;
 668         case HW_VAR_FW_LPS_ACTION:{
 669                 bool b_enter_fwlps = *((bool *)val);
 670
 671                 if (b_enter_fwlps)
 672                         _rtl8723be_fwlps_enter(hw);
 673                 else
 674                         _rtl8723be_fwlps_leave(hw);
 675                 }
 676                 break;
 677         case HW_VAR_H2C_FW_JOINBSSRPT:{
 678                 u8 mstatus = (*(u8 *)val);
 679
 680                 if (mstatus == RT_MEDIA_CONNECT) {
 681                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
 682                         _rtl8723be_download_rsvd_page(hw);
 683                 }
 684                 rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus);
 685                 }
 686                 break;
 687         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 688                 rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 689                 break;
 690         case HW_VAR_AID:{
 691                 u16 u2btmp;
 692                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 693                 u2btmp &= 0xC000;
 694                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
 695                                (u2btmp | mac->assoc_id));
 696                 }
 697                 break;
 698         case HW_VAR_CORRECT_TSF:{
 699                 u8 btype_ibss = ((u8 *)(val))[0];
 700
 701                 if (btype_ibss)
 702                         _rtl8723be_stop_tx_beacon(hw);
 703
 704                 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
 705
 706                 rtl_write_dword(rtlpriv, REG_TSFTR,
 707                                 (u32) (mac->tsf & 0xffffffff));
 708                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 709                                 (u32) ((mac->tsf >> 32) & 0xffffffff));
 710
 711                 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
 712
 713                 if (btype_ibss)
 714                         _rtl8723be_resume_tx_beacon(hw);
 715                 }
 716                 break;
 717         case HW_VAR_KEEP_ALIVE:{
 718                 u8 array[2];
 719                 array[0] = 0xff;
 720                 array[1] = *((u8 *)val);
 721                 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array);
 722                 }
 723                 break;
 724         default:
 725                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 726                          "switch case not process %x\n",
 727                          variable);
 728                 break;
 729         }
 730 }
 731
 732 static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 733 {
 734         struct rtl_priv *rtlpriv = rtl_priv(hw);
 735         bool status = true;
 736         long count = 0;
 737         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 738                     _LLT_OP(_LLT_WRITE_ACCESS);
 739
 740         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 741
 742         do {
 743                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 744                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 745                         break;
 746
 747                 if (count > POLLING_LLT_THRESHOLD) {
 748                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 749                                  "Failed to polling write LLT done at address %d!\n",
 750                                  address);
 751                         status = false;
 752                         break;
 753                 }
 754         } while (++count);
 755
 756         return status;
 757 }
 758
 759 static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
 760 {
 761         struct rtl_priv *rtlpriv = rtl_priv(hw);
 762         unsigned short i;
 763         u8 txpktbuf_bndy;
 764         u8 maxPage;
 765         bool status;
 766
 767         maxPage = 255;
 768         txpktbuf_bndy = 245;
 769
 770         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
 771                         (0x27FF0000 | txpktbuf_bndy));
 772         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 773
 774         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 775         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 776
 777         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 778         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 779         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 780
 781         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 782                 status = _rtl8723be_llt_write(hw, i, i + 1);
 783                 if (!status)
 784                         return status;
 785         }
 786
 787         status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 788
 789         if (!status)
 790                 return status;
 791
 792         for (i = txpktbuf_bndy; i < maxPage; i++) {
 793                 status = _rtl8723be_llt_write(hw, i, (i + 1));
 794                 if (!status)
 795                         return status;
 796         }
 797
 798         status = _rtl8723be_llt_write(hw, maxPage, txpktbuf_bndy);
 799         if (!status)
 800                 return status;
 801
 802         rtl_write_dword(rtlpriv, REG_RQPN, 0x80e40808);
 803         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 804
 805         return true;
 806 }
 807
 808 static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw)
 809 {
 810         struct rtl_priv *rtlpriv = rtl_priv(hw);
 811         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 812         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 813         struct rtl_led *pled0 = &(pcipriv->ledctl.sw_led0);
 814
 815         if (rtlpriv->rtlhal.up_first_time)
 816                 return;
 817
 818         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 819                 rtl8723be_sw_led_on(hw, pled0);
 820         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 821                 rtl8723be_sw_led_on(hw, pled0);
 822         else
 823                 rtl8723be_sw_led_off(hw, pled0);
 824 }
 825
 826 static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
 827 {
 828         struct rtl_priv *rtlpriv = rtl_priv(hw);
 829         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 830         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 831         unsigned char bytetmp;
 832         unsigned short wordtmp;
 833
 834         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 835
 836         /*Auto Power Down to CHIP-off State*/
 837         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 838         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 839
 840         /* HW Power on sequence */
 841         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 842                                       PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 843                                       RTL8723_NIC_ENABLE_FLOW)) {
 844                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 845                          "init MAC Fail as power on failure\n");
 846                 return false;
 847         }
 848
 849         bytetmp = rtl_read_byte(rtlpriv, REG_MULTI_FUNC_CTRL);
 850         rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3));
 851
 852         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 853         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 854
 855         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 856         bytetmp = 0xff;
 857         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 858         mdelay(2);
 859
 860         bytetmp = rtl_read_byte(rtlpriv, REG_HWSEQ_CTRL);
 861         bytetmp |= 0x7f;
 862         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 863         mdelay(2);
 864
 865         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 866         if (bytetmp & BIT(0)) {
 867                 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 868                 rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6));
 869         }
 870
 871         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 872         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
 873         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 874         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
 875
 876         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 877
 878         if (!rtlhal->mac_func_enable) {
 879                 if (_rtl8723be_llt_table_init(hw) == false)
 880                         return false;
 881         }
 882
 883         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 884         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 885
 886         /* Enable FW Beamformer Interrupt */
 887         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 888         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 889
 890         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 891         wordtmp &= 0xf;
 892         wordtmp |= 0xF5B1;
 893         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 894
 895         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 896         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 897         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
 898         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 899
 900         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 901                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 902                         DMA_BIT_MASK(32));
 903         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 904                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 905                         DMA_BIT_MASK(32));
 906         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 907                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 908         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 909                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 910         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 911                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 912         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 913                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 914         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 915                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 916                         DMA_BIT_MASK(32));
 917         rtl_write_dword(rtlpriv, REG_RX_DESA,
 918                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 919                         DMA_BIT_MASK(32));
 920
 921         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
 922         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0x77);
 923
 924         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 925
 926         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 927
 928         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
 929
 930         /* <20130114, Kordan> The following setting is
 931          * only for DPDT and Fixed board type.
 932          * TODO:  A better solution is configure it
 933          * according EFUSE during the run-time.
 934          */
 935         rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */
 936         rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */
 937         rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */;
 938         rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */;
 939         rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */;
 940         rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */;
 941         rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */;
 942         rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */;
 943
 944         bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
 945         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2)));
 946
 947         _rtl8723be_gen_refresh_led_state(hw);
 948         return true;
 949 }
 950
 951 static void _rtl8723be_hw_configure(struct ieee80211_hw *hw)
 952 {
 953         struct rtl_priv *rtlpriv = rtl_priv(hw);
 954         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 955         u32 reg_rrsr;
 956
 957         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 958         /* Init value for RRSR. */
 959         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
 960
 961         /* ARFB table 9 for 11ac 5G 2SS */
 962         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
 963
 964         /* ARFB table 10 for 11ac 5G 1SS */
 965         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
 966
 967         /* CF-End setting. */
 968         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
 969
 970         /* 0x456 = 0x70, sugguested by Zhilin */
 971         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
 972
 973         /* Set retry limit */
 974         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 975
 976         /* Set Data / Response auto rate fallack retry count */
 977         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 978         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 979         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 980         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 981
 982         rtlpci->reg_bcn_ctrl_val = 0x1d;
 983         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 984
 985         /* TBTT prohibit hold time. Suggested by designer TimChen. */
 986         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
 987
 988         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
 989
 990         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
 991         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 992
 993         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
 994
 995         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
 996
 997         rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x1F);
 998 }
 999
1000 static u8 _rtl8723be_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1001 {
1002         u16 read_addr = addr & 0xfffc;
1003         u8 ret = 0, tmp = 0, count = 0;
1004
1005         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1006         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1007         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1008         count = 0;
1009         while (tmp && count < 20) {
1010                 udelay(10);
1011                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1012                 count++;
1013         }
1014         if (0 == tmp) {
1015                 read_addr = REG_DBI_RDATA + addr % 4;
1016                 ret = rtl_read_byte(rtlpriv, read_addr);
1017         }
1018
1019         return ret;
1020 }
1021
1022 static void _rtl8723be_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1023 {
1024         u8 tmp = 0, count = 0;
1025         u16 write_addr = 0, remainder = addr % 4;
1026
1027         /* Write DBI 1Byte Data */
1028         write_addr = REG_DBI_WDATA + remainder;
1029         rtl_write_byte(rtlpriv, write_addr, data);
1030
1031         /* Write DBI 2Byte Address & Write Enable */
1032         write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1033         rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1034
1035         /* Write DBI Write Flag */
1036         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1037
1038         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1039         count = 0;
1040         while (tmp && count < 20) {
1041                 udelay(10);
1042                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1043                 count++;
1044         }
1045 }
1046
1047 static u16 _rtl8723be_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1048 {
1049         u16 ret = 0;
1050         u8 tmp = 0, count = 0;
1051
1052         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1053         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1054         count = 0;
1055         while (tmp && count < 20) {
1056                 udelay(10);
1057                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1058                 count++;
1059         }
1060
1061         if (0 == tmp)
1062                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1063
1064         return ret;
1065 }
1066
1067 static void _rtl8723be_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1068 {
1069         u8 tmp = 0, count = 0;
1070
1071         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1072         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1073         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1074         count = 0;
1075         while (tmp && count < 20) {
1076                 udelay(10);
1077                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1078                 count++;
1079         }
1080 }
1081
1082 static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
1083 {
1084         struct rtl_priv *rtlpriv = rtl_priv(hw);
1085         u8 tmp8 = 0;
1086         u16 tmp16 = 0;
1087
1088         /* <Roger_Notes> Overwrite following ePHY parameter for
1089          * some platform compatibility issue,
1090          * especially when CLKReq is enabled, 2012.11.09.
1091          */
1092         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x01);
1093         if (tmp16 != 0x0663)
1094                 _rtl8723be_mdio_write(rtlpriv, 0x01, 0x0663);
1095
1096         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x04);
1097         if (tmp16 != 0x7544)
1098                 _rtl8723be_mdio_write(rtlpriv, 0x04, 0x7544);
1099
1100         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x06);
1101         if (tmp16 != 0xB880)
1102                 _rtl8723be_mdio_write(rtlpriv, 0x06, 0xB880);
1103
1104         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x07);
1105         if (tmp16 != 0x4000)
1106                 _rtl8723be_mdio_write(rtlpriv, 0x07, 0x4000);
1107
1108         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x08);
1109         if (tmp16 != 0x9003)
1110                 _rtl8723be_mdio_write(rtlpriv, 0x08, 0x9003);
1111
1112         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x09);
1113         if (tmp16 != 0x0D03)
1114                 _rtl8723be_mdio_write(rtlpriv, 0x09, 0x0D03);
1115
1116         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0A);
1117         if (tmp16 != 0x4037)
1118                 _rtl8723be_mdio_write(rtlpriv, 0x0A, 0x4037);
1119
1120         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0B);
1121         if (tmp16 != 0x0070)
1122                 _rtl8723be_mdio_write(rtlpriv, 0x0B, 0x0070);
1123
1124         /* Configuration Space offset 0x70f BIT7 is used to control L0S */
1125         tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f);
1126         _rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7));
1127
1128         /* Configuration Space offset 0x719 Bit3 is for L1
1129          * BIT4 is for clock request
1130          */
1131         tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x719);
1132         _rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4));
1133 }
1134
1135 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
1136 {
1137         struct rtl_priv *rtlpriv = rtl_priv(hw);
1138         u8 sec_reg_value;
1139
1140         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1141                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1142                   rtlpriv->sec.pairwise_enc_algorithm,
1143                   rtlpriv->sec.group_enc_algorithm);
1144
1145         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1146                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1147                          "not open hw encryption\n");
1148                 return;
1149         }
1150
1151         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1152
1153         if (rtlpriv->sec.use_defaultkey) {
1154                 sec_reg_value |= SCR_TXUSEDK;
1155                 sec_reg_value |= SCR_RXUSEDK;
1156         }
1157
1158         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1159
1160         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1161
1162         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1163                  "The SECR-value %x\n", sec_reg_value);
1164
1165         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1166 }
1167
1168 static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1169 {
1170         struct rtl_priv *rtlpriv = rtl_priv(hw);
1171         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1172         u8 u1b_tmp;
1173
1174         rtlhal->mac_func_enable = false;
1175         /* Combo (PCIe + USB) Card and PCIe-MF Card */
1176         /* 1. Run LPS WL RFOFF flow */
1177         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1178                                  PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1179
1180         /* 2. 0x1F[7:0] = 0 */
1181         /* turn off RF */
1182         /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1183         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1184             rtlhal->fw_ready) {
1185                 rtl8723be_firmware_selfreset(hw);
1186         }
1187
1188         /* Reset MCU. Suggested by Filen. */
1189         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1190         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1191
1192         /* g.   MCUFWDL 0x80[1:0]=0      */
1193         /* reset MCU ready status */
1194         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1195
1196         /* HW card disable configuration. */
1197         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1198                                  PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1199
1200         /* Reset MCU IO Wrapper */
1201         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1202         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1203         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1204         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1205
1206         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1207         /* lock ISO/CLK/Power control register */
1208         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1209 }
1210
1211 static bool _rtl8723be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1212 {
1213         u8 tmp;
1214
1215         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1216         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1217         if (!(tmp & BIT(2))) {
1218                 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1219                 mdelay(100); /* Suggested by DD Justin_tsai. */
1220         }
1221
1222         /* read reg 0x350 Bit[25] if 1 : RX hang
1223          * read reg 0x350 Bit[24] if 1 : TX hang
1224          */
1225         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1226         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1227                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1228                          "CheckPcieDMAHang8723BE(): true!!\n");
1229                 return true;
1230         }
1231         return false;
1232 }
1233
1234 static void _rtl8723be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1235                                                 bool mac_power_on)
1236 {
1237         u8 tmp;
1238         bool release_mac_rx_pause;
1239         u8 backup_pcie_dma_pause;
1240
1241         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1242                  "ResetPcieInterfaceDMA8723BE()\n");
1243
1244         /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1245          * released by SD1 Alan.
1246          * 2013.05.07, by tynli.
1247          */
1248
1249         /* 1. disable register write lock
1250          *      write 0x1C bit[1:0] = 2'h0
1251          *      write 0xCC bit[2] = 1'b1
1252          */
1253         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1254         tmp &= ~(BIT(1) | BIT(0));
1255         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1256         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1257         tmp |= BIT(2);
1258         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1259
1260         /* 2. Check and pause TRX DMA
1261          *      write 0x284 bit[18] = 1'b1
1262          *      write 0x301 = 0xFF
1263          */
1264         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1265         if (tmp & BIT(2)) {
1266                 /* Already pause before the function for another purpose. */
1267                 release_mac_rx_pause = false;
1268         } else {
1269                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1270                 release_mac_rx_pause = true;
1271         }
1272
1273         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1274         if (backup_pcie_dma_pause != 0xFF)
1275                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1276
1277         if (mac_power_on) {
1278                 /* 3. reset TRX function
1279                  *      write 0x100 = 0x00
1280                  */
1281                 rtl_write_byte(rtlpriv, REG_CR, 0);
1282         }
1283
1284         /* 4. Reset PCIe DMA
1285          *      write 0x003 bit[0] = 0
1286          */
1287         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1288         tmp &= ~(BIT(0));
1289         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1290
1291         /* 5. Enable PCIe DMA
1292          *      write 0x003 bit[0] = 1
1293          */
1294         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1295         tmp |= BIT(0);
1296         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1297
1298         if (mac_power_on) {
1299                 /* 6. enable TRX function
1300                  *      write 0x100 = 0xFF
1301                  */
1302                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1303
1304                 /* We should init LLT & RQPN and
1305                  * prepare Tx/Rx descrptor address later
1306                  * because MAC function is reset.
1307                  */
1308         }
1309
1310         /* 7. Restore PCIe autoload down bit
1311          *      write 0xF8 bit[17] = 1'b1
1312          */
1313         tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1314         tmp |= BIT(1);
1315         rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1316
1317         /* In MAC power on state, BB and RF maybe in ON state,
1318          * if we release TRx DMA here
1319          * it will cause packets to be started to Tx/Rx,
1320          * so we release Tx/Rx DMA later.
1321          */
1322         if (!mac_power_on) {
1323                 /* 8. release TRX DMA
1324                  *      write 0x284 bit[18] = 1'b0
1325                  *      write 0x301 = 0x00
1326                  */
1327                 if (release_mac_rx_pause) {
1328                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1329                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1330                                        (tmp & (~BIT(2))));
1331                 }
1332                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1333                                backup_pcie_dma_pause);
1334         }
1335
1336         /* 9. lock system register
1337          *      write 0xCC bit[2] = 1'b0
1338          */
1339         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1340         tmp &= ~(BIT(2));
1341         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1342 }
1343
1344 int rtl8723be_hw_init(struct ieee80211_hw *hw)
1345 {
1346         struct rtl_priv *rtlpriv = rtl_priv(hw);
1347         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1348         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1349         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1350         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1351         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1352         bool rtstatus = true;
1353         int err;
1354         u8 tmp_u1b;
1355         unsigned long flags;
1356
1357         /* reenable interrupts to not interfere with other devices */
1358         local_save_flags(flags);
1359         local_irq_enable();
1360
1361         rtlhal->fw_ready = false;
1362         rtlpriv->rtlhal.being_init_adapter = true;
1363         rtlpriv->intf_ops->disable_aspm(hw);
1364
1365         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1366         if (tmp_u1b != 0 && tmp_u1b != 0xea) {
1367                 rtlhal->mac_func_enable = true;
1368         } else {
1369                 rtlhal->mac_func_enable = false;
1370                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON;
1371         }
1372
1373         if (_rtl8723be_check_pcie_dma_hang(rtlpriv)) {
1374                 _rtl8723be_reset_pcie_interface_dma(rtlpriv,
1375                                                     rtlhal->mac_func_enable);
1376                 rtlhal->mac_func_enable = false;
1377         }
1378         if (rtlhal->mac_func_enable) {
1379                 _rtl8723be_poweroff_adapter(hw);
1380                 rtlhal->mac_func_enable = false;
1381         }
1382         rtstatus = _rtl8723be_init_mac(hw);
1383         if (!rtstatus) {
1384                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1385                 err = 1;
1386                 goto exit;
1387         }
1388
1389         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1390         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b & 0x7F);
1391
1392         err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT);
1393         if (err) {
1394                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1395                          "Failed to download FW. Init HW without FW now..\n");
1396                 err = 1;
1397                 goto exit;
1398         }
1399         rtlhal->fw_ready = true;
1400
1401         rtlhal->last_hmeboxnum = 0;
1402         rtl8723be_phy_mac_config(hw);
1403         /* because last function modify RCR, so we update
1404          * rcr var here, or TP will unstable for receive_config
1405          * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1406          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1407          */
1408         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1409         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1410         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1411
1412         rtl8723be_phy_bb_config(hw);
1413         rtl8723be_phy_rf_config(hw);
1414
1415         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1416                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1417         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1418                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1419         rtlphy->rfreg_chnlval[0] &= 0xFFF03FF;
1420         rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11));
1421
1422         _rtl8723be_hw_configure(hw);
1423         rtlhal->mac_func_enable = true;
1424         rtl_cam_reset_all_entry(hw);
1425         rtl8723be_enable_hw_security_config(hw);
1426
1427         ppsc->rfpwr_state = ERFON;
1428
1429         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1430         _rtl8723be_enable_aspm_back_door(hw);
1431         rtlpriv->intf_ops->enable_aspm(hw);
1432
1433         rtl8723be_bt_hw_init(hw);
1434
1435         if (ppsc->rfpwr_state == ERFON) {
1436                 rtl8723be_phy_set_rfpath_switch(hw, 1);
1437                 /* when use 1ant NIC, iqk will disturb BT music
1438                  * root cause is not clear now, is something
1439                  * related with 'mdelay' and Reg[0x948]
1440                  */
1441                 if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2 ||
1442                     !rtlpriv->cfg->ops->get_btc_status()) {
1443                         rtl8723be_phy_iq_calibrate(hw, false);
1444                         rtlphy->iqk_initialized = true;
1445                 }
1446                 rtl8723be_dm_check_txpower_tracking(hw);
1447                 rtl8723be_phy_lc_calibrate(hw);
1448         }
1449         rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1450
1451         /* Release Rx DMA. */
1452         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1453         if (tmp_u1b & BIT(2)) {
1454                 /* Release Rx DMA if needed */
1455                 tmp_u1b &= (~BIT(2));
1456                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1457         }
1458         /* Release Tx/Rx PCIE DMA. */
1459         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1460
1461         rtl8723be_dm_init(hw);
1462 exit:
1463         local_irq_restore(flags);
1464         rtlpriv->rtlhal.being_init_adapter = false;
1465         return err;
1466 }
1467
1468 static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw)
1469 {
1470         struct rtl_priv *rtlpriv = rtl_priv(hw);
1471         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1472         enum version_8723e version = VERSION_UNKNOWN;
1473         u32 value32;
1474
1475         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1476         if ((value32 & (CHIP_8723B)) != CHIP_8723B)
1477                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "unkown chip version\n");
1478         else
1479                 version = (enum version_8723e)CHIP_8723B;
1480
1481         rtlphy->rf_type = RF_1T1R;
1482
1483         /* treat rtl8723be chip as  MP version in default */
1484         version = (enum version_8723e)(version | NORMAL_CHIP);
1485
1486         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1487         /* cut version */
1488         version |= (enum version_8723e)(value32 & CHIP_VER_RTL_MASK);
1489         /* Manufacture */
1490         if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01)
1491                 version = (enum version_8723e)(version | CHIP_VENDOR_SMIC);
1492
1493         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1494                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1495                   "RF_2T2R" : "RF_1T1R");
1496
1497         return version;
1498 }
1499
1500 static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
1501                                        enum nl80211_iftype type)
1502 {
1503         struct rtl_priv *rtlpriv = rtl_priv(hw);
1504         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1505         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1506         u8 mode = MSR_NOLINK;
1507
1508         switch (type) {
1509         case NL80211_IFTYPE_UNSPECIFIED:
1510                 mode = MSR_NOLINK;
1511                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1512                          "Set Network type to NO LINK!\n");
1513                 break;
1514         case NL80211_IFTYPE_ADHOC:
1515         case NL80211_IFTYPE_MESH_POINT:
1516                 mode = MSR_ADHOC;
1517                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1518                          "Set Network type to Ad Hoc!\n");
1519                 break;
1520         case NL80211_IFTYPE_STATION:
1521                 mode = MSR_INFRA;
1522                 ledaction = LED_CTL_LINK;
1523                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1524                          "Set Network type to STA!\n");
1525                 break;
1526         case NL80211_IFTYPE_AP:
1527                 mode = MSR_AP;
1528                 ledaction = LED_CTL_LINK;
1529                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1530                          "Set Network type to AP!\n");
1531                 break;
1532         default:
1533                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1534                          "Network type %d not support!\n", type);
1535                 return 1;
1536         }
1537
1538         /* MSR_INFRA == Link in infrastructure network;
1539          * MSR_ADHOC == Link in ad hoc network;
1540          * Therefore, check link state is necessary.
1541          *
1542          * MSR_AP == AP mode; link state is not cared here.
1543          */
1544         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1545                 mode = MSR_NOLINK;
1546                 ledaction = LED_CTL_NO_LINK;
1547         }
1548
1549         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1550                 _rtl8723be_stop_tx_beacon(hw);
1551                 _rtl8723be_enable_bcn_sub_func(hw);
1552         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1553                 _rtl8723be_resume_tx_beacon(hw);
1554                 _rtl8723be_disable_bcn_sub_func(hw);
1555         } else {
1556                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1557                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1558                          mode);
1559         }
1560
1561         rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1562         rtlpriv->cfg->ops->led_control(hw, ledaction);
1563         if (mode == MSR_AP)
1564                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1565         else
1566                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1567         return 0;
1568 }
1569
1570 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1571 {
1572         struct rtl_priv *rtlpriv = rtl_priv(hw);
1573         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1574         u32 reg_rcr = rtlpci->receive_config;
1575
1576         if (rtlpriv->psc.rfpwr_state != ERFON)
1577                 return;
1578
1579         if (check_bssid) {
1580                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1581                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1582                                               (u8 *)(&reg_rcr));
1583                 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
1584         } else if (!check_bssid) {
1585                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1586                 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
1587                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1588                                               (u8 *)(&reg_rcr));
1589         }
1590
1591 }
1592
1593 int rtl8723be_set_network_type(struct ieee80211_hw *hw,
1594                                enum nl80211_iftype type)
1595 {
1596         struct rtl_priv *rtlpriv = rtl_priv(hw);
1597
1598         if (_rtl8723be_set_media_status(hw, type))
1599                 return -EOPNOTSUPP;
1600
1601         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1602                 if (type != NL80211_IFTYPE_AP)
1603                         rtl8723be_set_check_bssid(hw, true);
1604         } else {
1605                 rtl8723be_set_check_bssid(hw, false);
1606         }
1607
1608         return 0;
1609 }
1610
1611 /* don't set REG_EDCA_BE_PARAM here
1612  * because mac80211 will send pkt when scan
1613  */
1614 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
1615 {
1616         struct rtl_priv *rtlpriv = rtl_priv(hw);
1617
1618         rtl8723_dm_init_edca_turbo(hw);
1619         switch (aci) {
1620         case AC1_BK:
1621                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1622                 break;
1623         case AC0_BE:
1624                 break;
1625         case AC2_VI:
1626                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1627                 break;
1628         case AC3_VO:
1629                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1630                 break;
1631         default:
1632                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1633                 break;
1634         }
1635 }
1636
1637 static void rtl8723be_clear_interrupt(struct ieee80211_hw *hw)
1638 {
1639         struct rtl_priv *rtlpriv = rtl_priv(hw);
1640         u32 tmp;
1641
1642         tmp = rtl_read_dword(rtlpriv, REG_HISR);
1643         rtl_write_dword(rtlpriv, REG_HISR, tmp);
1644
1645         tmp = rtl_read_dword(rtlpriv, REG_HISRE);
1646         rtl_write_dword(rtlpriv, REG_HISRE, tmp);
1647
1648         tmp = rtl_read_dword(rtlpriv, REG_HSISR);
1649         rtl_write_dword(rtlpriv, REG_HSISR, tmp);
1650 }
1651
1652 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
1653 {
1654         struct rtl_priv *rtlpriv = rtl_priv(hw);
1655         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1656
1657         rtl8723be_clear_interrupt(hw);/*clear it here first*/
1658
1659         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1660         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1661         rtlpci->irq_enabled = true;
1662
1663         /*enable system interrupt*/
1664         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1665 }
1666
1667 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw)
1668 {
1669         struct rtl_priv *rtlpriv = rtl_priv(hw);
1670         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1671
1672         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1673         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1674         rtlpci->irq_enabled = false;
1675         /*synchronize_irq(rtlpci->pdev->irq);*/
1676 }
1677
1678 void rtl8723be_card_disable(struct ieee80211_hw *hw)
1679 {
1680         struct rtl_priv *rtlpriv = rtl_priv(hw);
1681         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1682         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1683         enum nl80211_iftype opmode;
1684
1685         mac->link_state = MAC80211_NOLINK;
1686         opmode = NL80211_IFTYPE_UNSPECIFIED;
1687         _rtl8723be_set_media_status(hw, opmode);
1688         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1689             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1690                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1691         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1692         _rtl8723be_poweroff_adapter(hw);
1693
1694         /* after power off we should do iqk again */
1695         rtlpriv->phy.iqk_initialized = false;
1696 }
1697
1698 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw,
1699                                     u32 *p_inta, u32 *p_intb)
1700 {
1701         struct rtl_priv *rtlpriv = rtl_priv(hw);
1702         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1703
1704         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1705         rtl_write_dword(rtlpriv, ISR, *p_inta);
1706
1707         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) &
1708                                         rtlpci->irq_mask[1];
1709         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1710 }
1711
1712 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw)
1713 {
1714         struct rtl_priv *rtlpriv = rtl_priv(hw);
1715         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1716         u16 bcn_interval, atim_window;
1717
1718         bcn_interval = mac->beacon_interval;
1719         atim_window = 2;        /*FIX MERGE */
1720         rtl8723be_disable_interrupt(hw);
1721         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1722         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1723         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1724         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1725         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1726         rtl_write_byte(rtlpriv, 0x606, 0x30);
1727         rtl8723be_enable_interrupt(hw);
1728 }
1729
1730 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw)
1731 {
1732         struct rtl_priv *rtlpriv = rtl_priv(hw);
1733         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1734         u16 bcn_interval = mac->beacon_interval;
1735
1736         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1737                  "beacon_interval:%d\n", bcn_interval);
1738         rtl8723be_disable_interrupt(hw);
1739         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1740         rtl8723be_enable_interrupt(hw);
1741 }
1742
1743 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw,
1744                                    u32 add_msr, u32 rm_msr)
1745 {
1746         struct rtl_priv *rtlpriv = rtl_priv(hw);
1747         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1748
1749         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1750                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1751
1752         if (add_msr)
1753                 rtlpci->irq_mask[0] |= add_msr;
1754         if (rm_msr)
1755                 rtlpci->irq_mask[0] &= (~rm_msr);
1756         rtl8723be_disable_interrupt(hw);
1757         rtl8723be_enable_interrupt(hw);
1758 }
1759
1760 static u8 _rtl8723be_get_chnl_group(u8 chnl)
1761 {
1762         u8 group;
1763
1764         if (chnl < 3)
1765                 group = 0;
1766         else if (chnl < 9)
1767                 group = 1;
1768         else
1769                 group = 2;
1770         return group;
1771 }
1772
1773 static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1774                                         struct txpower_info_2g *pw2g,
1775                                         struct txpower_info_5g *pw5g,
1776                                         bool autoload_fail, u8 *hwinfo)
1777 {
1778         struct rtl_priv *rtlpriv = rtl_priv(hw);
1779         u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
1780
1781         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1782                  "hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
1783                  (addr + 1), hwinfo[addr + 1]);
1784         if (0xFF == hwinfo[addr + 1])  /*YJ,add,120316*/
1785                 autoload_fail = true;
1786
1787         if (autoload_fail) {
1788                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1789                          "auto load fail : Use Default value!\n");
1790                 for (path = 0; path < MAX_RF_PATH; path++) {
1791                         /* 2.4G default value */
1792                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1793                                 pw2g->index_cck_base[path][group] = 0x2D;
1794                                 pw2g->index_bw40_base[path][group] = 0x2D;
1795                         }
1796                         for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1797                                 if (cnt == 0) {
1798                                         pw2g->bw20_diff[path][0] = 0x02;
1799                                         pw2g->ofdm_diff[path][0] = 0x04;
1800                                 } else {
1801                                         pw2g->bw20_diff[path][cnt] = 0xFE;
1802                                         pw2g->bw40_diff[path][cnt] = 0xFE;
1803                                         pw2g->cck_diff[path][cnt] = 0xFE;
1804                                         pw2g->ofdm_diff[path][cnt] = 0xFE;
1805                                 }
1806                         }
1807                 }
1808                 return;
1809         }
1810
1811         for (path = 0; path < MAX_RF_PATH; path++) {
1812                 /*2.4G default value*/
1813                 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1814                         pw2g->index_cck_base[path][group] = hwinfo[addr++];
1815                         if (pw2g->index_cck_base[path][group] == 0xFF)
1816                                 pw2g->index_cck_base[path][group] = 0x2D;
1817
1818                 }
1819                 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1820                         pw2g->index_bw40_base[path][group] = hwinfo[addr++];
1821                         if (pw2g->index_bw40_base[path][group] == 0xFF)
1822                                 pw2g->index_bw40_base[path][group] = 0x2D;
1823                 }
1824                 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1825                         if (cnt == 0) {
1826                                 pw2g->bw40_diff[path][cnt] = 0;
1827                                 if (hwinfo[addr] == 0xFF) {
1828                                         pw2g->bw20_diff[path][cnt] = 0x02;
1829                                 } else {
1830                                         pw2g->bw20_diff[path][cnt] =
1831                                                 (hwinfo[addr] & 0xf0) >> 4;
1832                                         /*bit sign number to 8 bit sign number*/
1833                                         if (pw2g->bw20_diff[path][cnt] & BIT(3))
1834                                                 pw2g->bw20_diff[path][cnt] |=
1835                                                                           0xF0;
1836                                 }
1837
1838                                 if (hwinfo[addr] == 0xFF) {
1839                                         pw2g->ofdm_diff[path][cnt] = 0x04;
1840                                 } else {
1841                                         pw2g->ofdm_diff[path][cnt] =
1842                                                         (hwinfo[addr] & 0x0f);
1843                                         /*bit sign number to 8 bit sign number*/
1844                                         if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1845                                                 pw2g->ofdm_diff[path][cnt] |=
1846                                                                           0xF0;
1847                                 }
1848                                 pw2g->cck_diff[path][cnt] = 0;
1849                                 addr++;
1850                         } else {
1851                                 if (hwinfo[addr] == 0xFF) {
1852                                         pw2g->bw40_diff[path][cnt] = 0xFE;
1853                                 } else {
1854                                         pw2g->bw40_diff[path][cnt] =
1855                                                 (hwinfo[addr] & 0xf0) >> 4;
1856                                         if (pw2g->bw40_diff[path][cnt] & BIT(3))
1857                                                 pw2g->bw40_diff[path][cnt] |=
1858                                                                           0xF0;
1859                                 }
1860
1861                                 if (hwinfo[addr] == 0xFF) {
1862                                         pw2g->bw20_diff[path][cnt] = 0xFE;
1863                                 } else {
1864                                         pw2g->bw20_diff[path][cnt] =
1865                                                         (hwinfo[addr] & 0x0f);
1866                                         if (pw2g->bw20_diff[path][cnt] & BIT(3))
1867                                                 pw2g->bw20_diff[path][cnt] |=
1868                                                                           0xF0;
1869                                 }
1870                                 addr++;
1871
1872                                 if (hwinfo[addr] == 0xFF) {
1873                                         pw2g->ofdm_diff[path][cnt] = 0xFE;
1874                                 } else {
1875                                         pw2g->ofdm_diff[path][cnt] =
1876                                                 (hwinfo[addr] & 0xf0) >> 4;
1877                                         if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1878                                                 pw2g->ofdm_diff[path][cnt] |=
1879                                                                           0xF0;
1880                                 }
1881
1882                                 if (hwinfo[addr] == 0xFF)
1883                                         pw2g->cck_diff[path][cnt] = 0xFE;
1884                                 else {
1885                                         pw2g->cck_diff[path][cnt] =
1886                                                         (hwinfo[addr] & 0x0f);
1887                                         if (pw2g->cck_diff[path][cnt] & BIT(3))
1888                                                 pw2g->cck_diff[path][cnt] |=
1889                                                                          0xF0;
1890                                 }
1891                                 addr++;
1892                         }
1893                 }
1894
1895                 /*5G default value*/
1896                 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1897                         pw5g->index_bw40_base[path][group] = hwinfo[addr++];
1898                         if (pw5g->index_bw40_base[path][group] == 0xFF)
1899                                 pw5g->index_bw40_base[path][group] = 0xFE;
1900                 }
1901
1902                 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1903                         if (cnt == 0) {
1904                                 pw5g->bw40_diff[path][cnt] = 0;
1905
1906                                 if (hwinfo[addr] == 0xFF) {
1907                                         pw5g->bw20_diff[path][cnt] = 0;
1908                                 } else {
1909                                         pw5g->bw20_diff[path][0] =
1910                                                 (hwinfo[addr] & 0xf0) >> 4;
1911                                         if (pw5g->bw20_diff[path][cnt] & BIT(3))
1912                                                 pw5g->bw20_diff[path][cnt] |=
1913                                                                           0xF0;
1914                                 }
1915
1916                                 if (hwinfo[addr] == 0xFF)
1917                                         pw5g->ofdm_diff[path][cnt] = 0x04;
1918                                 else {
1919                                         pw5g->ofdm_diff[path][0] =
1920                                                         (hwinfo[addr] & 0x0f);
1921                                         if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1922                                                 pw5g->ofdm_diff[path][cnt] |=
1923                                                                           0xF0;
1924                                 }
1925                                 addr++;
1926                         } else {
1927                                 if (hwinfo[addr] == 0xFF) {
1928                                         pw5g->bw40_diff[path][cnt] = 0xFE;
1929                                 } else {
1930                                         pw5g->bw40_diff[path][cnt] =
1931                                                 (hwinfo[addr] & 0xf0) >> 4;
1932                                         if (pw5g->bw40_diff[path][cnt] & BIT(3))
1933                                                 pw5g->bw40_diff[path][cnt] |= 0xF0;
1934                                 }
1935
1936                                 if (hwinfo[addr] == 0xFF) {
1937                                         pw5g->bw20_diff[path][cnt] = 0xFE;
1938                                 } else {
1939                                         pw5g->bw20_diff[path][cnt] =
1940                                                         (hwinfo[addr] & 0x0f);
1941                                         if (pw5g->bw20_diff[path][cnt] & BIT(3))
1942                                                 pw5g->bw20_diff[path][cnt] |= 0xF0;
1943                                 }
1944                                 addr++;
1945                         }
1946                 }
1947
1948                 if (hwinfo[addr] == 0xFF) {
1949                         pw5g->ofdm_diff[path][1] = 0xFE;
1950                         pw5g->ofdm_diff[path][2] = 0xFE;
1951                 } else {
1952                         pw5g->ofdm_diff[path][1] = (hwinfo[addr] & 0xf0) >> 4;
1953                         pw5g->ofdm_diff[path][2] = (hwinfo[addr] & 0x0f);
1954                 }
1955                 addr++;
1956
1957                 if (hwinfo[addr] == 0xFF)
1958                         pw5g->ofdm_diff[path][3] = 0xFE;
1959                 else
1960                         pw5g->ofdm_diff[path][3] = (hwinfo[addr] & 0x0f);
1961                 addr++;
1962
1963                 for (cnt = 1; cnt < MAX_TX_COUNT; cnt++) {
1964                         if (pw5g->ofdm_diff[path][cnt] == 0xFF)
1965                                 pw5g->ofdm_diff[path][cnt] = 0xFE;
1966                         else if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1967                                 pw5g->ofdm_diff[path][cnt] |= 0xF0;
1968                 }
1969         }
1970 }
1971
1972 static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1973                                                    bool autoload_fail,
1974                                                    u8 *hwinfo)
1975 {
1976         struct rtl_priv *rtlpriv = rtl_priv(hw);
1977         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1978         struct txpower_info_2g pw2g;
1979         struct txpower_info_5g pw5g;
1980         u8 rf_path, index;
1981         u8 i;
1982
1983         _rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail,
1984                                              hwinfo);
1985
1986         for (rf_path = 0; rf_path < 2; rf_path++) {
1987                 for (i = 0; i < 14; i++) {
1988                         index = _rtl8723be_get_chnl_group(i+1);
1989
1990                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1991                                         pw2g.index_cck_base[rf_path][index];
1992                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1993                                         pw2g.index_bw40_base[rf_path][index];
1994                 }
1995                 for (i = 0; i < MAX_TX_COUNT; i++) {
1996                         rtlefuse->txpwr_ht20diff[rf_path][i] =
1997                                                 pw2g.bw20_diff[rf_path][i];
1998                         rtlefuse->txpwr_ht40diff[rf_path][i] =
1999                                                 pw2g.bw40_diff[rf_path][i];
2000                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2001                                                 pw2g.ofdm_diff[rf_path][i];
2002                 }
2003
2004                 for (i = 0; i < 14; i++) {
2005                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2006                                 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
2007                                 rf_path, i,
2008                                 rtlefuse->txpwrlevel_cck[rf_path][i],
2009                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
2010                 }
2011         }
2012
2013         if (!autoload_fail)
2014                 rtlefuse->eeprom_thermalmeter =
2015                                         hwinfo[EEPROM_THERMAL_METER_88E];
2016         else
2017                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2018
2019         if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
2020                 rtlefuse->apk_thermalmeterignore = true;
2021                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2022         }
2023
2024         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
2025         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2026                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
2027
2028         if (!autoload_fail) {
2029                 rtlefuse->eeprom_regulatory =
2030                         hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
2031                 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2032                         rtlefuse->eeprom_regulatory = 0;
2033         } else {
2034                 rtlefuse->eeprom_regulatory = 0;
2035         }
2036         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2037                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2038 }
2039
2040 static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw,
2041                                          bool pseudo_test)
2042 {
2043         struct rtl_priv *rtlpriv = rtl_priv(hw);
2044         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2045         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2046         u16 i, usvalue;
2047         u8 hwinfo[HWSET_MAX_SIZE];
2048         u16 eeprom_id;
2049         bool is_toshiba_smid1 = false;
2050         bool is_toshiba_smid2 = false;
2051         bool is_samsung_smid = false;
2052         bool is_lenovo_smid = false;
2053         u16 toshiba_smid1[] = {
2054                 0x6151, 0x6152, 0x6154, 0x6155, 0x6177, 0x6178, 0x6179, 0x6180,
2055                 0x7151, 0x7152, 0x7154, 0x7155, 0x7177, 0x7178, 0x7179, 0x7180,
2056                 0x8151, 0x8152, 0x8154, 0x8155, 0x8181, 0x8182, 0x8184, 0x8185,
2057                 0x9151, 0x9152, 0x9154, 0x9155, 0x9181, 0x9182, 0x9184, 0x9185
2058         };
2059         u16 toshiba_smid2[] = {
2060                 0x6181, 0x6184, 0x6185, 0x7181, 0x7182, 0x7184, 0x7185, 0x8181,
2061                 0x8182, 0x8184, 0x8185, 0x9181, 0x9182, 0x9184, 0x9185
2062         };
2063         u16 samsung_smid[] = {
2064                 0x6191, 0x6192, 0x6193, 0x7191, 0x7192, 0x7193, 0x8191, 0x8192,
2065                 0x8193, 0x9191, 0x9192, 0x9193
2066         };
2067         u16 lenovo_smid[] = {
2068                 0x8195, 0x9195, 0x7194, 0x8200, 0x8201, 0x8202, 0x9199, 0x9200
2069         };
2070
2071         if (pseudo_test) {
2072                 /* needs to be added */
2073                 return;
2074         }
2075         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2076                 rtl_efuse_shadow_map_update(hw);
2077
2078                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2079                        HWSET_MAX_SIZE);
2080         } else if (rtlefuse->epromtype == EEPROM_93C46) {
2081                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2082                          "RTL819X Not boot from eeprom, check it !!");
2083         }
2084         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
2085                       hwinfo, HWSET_MAX_SIZE);
2086
2087         eeprom_id = *((u16 *)&hwinfo[0]);
2088         if (eeprom_id != RTL8723BE_EEPROM_ID) {
2089                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2090                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
2091                 rtlefuse->autoload_failflag = true;
2092         } else {
2093                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2094                 rtlefuse->autoload_failflag = false;
2095         }
2096
2097         if (rtlefuse->autoload_failflag)
2098                 return;
2099
2100         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
2101         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
2102         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
2103         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
2104         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2105                  "EEPROMId = 0x%4x\n", eeprom_id);
2106         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2107                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
2108         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2109                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
2110         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2111                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
2112         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2113                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
2114
2115         for (i = 0; i < 6; i += 2) {
2116                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
2117                 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
2118         }
2119         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "dev_addr: %pM\n",
2120                  rtlefuse->dev_addr);
2121
2122         /*parse xtal*/
2123         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8723BE];
2124         if (rtlefuse->crystalcap == 0xFF)
2125                 rtlefuse->crystalcap = 0x20;
2126
2127         _rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2128                                                hwinfo);
2129
2130         rtl8723be_read_bt_coexist_info_from_hwpg(hw,
2131                                                  rtlefuse->autoload_failflag,
2132                                                  hwinfo);
2133
2134         rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
2135         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
2136         rtlefuse->txpwr_fromeprom = true;
2137         rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
2138
2139         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2140                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
2141
2142         /* set channel plan to world wide 13 */
2143         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
2144
2145         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2146                 /* Does this one have a Toshiba SMID from group 1? */
2147                 for (i = 0; i < sizeof(toshiba_smid1) / sizeof(u16); i++) {
2148                         if (rtlefuse->eeprom_smid == toshiba_smid1[i]) {
2149                                 is_toshiba_smid1 = true;
2150                                 break;
2151                         }
2152                 }
2153                 /* Does this one have a Toshiba SMID from group 2? */
2154                 for (i = 0; i < sizeof(toshiba_smid2) / sizeof(u16); i++) {
2155                         if (rtlefuse->eeprom_smid == toshiba_smid2[i]) {
2156                                 is_toshiba_smid2 = true;
2157                                 break;
2158                         }
2159                 }
2160                 /* Does this one have a Samsung SMID? */
2161                 for (i = 0; i < sizeof(samsung_smid) / sizeof(u16); i++) {
2162                         if (rtlefuse->eeprom_smid == samsung_smid[i]) {
2163                                 is_samsung_smid = true;
2164                                 break;
2165                         }
2166                 }
2167                 /* Does this one have a Lenovo SMID? */
2168                 for (i = 0; i < sizeof(lenovo_smid) / sizeof(u16); i++) {
2169                         if (rtlefuse->eeprom_smid == lenovo_smid[i]) {
2170                                 is_lenovo_smid = true;
2171                                 break;
2172                         }
2173                 }
2174                 switch (rtlefuse->eeprom_oemid) {
2175                 case EEPROM_CID_DEFAULT:
2176                         if (rtlefuse->eeprom_did == 0x8176) {
2177                                 if (rtlefuse->eeprom_svid == 0x10EC &&
2178                                     is_toshiba_smid1) {
2179                                         rtlhal->oem_id = RT_CID_TOSHIBA;
2180                                 } else if (rtlefuse->eeprom_svid == 0x1025) {
2181                                         rtlhal->oem_id = RT_CID_819X_ACER;
2182                                 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2183                                            is_samsung_smid) {
2184                                         rtlhal->oem_id = RT_CID_819X_SAMSUNG;
2185                                 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2186                                            is_lenovo_smid) {
2187                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
2188                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2189                                             rtlefuse->eeprom_smid == 0x8197) ||
2190                                            (rtlefuse->eeprom_svid == 0x10EC &&
2191                                             rtlefuse->eeprom_smid == 0x9196)) {
2192                                         rtlhal->oem_id = RT_CID_819X_CLEVO;
2193                                 } else if ((rtlefuse->eeprom_svid == 0x1028 &&
2194                                             rtlefuse->eeprom_smid == 0x8194) ||
2195                                            (rtlefuse->eeprom_svid == 0x1028 &&
2196                                             rtlefuse->eeprom_smid == 0x8198) ||
2197                                            (rtlefuse->eeprom_svid == 0x1028 &&
2198                                             rtlefuse->eeprom_smid == 0x9197) ||
2199                                            (rtlefuse->eeprom_svid == 0x1028 &&
2200                                             rtlefuse->eeprom_smid == 0x9198)) {
2201                                         rtlhal->oem_id = RT_CID_819X_DELL;
2202                                 } else if ((rtlefuse->eeprom_svid == 0x103C &&
2203                                             rtlefuse->eeprom_smid == 0x1629)) {
2204                                         rtlhal->oem_id = RT_CID_819X_HP;
2205                                 } else if ((rtlefuse->eeprom_svid == 0x1A32 &&
2206                                            rtlefuse->eeprom_smid == 0x2315)) {
2207                                         rtlhal->oem_id = RT_CID_819X_QMI;
2208                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2209                                            rtlefuse->eeprom_smid == 0x8203)) {
2210                                         rtlhal->oem_id = RT_CID_819X_PRONETS;
2211                                 } else if ((rtlefuse->eeprom_svid == 0x1043 &&
2212                                            rtlefuse->eeprom_smid == 0x84B5)) {
2213                                         rtlhal->oem_id = RT_CID_819X_EDIMAX_ASUS;
2214                                 } else {
2215                                         rtlhal->oem_id = RT_CID_DEFAULT;
2216                                 }
2217                         } else if (rtlefuse->eeprom_did == 0x8178) {
2218                                 if (rtlefuse->eeprom_svid == 0x10EC &&
2219                                     is_toshiba_smid2)
2220                                         rtlhal->oem_id = RT_CID_TOSHIBA;
2221                                 else if (rtlefuse->eeprom_svid == 0x1025)
2222                                         rtlhal->oem_id = RT_CID_819X_ACER;
2223                                 else if ((rtlefuse->eeprom_svid == 0x10EC &&
2224                                           rtlefuse->eeprom_smid == 0x8186))
2225                                         rtlhal->oem_id = RT_CID_819X_PRONETS;
2226                                 else if ((rtlefuse->eeprom_svid == 0x1043 &&
2227                                           rtlefuse->eeprom_smid == 0x84B6))
2228                                         rtlhal->oem_id =
2229                                                         RT_CID_819X_EDIMAX_ASUS;
2230                                 else
2231                                         rtlhal->oem_id = RT_CID_DEFAULT;
2232                         } else {
2233                                         rtlhal->oem_id = RT_CID_DEFAULT;
2234                         }
2235                         break;
2236                 case EEPROM_CID_TOSHIBA:
2237                         rtlhal->oem_id = RT_CID_TOSHIBA;
2238                         break;
2239                 case EEPROM_CID_CCX:
2240                         rtlhal->oem_id = RT_CID_CCX;
2241                         break;
2242                 case EEPROM_CID_QMI:
2243                         rtlhal->oem_id = RT_CID_819X_QMI;
2244                         break;
2245                 case EEPROM_CID_WHQL:
2246                         break;
2247                 default:
2248                         rtlhal->oem_id = RT_CID_DEFAULT;
2249                         break;
2250                 }
2251         }
2252 }
2253
2254 static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw)
2255 {
2256         struct rtl_priv *rtlpriv = rtl_priv(hw);
2257         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2258         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2259
2260         pcipriv->ledctl.led_opendrain = true;
2261         switch (rtlhal->oem_id) {
2262         case RT_CID_819X_HP:
2263                 pcipriv->ledctl.led_opendrain = true;
2264                 break;
2265         case RT_CID_819X_LENOVO:
2266         case RT_CID_DEFAULT:
2267         case RT_CID_TOSHIBA:
2268         case RT_CID_CCX:
2269         case RT_CID_819X_ACER:
2270         case RT_CID_WHQL:
2271         default:
2272                 break;
2273         }
2274         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2275                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2276 }
2277
2278 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
2279 {
2280         struct rtl_priv *rtlpriv = rtl_priv(hw);
2281         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2282         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2283         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2284         u8 tmp_u1b;
2285
2286         rtlhal->version = _rtl8723be_read_chip_version(hw);
2287         if (get_rf_type(rtlphy) == RF_1T1R)
2288                 rtlpriv->dm.rfpath_rxenable[0] = true;
2289         else
2290                 rtlpriv->dm.rfpath_rxenable[0] =
2291                     rtlpriv->dm.rfpath_rxenable[1] = true;
2292         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2293                  rtlhal->version);
2294         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2295         if (tmp_u1b & BIT(4)) {
2296                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2297                 rtlefuse->epromtype = EEPROM_93C46;
2298         } else {
2299                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2300                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2301         }
2302         if (tmp_u1b & BIT(5)) {
2303                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2304                 rtlefuse->autoload_failflag = false;
2305                 _rtl8723be_read_adapter_info(hw, false);
2306         } else {
2307                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2308         }
2309         _rtl8723be_hal_customized_behavior(hw);
2310 }
2311
2312 static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
2313                                           u8 rate_index)
2314 {
2315         u8 ret = 0;
2316         switch (rate_index) {
2317         case RATR_INX_WIRELESS_NGB:
2318                 ret = 1;
2319                 break;
2320         case RATR_INX_WIRELESS_N:
2321         case RATR_INX_WIRELESS_NG:
2322                 ret = 5;
2323                 break;
2324         case RATR_INX_WIRELESS_NB:
2325                 ret = 3;
2326                 break;
2327         case RATR_INX_WIRELESS_GB:
2328                 ret = 6;
2329                 break;
2330         case RATR_INX_WIRELESS_G:
2331                 ret = 7;
2332                 break;
2333         case RATR_INX_WIRELESS_B:
2334                 ret = 8;
2335                 break;
2336         default:
2337                 ret = 0;
2338                 break;
2339         }
2340         return ret;
2341 }
2342
2343 static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2344                                            struct ieee80211_sta *sta,
2345                                            u8 rssi_level)
2346 {
2347         struct rtl_priv *rtlpriv = rtl_priv(hw);
2348         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2349         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2350         struct rtl_sta_info *sta_entry = NULL;
2351         u32 ratr_bitmap;
2352         u8 ratr_index;
2353         u8 curtxbw_40mhz = (sta->ht_cap.cap &
2354                               IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2355         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2356                                 1 : 0;
2357         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2358                                 1 : 0;
2359         enum wireless_mode wirelessmode = 0;
2360         bool shortgi = false;
2361         u8 rate_mask[7];
2362         u8 macid = 0;
2363
2364         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2365         wirelessmode = sta_entry->wireless_mode;
2366         if (mac->opmode == NL80211_IFTYPE_STATION ||
2367             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2368                 curtxbw_40mhz = mac->bw_40;
2369         else if (mac->opmode == NL80211_IFTYPE_AP ||
2370                  mac->opmode == NL80211_IFTYPE_ADHOC)
2371                 macid = sta->aid + 1;
2372
2373         ratr_bitmap = sta->supp_rates[0];
2374
2375         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2376                 ratr_bitmap = 0xfff;
2377
2378         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2379                         sta->ht_cap.mcs.rx_mask[0] << 12);
2380         switch (wirelessmode) {
2381         case WIRELESS_MODE_B:
2382                 ratr_index = RATR_INX_WIRELESS_B;
2383                 if (ratr_bitmap & 0x0000000c)
2384                         ratr_bitmap &= 0x0000000d;
2385                 else
2386                         ratr_bitmap &= 0x0000000f;
2387                 break;
2388         case WIRELESS_MODE_G:
2389                 ratr_index = RATR_INX_WIRELESS_GB;
2390
2391                 if (rssi_level == 1)
2392                         ratr_bitmap &= 0x00000f00;
2393                 else if (rssi_level == 2)
2394                         ratr_bitmap &= 0x00000ff0;
2395                 else
2396                         ratr_bitmap &= 0x00000ff5;
2397                 break;
2398         case WIRELESS_MODE_N_24G:
2399         case WIRELESS_MODE_N_5G:
2400                 ratr_index = RATR_INX_WIRELESS_NGB;
2401                 if (rtlphy->rf_type == RF_1T1R) {
2402                         if (curtxbw_40mhz) {
2403                                 if (rssi_level == 1)
2404                                         ratr_bitmap &= 0x000f0000;
2405                                 else if (rssi_level == 2)
2406                                         ratr_bitmap &= 0x000ff000;
2407                                 else
2408                                         ratr_bitmap &= 0x000ff015;
2409                         } else {
2410                                 if (rssi_level == 1)
2411                                         ratr_bitmap &= 0x000f0000;
2412                                 else if (rssi_level == 2)
2413                                         ratr_bitmap &= 0x000ff000;
2414                                 else
2415                                         ratr_bitmap &= 0x000ff005;
2416                         }
2417                 } else {
2418                         if (curtxbw_40mhz) {
2419                                 if (rssi_level == 1)
2420                                         ratr_bitmap &= 0x0f8f0000;
2421                                 else if (rssi_level == 2)
2422                                         ratr_bitmap &= 0x0f8ff000;
2423                                 else
2424                                         ratr_bitmap &= 0x0f8ff015;
2425                         } else {
2426                                 if (rssi_level == 1)
2427                                         ratr_bitmap &= 0x0f8f0000;
2428                                 else if (rssi_level == 2)
2429                                         ratr_bitmap &= 0x0f8ff000;
2430                                 else
2431                                         ratr_bitmap &= 0x0f8ff005;
2432                         }
2433                 }
2434                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2435                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2436                         if (macid == 0)
2437                                 shortgi = true;
2438                         else if (macid == 1)
2439                                 shortgi = false;
2440                 }
2441                 break;
2442         default:
2443                 ratr_index = RATR_INX_WIRELESS_NGB;
2444
2445                 if (rtlphy->rf_type == RF_1T2R)
2446                         ratr_bitmap &= 0x000ff0ff;
2447                 else
2448                         ratr_bitmap &= 0x0f0ff0ff;
2449                 break;
2450         }
2451
2452         sta_entry->ratr_index = ratr_index;
2453
2454         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2455                  "ratr_bitmap :%x\n", ratr_bitmap);
2456         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2457                                        (ratr_index << 28);
2458         rate_mask[0] = macid;
2459         rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) |
2460                                                       (shortgi ? 0x80 : 0x00);
2461         rate_mask[2] = curtxbw_40mhz;
2462
2463         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2464         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2465         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2466         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2467
2468         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2469                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2470                  ratr_index, ratr_bitmap,
2471                  rate_mask[0], rate_mask[1],
2472                  rate_mask[2], rate_mask[3],
2473                  rate_mask[4], rate_mask[5],
2474                  rate_mask[6]);
2475         rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask);
2476         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2477 }
2478
2479 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2480                                    struct ieee80211_sta *sta,
2481                                    u8 rssi_level)
2482 {
2483         struct rtl_priv *rtlpriv = rtl_priv(hw);
2484         if (rtlpriv->dm.useramask)
2485                 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level);
2486 }
2487
2488 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw)
2489 {
2490         struct rtl_priv *rtlpriv = rtl_priv(hw);
2491         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2492         u16 sifs_timer;
2493
2494         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2495         if (!mac->ht_enable)
2496                 sifs_timer = 0x0a0a;
2497         else
2498                 sifs_timer = 0x0e0e;
2499         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2500 }
2501
2502 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2503 {
2504         struct rtl_priv *rtlpriv = rtl_priv(hw);
2505         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2506         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2507         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2508         u8 u1tmp;
2509         bool b_actuallyset = false;
2510
2511         if (rtlpriv->rtlhal.being_init_adapter)
2512                 return false;
2513
2514         if (ppsc->swrf_processing)
2515                 return false;
2516
2517         spin_lock(&rtlpriv->locks.rf_ps_lock);
2518         if (ppsc->rfchange_inprogress) {
2519                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2520                 return false;
2521         } else {
2522                 ppsc->rfchange_inprogress = true;
2523                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2524         }
2525
2526         cur_rfstate = ppsc->rfpwr_state;
2527
2528         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2529                        rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
2530
2531         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2532
2533         if (rtlphy->polarity_ctl)
2534                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2535         else
2536                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2537
2538         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2539                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2540                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2541
2542                 e_rfpowerstate_toset = ERFON;
2543                 ppsc->hwradiooff = false;
2544                 b_actuallyset = true;
2545         } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2546                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2547                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2548
2549                 e_rfpowerstate_toset = ERFOFF;
2550                 ppsc->hwradiooff = true;
2551                 b_actuallyset = true;
2552         }
2553
2554         if (b_actuallyset) {
2555                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2556                 ppsc->rfchange_inprogress = false;
2557                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2558         } else {
2559                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2560                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2561
2562                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2563                 ppsc->rfchange_inprogress = false;
2564                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2565         }
2566
2567         *valid = 1;
2568         return !ppsc->hwradiooff;
2569
2570 }
2571
2572 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2573                        u8 *p_macaddr, bool is_group, u8 enc_algo,
2574                        bool is_wepkey, bool clear_all)
2575 {
2576         struct rtl_priv *rtlpriv = rtl_priv(hw);
2577         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2578         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2579         u8 *macaddr = p_macaddr;
2580         u32 entry_id = 0;
2581         bool is_pairwise = false;
2582
2583         static u8 cam_const_addr[4][6] = {
2584                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2585                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2586                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2587                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2588         };
2589         static u8 cam_const_broad[] = {
2590                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2591         };
2592
2593         if (clear_all) {
2594                 u8 idx = 0;
2595                 u8 cam_offset = 0;
2596                 u8 clear_number = 5;
2597
2598                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2599
2600                 for (idx = 0; idx < clear_number; idx++) {
2601                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2602                         rtl_cam_empty_entry(hw, cam_offset + idx);
2603
2604                         if (idx < 5) {
2605                                 memset(rtlpriv->sec.key_buf[idx], 0,
2606                                        MAX_KEY_LEN);
2607                                 rtlpriv->sec.key_len[idx] = 0;
2608                         }
2609                 }
2610
2611         } else {
2612                 switch (enc_algo) {
2613                 case WEP40_ENCRYPTION:
2614                         enc_algo = CAM_WEP40;
2615                         break;
2616                 case WEP104_ENCRYPTION:
2617                         enc_algo = CAM_WEP104;
2618                         break;
2619                 case TKIP_ENCRYPTION:
2620                         enc_algo = CAM_TKIP;
2621                         break;
2622                 case AESCCMP_ENCRYPTION:
2623                         enc_algo = CAM_AES;
2624                         break;
2625                 default:
2626                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2627                                  "switch case not process\n");
2628                         enc_algo = CAM_TKIP;
2629                         break;
2630                 }
2631
2632                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2633                         macaddr = cam_const_addr[key_index];
2634                         entry_id = key_index;
2635                 } else {
2636                         if (is_group) {
2637                                 macaddr = cam_const_broad;
2638                                 entry_id = key_index;
2639                         } else {
2640                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2641                                         entry_id = rtl_cam_get_free_entry(hw,
2642                                                                 p_macaddr);
2643                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2644                                                 RT_TRACE(rtlpriv, COMP_SEC,
2645                                                          DBG_EMERG,
2646                                                          "Can not find free hw security cam entry\n");
2647                                                 return;
2648                                         }
2649                                 } else {
2650                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2651                                 }
2652
2653                                 key_index = PAIRWISE_KEYIDX;
2654                                 is_pairwise = true;
2655                         }
2656                 }
2657
2658                 if (rtlpriv->sec.key_len[key_index] == 0) {
2659                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2660                                  "delete one entry, entry_id is %d\n",
2661                                   entry_id);
2662                         if (mac->opmode == NL80211_IFTYPE_AP)
2663                                 rtl_cam_del_entry(hw, p_macaddr);
2664                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2665                 } else {
2666                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2667                                  "add one entry\n");
2668                         if (is_pairwise) {
2669                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2670                                          "set Pairwiase key\n");
2671
2672                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2673                                                entry_id, enc_algo,
2674                                                CAM_CONFIG_NO_USEDK,
2675                                                rtlpriv->sec.key_buf[key_index]);
2676                         } else {
2677                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2678                                          "set group key\n");
2679
2680                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2681                                         rtl_cam_add_one_entry(hw,
2682                                                 rtlefuse->dev_addr,
2683                                                 PAIRWISE_KEYIDX,
2684                                                 CAM_PAIRWISE_KEY_POSITION,
2685                                                 enc_algo,
2686                                                 CAM_CONFIG_NO_USEDK,
2687                                                 rtlpriv->sec.key_buf
2688                                                 [entry_id]);
2689                                 }
2690
2691                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2692                                                 entry_id, enc_algo,
2693                                                 CAM_CONFIG_NO_USEDK,
2694                                                 rtlpriv->sec.key_buf[entry_id]);
2695                         }
2696                 }
2697         }
2698 }
2699
2700 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2701                                               bool auto_load_fail, u8 *hwinfo)
2702 {
2703         struct rtl_priv *rtlpriv = rtl_priv(hw);
2704         u8 value;
2705         u32 tmpu_32;
2706
2707         if (!auto_load_fail) {
2708                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2709                 if (tmpu_32 & BIT(18))
2710                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
2711                 else
2712                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
2713                 value = hwinfo[EEPROM_RF_BT_SETTING_8723B];
2714                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2715                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
2716         } else {
2717                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2718                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2719                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
2720         }
2721
2722 }
2723
2724 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw)
2725 {
2726         struct rtl_priv *rtlpriv = rtl_priv(hw);
2727
2728         /* 0:Low, 1:High, 2:From Efuse. */
2729         rtlpriv->btcoexist.reg_bt_iso = 2;
2730         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2731         rtlpriv->btcoexist.reg_bt_sco = 3;
2732         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2733         rtlpriv->btcoexist.reg_bt_sco = 0;
2734 }
2735
2736 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw)
2737 {
2738         struct rtl_priv *rtlpriv = rtl_priv(hw);
2739
2740         if (rtlpriv->cfg->ops->get_btc_status())
2741                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2742
2743 }
2744
2745 void rtl8723be_suspend(struct ieee80211_hw *hw)
2746 {
2747 }
2748
2749 void rtl8723be_resume(struct ieee80211_hw *hw)
2750 {
2751 }