kernel/drivers/net/wireless/rtlwifi/rtl8192ee/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "dm.h"
  37 #include "fw.h"
  38 #include "led.h"
  39 #include "hw.h"
  40 #include "../pwrseqcmd.h"
  41 #include "pwrseq.h"
  42
  43 #define LLT_CONFIG      5
  44
  45 static void _rtl92ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  46                                       u8 set_bits, u8 clear_bits)
  47 {
  48         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  49         struct rtl_priv *rtlpriv = rtl_priv(hw);
  50
  51         rtlpci->reg_bcn_ctrl_val |= set_bits;
  52         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  53
  54         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  55 }
  56
  57 static void _rtl92ee_stop_tx_beacon(struct ieee80211_hw *hw)
  58 {
  59         struct rtl_priv *rtlpriv = rtl_priv(hw);
  60         u8 tmp;
  61
  62         tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  63         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp & (~BIT(6)));
  64         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  65         tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  66         tmp &= ~(BIT(0));
  67         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
  68 }
  69
  70 static void _rtl92ee_resume_tx_beacon(struct ieee80211_hw *hw)
  71 {
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73         u8 tmp;
  74
  75         tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  76         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp | BIT(6));
  77         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  78         tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  79         tmp |= BIT(0);
  80         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
  81 }
  82
  83 static void _rtl92ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
  84 {
  85         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
  86 }
  87
  88 static void _rtl92ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
  89 {
  90         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
  91 }
  92
  93 static void _rtl92ee_set_fw_clock_on(struct ieee80211_hw *hw,
  94                                      u8 rpwm_val, bool b_need_turn_off_ckk)
  95 {
  96         struct rtl_priv *rtlpriv = rtl_priv(hw);
  97         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  98         bool b_support_remote_wake_up;
  99         u32 count = 0, isr_regaddr, content;
 100         bool b_schedule_timer = b_need_turn_off_ckk;
 101
 102         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 103                                       (u8 *)(&b_support_remote_wake_up));
 104
 105         if (!rtlhal->fw_ready)
 106                 return;
 107         if (!rtlpriv->psc.fw_current_inpsmode)
 108                 return;
 109
 110         while (1) {
 111                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 112                 if (rtlhal->fw_clk_change_in_progress) {
 113                         while (rtlhal->fw_clk_change_in_progress) {
 114                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 115                                 count++;
 116                                 udelay(100);
 117                                 if (count > 1000)
 118                                         return;
 119                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 120                         }
 121                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 122                 } else {
 123                         rtlhal->fw_clk_change_in_progress = false;
 124                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 125                         break;
 126                 }
 127         }
 128
 129         if (IS_IN_LOW_POWER_STATE_92E(rtlhal->fw_ps_state)) {
 130                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 131                                               (u8 *)(&rpwm_val));
 132                 if (FW_PS_IS_ACK(rpwm_val)) {
 133                         isr_regaddr = REG_HISR;
 134                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 135                         while (!(content & IMR_CPWM) && (count < 500)) {
 136                                 udelay(50);
 137                                 count++;
 138                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 139                         }
 140
 141                         if (content & IMR_CPWM) {
 142                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 143                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_92E;
 144                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 145                                          "Receive CPWM INT!!! PSState = %X\n",
 146                                          rtlhal->fw_ps_state);
 147                         }
 148                 }
 149
 150                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 151                 rtlhal->fw_clk_change_in_progress = false;
 152                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 153                 if (b_schedule_timer) {
 154                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 155                                   jiffies + MSECS(10));
 156                 }
 157         } else  {
 158                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 159                 rtlhal->fw_clk_change_in_progress = false;
 160                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 161         }
 162 }
 163
 164 static void _rtl92ee_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
 165 {
 166         struct rtl_priv *rtlpriv = rtl_priv(hw);
 167         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 168         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 169         struct rtl8192_tx_ring *ring;
 170         enum rf_pwrstate rtstate;
 171         bool b_schedule_timer = false;
 172         u8 queue;
 173
 174         if (!rtlhal->fw_ready)
 175                 return;
 176         if (!rtlpriv->psc.fw_current_inpsmode)
 177                 return;
 178         if (!rtlhal->allow_sw_to_change_hwclc)
 179                 return;
 180
 181         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 182         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 183                 return;
 184
 185         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 186                 ring = &rtlpci->tx_ring[queue];
 187                 if (skb_queue_len(&ring->queue)) {
 188                         b_schedule_timer = true;
 189                         break;
 190                 }
 191         }
 192
 193         if (b_schedule_timer) {
 194                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 195                           jiffies + MSECS(10));
 196                 return;
 197         }
 198
 199         if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
 200                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 201                 if (!rtlhal->fw_clk_change_in_progress) {
 202                         rtlhal->fw_clk_change_in_progress = true;
 203                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 204                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 205                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 206                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 207                                                       (u8 *)(&rpwm_val));
 208                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 209                         rtlhal->fw_clk_change_in_progress = false;
 210                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 211                 } else {
 212                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 213                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 214                                   jiffies + MSECS(10));
 215                 }
 216         }
 217 }
 218
 219 static void _rtl92ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 220 {
 221         u8 rpwm_val = 0;
 222
 223         rpwm_val |= (FW_PS_STATE_RF_OFF_92E | FW_PS_ACK);
 224         _rtl92ee_set_fw_clock_on(hw, rpwm_val, true);
 225 }
 226
 227 static void _rtl92ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
 228 {
 229         u8 rpwm_val = 0;
 230
 231         rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR;
 232         _rtl92ee_set_fw_clock_off(hw, rpwm_val);
 233 }
 234
 235 void rtl92ee_fw_clk_off_timer_callback(unsigned long data)
 236 {
 237         struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
 238
 239         _rtl92ee_set_fw_ps_rf_off_low_power(hw);
 240 }
 241
 242 static void _rtl92ee_fwlps_leave(struct ieee80211_hw *hw)
 243 {
 244         struct rtl_priv *rtlpriv = rtl_priv(hw);
 245         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 246         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 247         bool fw_current_inps = false;
 248         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 249
 250         if (ppsc->low_power_enable) {
 251                 rpwm_val = (FW_PS_STATE_ALL_ON_92E | FW_PS_ACK);/* RF on */
 252                 _rtl92ee_set_fw_clock_on(hw, rpwm_val, false);
 253                 rtlhal->allow_sw_to_change_hwclc = false;
 254                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 255                                               (u8 *)(&fw_pwrmode));
 256                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 257                                               (u8 *)(&fw_current_inps));
 258         } else {
 259                 rpwm_val = FW_PS_STATE_ALL_ON_92E;      /* RF on */
 260                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 261                                               (u8 *)(&rpwm_val));
 262                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 263                                               (u8 *)(&fw_pwrmode));
 264                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 265                                               (u8 *)(&fw_current_inps));
 266         }
 267 }
 268
 269 static void _rtl92ee_fwlps_enter(struct ieee80211_hw *hw)
 270 {
 271         struct rtl_priv *rtlpriv = rtl_priv(hw);
 272         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 273         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 274         bool fw_current_inps = true;
 275         u8 rpwm_val;
 276
 277         if (ppsc->low_power_enable) {
 278                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR;  /* RF off */
 279                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 280                                               (u8 *)(&fw_current_inps));
 281                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 282                                               (u8 *)(&ppsc->fwctrl_psmode));
 283                 rtlhal->allow_sw_to_change_hwclc = true;
 284                 _rtl92ee_set_fw_clock_off(hw, rpwm_val);
 285         } else {
 286                 rpwm_val = FW_PS_STATE_RF_OFF_92E;      /* RF off */
 287                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 288                                               (u8 *)(&fw_current_inps));
 289                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 290                                               (u8 *)(&ppsc->fwctrl_psmode));
 291                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 292                                               (u8 *)(&rpwm_val));
 293         }
 294 }
 295
 296 void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 297 {
 298         struct rtl_priv *rtlpriv = rtl_priv(hw);
 299         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 300         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 301
 302         switch (variable) {
 303         case HW_VAR_RCR:
 304                 *((u32 *)(val)) = rtlpci->receive_config;
 305                 break;
 306         case HW_VAR_RF_STATE:
 307                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 308                 break;
 309         case HW_VAR_FWLPS_RF_ON:{
 310                         enum rf_pwrstate rfstate;
 311                         u32 val_rcr;
 312
 313                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 314                                                       (u8 *)(&rfstate));
 315                         if (rfstate == ERFOFF) {
 316                                 *((bool *)(val)) = true;
 317                         } else {
 318                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 319                                 val_rcr &= 0x00070000;
 320                                 if (val_rcr)
 321                                         *((bool *)(val)) = false;
 322                                 else
 323                                         *((bool *)(val)) = true;
 324                         }
 325                 }
 326                 break;
 327         case HW_VAR_FW_PSMODE_STATUS:
 328                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 329                 break;
 330         case HW_VAR_CORRECT_TSF:{
 331                 u64 tsf;
 332                 u32 *ptsf_low = (u32 *)&tsf;
 333                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 334
 335                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 336                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 337
 338                 *((u64 *)(val)) = tsf;
 339                 }
 340                 break;
 341         default:
 342                 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
 343                          "switch case not process %x\n", variable);
 344                 break;
 345         }
 346 }
 347
 348 static void _rtl92ee_download_rsvd_page(struct ieee80211_hw *hw)
 349 {
 350         struct rtl_priv *rtlpriv = rtl_priv(hw);
 351         u8 tmp_regcr, tmp_reg422;
 352         u8 bcnvalid_reg, txbc_reg;
 353         u8 count = 0, dlbcn_count = 0;
 354         bool b_recover = false;
 355
 356         /*Set REG_CR bit 8. DMA beacon by SW.*/
 357         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 358         rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0));
 359
 360         /* Disable Hw protection for a time which revserd for Hw sending beacon.
 361          * Fix download reserved page packet fail
 362          * that access collision with the protection time.
 363          * 2010.05.11. Added by tynli.
 364          */
 365         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 366         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
 367
 368         /* Set FWHW_TXQ_CTRL 0x422[6]=0 to
 369          * tell Hw the packet is not a real beacon frame.
 370          */
 371         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 372         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
 373
 374         if (tmp_reg422 & BIT(6))
 375                 b_recover = true;
 376
 377         do {
 378                 /* Clear beacon valid check bit */
 379                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
 380                 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2,
 381                                bcnvalid_reg | BIT(0));
 382
 383                 /* download rsvd page */
 384                 rtl92ee_set_fw_rsvdpagepkt(hw, false);
 385
 386                 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
 387                 count = 0;
 388                 while ((txbc_reg & BIT(4)) && count < 20) {
 389                         count++;
 390                         udelay(10);
 391                         txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
 392                 }
 393                 rtl_write_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3,
 394                                txbc_reg | BIT(4));
 395
 396                 /* check rsvd page download OK. */
 397                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
 398                 count = 0;
 399                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 400                         count++;
 401                         udelay(50);
 402                         bcnvalid_reg = rtl_read_byte(rtlpriv,
 403                                                      REG_DWBCN0_CTRL + 2);
 404                 }
 405
 406                 if (bcnvalid_reg & BIT(0))
 407                         rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0));
 408
 409                 dlbcn_count++;
 410         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 411
 412         if (!(bcnvalid_reg & BIT(0)))
 413                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 414                          "Download RSVD page failed!\n");
 415
 416         /* Enable Bcn */
 417         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 418         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
 419
 420         if (b_recover)
 421                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 422
 423         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 424         rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0)));
 425 }
 426
 427 void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 428 {
 429         struct rtl_priv *rtlpriv = rtl_priv(hw);
 430         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 431         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 432         struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw));
 433         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 434         u8 idx;
 435
 436         switch (variable) {
 437         case HW_VAR_ETHER_ADDR:
 438                 for (idx = 0; idx < ETH_ALEN; idx++)
 439                         rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
 440                 break;
 441         case HW_VAR_BASIC_RATE:{
 442                 u16 b_rate_cfg = ((u16 *)val)[0];
 443
 444                 b_rate_cfg = b_rate_cfg & 0x15f;
 445                 b_rate_cfg |= 0x01;
 446                 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1));
 447                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 448                 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
 449                 break; }
 450         case HW_VAR_BSSID:
 451                 for (idx = 0; idx < ETH_ALEN; idx++)
 452                         rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
 453                 break;
 454         case HW_VAR_SIFS:
 455                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 456                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 457
 458                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 459                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 460
 461                 if (!mac->ht_enable)
 462                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
 463                 else
 464                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 465                                        *((u16 *)val));
 466                 break;
 467         case HW_VAR_SLOT_TIME:{
 468                 u8 e_aci;
 469
 470                 RT_TRACE(rtlpriv, COMP_MLME, DBG_TRACE,
 471                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 472
 473                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 474
 475                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 476                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 477                                                       (u8 *)(&e_aci));
 478                 }
 479                 break; }
 480         case HW_VAR_ACK_PREAMBLE:{
 481                 u8 reg_tmp;
 482                 u8 short_preamble = (bool)(*(u8 *)val);
 483
 484                 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5;
 485                 if (short_preamble)
 486                         reg_tmp |= 0x80;
 487                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 488                 rtlpriv->mac80211.short_preamble = short_preamble;
 489                 }
 490                 break;
 491         case HW_VAR_WPA_CONFIG:
 492                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 493                 break;
 494         case HW_VAR_AMPDU_FACTOR:{
 495                 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 496                 u8 fac;
 497                 u8 *reg = NULL;
 498                 u8 i = 0;
 499
 500                 reg = regtoset_normal;
 501
 502                 fac = *((u8 *)val);
 503                 if (fac <= 3) {
 504                         fac = (1 << (fac + 2));
 505                         if (fac > 0xf)
 506                                 fac = 0xf;
 507                         for (i = 0; i < 4; i++) {
 508                                 if ((reg[i] & 0xf0) > (fac << 4))
 509                                         reg[i] = (reg[i] & 0x0f) |
 510                                                 (fac << 4);
 511                                 if ((reg[i] & 0x0f) > fac)
 512                                         reg[i] = (reg[i] & 0xf0) | fac;
 513                                 rtl_write_byte(rtlpriv,
 514                                                (REG_AGGLEN_LMT + i),
 515                                                reg[i]);
 516                         }
 517                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 518                                  "Set HW_VAR_AMPDU_FACTOR:%#x\n", fac);
 519                 }
 520                 }
 521                 break;
 522         case HW_VAR_AC_PARAM:{
 523                 u8 e_aci = *((u8 *)val);
 524
 525                 if (rtlpci->acm_method != EACMWAY2_SW)
 526                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 527                                                       (u8 *)(&e_aci));
 528                 }
 529                 break;
 530         case HW_VAR_ACM_CTRL:{
 531                 u8 e_aci = *((u8 *)val);
 532                 union aci_aifsn *aifs = (union aci_aifsn *)(&mac->ac[0].aifs);
 533
 534                 u8 acm = aifs->f.acm;
 535                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 536
 537                 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 538
 539                 if (acm) {
 540                         switch (e_aci) {
 541                         case AC0_BE:
 542                                 acm_ctrl |= ACMHW_BEQEN;
 543                                 break;
 544                         case AC2_VI:
 545                                 acm_ctrl |= ACMHW_VIQEN;
 546                                 break;
 547                         case AC3_VO:
 548                                 acm_ctrl |= ACMHW_VOQEN;
 549                                 break;
 550                         default:
 551                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 552                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 553                                          acm);
 554                                 break;
 555                         }
 556                 } else {
 557                         switch (e_aci) {
 558                         case AC0_BE:
 559                                 acm_ctrl &= (~ACMHW_BEQEN);
 560                                 break;
 561                         case AC2_VI:
 562                                 acm_ctrl &= (~ACMHW_VIQEN);
 563                                 break;
 564                         case AC3_VO:
 565                                 acm_ctrl &= (~ACMHW_VOQEN);
 566                                 break;
 567                         default:
 568                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
 569                                          "switch case not process\n");
 570                                 break;
 571                         }
 572                 }
 573
 574                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 575                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 576                           acm_ctrl);
 577                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 578                 }
 579                 break;
 580         case HW_VAR_RCR:{
 581                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 582                 rtlpci->receive_config = ((u32 *)(val))[0];
 583                 }
 584                 break;
 585         case HW_VAR_RETRY_LIMIT:{
 586                 u8 retry_limit = ((u8 *)(val))[0];
 587
 588                 rtl_write_word(rtlpriv, REG_RETRY_LIMIT,
 589                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 590                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 591                 }
 592                 break;
 593         case HW_VAR_DUAL_TSF_RST:
 594                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 595                 break;
 596         case HW_VAR_EFUSE_BYTES:
 597                 efuse->efuse_usedbytes = *((u16 *)val);
 598                 break;
 599         case HW_VAR_EFUSE_USAGE:
 600                 efuse->efuse_usedpercentage = *((u8 *)val);
 601                 break;
 602         case HW_VAR_IO_CMD:
 603                 rtl92ee_phy_set_io_cmd(hw, (*(enum io_type *)val));
 604                 break;
 605         case HW_VAR_SET_RPWM:{
 606                 u8 rpwm_val;
 607
 608                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 609                 udelay(1);
 610
 611                 if (rpwm_val & BIT(7)) {
 612                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
 613                 } else {
 614                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 615                                        ((*(u8 *)val) | BIT(7)));
 616                 }
 617                 }
 618                 break;
 619         case HW_VAR_H2C_FW_PWRMODE:
 620                 rtl92ee_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 621                 break;
 622         case HW_VAR_FW_PSMODE_STATUS:
 623                 ppsc->fw_current_inpsmode = *((bool *)val);
 624                 break;
 625         case HW_VAR_RESUME_CLK_ON:
 626                 _rtl92ee_set_fw_ps_rf_on(hw);
 627                 break;
 628         case HW_VAR_FW_LPS_ACTION:{
 629                 bool b_enter_fwlps = *((bool *)val);
 630
 631                 if (b_enter_fwlps)
 632                         _rtl92ee_fwlps_enter(hw);
 633                 else
 634                         _rtl92ee_fwlps_leave(hw);
 635                 }
 636                 break;
 637         case HW_VAR_H2C_FW_JOINBSSRPT:{
 638                 u8 mstatus = (*(u8 *)val);
 639
 640                 if (mstatus == RT_MEDIA_CONNECT) {
 641                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
 642                         _rtl92ee_download_rsvd_page(hw);
 643                 }
 644                 rtl92ee_set_fw_media_status_rpt_cmd(hw, mstatus);
 645                 }
 646                 break;
 647         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 648                 rtl92ee_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 649                 break;
 650         case HW_VAR_AID:{
 651                 u16 u2btmp;
 652
 653                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 654                 u2btmp &= 0xC000;
 655                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
 656                                (u2btmp | mac->assoc_id));
 657                 }
 658                 break;
 659         case HW_VAR_CORRECT_TSF:{
 660                 u8 btype_ibss = ((u8 *)(val))[0];
 661
 662                 if (btype_ibss)
 663                         _rtl92ee_stop_tx_beacon(hw);
 664
 665                 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 666
 667                 rtl_write_dword(rtlpriv, REG_TSFTR,
 668                                 (u32)(mac->tsf & 0xffffffff));
 669                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 670                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 671
 672                 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 673
 674                 if (btype_ibss)
 675                         _rtl92ee_resume_tx_beacon(hw);
 676                 }
 677                 break;
 678         case HW_VAR_KEEP_ALIVE: {
 679                 u8 array[2];
 680
 681                 array[0] = 0xff;
 682                 array[1] = *((u8 *)val);
 683                 rtl92ee_fill_h2c_cmd(hw, H2C_92E_KEEP_ALIVE_CTRL, 2, array);
 684                 }
 685                 break;
 686         default:
 687                 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
 688                          "switch case not process %x\n", variable);
 689                 break;
 690         }
 691 }
 692
 693 static bool _rtl92ee_llt_table_init(struct ieee80211_hw *hw)
 694 {
 695         struct rtl_priv *rtlpriv = rtl_priv(hw);
 696         u8 txpktbuf_bndy;
 697         u8 u8tmp, testcnt = 0;
 698
 699         txpktbuf_bndy = 0xFA;
 700
 701         rtl_write_dword(rtlpriv, REG_RQPN, 0x80E90808);
 702
 703         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 704         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1);
 705
 706         rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 1, txpktbuf_bndy);
 707         rtl_write_byte(rtlpriv, REG_DWBCN1_CTRL + 1, txpktbuf_bndy);
 708
 709         rtl_write_byte(rtlpriv, REG_BCNQ_BDNY, txpktbuf_bndy);
 710         rtl_write_byte(rtlpriv, REG_BCNQ1_BDNY, txpktbuf_bndy);
 711
 712         rtl_write_byte(rtlpriv, REG_MGQ_BDNY, txpktbuf_bndy);
 713         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 714
 715         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 716         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 717
 718         u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
 719         rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0));
 720
 721         while (u8tmp & BIT(0)) {
 722                 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
 723                 udelay(10);
 724                 testcnt++;
 725                 if (testcnt > 10)
 726                         break;
 727         }
 728
 729         return true;
 730 }
 731
 732 static void _rtl92ee_gen_refresh_led_state(struct ieee80211_hw *hw)
 733 {
 734         struct rtl_priv *rtlpriv = rtl_priv(hw);
 735         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 736         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 737         struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
 738
 739         if (rtlpriv->rtlhal.up_first_time)
 740                 return;
 741
 742         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 743                 rtl92ee_sw_led_on(hw, pled0);
 744         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 745                 rtl92ee_sw_led_on(hw, pled0);
 746         else
 747                 rtl92ee_sw_led_off(hw, pled0);
 748 }
 749
 750 static bool _rtl92ee_init_mac(struct ieee80211_hw *hw)
 751 {
 752         struct rtl_priv *rtlpriv = rtl_priv(hw);
 753         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 754         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 755
 756         u8 bytetmp;
 757         u16 wordtmp;
 758         u32 dwordtmp;
 759
 760         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
 761
 762         dwordtmp = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
 763         if (dwordtmp & BIT(24)) {
 764                 rtl_write_byte(rtlpriv, 0x7c, 0xc3);
 765         } else {
 766                 bytetmp = rtl_read_byte(rtlpriv, 0x16);
 767                 rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6));
 768                 rtl_write_byte(rtlpriv, 0x7c, 0x83);
 769         }
 770         /* 1. 40Mhz crystal source*/
 771         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
 772         bytetmp &= 0xfb;
 773         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
 774
 775         dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
 776         dwordtmp &= 0xfffffc7f;
 777         rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
 778
 779         /* 2. 92E AFE parameter
 780          * MP chip then check version
 781          */
 782         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
 783         bytetmp &= 0xbf;
 784         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
 785
 786         dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
 787         dwordtmp &= 0xffdfffff;
 788         rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
 789
 790         /* HW Power on sequence */
 791         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
 792                                       PWR_INTF_PCI_MSK,
 793                                       RTL8192E_NIC_ENABLE_FLOW)) {
 794                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 795                          "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
 796                 return false;
 797         }
 798
 799         /* Release MAC IO register reset */
 800         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 801         bytetmp = 0xff;
 802         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 803         mdelay(2);
 804         bytetmp = 0x7f;
 805         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 806         mdelay(2);
 807
 808         /* Add for wakeup online */
 809         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 810         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
 811         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 812         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
 813         /* Release MAC IO register reset */
 814         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 815
 816         if (!rtlhal->mac_func_enable) {
 817                 if (_rtl92ee_llt_table_init(hw) == false) {
 818                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 819                                  "LLT table init fail\n");
 820                         return false;
 821                 }
 822         }
 823
 824         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 825         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 826
 827         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 828         wordtmp &= 0xf;
 829         wordtmp |= 0xF5B1;
 830         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 831         /* Reported Tx status from HW for rate adaptive.*/
 832         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 833
 834         /* Set RCR register */
 835         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 836         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
 837
 838         /* Set TCR register */
 839         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 840
 841         /* Set TX/RX descriptor physical address(from OS API). */
 842         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 843                         ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &
 844                         DMA_BIT_MASK(32));
 845         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 846                         (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma &
 847                         DMA_BIT_MASK(32));
 848         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 849                         (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma &
 850                         DMA_BIT_MASK(32));
 851         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 852                         (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma &
 853                         DMA_BIT_MASK(32));
 854
 855         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 856                         (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma &
 857                         DMA_BIT_MASK(32));
 858
 859         dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_DESA);
 860
 861         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 862                         (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma &
 863                         DMA_BIT_MASK(32));
 864         rtl_write_dword(rtlpriv, REG_HQ0_DESA,
 865                         (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma &
 866                         DMA_BIT_MASK(32));
 867
 868         rtl_write_dword(rtlpriv, REG_RX_DESA,
 869                         (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 870                         DMA_BIT_MASK(32));
 871
 872         /* if we want to support 64 bit DMA, we should set it here,
 873          * but now we do not support 64 bit DMA
 874          */
 875
 876         rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0x3fffffff);
 877
 878         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
 879         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0xF7);
 880
 881         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 882
 883         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 884
 885         rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM,
 886                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 887         rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
 888                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 889         rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM,
 890                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 891         rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM,
 892                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 893         rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
 894                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 895         rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM,
 896                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 897         rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM,
 898                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 899         rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM,
 900                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 901         rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM,
 902                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 903         rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM,
 904                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 905         rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM,
 906                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 907         rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM,
 908                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 909         rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM,
 910                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 911         rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM,
 912                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 913         /*Rx*/
 914 #if (DMA_IS_64BIT == 1)
 915         rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
 916                        RX_DESC_NUM_92E |
 917                        ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x8000);
 918 #else
 919         rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
 920                        RX_DESC_NUM_92E |
 921                        ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x0000);
 922 #endif
 923
 924         rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF);
 925
 926         _rtl92ee_gen_refresh_led_state(hw);
 927         return true;
 928 }
 929
 930 static void _rtl92ee_hw_configure(struct ieee80211_hw *hw)
 931 {
 932         struct rtl_priv *rtlpriv = rtl_priv(hw);
 933         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 934         u32 reg_rrsr;
 935
 936         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 937         /* Init value for RRSR. */
 938         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
 939
 940         /* ARFB table 9 for 11ac 5G 2SS */
 941         rtl_write_dword(rtlpriv, REG_ARFR0, 0x00000010);
 942         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0x3e0ff000);
 943
 944         /* ARFB table 10 for 11ac 5G 1SS */
 945         rtl_write_dword(rtlpriv, REG_ARFR1, 0x00000010);
 946         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x000ff000);
 947
 948         /* Set SLOT time */
 949         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 950
 951         /* CF-End setting. */
 952         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 953
 954         /* Set retry limit */
 955         rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 0x0707);
 956
 957         /* BAR settings */
 958         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x0201ffff);
 959
 960         /* Set Data / Response auto rate fallack retry count */
 961         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 962         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 963         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 964         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 965
 966         /* Beacon related, for rate adaptive */
 967         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 968         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 969
 970         rtlpci->reg_bcn_ctrl_val = 0x1d;
 971         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 972
 973         /* Marked out by Bruce, 2010-09-09.
 974          * This register is configured for the 2nd Beacon (multiple BSSID).
 975          * We shall disable this register if we only support 1 BSSID.
 976          * vivi guess 92d also need this, also 92d now doesnot set this reg
 977          */
 978         rtl_write_byte(rtlpriv, REG_BCN_CTRL_1, 0);
 979
 980         /* TBTT prohibit hold time. Suggested by designer TimChen. */
 981         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
 982
 983         rtl_write_byte(rtlpriv, REG_PIFS, 0);
 984         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 985
 986         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
 987         rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x08ff);
 988
 989         /* For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
 990         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 991
 992         /* ACKTO for IOT issue. */
 993         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 994
 995         /* Set Spec SIFS (used in NAV) */
 996         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x100a);
 997         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x100a);
 998
 999         /* Set SIFS for CCK */
1000         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x100a);
1001
1002         /* Set SIFS for OFDM */
1003         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x100a);
1004
1005         /* Note Data sheet don't define */
1006         rtl_write_word(rtlpriv, 0x4C7, 0x80);
1007
1008         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1009
1010         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1717);
1011
1012         /* Set Multicast Address. 2009.01.07. by tynli. */
1013         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
1014         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
1015 }
1016
1017 static void _rtl92ee_enable_aspm_back_door(struct ieee80211_hw *hw)
1018 {
1019         struct rtl_priv *rtlpriv = rtl_priv(hw);
1020         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1021         u32 tmp32 = 0, count = 0;
1022         u8 tmp8 = 0;
1023
1024         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x78);
1025         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1026         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1027         count = 0;
1028         while (tmp8 && count < 20) {
1029                 udelay(10);
1030                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1031                 count++;
1032         }
1033
1034         if (0 == tmp8) {
1035                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1036                 if ((tmp32 & 0xff00) != 0x2000) {
1037                         tmp32 &= 0xffff00ff;
1038                         rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1039                                         tmp32 | BIT(13));
1040                         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf078);
1041                         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1042
1043                         tmp8 = rtl_read_byte(rtlpriv,
1044                                              REG_BACKDOOR_DBI_DATA + 2);
1045                         count = 0;
1046                         while (tmp8 && count < 20) {
1047                                 udelay(10);
1048                                 tmp8 = rtl_read_byte(rtlpriv,
1049                                                      REG_BACKDOOR_DBI_DATA + 2);
1050                                 count++;
1051                         }
1052                 }
1053         }
1054
1055         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x70c);
1056         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1057         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1058         count = 0;
1059         while (tmp8 && count < 20) {
1060                 udelay(10);
1061                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1062                 count++;
1063         }
1064         if (0 == tmp8) {
1065                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1066                 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1067                                 tmp32 | BIT(31));
1068                 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf70c);
1069                 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1070         }
1071
1072         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1073         count = 0;
1074         while (tmp8 && count < 20) {
1075                 udelay(10);
1076                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1077                 count++;
1078         }
1079
1080         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x718);
1081         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1082         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1083         count = 0;
1084         while (tmp8 && count < 20) {
1085                 udelay(10);
1086                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1087                 count++;
1088         }
1089         if (ppsc->support_backdoor || (0 == tmp8)) {
1090                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1091                 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1092                                 tmp32 | BIT(11) | BIT(12));
1093                 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf718);
1094                 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1095         }
1096         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1097         count = 0;
1098         while (tmp8 && count < 20) {
1099                 udelay(10);
1100                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1101                 count++;
1102         }
1103 }
1104
1105 void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw)
1106 {
1107         struct rtl_priv *rtlpriv = rtl_priv(hw);
1108         u8 sec_reg_value;
1109         u8 tmp;
1110
1111         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1112                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1113                   rtlpriv->sec.pairwise_enc_algorithm,
1114                   rtlpriv->sec.group_enc_algorithm);
1115
1116         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1117                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1118                          "not open hw encryption\n");
1119                 return;
1120         }
1121
1122         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1123
1124         if (rtlpriv->sec.use_defaultkey) {
1125                 sec_reg_value |= SCR_TXUSEDK;
1126                 sec_reg_value |= SCR_RXUSEDK;
1127         }
1128
1129         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1130
1131         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1132         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1133
1134         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1135                  "The SECR-value %x\n", sec_reg_value);
1136
1137         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1138 }
1139
1140 static bool _rtl8192ee_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1141 {
1142         u8 tmp;
1143
1144         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1145         tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3);
1146         if (!(tmp & BIT(2))) {
1147                 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3,
1148                                tmp | BIT(2));
1149                 mdelay(100); /* Suggested by DD Justin_tsai. */
1150         }
1151
1152         /* read reg 0x350 Bit[25] if 1 : RX hang
1153          * read reg 0x350 Bit[24] if 1 : TX hang
1154          */
1155         tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3);
1156         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1157                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1158                          "CheckPcieDMAHang8192EE(): true!!\n");
1159                 return true;
1160         }
1161         return false;
1162 }
1163
1164 static void _rtl8192ee_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1165                                                 bool mac_power_on)
1166 {
1167         u8 tmp;
1168         bool release_mac_rx_pause;
1169         u8 backup_pcie_dma_pause;
1170
1171         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1172                  "ResetPcieInterfaceDMA8192EE()\n");
1173
1174         /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1175          * released by SD1 Alan.
1176          */
1177
1178         /* 1. disable register write lock
1179          *      write 0x1C bit[1:0] = 2'h0
1180          *      write 0xCC bit[2] = 1'b1
1181          */
1182         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1183         tmp &= ~(BIT(1) | BIT(0));
1184         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1185         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1186         tmp |= BIT(2);
1187         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1188
1189         /* 2. Check and pause TRX DMA
1190          *      write 0x284 bit[18] = 1'b1
1191          *      write 0x301 = 0xFF
1192          */
1193         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1194         if (tmp & BIT(2)) {
1195                 /* Already pause before the function for another reason. */
1196                 release_mac_rx_pause = false;
1197         } else {
1198                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1199                 release_mac_rx_pause = true;
1200         }
1201
1202         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1203         if (backup_pcie_dma_pause != 0xFF)
1204                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1205
1206         if (mac_power_on) {
1207                 /* 3. reset TRX function
1208                  *      write 0x100 = 0x00
1209                  */
1210                 rtl_write_byte(rtlpriv, REG_CR, 0);
1211         }
1212
1213         /* 4. Reset PCIe DMA
1214          *      write 0x003 bit[0] = 0
1215          */
1216         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1217         tmp &= ~(BIT(0));
1218         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1219
1220         /* 5. Enable PCIe DMA
1221          *      write 0x003 bit[0] = 1
1222          */
1223         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1224         tmp |= BIT(0);
1225         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1226
1227         if (mac_power_on) {
1228                 /* 6. enable TRX function
1229                  *      write 0x100 = 0xFF
1230                  */
1231                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1232
1233                 /* We should init LLT & RQPN and
1234                  * prepare Tx/Rx descrptor address later
1235                  * because MAC function is reset.
1236                  */
1237         }
1238
1239         /* 7. Restore PCIe autoload down bit
1240          *      write 0xF8 bit[17] = 1'b1
1241          */
1242         tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1243         tmp |= BIT(1);
1244         rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1245
1246         /* In MAC power on state, BB and RF maybe in ON state,
1247          * if we release TRx DMA here
1248          * it will cause packets to be started to Tx/Rx,
1249          * so we release Tx/Rx DMA later.
1250          */
1251         if (!mac_power_on) {
1252                 /* 8. release TRX DMA
1253                  *      write 0x284 bit[18] = 1'b0
1254                  *      write 0x301 = 0x00
1255                  */
1256                 if (release_mac_rx_pause) {
1257                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1258                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1259                                        (tmp & (~BIT(2))));
1260                 }
1261                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1262                                backup_pcie_dma_pause);
1263         }
1264
1265         /* 9. lock system register
1266          *      write 0xCC bit[2] = 1'b0
1267          */
1268         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1269         tmp &= ~(BIT(2));
1270         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1271 }
1272
1273 int rtl92ee_hw_init(struct ieee80211_hw *hw)
1274 {
1275         struct rtl_priv *rtlpriv = rtl_priv(hw);
1276         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1277         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1278         struct rtl_phy *rtlphy = &rtlpriv->phy;
1279         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1280         bool rtstatus = true;
1281         int err = 0;
1282         u8 tmp_u1b, u1byte;
1283         u32 tmp_u4b;
1284
1285         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n");
1286         rtlpriv->rtlhal.being_init_adapter = true;
1287         rtlpriv->intf_ops->disable_aspm(hw);
1288
1289         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1290         u1byte = rtl_read_byte(rtlpriv, REG_CR);
1291         if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1292                 rtlhal->mac_func_enable = true;
1293         } else {
1294                 rtlhal->mac_func_enable = false;
1295                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1296         }
1297
1298         if (_rtl8192ee_check_pcie_dma_hang(rtlpriv)) {
1299                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "92ee dma hang!\n");
1300                 _rtl8192ee_reset_pcie_interface_dma(rtlpriv,
1301                                                     rtlhal->mac_func_enable);
1302                 rtlhal->mac_func_enable = false;
1303         }
1304
1305         rtstatus = _rtl92ee_init_mac(hw);
1306
1307         rtl_write_byte(rtlpriv, 0x577, 0x03);
1308
1309         /*for Crystal 40 Mhz setting */
1310         rtl_write_byte(rtlpriv, REG_AFE_CTRL4, 0x2A);
1311         rtl_write_byte(rtlpriv, REG_AFE_CTRL4 + 1, 0x00);
1312         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, 0x83);
1313
1314         /*Forced the antenna b to wifi */
1315         if (rtlpriv->btcoexist.btc_info.btcoexist == 1) {
1316                 rtl_write_byte(rtlpriv, 0x64, 0);
1317                 rtl_write_byte(rtlpriv, 0x65, 1);
1318         }
1319         if (!rtstatus) {
1320                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1321                 err = 1;
1322                 return err;
1323         }
1324         rtlhal->rx_tag = 0;
1325         rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000);
1326         err = rtl92ee_download_fw(hw, false);
1327         if (err) {
1328                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1329                          "Failed to download FW. Init HW without FW now..\n");
1330                 err = 1;
1331                 rtlhal->fw_ready = false;
1332                 return err;
1333         }
1334         rtlhal->fw_ready = true;
1335         /*fw related variable initialize */
1336         ppsc->fw_current_inpsmode = false;
1337         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1338         rtlhal->fw_clk_change_in_progress = false;
1339         rtlhal->allow_sw_to_change_hwclc = false;
1340         rtlhal->last_hmeboxnum = 0;
1341
1342         rtl92ee_phy_mac_config(hw);
1343
1344         rtl92ee_phy_bb_config(hw);
1345
1346         rtl92ee_phy_rf_config(hw);
1347
1348         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A,
1349                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1350         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B,
1351                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1352         rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
1353                                                     RFREG_OFFSET_MASK);
1354         rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) |
1355                                    BIT(10) | BIT(11);
1356
1357         rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
1358                       rtlphy->rfreg_chnlval[0]);
1359         rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
1360                       rtlphy->rfreg_chnlval[0]);
1361
1362         /*---- Set CCK and OFDM Block "ON"----*/
1363         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1364         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1365
1366         /* Must set this,
1367          * otherwise the rx sensitivity will be very pool. Maddest
1368          */
1369         rtl_set_rfreg(hw, RF90_PATH_A, 0xB1, RFREG_OFFSET_MASK, 0x54418);
1370
1371         /*Set Hardware(MAC default setting.)*/
1372         _rtl92ee_hw_configure(hw);
1373
1374         rtlhal->mac_func_enable = true;
1375
1376         rtl_cam_reset_all_entry(hw);
1377         rtl92ee_enable_hw_security_config(hw);
1378
1379         ppsc->rfpwr_state = ERFON;
1380
1381         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1382         _rtl92ee_enable_aspm_back_door(hw);
1383         rtlpriv->intf_ops->enable_aspm(hw);
1384
1385         rtl92ee_bt_hw_init(hw);
1386
1387         rtlpriv->rtlhal.being_init_adapter = false;
1388
1389         if (ppsc->rfpwr_state == ERFON) {
1390                 if (rtlphy->iqk_initialized) {
1391                         rtl92ee_phy_iq_calibrate(hw, true);
1392                 } else {
1393                         rtl92ee_phy_iq_calibrate(hw, false);
1394                         rtlphy->iqk_initialized = true;
1395                 }
1396         }
1397
1398         rtlphy->rfpath_rx_enable[0] = true;
1399         if (rtlphy->rf_type == RF_2T2R)
1400                 rtlphy->rfpath_rx_enable[1] = true;
1401
1402         efuse_one_byte_read(hw, 0x1FA, &tmp_u1b);
1403         if (!(tmp_u1b & BIT(0))) {
1404                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1405                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1406         }
1407
1408         if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) {
1409                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1410                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path B\n");
1411         }
1412
1413         rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1414
1415         /*Fixed LDPC rx hang issue. */
1416         tmp_u4b = rtl_read_dword(rtlpriv, REG_SYS_SWR_CTRL1);
1417         rtl_write_byte(rtlpriv, REG_SYS_SWR_CTRL2, 0x75);
1418         tmp_u4b =  (tmp_u4b & 0xfff00fff) | (0x7E << 12);
1419         rtl_write_dword(rtlpriv, REG_SYS_SWR_CTRL1, tmp_u4b);
1420
1421         rtl92ee_dm_init(hw);
1422
1423         rtl_write_dword(rtlpriv, 0x4fc, 0);
1424
1425         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1426                  "end of Rtl8192EE hw init %x\n", err);
1427         return 0;
1428 }
1429
1430 static enum version_8192e _rtl92ee_read_chip_version(struct ieee80211_hw *hw)
1431 {
1432         struct rtl_priv *rtlpriv = rtl_priv(hw);
1433         struct rtl_phy *rtlphy = &rtlpriv->phy;
1434         enum version_8192e version = VERSION_UNKNOWN;
1435         u32 value32;
1436
1437         rtlphy->rf_type = RF_2T2R;
1438
1439         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1440         if (value32 & TRP_VAUX_EN)
1441                 version = (enum version_8192e)VERSION_TEST_CHIP_2T2R_8192E;
1442         else
1443                 version = (enum version_8192e)VERSION_NORMAL_CHIP_2T2R_8192E;
1444
1445         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1446                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1447                   "RF_2T2R" : "RF_1T1R");
1448
1449         return version;
1450 }
1451
1452 static int _rtl92ee_set_media_status(struct ieee80211_hw *hw,
1453                                      enum nl80211_iftype type)
1454 {
1455         struct rtl_priv *rtlpriv = rtl_priv(hw);
1456         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1457         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1458         u8 mode = MSR_NOLINK;
1459
1460         switch (type) {
1461         case NL80211_IFTYPE_UNSPECIFIED:
1462                 mode = MSR_NOLINK;
1463                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1464                          "Set Network type to NO LINK!\n");
1465                 break;
1466         case NL80211_IFTYPE_ADHOC:
1467         case NL80211_IFTYPE_MESH_POINT:
1468                 mode = MSR_ADHOC;
1469                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1470                          "Set Network type to Ad Hoc!\n");
1471                 break;
1472         case NL80211_IFTYPE_STATION:
1473                 mode = MSR_INFRA;
1474                 ledaction = LED_CTL_LINK;
1475                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1476                          "Set Network type to STA!\n");
1477                 break;
1478         case NL80211_IFTYPE_AP:
1479                 mode = MSR_AP;
1480                 ledaction = LED_CTL_LINK;
1481                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1482                          "Set Network type to AP!\n");
1483                 break;
1484         default:
1485                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1486                          "Network type %d not support!\n", type);
1487                 return 1;
1488         }
1489
1490         /* MSR_INFRA == Link in infrastructure network;
1491          * MSR_ADHOC == Link in ad hoc network;
1492          * Therefore, check link state is necessary.
1493          *
1494          * MSR_AP == AP mode; link state is not cared here.
1495          */
1496         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1497                 mode = MSR_NOLINK;
1498                 ledaction = LED_CTL_NO_LINK;
1499         }
1500
1501         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1502                 _rtl92ee_stop_tx_beacon(hw);
1503                 _rtl92ee_enable_bcn_sub_func(hw);
1504         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1505                 _rtl92ee_resume_tx_beacon(hw);
1506                 _rtl92ee_disable_bcn_sub_func(hw);
1507         } else {
1508                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1509                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1510                          mode);
1511         }
1512
1513         rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1514         rtlpriv->cfg->ops->led_control(hw, ledaction);
1515         if (mode == MSR_AP)
1516                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1517         else
1518                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1519         return 0;
1520 }
1521
1522 void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1523 {
1524         struct rtl_priv *rtlpriv = rtl_priv(hw);
1525         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1526         u32 reg_rcr = rtlpci->receive_config;
1527
1528         if (rtlpriv->psc.rfpwr_state != ERFON)
1529                 return;
1530
1531         if (check_bssid) {
1532                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1533                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1534                                               (u8 *)(&reg_rcr));
1535                 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1536         } else {
1537                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1538                 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1539                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1540                                               (u8 *)(&reg_rcr));
1541         }
1542 }
1543
1544 int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1545 {
1546         struct rtl_priv *rtlpriv = rtl_priv(hw);
1547
1548         if (_rtl92ee_set_media_status(hw, type))
1549                 return -EOPNOTSUPP;
1550
1551         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1552                 if (type != NL80211_IFTYPE_AP &&
1553                     type != NL80211_IFTYPE_MESH_POINT)
1554                         rtl92ee_set_check_bssid(hw, true);
1555         } else {
1556                 rtl92ee_set_check_bssid(hw, false);
1557         }
1558
1559         return 0;
1560 }
1561
1562 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1563 void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci)
1564 {
1565         struct rtl_priv *rtlpriv = rtl_priv(hw);
1566
1567         rtl92ee_dm_init_edca_turbo(hw);
1568         switch (aci) {
1569         case AC1_BK:
1570                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1571                 break;
1572         case AC0_BE:
1573                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1574                 break;
1575         case AC2_VI:
1576                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1577                 break;
1578         case AC3_VO:
1579                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1580                 break;
1581         default:
1582                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1583                 break;
1584         }
1585 }
1586
1587 static void rtl92ee_clear_interrupt(struct ieee80211_hw *hw)
1588 {
1589         struct rtl_priv *rtlpriv = rtl_priv(hw);
1590         u32 tmp;
1591
1592         tmp = rtl_read_dword(rtlpriv, REG_HISR);
1593         rtl_write_dword(rtlpriv, REG_HISR, tmp);
1594
1595         tmp = rtl_read_dword(rtlpriv, REG_HISRE);
1596         rtl_write_dword(rtlpriv, REG_HISRE, tmp);
1597
1598         tmp = rtl_read_dword(rtlpriv, REG_HSISR);
1599         rtl_write_dword(rtlpriv, REG_HSISR, tmp);
1600 }
1601
1602 void rtl92ee_enable_interrupt(struct ieee80211_hw *hw)
1603 {
1604         struct rtl_priv *rtlpriv = rtl_priv(hw);
1605         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1606
1607         rtl92ee_clear_interrupt(hw);/*clear it here first*/
1608
1609         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1610         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1611         rtlpci->irq_enabled = true;
1612 }
1613
1614 void rtl92ee_disable_interrupt(struct ieee80211_hw *hw)
1615 {
1616         struct rtl_priv *rtlpriv = rtl_priv(hw);
1617         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1618
1619         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1620         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1621         rtlpci->irq_enabled = false;
1622         /*synchronize_irq(rtlpci->pdev->irq);*/
1623 }
1624
1625 static void _rtl92ee_poweroff_adapter(struct ieee80211_hw *hw)
1626 {
1627         struct rtl_priv *rtlpriv = rtl_priv(hw);
1628         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1629         u8 u1b_tmp;
1630
1631         rtlhal->mac_func_enable = false;
1632
1633         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1634
1635         /* Run LPS WL RFOFF flow */
1636         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1637                                  PWR_INTF_PCI_MSK, RTL8192E_NIC_LPS_ENTER_FLOW);
1638         /* turn off RF */
1639         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1640
1641         /* ==== Reset digital sequence   ======  */
1642         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1643                 rtl92ee_firmware_selfreset(hw);
1644
1645         /* Reset MCU  */
1646         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1647         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1648
1649         /* reset MCU ready status */
1650         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1651
1652         /* HW card disable configuration. */
1653         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1654                                  PWR_INTF_PCI_MSK, RTL8192E_NIC_DISABLE_FLOW);
1655
1656         /* Reset MCU IO Wrapper */
1657         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1658         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1659         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1660         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0)));
1661
1662         /* lock ISO/CLK/Power control register */
1663         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1664 }
1665
1666 void rtl92ee_card_disable(struct ieee80211_hw *hw)
1667 {
1668         struct rtl_priv *rtlpriv = rtl_priv(hw);
1669         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1670         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1671         enum nl80211_iftype opmode;
1672
1673         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n");
1674
1675         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1676
1677         mac->link_state = MAC80211_NOLINK;
1678         opmode = NL80211_IFTYPE_UNSPECIFIED;
1679
1680         _rtl92ee_set_media_status(hw, opmode);
1681
1682         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1683             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1684                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1685
1686         _rtl92ee_poweroff_adapter(hw);
1687
1688         /* after power off we should do iqk again */
1689         rtlpriv->phy.iqk_initialized = false;
1690 }
1691
1692 void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw,
1693                                   u32 *p_inta, u32 *p_intb)
1694 {
1695         struct rtl_priv *rtlpriv = rtl_priv(hw);
1696         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1697
1698         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1699         rtl_write_dword(rtlpriv, ISR, *p_inta);
1700
1701         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1702         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1703 }
1704
1705 void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1706 {
1707         struct rtl_priv *rtlpriv = rtl_priv(hw);
1708         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1709         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1710         u16 bcn_interval, atim_window;
1711
1712         bcn_interval = mac->beacon_interval;
1713         atim_window = 2;        /*FIX MERGE */
1714         rtl92ee_disable_interrupt(hw);
1715         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1716         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1717         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1718         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1719         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1720         rtl_write_byte(rtlpriv, 0x606, 0x30);
1721         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1722         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
1723 }
1724
1725 void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw)
1726 {
1727         struct rtl_priv *rtlpriv = rtl_priv(hw);
1728         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1729         u16 bcn_interval = mac->beacon_interval;
1730
1731         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1732                  "beacon_interval:%d\n", bcn_interval);
1733         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1734 }
1735
1736 void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw,
1737                                    u32 add_msr, u32 rm_msr)
1738 {
1739         struct rtl_priv *rtlpriv = rtl_priv(hw);
1740         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1741
1742         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1743                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1744
1745         if (add_msr)
1746                 rtlpci->irq_mask[0] |= add_msr;
1747         if (rm_msr)
1748                 rtlpci->irq_mask[0] &= (~rm_msr);
1749         rtl92ee_disable_interrupt(hw);
1750         rtl92ee_enable_interrupt(hw);
1751 }
1752
1753 static u8 _rtl92ee_get_chnl_group(u8 chnl)
1754 {
1755         u8 group = 0;
1756
1757         if (chnl <= 14) {
1758                 if (1 <= chnl && chnl <= 2)
1759                         group = 0;
1760                 else if (3 <= chnl && chnl <= 5)
1761                         group = 1;
1762                 else if (6 <= chnl && chnl <= 8)
1763                         group = 2;
1764                 else if (9 <= chnl && chnl <= 11)
1765                         group = 3;
1766                 else if (12 <= chnl && chnl <= 14)
1767                         group = 4;
1768         } else {
1769                 if (36 <= chnl && chnl <= 42)
1770                         group = 0;
1771                 else if (44 <= chnl && chnl <= 48)
1772                         group = 1;
1773                 else if (50 <= chnl && chnl <= 58)
1774                         group = 2;
1775                 else if (60 <= chnl && chnl <= 64)
1776                         group = 3;
1777                 else if (100 <= chnl && chnl <= 106)
1778                         group = 4;
1779                 else if (108 <= chnl && chnl <= 114)
1780                         group = 5;
1781                 else if (116 <= chnl && chnl <= 122)
1782                         group = 6;
1783                 else if (124 <= chnl && chnl <= 130)
1784                         group = 7;
1785                 else if (132 <= chnl && chnl <= 138)
1786                         group = 8;
1787                 else if (140 <= chnl && chnl <= 144)
1788                         group = 9;
1789                 else if (149 <= chnl && chnl <= 155)
1790                         group = 10;
1791                 else if (157 <= chnl && chnl <= 161)
1792                         group = 11;
1793                 else if (165 <= chnl && chnl <= 171)
1794                         group = 12;
1795                 else if (173 <= chnl && chnl <= 177)
1796                         group = 13;
1797         }
1798         return group;
1799 }
1800
1801 static void _rtl8192ee_read_power_value_fromprom(struct ieee80211_hw *hw,
1802                                                  struct txpower_info_2g *pwr2g,
1803                                                  struct txpower_info_5g *pwr5g,
1804                                                  bool autoload_fail, u8 *hwinfo)
1805 {
1806         struct rtl_priv *rtlpriv = rtl_priv(hw);
1807         u32 rf, addr = EEPROM_TX_PWR_INX, group, i = 0;
1808
1809         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1810                  "hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]=0x%x\n",
1811                  (addr + 1), hwinfo[addr + 1]);
1812         if (0xFF == hwinfo[addr+1])  /*YJ,add,120316*/
1813                 autoload_fail = true;
1814
1815         if (autoload_fail) {
1816                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1817                          "auto load fail : Use Default value!\n");
1818                 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1819                         /* 2.4G default value */
1820                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1821                                 pwr2g->index_cck_base[rf][group] = 0x2D;
1822                                 pwr2g->index_bw40_base[rf][group] = 0x2D;
1823                         }
1824                         for (i = 0; i < MAX_TX_COUNT; i++) {
1825                                 if (i == 0) {
1826                                         pwr2g->bw20_diff[rf][0] = 0x02;
1827                                         pwr2g->ofdm_diff[rf][0] = 0x04;
1828                                 } else {
1829                                         pwr2g->bw20_diff[rf][i] = 0xFE;
1830                                         pwr2g->bw40_diff[rf][i] = 0xFE;
1831                                         pwr2g->cck_diff[rf][i] = 0xFE;
1832                                         pwr2g->ofdm_diff[rf][i] = 0xFE;
1833                                 }
1834                         }
1835
1836                         /*5G default value*/
1837                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
1838                                 pwr5g->index_bw40_base[rf][group] = 0x2A;
1839
1840                         for (i = 0; i < MAX_TX_COUNT; i++) {
1841                                 if (i == 0) {
1842                                         pwr5g->ofdm_diff[rf][0] = 0x04;
1843                                         pwr5g->bw20_diff[rf][0] = 0x00;
1844                                         pwr5g->bw80_diff[rf][0] = 0xFE;
1845                                         pwr5g->bw160_diff[rf][0] = 0xFE;
1846                                 } else {
1847                                         pwr5g->ofdm_diff[rf][0] = 0xFE;
1848                                         pwr5g->bw20_diff[rf][0] = 0xFE;
1849                                         pwr5g->bw40_diff[rf][0] = 0xFE;
1850                                         pwr5g->bw80_diff[rf][0] = 0xFE;
1851                                         pwr5g->bw160_diff[rf][0] = 0xFE;
1852                                 }
1853                         }
1854                 }
1855                 return;
1856         }
1857
1858         rtl_priv(hw)->efuse.txpwr_fromeprom = true;
1859
1860         for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1861                 /*2.4G default value*/
1862                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1863                         pwr2g->index_cck_base[rf][group] = hwinfo[addr++];
1864                         if (pwr2g->index_cck_base[rf][group] == 0xFF)
1865                                 pwr2g->index_cck_base[rf][group] = 0x2D;
1866                 }
1867                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
1868                         pwr2g->index_bw40_base[rf][group] = hwinfo[addr++];
1869                         if (pwr2g->index_bw40_base[rf][group] == 0xFF)
1870                                 pwr2g->index_bw40_base[rf][group] = 0x2D;
1871                 }
1872                 for (i = 0; i < MAX_TX_COUNT; i++) {
1873                         if (i == 0) {
1874                                 pwr2g->bw40_diff[rf][i] = 0;
1875                                 if (hwinfo[addr] == 0xFF) {
1876                                         pwr2g->bw20_diff[rf][i] = 0x02;
1877                                 } else {
1878                                         pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1879                                                                    & 0xf0) >> 4;
1880                                         if (pwr2g->bw20_diff[rf][i] & BIT(3))
1881                                                 pwr2g->bw20_diff[rf][i] |= 0xF0;
1882                                 }
1883
1884                                 if (hwinfo[addr] == 0xFF) {
1885                                         pwr2g->ofdm_diff[rf][i] = 0x04;
1886                                 } else {
1887                                         pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1888                                                                    & 0x0f);
1889                                         if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1890                                                 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1891                                 }
1892                                 pwr2g->cck_diff[rf][i] = 0;
1893                                 addr++;
1894                         } else {
1895                                 if (hwinfo[addr] == 0xFF) {
1896                                         pwr2g->bw40_diff[rf][i] = 0xFE;
1897                                 } else {
1898                                         pwr2g->bw40_diff[rf][i] = (hwinfo[addr]
1899                                                                    & 0xf0) >> 4;
1900                                         if (pwr2g->bw40_diff[rf][i] & BIT(3))
1901                                                 pwr2g->bw40_diff[rf][i] |= 0xF0;
1902                                 }
1903
1904                                 if (hwinfo[addr] == 0xFF) {
1905                                         pwr2g->bw20_diff[rf][i] = 0xFE;
1906                                 } else {
1907                                         pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1908                                                                    & 0x0f);
1909                                         if (pwr2g->bw20_diff[rf][i] & BIT(3))
1910                                                 pwr2g->bw20_diff[rf][i] |= 0xF0;
1911                                 }
1912                                 addr++;
1913
1914                                 if (hwinfo[addr] == 0xFF) {
1915                                         pwr2g->ofdm_diff[rf][i] = 0xFE;
1916                                 } else {
1917                                         pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1918                                                                    & 0xf0) >> 4;
1919                                         if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1920                                                 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1921                                 }
1922
1923                                 if (hwinfo[addr] == 0xFF) {
1924                                         pwr2g->cck_diff[rf][i] = 0xFE;
1925                                 } else {
1926                                         pwr2g->cck_diff[rf][i] = (hwinfo[addr]
1927                                                                   & 0x0f);
1928                                         if (pwr2g->cck_diff[rf][i] & BIT(3))
1929                                                 pwr2g->cck_diff[rf][i] |= 0xF0;
1930                                 }
1931                                 addr++;
1932                         }
1933                 }
1934
1935                 /*5G default value*/
1936                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1937                         pwr5g->index_bw40_base[rf][group] = hwinfo[addr++];
1938                         if (pwr5g->index_bw40_base[rf][group] == 0xFF)
1939                                 pwr5g->index_bw40_base[rf][group] = 0xFE;
1940                 }
1941
1942                 for (i = 0; i < MAX_TX_COUNT; i++) {
1943                         if (i == 0) {
1944                                 pwr5g->bw40_diff[rf][i] = 0;
1945
1946                                 if (hwinfo[addr] == 0xFF) {
1947                                         pwr5g->bw20_diff[rf][i] = 0;
1948                                 } else {
1949                                         pwr5g->bw20_diff[rf][0] = (hwinfo[addr]
1950                                                                    & 0xf0) >> 4;
1951                                         if (pwr5g->bw20_diff[rf][i] & BIT(3))
1952                                                 pwr5g->bw20_diff[rf][i] |= 0xF0;
1953                                 }
1954
1955                                 if (hwinfo[addr] == 0xFF) {
1956                                         pwr5g->ofdm_diff[rf][i] = 0x04;
1957                                 } else {
1958                                         pwr5g->ofdm_diff[rf][0] = (hwinfo[addr]
1959                                                                    & 0x0f);
1960                                         if (pwr5g->ofdm_diff[rf][i] & BIT(3))
1961                                                 pwr5g->ofdm_diff[rf][i] |= 0xF0;
1962                                 }
1963                                 addr++;
1964                         } else {
1965                                 if (hwinfo[addr] == 0xFF) {
1966                                         pwr5g->bw40_diff[rf][i] = 0xFE;
1967                                 } else {
1968                                         pwr5g->bw40_diff[rf][i] = (hwinfo[addr]
1969                                                                   & 0xf0) >> 4;
1970                                         if (pwr5g->bw40_diff[rf][i] & BIT(3))
1971                                                 pwr5g->bw40_diff[rf][i] |= 0xF0;
1972                                 }
1973
1974                                 if (hwinfo[addr] == 0xFF) {
1975                                         pwr5g->bw20_diff[rf][i] = 0xFE;
1976                                 } else {
1977                                         pwr5g->bw20_diff[rf][i] = (hwinfo[addr]
1978                                                                    & 0x0f);
1979                                         if (pwr5g->bw20_diff[rf][i] & BIT(3))
1980                                                 pwr5g->bw20_diff[rf][i] |= 0xF0;
1981                                 }
1982                                 addr++;
1983                         }
1984                 }
1985
1986                 if (hwinfo[addr] == 0xFF) {
1987                         pwr5g->ofdm_diff[rf][1] = 0xFE;
1988                         pwr5g->ofdm_diff[rf][2] = 0xFE;
1989                 } else {
1990                         pwr5g->ofdm_diff[rf][1] = (hwinfo[addr] & 0xf0) >> 4;
1991                         pwr5g->ofdm_diff[rf][2] = (hwinfo[addr] & 0x0f);
1992                 }
1993                 addr++;
1994
1995                 if (hwinfo[addr] == 0xFF)
1996                         pwr5g->ofdm_diff[rf][3] = 0xFE;
1997                 else
1998                         pwr5g->ofdm_diff[rf][3] = (hwinfo[addr] & 0x0f);
1999                 addr++;
2000
2001                 for (i = 1; i < MAX_TX_COUNT; i++) {
2002                         if (pwr5g->ofdm_diff[rf][i] == 0xFF)
2003                                 pwr5g->ofdm_diff[rf][i] = 0xFE;
2004                         else if (pwr5g->ofdm_diff[rf][i] & BIT(3))
2005                                 pwr5g->ofdm_diff[rf][i] |= 0xF0;
2006                 }
2007
2008                 for (i = 0; i < MAX_TX_COUNT; i++) {
2009                         if (hwinfo[addr] == 0xFF) {
2010                                 pwr5g->bw80_diff[rf][i] = 0xFE;
2011                         } else {
2012                                 pwr5g->bw80_diff[rf][i] = (hwinfo[addr] & 0xf0)
2013                                                           >> 4;
2014                                 if (pwr5g->bw80_diff[rf][i] & BIT(3))
2015                                         pwr5g->bw80_diff[rf][i] |= 0xF0;
2016                         }
2017
2018                         if (hwinfo[addr] == 0xFF) {
2019                                 pwr5g->bw160_diff[rf][i] = 0xFE;
2020                         } else {
2021                                 pwr5g->bw160_diff[rf][i] =
2022                                   (hwinfo[addr] & 0x0f);
2023                                 if (pwr5g->bw160_diff[rf][i] & BIT(3))
2024                                         pwr5g->bw160_diff[rf][i] |= 0xF0;
2025                         }
2026                         addr++;
2027                 }
2028         }
2029 }
2030
2031 static void _rtl92ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2032                                                  bool autoload_fail, u8 *hwinfo)
2033 {
2034         struct rtl_priv *rtlpriv = rtl_priv(hw);
2035         struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw));
2036         struct txpower_info_2g pwr2g;
2037         struct txpower_info_5g pwr5g;
2038         u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2039                 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2040                 56, 58, 60, 62, 64, 100, 102, 104, 106,
2041                 108, 110, 112, 114, 116, 118, 120, 122,
2042                 124, 126, 128, 130, 132, 134, 136, 138,
2043                 140, 142, 144, 149, 151, 153, 155, 157,
2044                 159, 161, 163, 165, 167, 168, 169, 171,
2045                 173, 175, 177
2046         };
2047         u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
2048                 42, 58, 106, 122, 138, 155, 171
2049         };
2050         u8 rf, idx;
2051         u8 i;
2052
2053         _rtl8192ee_read_power_value_fromprom(hw, &pwr2g, &pwr5g,
2054                                              autoload_fail, hwinfo);
2055
2056         for (rf = 0; rf < MAX_RF_PATH; rf++) {
2057                 for (i = 0; i < 14; i++) {
2058                         idx = _rtl92ee_get_chnl_group(i + 1);
2059
2060                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2061                                 efu->txpwrlevel_cck[rf][i] =
2062                                                 pwr2g.index_cck_base[rf][5];
2063                                 efu->txpwrlevel_ht40_1s[rf][i] =
2064                                                 pwr2g.index_bw40_base[rf][idx];
2065                         } else {
2066                                 efu->txpwrlevel_cck[rf][i] =
2067                                                 pwr2g.index_cck_base[rf][idx];
2068                                 efu->txpwrlevel_ht40_1s[rf][i] =
2069                                                 pwr2g.index_bw40_base[rf][idx];
2070                         }
2071                 }
2072                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2073                         idx = _rtl92ee_get_chnl_group(channel5g[i]);
2074                         efu->txpwr_5g_bw40base[rf][i] =
2075                                         pwr5g.index_bw40_base[rf][idx];
2076                 }
2077                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2078                         u8 upper, lower;
2079
2080                         idx = _rtl92ee_get_chnl_group(channel5g_80m[i]);
2081                         upper = pwr5g.index_bw40_base[rf][idx];
2082                         lower = pwr5g.index_bw40_base[rf][idx + 1];
2083
2084                         efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2;
2085                 }
2086                 for (i = 0; i < MAX_TX_COUNT; i++) {
2087                         efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i];
2088                         efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i];
2089                         efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i];
2090                         efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i];
2091
2092                         efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i];
2093                         efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i];
2094                         efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i];
2095                         efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i];
2096                 }
2097         }
2098
2099         if (!autoload_fail)
2100                 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_92E];
2101         else
2102                 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2103
2104         if (efu->eeprom_thermalmeter == 0xff || autoload_fail) {
2105                 efu->apk_thermalmeterignore = true;
2106                 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2107         }
2108
2109         efu->thermalmeter[0] = efu->eeprom_thermalmeter;
2110         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2111                 "thermalmeter = 0x%x\n", efu->eeprom_thermalmeter);
2112
2113         if (!autoload_fail) {
2114                 efu->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION_92E]
2115                                          & 0x07;
2116                 if (hwinfo[EEPROM_RF_BOARD_OPTION_92E] == 0xFF)
2117                         efu->eeprom_regulatory = 0;
2118         } else {
2119                 efu->eeprom_regulatory = 0;
2120         }
2121         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2122                 "eeprom_regulatory = 0x%x\n", efu->eeprom_regulatory);
2123 }
2124
2125 static void _rtl92ee_read_adapter_info(struct ieee80211_hw *hw)
2126 {
2127         struct rtl_priv *rtlpriv = rtl_priv(hw);
2128         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2129         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2130         u16 i, usvalue;
2131         u8 hwinfo[HWSET_MAX_SIZE];
2132         u16 eeprom_id;
2133
2134         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2135                 rtl_efuse_shadow_map_update(hw);
2136
2137                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2138                        HWSET_MAX_SIZE);
2139         } else if (rtlefuse->epromtype == EEPROM_93C46) {
2140                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2141                          "RTL819X Not boot from eeprom, check it !!");
2142                 return;
2143         } else {
2144                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2145                          "boot from neither eeprom nor efuse, check it !!");
2146                 return;
2147         }
2148
2149         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
2150                       hwinfo, HWSET_MAX_SIZE);
2151
2152         eeprom_id = *((u16 *)&hwinfo[0]);
2153         if (eeprom_id != RTL8192E_EEPROM_ID) {
2154                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2155                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
2156                 rtlefuse->autoload_failflag = true;
2157         } else {
2158                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2159                 rtlefuse->autoload_failflag = false;
2160         }
2161
2162         if (rtlefuse->autoload_failflag)
2163                 return;
2164         /*VID DID SVID SDID*/
2165         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
2166         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
2167         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
2168         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
2169         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROMId = 0x%4x\n", eeprom_id);
2170         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2171                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
2172         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2173                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
2174         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2175                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
2176         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2177                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
2178         /*customer ID*/
2179         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
2180         if (rtlefuse->eeprom_oemid == 0xFF)
2181                 rtlefuse->eeprom_oemid = 0;
2182
2183         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2184                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
2185         /*EEPROM version*/
2186         rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION];
2187         /*mac address*/
2188         for (i = 0; i < 6; i += 2) {
2189                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
2190                 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
2191         }
2192
2193         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2194                  "dev_addr: %pM\n", rtlefuse->dev_addr);
2195         /*channel plan */
2196         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
2197         /* set channel paln to world wide 13 */
2198         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
2199         /*tx power*/
2200         _rtl92ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2201                                              hwinfo);
2202
2203         rtl92ee_read_bt_coexist_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2204                                                hwinfo);
2205
2206         /*board type*/
2207         rtlefuse->board_type = (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E])
2208                                 & 0xE0) >> 5);
2209         if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) == 0xFF)
2210                 rtlefuse->board_type = 0;
2211
2212         rtlhal->board_type = rtlefuse->board_type;
2213         /*parse xtal*/
2214         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_92E];
2215         if (hwinfo[EEPROM_XTAL_92E] == 0xFF)
2216                 rtlefuse->crystalcap = 0x20;
2217
2218         /*antenna diversity*/
2219         rtlefuse->antenna_div_type = NO_ANTDIV;
2220         rtlefuse->antenna_div_cfg = 0;
2221
2222         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2223                 switch (rtlefuse->eeprom_oemid) {
2224                 case EEPROM_CID_DEFAULT:
2225                         if (rtlefuse->eeprom_did == 0x818B) {
2226                                 if ((rtlefuse->eeprom_svid == 0x10EC) &&
2227                                     (rtlefuse->eeprom_smid == 0x001B))
2228                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
2229                         } else {
2230                                 rtlhal->oem_id = RT_CID_DEFAULT;
2231                         }
2232                         break;
2233                 default:
2234                         rtlhal->oem_id = RT_CID_DEFAULT;
2235                         break;
2236                 }
2237         }
2238 }
2239
2240 static void _rtl92ee_hal_customized_behavior(struct ieee80211_hw *hw)
2241 {
2242         struct rtl_priv *rtlpriv = rtl_priv(hw);
2243         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2244         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2245
2246         pcipriv->ledctl.led_opendrain = true;
2247
2248         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2249                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2250 }
2251
2252 void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw)
2253 {
2254         struct rtl_priv *rtlpriv = rtl_priv(hw);
2255         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2256         struct rtl_phy *rtlphy = &rtlpriv->phy;
2257         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2258         u8 tmp_u1b;
2259
2260         rtlhal->version = _rtl92ee_read_chip_version(hw);
2261         if (get_rf_type(rtlphy) == RF_1T1R) {
2262                 rtlpriv->dm.rfpath_rxenable[0] = true;
2263         } else {
2264                 rtlpriv->dm.rfpath_rxenable[0] = true;
2265                 rtlpriv->dm.rfpath_rxenable[1] = true;
2266         }
2267         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2268                  rtlhal->version);
2269         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2270         if (tmp_u1b & BIT(4)) {
2271                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2272                 rtlefuse->epromtype = EEPROM_93C46;
2273         } else {
2274                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2275                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2276         }
2277         if (tmp_u1b & BIT(5)) {
2278                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2279                 rtlefuse->autoload_failflag = false;
2280                 _rtl92ee_read_adapter_info(hw);
2281         } else {
2282                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2283         }
2284         _rtl92ee_hal_customized_behavior(hw);
2285
2286         rtlphy->rfpath_rx_enable[0] = true;
2287         if (rtlphy->rf_type == RF_2T2R)
2288                 rtlphy->rfpath_rx_enable[1] = true;
2289 }
2290
2291 static u8 _rtl92ee_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, u8 rate_index)
2292 {
2293         u8 ret = 0;
2294
2295         switch (rate_index) {
2296         case RATR_INX_WIRELESS_NGB:
2297                 ret = 0;
2298                 break;
2299         case RATR_INX_WIRELESS_N:
2300         case RATR_INX_WIRELESS_NG:
2301                 ret = 4;
2302                 break;
2303         case RATR_INX_WIRELESS_NB:
2304                 ret = 2;
2305                 break;
2306         case RATR_INX_WIRELESS_GB:
2307                 ret = 6;
2308                 break;
2309         case RATR_INX_WIRELESS_G:
2310                 ret = 7;
2311                 break;
2312         case RATR_INX_WIRELESS_B:
2313                 ret = 8;
2314                 break;
2315         default:
2316                 ret = 0;
2317                 break;
2318         }
2319         return ret;
2320 }
2321
2322 static void rtl92ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2323                                          struct ieee80211_sta *sta,
2324                                          u8 rssi_level)
2325 {
2326         struct rtl_priv *rtlpriv = rtl_priv(hw);
2327         struct rtl_phy *rtlphy = &rtlpriv->phy;
2328         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2329         struct rtl_sta_info *sta_entry = NULL;
2330         u32 ratr_bitmap;
2331         u8 ratr_index;
2332         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2333                              ? 1 : 0;
2334         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2335                                 1 : 0;
2336         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2337                                 1 : 0;
2338         enum wireless_mode wirelessmode = 0;
2339         bool b_shortgi = false;
2340         u8 rate_mask[7] = {0};
2341         u8 macid = 0;
2342         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2343         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2344         wirelessmode = sta_entry->wireless_mode;
2345         if (mac->opmode == NL80211_IFTYPE_STATION ||
2346             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2347                 curtxbw_40mhz = mac->bw_40;
2348         else if (mac->opmode == NL80211_IFTYPE_AP ||
2349                  mac->opmode == NL80211_IFTYPE_ADHOC)
2350                 macid = sta->aid + 1;
2351
2352         ratr_bitmap = sta->supp_rates[0];
2353         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2354                 ratr_bitmap = 0xfff;
2355
2356         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2357                         sta->ht_cap.mcs.rx_mask[0] << 12);
2358
2359         switch (wirelessmode) {
2360         case WIRELESS_MODE_B:
2361                 ratr_index = RATR_INX_WIRELESS_B;
2362                 if (ratr_bitmap & 0x0000000c)
2363                         ratr_bitmap &= 0x0000000d;
2364                 else
2365                         ratr_bitmap &= 0x0000000f;
2366                 break;
2367         case WIRELESS_MODE_G:
2368                 ratr_index = RATR_INX_WIRELESS_GB;
2369
2370                 if (rssi_level == 1)
2371                         ratr_bitmap &= 0x00000f00;
2372                 else if (rssi_level == 2)
2373                         ratr_bitmap &= 0x00000ff0;
2374                 else
2375                         ratr_bitmap &= 0x00000ff5;
2376                 break;
2377         case WIRELESS_MODE_N_24G:
2378                 if (curtxbw_40mhz)
2379                         ratr_index = RATR_INX_WIRELESS_NGB;
2380                 else
2381                         ratr_index = RATR_INX_WIRELESS_NB;
2382
2383                 if (rtlphy->rf_type == RF_1T1R) {
2384                         if (curtxbw_40mhz) {
2385                                 if (rssi_level == 1)
2386                                         ratr_bitmap &= 0x000f0000;
2387                                 else if (rssi_level == 2)
2388                                         ratr_bitmap &= 0x000ff000;
2389                                 else
2390                                         ratr_bitmap &= 0x000ff015;
2391                         } else {
2392                                 if (rssi_level == 1)
2393                                         ratr_bitmap &= 0x000f0000;
2394                                 else if (rssi_level == 2)
2395                                         ratr_bitmap &= 0x000ff000;
2396                                 else
2397                                         ratr_bitmap &= 0x000ff005;
2398                         }
2399                 } else {
2400                         if (curtxbw_40mhz) {
2401                                 if (rssi_level == 1)
2402                                         ratr_bitmap &= 0x0f8f0000;
2403                                 else if (rssi_level == 2)
2404                                         ratr_bitmap &= 0x0ffff000;
2405                                 else
2406                                         ratr_bitmap &= 0x0ffff015;
2407                         } else {
2408                                 if (rssi_level == 1)
2409                                         ratr_bitmap &= 0x0f8f0000;
2410                                 else if (rssi_level == 2)
2411                                         ratr_bitmap &= 0x0ffff000;
2412                                 else
2413                                         ratr_bitmap &= 0x0ffff005;
2414                         }
2415                 }
2416
2417                 if ((curtxbw_40mhz && b_curshortgi_40mhz) ||
2418                     (!curtxbw_40mhz && b_curshortgi_20mhz)) {
2419                         if (macid == 0)
2420                                 b_shortgi = true;
2421                         else if (macid == 1)
2422                                 b_shortgi = false;
2423                 }
2424                 break;
2425         default:
2426                 ratr_index = RATR_INX_WIRELESS_NGB;
2427
2428                 if (rtlphy->rf_type == RF_1T1R)
2429                         ratr_bitmap &= 0x000ff0ff;
2430                 else
2431                         ratr_bitmap &= 0x0f8ff0ff;
2432                 break;
2433         }
2434         ratr_index = _rtl92ee_mrate_idx_to_arfr_id(hw, ratr_index);
2435         sta_entry->ratr_index = ratr_index;
2436
2437         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2438                  "ratr_bitmap :%x\n", ratr_bitmap);
2439         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2440                                        (ratr_index << 28);
2441         rate_mask[0] = macid;
2442         rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
2443         rate_mask[2] = curtxbw_40mhz;
2444         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2445         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2446         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2447         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2448         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2449                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2450                   ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2451                   rate_mask[2], rate_mask[3], rate_mask[4],
2452                   rate_mask[5], rate_mask[6]);
2453         rtl92ee_fill_h2c_cmd(hw, H2C_92E_RA_MASK, 7, rate_mask);
2454         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2455 }
2456
2457 void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2458                                  struct ieee80211_sta *sta, u8 rssi_level)
2459 {
2460         struct rtl_priv *rtlpriv = rtl_priv(hw);
2461
2462         if (rtlpriv->dm.useramask)
2463                 rtl92ee_update_hal_rate_mask(hw, sta, rssi_level);
2464 }
2465
2466 void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw)
2467 {
2468         struct rtl_priv *rtlpriv = rtl_priv(hw);
2469         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2470         u16 sifs_timer;
2471
2472         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2473                                       (u8 *)&mac->slot_time);
2474         if (!mac->ht_enable)
2475                 sifs_timer = 0x0a0a;
2476         else
2477                 sifs_timer = 0x0e0e;
2478         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2479 }
2480
2481 bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2482 {
2483         *valid = 1;
2484         return true;
2485 }
2486
2487 void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2488                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2489                      bool is_wepkey, bool clear_all)
2490 {
2491         struct rtl_priv *rtlpriv = rtl_priv(hw);
2492         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2493         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2494         u8 *macaddr = p_macaddr;
2495         u32 entry_id = 0;
2496         bool is_pairwise = false;
2497
2498         static u8 cam_const_addr[4][6] = {
2499                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2500                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2501                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2502                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2503         };
2504         static u8 cam_const_broad[] = {
2505                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2506         };
2507
2508         if (clear_all) {
2509                 u8 idx = 0;
2510                 u8 cam_offset = 0;
2511                 u8 clear_number = 5;
2512
2513                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2514
2515                 for (idx = 0; idx < clear_number; idx++) {
2516                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2517                         rtl_cam_empty_entry(hw, cam_offset + idx);
2518
2519                         if (idx < 5) {
2520                                 memset(rtlpriv->sec.key_buf[idx], 0,
2521                                        MAX_KEY_LEN);
2522                                 rtlpriv->sec.key_len[idx] = 0;
2523                         }
2524                 }
2525
2526         } else {
2527                 switch (enc_algo) {
2528                 case WEP40_ENCRYPTION:
2529                         enc_algo = CAM_WEP40;
2530                         break;
2531                 case WEP104_ENCRYPTION:
2532                         enc_algo = CAM_WEP104;
2533                         break;
2534                 case TKIP_ENCRYPTION:
2535                         enc_algo = CAM_TKIP;
2536                         break;
2537                 case AESCCMP_ENCRYPTION:
2538                         enc_algo = CAM_AES;
2539                         break;
2540                 default:
2541                         RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
2542                                  "switch case not process\n");
2543                         enc_algo = CAM_TKIP;
2544                         break;
2545                 }
2546
2547                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2548                         macaddr = cam_const_addr[key_index];
2549                         entry_id = key_index;
2550                 } else {
2551                         if (is_group) {
2552                                 macaddr = cam_const_broad;
2553                                 entry_id = key_index;
2554                         } else {
2555                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2556                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2557                                         entry_id = rtl_cam_get_free_entry(hw,
2558                                                                      p_macaddr);
2559                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2560                                                 RT_TRACE(rtlpriv, COMP_SEC,
2561                                                          DBG_EMERG,
2562                                                          "Can not find free hw security cam entry\n");
2563                                                 return;
2564                                         }
2565                                 } else {
2566                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2567                                 }
2568
2569                                 key_index = PAIRWISE_KEYIDX;
2570                                 is_pairwise = true;
2571                         }
2572                 }
2573
2574                 if (rtlpriv->sec.key_len[key_index] == 0) {
2575                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2576                                  "delete one entry, entry_id is %d\n",
2577                                  entry_id);
2578                         if (mac->opmode == NL80211_IFTYPE_AP ||
2579                             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2580                                 rtl_cam_del_entry(hw, p_macaddr);
2581                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2582                 } else {
2583                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2584                                  "add one entry\n");
2585                         if (is_pairwise) {
2586                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2587                                          "set Pairwiase key\n");
2588
2589                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2590                                                entry_id, enc_algo,
2591                                                CAM_CONFIG_NO_USEDK,
2592                                                rtlpriv->sec.key_buf[key_index]);
2593                         } else {
2594                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2595                                          "set group key\n");
2596
2597                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2598                                         rtl_cam_add_one_entry(hw,
2599                                                 rtlefuse->dev_addr,
2600                                                 PAIRWISE_KEYIDX,
2601                                                 CAM_PAIRWISE_KEY_POSITION,
2602                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2603                                                 rtlpriv->sec.key_buf[entry_id]);
2604                                 }
2605
2606                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2607                                                 entry_id, enc_algo,
2608                                                 CAM_CONFIG_NO_USEDK,
2609                                                 rtlpriv->sec.key_buf[entry_id]);
2610                         }
2611                 }
2612         }
2613 }
2614
2615 void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2616                                             bool auto_load_fail, u8 *hwinfo)
2617 {
2618         struct rtl_priv *rtlpriv = rtl_priv(hw);
2619         u8 value;
2620
2621         if (!auto_load_fail) {
2622                 value = hwinfo[EEPROM_RF_BOARD_OPTION_92E];
2623                 if (((value & 0xe0) >> 5) == 0x1)
2624                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
2625                 else
2626                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
2627
2628                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2629                 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X2;
2630         } else {
2631                 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2632                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2633                 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X1;
2634         }
2635 }
2636
2637 void rtl92ee_bt_reg_init(struct ieee80211_hw *hw)
2638 {
2639         struct rtl_priv *rtlpriv = rtl_priv(hw);
2640
2641         /* 0:Low, 1:High, 2:From Efuse. */
2642         rtlpriv->btcoexist.reg_bt_iso = 2;
2643         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2644         rtlpriv->btcoexist.reg_bt_sco = 3;
2645         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2646         rtlpriv->btcoexist.reg_bt_sco = 0;
2647 }
2648
2649 void rtl92ee_bt_hw_init(struct ieee80211_hw *hw)
2650 {
2651         struct rtl_priv *rtlpriv = rtl_priv(hw);
2652
2653         if (rtlpriv->cfg->ops->get_btc_status())
2654                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2655 }
2656
2657 void rtl92ee_suspend(struct ieee80211_hw *hw)
2658 {
2659 }
2660
2661 void rtl92ee_resume(struct ieee80211_hw *hw)
2662 {
2663 }
2664
2665 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2666 void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw,
2667                                 bool allow_all_da, bool write_into_reg)
2668 {
2669         struct rtl_priv *rtlpriv = rtl_priv(hw);
2670         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2671
2672         if (allow_all_da)       /* Set BIT0 */
2673                 rtlpci->receive_config |= RCR_AAP;
2674         else                    /* Clear BIT0 */
2675                 rtlpci->receive_config &= ~RCR_AAP;
2676
2677         if (write_into_reg)
2678                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2679
2680         RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2681                  "receive_config=0x%08X, write_into_reg=%d\n",
2682                   rtlpci->receive_config, write_into_reg);
2683 }