kernel/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../cam.h"
  34 #include "../ps.h"
  35 #include "../usb.h"
  36 #include "reg.h"
  37 #include "def.h"
  38 #include "phy.h"
  39 #include "../rtl8192c/phy_common.h"
  40 #include "mac.h"
  41 #include "dm.h"
  42 #include "../rtl8192c/dm_common.h"
  43 #include "../rtl8192c/fw_common.h"
  44 #include "hw.h"
  45 #include "../rtl8192ce/hw.h"
  46 #include "trx.h"
  47 #include "led.h"
  48 #include "table.h"
  49
  50 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
  51 {
  52         struct rtl_priv *rtlpriv = rtl_priv(hw);
  53         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  54         struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
  55
  56         rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
  57         rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
  58         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  59                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  60                         RTL8192CUPHY_REG_Array_PG_HPLength;
  61                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  62                         RTL8192CUPHY_REG_Array_PG_HP;
  63         } else {
  64                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  65                         RTL8192CUPHY_REG_ARRAY_PGLENGTH;
  66                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  67                         RTL8192CUPHY_REG_ARRAY_PG;
  68         }
  69         /* 2T */
  70         rtlphy->hwparam_tables[PHY_REG_2T].length =
  71                         RTL8192CUPHY_REG_2TARRAY_LENGTH;
  72         rtlphy->hwparam_tables[PHY_REG_2T].pdata =
  73                         RTL8192CUPHY_REG_2TARRAY;
  74         rtlphy->hwparam_tables[RADIOA_2T].length =
  75                         RTL8192CURADIOA_2TARRAYLENGTH;
  76         rtlphy->hwparam_tables[RADIOA_2T].pdata =
  77                         RTL8192CURADIOA_2TARRAY;
  78         rtlphy->hwparam_tables[RADIOB_2T].length =
  79                         RTL8192CURADIOB_2TARRAYLENGTH;
  80         rtlphy->hwparam_tables[RADIOB_2T].pdata =
  81                         RTL8192CU_RADIOB_2TARRAY;
  82         rtlphy->hwparam_tables[AGCTAB_2T].length =
  83                         RTL8192CUAGCTAB_2TARRAYLENGTH;
  84         rtlphy->hwparam_tables[AGCTAB_2T].pdata =
  85                         RTL8192CUAGCTAB_2TARRAY;
  86         /* 1T */
  87         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  88                 rtlphy->hwparam_tables[PHY_REG_1T].length =
  89                         RTL8192CUPHY_REG_1T_HPArrayLength;
  90                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
  91                         RTL8192CUPHY_REG_1T_HPArray;
  92                 rtlphy->hwparam_tables[RADIOA_1T].length =
  93                         RTL8192CURadioA_1T_HPArrayLength;
  94                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
  95                         RTL8192CURadioA_1T_HPArray;
  96                 rtlphy->hwparam_tables[RADIOB_1T].length =
  97                         RTL8192CURADIOB_1TARRAYLENGTH;
  98                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
  99                         RTL8192CU_RADIOB_1TARRAY;
 100                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 101                         RTL8192CUAGCTAB_1T_HPArrayLength;
 102                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 103                         Rtl8192CUAGCTAB_1T_HPArray;
 104         } else {
 105                 rtlphy->hwparam_tables[PHY_REG_1T].length =
 106                          RTL8192CUPHY_REG_1TARRAY_LENGTH;
 107                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
 108                         RTL8192CUPHY_REG_1TARRAY;
 109                 rtlphy->hwparam_tables[RADIOA_1T].length =
 110                         RTL8192CURADIOA_1TARRAYLENGTH;
 111                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
 112                         RTL8192CU_RADIOA_1TARRAY;
 113                 rtlphy->hwparam_tables[RADIOB_1T].length =
 114                         RTL8192CURADIOB_1TARRAYLENGTH;
 115                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
 116                         RTL8192CU_RADIOB_1TARRAY;
 117                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 118                         RTL8192CUAGCTAB_1TARRAYLENGTH;
 119                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 120                         RTL8192CUAGCTAB_1TARRAY;
 121         }
 122 }
 123
 124 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
 125                                                  bool autoload_fail,
 126                                                  u8 *hwinfo)
 127 {
 128         struct rtl_priv *rtlpriv = rtl_priv(hw);
 129         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 130         u8 rf_path, index, tempval;
 131         u16 i;
 132
 133         for (rf_path = 0; rf_path < 2; rf_path++) {
 134                 for (i = 0; i < 3; i++) {
 135                         if (!autoload_fail) {
 136                                 rtlefuse->
 137                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 138                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
 139                                 rtlefuse->
 140                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 141                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
 142                                            i];
 143                         } else {
 144                                 rtlefuse->
 145                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 146                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 147                                 rtlefuse->
 148                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 149                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 150                         }
 151                 }
 152         }
 153         for (i = 0; i < 3; i++) {
 154                 if (!autoload_fail)
 155                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
 156                 else
 157                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
 158                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
 159                     (tempval & 0xf);
 160                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
 161                     ((tempval & 0xf0) >> 4);
 162         }
 163         for (rf_path = 0; rf_path < 2; rf_path++)
 164                 for (i = 0; i < 3; i++)
 165                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 166                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
 167                                 rf_path, i,
 168                                 rtlefuse->
 169                                 eeprom_chnlarea_txpwr_cck[rf_path][i]);
 170         for (rf_path = 0; rf_path < 2; rf_path++)
 171                 for (i = 0; i < 3; i++)
 172                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 173                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
 174                                 rf_path, i,
 175                                 rtlefuse->
 176                                 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
 177         for (rf_path = 0; rf_path < 2; rf_path++)
 178                 for (i = 0; i < 3; i++)
 179                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 180                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
 181                                 rf_path, i,
 182                                 rtlefuse->
 183                                 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
 184         for (rf_path = 0; rf_path < 2; rf_path++) {
 185                 for (i = 0; i < 14; i++) {
 186                         index = rtl92c_get_chnl_group((u8)i);
 187                         rtlefuse->txpwrlevel_cck[rf_path][i] =
 188                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
 189                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
 190                             rtlefuse->
 191                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
 192                         if ((rtlefuse->
 193                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
 194                              rtlefuse->
 195                              eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
 196                             > 0) {
 197                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
 198                                     rtlefuse->
 199                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
 200                                     [index] - rtlefuse->
 201                                     eprom_chnl_txpwr_ht40_2sdf[rf_path]
 202                                     [index];
 203                         } else {
 204                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
 205                         }
 206                 }
 207                 for (i = 0; i < 14; i++) {
 208                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 209                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
 210                                 rtlefuse->txpwrlevel_cck[rf_path][i],
 211                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
 212                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
 213                 }
 214         }
 215         for (i = 0; i < 3; i++) {
 216                 if (!autoload_fail) {
 217                         rtlefuse->eeprom_pwrlimit_ht40[i] =
 218                             hwinfo[EEPROM_TXPWR_GROUP + i];
 219                         rtlefuse->eeprom_pwrlimit_ht20[i] =
 220                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
 221                 } else {
 222                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
 223                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
 224                 }
 225         }
 226         for (rf_path = 0; rf_path < 2; rf_path++) {
 227                 for (i = 0; i < 14; i++) {
 228                         index = rtl92c_get_chnl_group((u8)i);
 229                         if (rf_path == RF90_PATH_A) {
 230                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 231                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
 232                                      & 0xf);
 233                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 234                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
 235                                      & 0xf);
 236                         } else if (rf_path == RF90_PATH_B) {
 237                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 238                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
 239                                       & 0xf0) >> 4);
 240                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 241                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
 242                                       & 0xf0) >> 4);
 243                         }
 244                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 245                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
 246                                 rf_path, i,
 247                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
 248                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 249                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
 250                                 rf_path, i,
 251                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
 252                 }
 253         }
 254         for (i = 0; i < 14; i++) {
 255                 index = rtl92c_get_chnl_group((u8)i);
 256                 if (!autoload_fail)
 257                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
 258                 else
 259                         tempval = EEPROM_DEFAULT_HT20_DIFF;
 260                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
 261                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
 262                     ((tempval >> 4) & 0xF);
 263                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
 264                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
 265                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
 266                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
 267                 index = rtl92c_get_chnl_group((u8)i);
 268                 if (!autoload_fail)
 269                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
 270                 else
 271                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
 272                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
 273                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
 274                     ((tempval >> 4) & 0xF);
 275         }
 276         rtlefuse->legacy_ht_txpowerdiff =
 277             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
 278         for (i = 0; i < 14; i++)
 279                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 280                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
 281                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
 282         for (i = 0; i < 14; i++)
 283                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 284                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
 285                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
 286         for (i = 0; i < 14; i++)
 287                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 288                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
 289                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
 290         for (i = 0; i < 14; i++)
 291                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 292                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
 293                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
 294         if (!autoload_fail)
 295                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
 296         else
 297                 rtlefuse->eeprom_regulatory = 0;
 298         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 299                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
 300         if (!autoload_fail) {
 301                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
 302                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
 303         } else {
 304                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
 305                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
 306         }
 307         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 308                 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
 309                 rtlefuse->eeprom_tssi[RF90_PATH_A],
 310                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
 311         if (!autoload_fail)
 312                 tempval = hwinfo[EEPROM_THERMAL_METER];
 313         else
 314                 tempval = EEPROM_DEFAULT_THERMALMETER;
 315         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
 316         if (rtlefuse->eeprom_thermalmeter < 0x06 ||
 317             rtlefuse->eeprom_thermalmeter > 0x1c)
 318                 rtlefuse->eeprom_thermalmeter = 0x12;
 319         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
 320                 rtlefuse->apk_thermalmeterignore = true;
 321         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
 322         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 323                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
 324 }
 325
 326 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
 327 {
 328         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 329         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 330         u8 boardType;
 331
 332         if (IS_NORMAL_CHIP(rtlhal->version)) {
 333                 boardType = ((contents[EEPROM_RF_OPT1]) &
 334                             BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
 335         } else {
 336                 boardType = contents[EEPROM_RF_OPT4];
 337                 boardType &= BOARD_TYPE_TEST_MASK;
 338         }
 339         rtlefuse->board_type = boardType;
 340         if (IS_HIGHT_PA(rtlefuse->board_type))
 341                 rtlefuse->external_pa = 1;
 342         pr_info("Board Type %x\n", rtlefuse->board_type);
 343 }
 344
 345 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
 346 {
 347         struct rtl_priv *rtlpriv = rtl_priv(hw);
 348         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 349         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 350         u16 i, usvalue;
 351         u8 hwinfo[HWSET_MAX_SIZE] = {0};
 352         u16 eeprom_id;
 353
 354         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 355                 rtl_efuse_shadow_map_update(hw);
 356                 memcpy((void *)hwinfo,
 357                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
 358                        HWSET_MAX_SIZE);
 359         } else if (rtlefuse->epromtype == EEPROM_93C46) {
 360                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 361                          "RTL819X Not boot from eeprom, check it !!\n");
 362         }
 363         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, "MAP",
 364                       hwinfo, HWSET_MAX_SIZE);
 365         eeprom_id = le16_to_cpu(*((__le16 *)&hwinfo[0]));
 366         if (eeprom_id != RTL8190_EEPROM_ID) {
 367                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 368                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
 369                 rtlefuse->autoload_failflag = true;
 370         } else {
 371                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
 372                 rtlefuse->autoload_failflag = false;
 373         }
 374         if (rtlefuse->autoload_failflag)
 375                 return;
 376         for (i = 0; i < 6; i += 2) {
 377                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
 378                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
 379         }
 380         pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
 381         _rtl92cu_read_txpower_info_from_hwpg(hw,
 382                                            rtlefuse->autoload_failflag, hwinfo);
 383         rtlefuse->eeprom_vid = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VID]);
 384         rtlefuse->eeprom_did = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_DID]);
 385         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, " VID = 0x%02x PID = 0x%02x\n",
 386                  rtlefuse->eeprom_vid, rtlefuse->eeprom_did);
 387         rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
 388         rtlefuse->eeprom_version =
 389                          le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VERSION]);
 390         rtlefuse->txpwr_fromeprom = true;
 391         rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
 392         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
 393                  rtlefuse->eeprom_oemid);
 394         if (rtlhal->oem_id == RT_CID_DEFAULT) {
 395                 switch (rtlefuse->eeprom_oemid) {
 396                 case EEPROM_CID_DEFAULT:
 397                         if (rtlefuse->eeprom_did == 0x8176) {
 398                                 if ((rtlefuse->eeprom_svid == 0x103C &&
 399                                      rtlefuse->eeprom_smid == 0x1629))
 400                                         rtlhal->oem_id = RT_CID_819X_HP;
 401                                 else
 402                                         rtlhal->oem_id = RT_CID_DEFAULT;
 403                         } else {
 404                                 rtlhal->oem_id = RT_CID_DEFAULT;
 405                         }
 406                         break;
 407                 case EEPROM_CID_TOSHIBA:
 408                         rtlhal->oem_id = RT_CID_TOSHIBA;
 409                         break;
 410                 case EEPROM_CID_QMI:
 411                         rtlhal->oem_id = RT_CID_819X_QMI;
 412                         break;
 413                 case EEPROM_CID_WHQL:
 414                 default:
 415                         rtlhal->oem_id = RT_CID_DEFAULT;
 416                         break;
 417                 }
 418         }
 419         _rtl92cu_read_board_type(hw, hwinfo);
 420 }
 421
 422 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
 423 {
 424         struct rtl_priv *rtlpriv = rtl_priv(hw);
 425         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 426         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 427
 428         switch (rtlhal->oem_id) {
 429         case RT_CID_819X_HP:
 430                 usb_priv->ledctl.led_opendrain = true;
 431                 break;
 432         case RT_CID_819X_LENOVO:
 433         case RT_CID_DEFAULT:
 434         case RT_CID_TOSHIBA:
 435         case RT_CID_CCX:
 436         case RT_CID_819X_ACER:
 437         case RT_CID_WHQL:
 438         default:
 439                 break;
 440         }
 441         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
 442                  rtlhal->oem_id);
 443 }
 444
 445 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
 446 {
 447
 448         struct rtl_priv *rtlpriv = rtl_priv(hw);
 449         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 450         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 451         u8 tmp_u1b;
 452
 453         if (!IS_NORMAL_CHIP(rtlhal->version))
 454                 return;
 455         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
 456         rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
 457                                EEPROM_93C46 : EEPROM_BOOT_EFUSE;
 458         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
 459                  tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
 460         rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
 461         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
 462                  tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
 463         _rtl92cu_read_adapter_info(hw);
 464         _rtl92cu_hal_customized_behavior(hw);
 465         return;
 466 }
 467
 468 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
 469 {
 470         struct rtl_priv *rtlpriv = rtl_priv(hw);
 471         int             status = 0;
 472         u16             value16;
 473         u8              value8;
 474         /*  polling autoload done. */
 475         u32     pollingCount = 0;
 476
 477         do {
 478                 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
 479                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 480                                  "Autoload Done!\n");
 481                         break;
 482                 }
 483                 if (pollingCount++ > 100) {
 484                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 485                                  "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
 486                         return -ENODEV;
 487                 }
 488         } while (true);
 489         /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
 490         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
 491         /* Power on when re-enter from IPS/Radio off/card disable */
 492         /* enable SPS into PWM mode */
 493         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 494         udelay(100);
 495         value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
 496         if (0 == (value8 & LDV12_EN)) {
 497                 value8 |= LDV12_EN;
 498                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
 499                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 500                          " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
 501                          value8);
 502                 udelay(100);
 503                 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 504                 value8 &= ~ISO_MD2PP;
 505                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
 506         }
 507         /*  auto enable WLAN */
 508         pollingCount = 0;
 509         value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
 510         value16 |= APFM_ONMAC;
 511         rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
 512         do {
 513                 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
 514                         pr_info("MAC auto ON okay!\n");
 515                         break;
 516                 }
 517                 if (pollingCount++ > 1000) {
 518                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 519                                  "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
 520                         return -ENODEV;
 521                 }
 522         } while (true);
 523         /* Enable Radio ,GPIO ,and LED function */
 524         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
 525         /* release RF digital isolation */
 526         value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 527         value16 &= ~ISO_DIOR;
 528         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
 529         /* Reconsider when to do this operation after asking HWSD. */
 530         pollingCount = 0;
 531         rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
 532                                                 REG_APSD_CTRL) & ~BIT(6)));
 533         do {
 534                 pollingCount++;
 535         } while ((pollingCount < 200) &&
 536                  (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
 537         /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 538         value16 = rtl_read_word(rtlpriv,  REG_CR);
 539         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
 540                     PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
 541         rtl_write_word(rtlpriv, REG_CR, value16);
 542         return status;
 543 }
 544
 545 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
 546                                               bool wmm_enable,
 547                                               u8 out_ep_num,
 548                                               u8 queue_sel)
 549 {
 550         struct rtl_priv *rtlpriv = rtl_priv(hw);
 551         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 552         bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
 553         u32 outEPNum = (u32)out_ep_num;
 554         u32 numHQ = 0;
 555         u32 numLQ = 0;
 556         u32 numNQ = 0;
 557         u32 numPubQ;
 558         u32 value32;
 559         u8 value8;
 560         u32 txQPageNum, txQPageUnit, txQRemainPage;
 561
 562         if (!wmm_enable) {
 563                 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
 564                           CHIP_A_PAGE_NUM_PUBQ;
 565                 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
 566
 567                 txQPageUnit = txQPageNum/outEPNum;
 568                 txQRemainPage = txQPageNum % outEPNum;
 569                 if (queue_sel & TX_SELE_HQ)
 570                         numHQ = txQPageUnit;
 571                 if (queue_sel & TX_SELE_LQ)
 572                         numLQ = txQPageUnit;
 573                 /* HIGH priority queue always present in the configuration of
 574                  * 2 out-ep. Remainder pages have assigned to High queue */
 575                 if ((outEPNum > 1) && (txQRemainPage))
 576                         numHQ += txQRemainPage;
 577                 /* NOTE: This step done before writting REG_RQPN. */
 578                 if (isChipN) {
 579                         if (queue_sel & TX_SELE_NQ)
 580                                 numNQ = txQPageUnit;
 581                         value8 = (u8)_NPQ(numNQ);
 582                         rtl_write_byte(rtlpriv,  REG_RQPN_NPQ, value8);
 583                 }
 584         } else {
 585                 /* for WMM ,number of out-ep must more than or equal to 2! */
 586                 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
 587                           WMM_CHIP_A_PAGE_NUM_PUBQ;
 588                 if (queue_sel & TX_SELE_HQ) {
 589                         numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
 590                                 WMM_CHIP_A_PAGE_NUM_HPQ;
 591                 }
 592                 if (queue_sel & TX_SELE_LQ) {
 593                         numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
 594                                 WMM_CHIP_A_PAGE_NUM_LPQ;
 595                 }
 596                 /* NOTE: This step done before writting REG_RQPN. */
 597                 if (isChipN) {
 598                         if (queue_sel & TX_SELE_NQ)
 599                                 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
 600                         value8 = (u8)_NPQ(numNQ);
 601                         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
 602                 }
 603         }
 604         /* TX DMA */
 605         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 606         rtl_write_dword(rtlpriv, REG_RQPN, value32);
 607 }
 608
 609 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
 610 {
 611         struct rtl_priv *rtlpriv = rtl_priv(hw);
 612         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 613         u8      txpktbuf_bndy;
 614         u8      value8;
 615
 616         if (!wmm_enable)
 617                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 618         else /* for WMM */
 619                 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
 620                                                 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
 621                                                 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
 622         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 623         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 624         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 625         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 626         rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
 627         rtl_write_word(rtlpriv,  (REG_TRXFF_BNDY + 2), 0x27FF);
 628         value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
 629         rtl_write_byte(rtlpriv, REG_PBP, value8);
 630 }
 631
 632 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
 633                                             u16 bkQ, u16 viQ, u16 voQ,
 634                                             u16 mgtQ, u16 hiQ)
 635 {
 636         struct rtl_priv *rtlpriv = rtl_priv(hw);
 637         u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
 638
 639         value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
 640                    _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
 641                    _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 642         rtl_write_word(rtlpriv,  REG_TRXDMA_CTRL, value16);
 643 }
 644
 645 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
 646                                                     bool wmm_enable,
 647                                                     u8 queue_sel)
 648 {
 649         u16 uninitialized_var(value);
 650
 651         switch (queue_sel) {
 652         case TX_SELE_HQ:
 653                 value = QUEUE_HIGH;
 654                 break;
 655         case TX_SELE_LQ:
 656                 value = QUEUE_LOW;
 657                 break;
 658         case TX_SELE_NQ:
 659                 value = QUEUE_NORMAL;
 660                 break;
 661         default:
 662                 WARN_ON(1); /* Shall not reach here! */
 663                 break;
 664         }
 665         _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
 666                                         value, value);
 667         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 668 }
 669
 670 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
 671                                                                 bool wmm_enable,
 672                                                                 u8 queue_sel)
 673 {
 674         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 675         u16 uninitialized_var(valueHi);
 676         u16 uninitialized_var(valueLow);
 677
 678         switch (queue_sel) {
 679         case (TX_SELE_HQ | TX_SELE_LQ):
 680                 valueHi = QUEUE_HIGH;
 681                 valueLow = QUEUE_LOW;
 682                 break;
 683         case (TX_SELE_NQ | TX_SELE_LQ):
 684                 valueHi = QUEUE_NORMAL;
 685                 valueLow = QUEUE_LOW;
 686                 break;
 687         case (TX_SELE_HQ | TX_SELE_NQ):
 688                 valueHi = QUEUE_HIGH;
 689                 valueLow = QUEUE_NORMAL;
 690                 break;
 691         default:
 692                 WARN_ON(1);
 693                 break;
 694         }
 695         if (!wmm_enable) {
 696                 beQ = valueLow;
 697                 bkQ = valueLow;
 698                 viQ = valueHi;
 699                 voQ = valueHi;
 700                 mgtQ = valueHi;
 701                 hiQ = valueHi;
 702         } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
 703                 beQ = valueHi;
 704                 bkQ = valueLow;
 705                 viQ = valueLow;
 706                 voQ = valueHi;
 707                 mgtQ = valueHi;
 708                 hiQ = valueHi;
 709         }
 710         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 711         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 712 }
 713
 714 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
 715                                                       bool wmm_enable,
 716                                                       u8 queue_sel)
 717 {
 718         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 719         struct rtl_priv *rtlpriv = rtl_priv(hw);
 720
 721         if (!wmm_enable) { /* typical setting */
 722                 beQ     = QUEUE_LOW;
 723                 bkQ     = QUEUE_LOW;
 724                 viQ     = QUEUE_NORMAL;
 725                 voQ     = QUEUE_HIGH;
 726                 mgtQ    = QUEUE_HIGH;
 727                 hiQ     = QUEUE_HIGH;
 728         } else { /* for WMM */
 729                 beQ     = QUEUE_LOW;
 730                 bkQ     = QUEUE_NORMAL;
 731                 viQ     = QUEUE_NORMAL;
 732                 voQ     = QUEUE_HIGH;
 733                 mgtQ    = QUEUE_HIGH;
 734                 hiQ     = QUEUE_HIGH;
 735         }
 736         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 737         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
 738                  queue_sel);
 739 }
 740
 741 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
 742                                                bool wmm_enable,
 743                                                u8 out_ep_num,
 744                                                u8 queue_sel)
 745 {
 746         switch (out_ep_num) {
 747         case 1:
 748                 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
 749                                                         queue_sel);
 750                 break;
 751         case 2:
 752                 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
 753                                                         queue_sel);
 754                 break;
 755         case 3:
 756                 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
 757                                                           queue_sel);
 758                 break;
 759         default:
 760                 WARN_ON(1); /* Shall not reach here! */
 761                 break;
 762         }
 763 }
 764
 765 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
 766                                                bool wmm_enable,
 767                                                u8 out_ep_num,
 768                                                u8 queue_sel)
 769 {
 770         u8 hq_sele = 0;
 771         struct rtl_priv *rtlpriv = rtl_priv(hw);
 772
 773         switch (out_ep_num) {
 774         case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
 775                 if (!wmm_enable) /* typical setting */
 776                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
 777                                    HQSEL_HIQ;
 778                 else    /* for WMM */
 779                         hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
 780                                   HQSEL_HIQ;
 781                 break;
 782         case 1:
 783                 if (TX_SELE_LQ == queue_sel) {
 784                         /* map all endpoint to Low queue */
 785                         hq_sele = 0;
 786                 } else if (TX_SELE_HQ == queue_sel) {
 787                         /* map all endpoint to High queue */
 788                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
 789                                    HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
 790                 }
 791                 break;
 792         default:
 793                 WARN_ON(1); /* Shall not reach here! */
 794                 break;
 795         }
 796         rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
 797         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
 798                  hq_sele);
 799 }
 800
 801 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
 802                                                 bool wmm_enable,
 803                                                 u8 out_ep_num,
 804                                                 u8 queue_sel)
 805 {
 806         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 807         if (IS_NORMAL_CHIP(rtlhal->version))
 808                 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
 809                                                    queue_sel);
 810         else
 811                 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
 812                                                    queue_sel);
 813 }
 814
 815 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
 816 {
 817 }
 818
 819 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
 820 {
 821         u16                     value16;
 822
 823         struct rtl_priv *rtlpriv = rtl_priv(hw);
 824         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 825
 826         mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
 827                       RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
 828                       RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
 829         rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
 830         /* Accept all multicast address */
 831         rtl_write_dword(rtlpriv,  REG_MAR, 0xFFFFFFFF);
 832         rtl_write_dword(rtlpriv,  REG_MAR + 4, 0xFFFFFFFF);
 833         /* Accept all management frames */
 834         value16 = 0xFFFF;
 835         rtl92c_set_mgt_filter(hw, value16);
 836         /* Reject all control frame - default value is 0 */
 837         rtl92c_set_ctrl_filter(hw, 0x0);
 838         /* Accept all data frames */
 839         value16 = 0xFFFF;
 840         rtl92c_set_data_filter(hw, value16);
 841 }
 842
 843 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
 844 {
 845         struct rtl_priv *rtlpriv = rtl_priv(hw);
 846         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 847         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 848         struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
 849         int err = 0;
 850         u32     boundary = 0;
 851         u8 wmm_enable = false; /* TODO */
 852         u8 out_ep_nums = rtlusb->out_ep_nums;
 853         u8 queue_sel = rtlusb->out_queue_sel;
 854         err = _rtl92cu_init_power_on(hw);
 855
 856         if (err) {
 857                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 858                          "Failed to init power on!\n");
 859                 return err;
 860         }
 861         if (!wmm_enable) {
 862                 boundary = TX_PAGE_BOUNDARY;
 863         } else { /* for WMM */
 864                 boundary = (IS_NORMAL_CHIP(rtlhal->version))
 865                                         ? WMM_CHIP_B_TX_PAGE_BOUNDARY
 866                                         : WMM_CHIP_A_TX_PAGE_BOUNDARY;
 867         }
 868         if (false == rtl92c_init_llt_table(hw, boundary)) {
 869                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 870                          "Failed to init LLT Table!\n");
 871                 return -EINVAL;
 872         }
 873         _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
 874                                           queue_sel);
 875         _rtl92c_init_trx_buffer(hw, wmm_enable);
 876         _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
 877                                      queue_sel);
 878         /* Get Rx PHY status in order to report RSSI and others. */
 879         rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
 880         rtl92c_init_interrupt(hw);
 881         rtl92c_init_network_type(hw);
 882         _rtl92cu_init_wmac_setting(hw);
 883         rtl92c_init_adaptive_ctrl(hw);
 884         rtl92c_init_edca(hw);
 885         rtl92c_init_rate_fallback(hw);
 886         rtl92c_init_retry_function(hw);
 887         _rtl92cu_init_usb_aggregation(hw);
 888         rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
 889         rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
 890         rtl92c_init_beacon_parameters(hw, rtlhal->version);
 891         rtl92c_init_ampdu_aggregation(hw);
 892         rtl92c_init_beacon_max_error(hw, true);
 893         return err;
 894 }
 895
 896 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
 897 {
 898         struct rtl_priv *rtlpriv = rtl_priv(hw);
 899         u8 sec_reg_value = 0x0;
 900         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 901
 902         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 903                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 904                  rtlpriv->sec.pairwise_enc_algorithm,
 905                  rtlpriv->sec.group_enc_algorithm);
 906         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 907                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 908                          "not open sw encryption\n");
 909                 return;
 910         }
 911         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 912         if (rtlpriv->sec.use_defaultkey) {
 913                 sec_reg_value |= SCR_TxUseDK;
 914                 sec_reg_value |= SCR_RxUseDK;
 915         }
 916         if (IS_NORMAL_CHIP(rtlhal->version))
 917                 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 918         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 919         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
 920                  sec_reg_value);
 921         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 922 }
 923
 924 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
 925 {
 926         struct rtl_priv *rtlpriv = rtl_priv(hw);
 927         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
 928
 929         /* To Fix MAC loopback mode fail. */
 930         rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
 931         rtl_write_byte(rtlpriv, 0x15, 0xe9);
 932         /* HW SEQ CTRL */
 933         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 934         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 935         /* fixed USB interface interference issue */
 936         rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
 937         rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
 938         rtl_write_byte(rtlpriv, 0xfe42, 0x80);
 939         rtlusb->reg_bcn_ctrl_val = 0x18;
 940         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
 941 }
 942
 943 static void _InitPABias(struct ieee80211_hw *hw)
 944 {
 945         struct rtl_priv *rtlpriv = rtl_priv(hw);
 946         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 947         u8 pa_setting;
 948
 949         /* FIXED PA current issue */
 950         pa_setting = efuse_read_1byte(hw, 0x1FA);
 951         if (!(pa_setting & BIT(0))) {
 952                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
 953                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
 954                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
 955                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
 956         }
 957         if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
 958             IS_92C_SERIAL(rtlhal->version)) {
 959                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
 960                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
 961                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
 962                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
 963         }
 964         if (!(pa_setting & BIT(4))) {
 965                 pa_setting = rtl_read_byte(rtlpriv, 0x16);
 966                 pa_setting &= 0x0F;
 967                 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
 968         }
 969 }
 970
 971 static void _update_mac_setting(struct ieee80211_hw *hw)
 972 {
 973         struct rtl_priv *rtlpriv = rtl_priv(hw);
 974         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 975
 976         mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
 977         mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
 978         mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
 979         mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
 980 }
 981
 982 int rtl92cu_hw_init(struct ieee80211_hw *hw)
 983 {
 984         struct rtl_priv *rtlpriv = rtl_priv(hw);
 985         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 986         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 987         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 988         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 989         int err = 0;
 990         static bool iqk_initialized;
 991         unsigned long flags;
 992
 993         /* As this function can take a very long time (up to 350 ms)
 994          * and can be called with irqs disabled, reenable the irqs
 995          * to let the other devices continue being serviced.
 996          *
 997          * It is safe doing so since our own interrupts will only be enabled
 998          * in a subsequent step.
 999          */
1000         local_save_flags(flags);
1001         local_irq_enable();
1002
1003         rtlhal->fw_ready = false;
1004         rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1005         err = _rtl92cu_init_mac(hw);
1006         if (err) {
1007                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n");
1008                 goto exit;
1009         }
1010         err = rtl92c_download_fw(hw);
1011         if (err) {
1012                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1013                          "Failed to download FW. Init HW without FW now..\n");
1014                 err = 1;
1015                 goto exit;
1016         }
1017
1018         rtlhal->fw_ready = true;
1019         rtlhal->last_hmeboxnum = 0; /* h2c */
1020         _rtl92cu_phy_param_tab_init(hw);
1021         rtl92cu_phy_mac_config(hw);
1022         rtl92cu_phy_bb_config(hw);
1023         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1024         rtl92c_phy_rf_config(hw);
1025         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1026             !IS_92C_SERIAL(rtlhal->version)) {
1027                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1028                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1029         }
1030         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1031                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1032         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1033                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1034         rtl92cu_bb_block_on(hw);
1035         rtl_cam_reset_all_entry(hw);
1036         rtl92cu_enable_hw_security_config(hw);
1037         ppsc->rfpwr_state = ERFON;
1038         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1039         if (ppsc->rfpwr_state == ERFON) {
1040                 rtl92c_phy_set_rfpath_switch(hw, 1);
1041                 if (iqk_initialized) {
1042                         rtl92c_phy_iq_calibrate(hw, true);
1043                 } else {
1044                         rtl92c_phy_iq_calibrate(hw, false);
1045                         iqk_initialized = true;
1046                 }
1047                 rtl92c_dm_check_txpower_tracking(hw);
1048                 rtl92c_phy_lc_calibrate(hw);
1049         }
1050         _rtl92cu_hw_configure(hw);
1051         _InitPABias(hw);
1052         _update_mac_setting(hw);
1053         rtl92c_dm_init(hw);
1054 exit:
1055         local_irq_restore(flags);
1056         return err;
1057 }
1058
1059 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1060 {
1061         struct rtl_priv *rtlpriv = rtl_priv(hw);
1062 /**************************************
1063 a.      TXPAUSE 0x522[7:0] = 0xFF       Pause MAC TX queue
1064 b.      RF path 0 offset 0x00 = 0x00    disable RF
1065 c.      APSD_CTRL 0x600[7:0] = 0x40
1066 d.      SYS_FUNC_EN 0x02[7:0] = 0x16    reset BB state machine
1067 e.      SYS_FUNC_EN 0x02[7:0] = 0x14    reset BB state machine
1068 ***************************************/
1069         u8 eRFPath = 0, value8 = 0;
1070         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1071         rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1072
1073         value8 |= APSDOFF;
1074         rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1075         value8 = 0;
1076         value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1077         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1078         value8 &= (~FEN_BB_GLB_RSTn);
1079         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1080 }
1081
1082 static void  _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1083 {
1084         struct rtl_priv *rtlpriv = rtl_priv(hw);
1085         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1086
1087         if (rtlhal->fw_version <=  0x20) {
1088                 /*****************************
1089                 f. MCUFWDL 0x80[7:0]=0          reset MCU ready status
1090                 g. SYS_FUNC_EN 0x02[10]= 0      reset MCU reg, (8051 reset)
1091                 h. SYS_FUNC_EN 0x02[15-12]= 5   reset MAC reg, DCORE
1092                 i. SYS_FUNC_EN 0x02[10]= 1      enable MCU reg, (8051 enable)
1093                 ******************************/
1094                 u16 valu16 = 0;
1095
1096                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1097                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1098                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1099                                (~FEN_CPUEN))); /* reset MCU ,8051 */
1100                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1101                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1102                               (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1103                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1104                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1105                                FEN_CPUEN)); /* enable MCU ,8051 */
1106         } else {
1107                 u8 retry_cnts = 0;
1108
1109                 /* IF fw in RAM code, do reset */
1110                 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1111                         /* reset MCU ready status */
1112                         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1113                         /* 8051 reset by self */
1114                         rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1115                         while ((retry_cnts++ < 100) &&
1116                                (FEN_CPUEN & rtl_read_word(rtlpriv,
1117                                REG_SYS_FUNC_EN))) {
1118                                 udelay(50);
1119                         }
1120                         if (retry_cnts >= 100) {
1121                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1122                                          "#####=> 8051 reset failed!.........................\n");
1123                                 /* if 8051 reset fail, reset MAC. */
1124                                 rtl_write_byte(rtlpriv,
1125                                                REG_SYS_FUNC_EN + 1,
1126                                                0x50);
1127                                 udelay(100);
1128                         }
1129                 }
1130                 /* Reset MAC and Enable 8051 */
1131                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1132                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1133         }
1134         if (bWithoutHWSM) {
1135                 /*****************************
1136                   Without HW auto state machine
1137                 g.SYS_CLKR 0x08[15:0] = 0x30A3          disable MAC clock
1138                 h.AFE_PLL_CTRL 0x28[7:0] = 0x80         disable AFE PLL
1139                 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F     gated AFE DIG_CLOCK
1140                 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9         isolated digital to PON
1141                 ******************************/
1142                 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1143                 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1144                 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1145                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1146         }
1147 }
1148
1149 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1150 {
1151         struct rtl_priv *rtlpriv = rtl_priv(hw);
1152 /*****************************
1153 k. SYS_FUNC_EN 0x03[7:0] = 0x44         disable ELDR runction
1154 l. SYS_CLKR 0x08[15:0] = 0x3083         disable ELDR clock
1155 m. SYS_ISO_CTRL 0x01[7:0] = 0x83        isolated ELDR to PON
1156 ******************************/
1157         rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1158         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1159 }
1160
1161 static void _DisableGPIO(struct ieee80211_hw *hw)
1162 {
1163         struct rtl_priv *rtlpriv = rtl_priv(hw);
1164 /***************************************
1165 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1166 k. Value = GPIO_PIN_CTRL[7:0]
1167 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1168 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1169 n. LEDCFG 0x4C[15:0] = 0x8080
1170 ***************************************/
1171         u8      value8;
1172         u16     value16;
1173         u32     value32;
1174
1175         /* 1. Disable GPIO[7:0] */
1176         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1177         value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1178         value8 = (u8)(value32&0x000000FF);
1179         value32 |= ((value8<<8) | 0x00FF0000);
1180         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1181         /* 2. Disable GPIO[10:8] */
1182         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1183         value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1184         value8 = (u8)(value16&0x000F);
1185         value16 |= ((value8<<4) | 0x0780);
1186         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1187         /* 3. Disable LED0 & 1 */
1188         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1189 }
1190
1191 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1192 {
1193         struct rtl_priv *rtlpriv = rtl_priv(hw);
1194         u16 value16 = 0;
1195         u8 value8 = 0;
1196
1197         if (bWithoutHWSM) {
1198                 /*****************************
1199                 n. LDOA15_CTRL 0x20[7:0] = 0x04  disable A15 power
1200                 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1201                 r. When driver call disable, the ASIC will turn off remaining
1202                    clock automatically
1203                 ******************************/
1204                 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1205                 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1206                 value8 &= (~LDV12_EN);
1207                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1208         }
1209
1210 /*****************************
1211 h. SPS0_CTRL 0x11[7:0] = 0x23           enter PFM mode
1212 i. APS_FSMCO 0x04[15:0] = 0x4802        set USB suspend
1213 ******************************/
1214         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1215         value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1216         rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1217         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1218 }
1219
1220 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1221 {
1222         /* ==== RF Off Sequence ==== */
1223         _DisableRFAFEAndResetBB(hw);
1224         /* ==== Reset digital sequence   ====== */
1225         _ResetDigitalProcedure1(hw, false);
1226         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1227         _DisableGPIO(hw);
1228         /* ==== Disable analog sequence === */
1229         _DisableAnalog(hw, false);
1230 }
1231
1232 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1233 {
1234         /*==== RF Off Sequence ==== */
1235         _DisableRFAFEAndResetBB(hw);
1236         /*  ==== Reset digital sequence   ====== */
1237         _ResetDigitalProcedure1(hw, true);
1238         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1239         _DisableGPIO(hw);
1240         /*  ==== Reset digital sequence   ====== */
1241         _ResetDigitalProcedure2(hw);
1242         /*  ==== Disable analog sequence === */
1243         _DisableAnalog(hw, true);
1244 }
1245
1246 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1247                                       u8 set_bits, u8 clear_bits)
1248 {
1249         struct rtl_priv *rtlpriv = rtl_priv(hw);
1250         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1251
1252         rtlusb->reg_bcn_ctrl_val |= set_bits;
1253         rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1254         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1255 }
1256
1257 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1258 {
1259         struct rtl_priv *rtlpriv = rtl_priv(hw);
1260         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1261         u8 tmp1byte = 0;
1262         if (IS_NORMAL_CHIP(rtlhal->version)) {
1263                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1264                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1265                                tmp1byte & (~BIT(6)));
1266                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1267                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1268                 tmp1byte &= ~(BIT(0));
1269                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1270         } else {
1271                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1272                                rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1273         }
1274 }
1275
1276 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1277 {
1278         struct rtl_priv *rtlpriv = rtl_priv(hw);
1279         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1280         u8 tmp1byte = 0;
1281
1282         if (IS_NORMAL_CHIP(rtlhal->version)) {
1283                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1284                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1285                                tmp1byte | BIT(6));
1286                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1287                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1288                 tmp1byte |= BIT(0);
1289                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1290         } else {
1291                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1292                                rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1293         }
1294 }
1295
1296 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1297 {
1298         struct rtl_priv *rtlpriv = rtl_priv(hw);
1299         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1300
1301         if (IS_NORMAL_CHIP(rtlhal->version))
1302                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1303         else
1304                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1305 }
1306
1307 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1308 {
1309         struct rtl_priv *rtlpriv = rtl_priv(hw);
1310         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1311
1312         if (IS_NORMAL_CHIP(rtlhal->version))
1313                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1314         else
1315                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1316 }
1317
1318 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1319                                      enum nl80211_iftype type)
1320 {
1321         struct rtl_priv *rtlpriv = rtl_priv(hw);
1322         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1323         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1324
1325         bt_msr &= 0xfc;
1326         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1327         if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1328             NL80211_IFTYPE_STATION) {
1329                 _rtl92cu_stop_tx_beacon(hw);
1330                 _rtl92cu_enable_bcn_sub_func(hw);
1331         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1332                 _rtl92cu_resume_tx_beacon(hw);
1333                 _rtl92cu_disable_bcn_sub_func(hw);
1334         } else {
1335                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1336                          "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1337                          type);
1338         }
1339         switch (type) {
1340         case NL80211_IFTYPE_UNSPECIFIED:
1341                 bt_msr |= MSR_NOLINK;
1342                 ledaction = LED_CTL_LINK;
1343                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1344                          "Set Network type to NO LINK!\n");
1345                 break;
1346         case NL80211_IFTYPE_ADHOC:
1347                 bt_msr |= MSR_ADHOC;
1348                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1349                          "Set Network type to Ad Hoc!\n");
1350                 break;
1351         case NL80211_IFTYPE_STATION:
1352                 bt_msr |= MSR_INFRA;
1353                 ledaction = LED_CTL_LINK;
1354                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1355                          "Set Network type to STA!\n");
1356                 break;
1357         case NL80211_IFTYPE_AP:
1358                 bt_msr |= MSR_AP;
1359                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1360                          "Set Network type to AP!\n");
1361                 break;
1362         default:
1363                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1364                          "Network type %d not supported!\n", type);
1365                 goto error_out;
1366         }
1367         rtl_write_byte(rtlpriv, MSR, bt_msr);
1368         rtlpriv->cfg->ops->led_control(hw, ledaction);
1369         if ((bt_msr & MSR_MASK) == MSR_AP)
1370                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1371         else
1372                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1373         return 0;
1374 error_out:
1375         return 1;
1376 }
1377
1378 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1379 {
1380         struct rtl_priv *rtlpriv = rtl_priv(hw);
1381         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1382         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1383         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1384         enum nl80211_iftype opmode;
1385
1386         mac->link_state = MAC80211_NOLINK;
1387         opmode = NL80211_IFTYPE_UNSPECIFIED;
1388         _rtl92cu_set_media_status(hw, opmode);
1389         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1390         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1391         if (rtlusb->disableHWSM)
1392                 _CardDisableHWSM(hw);
1393         else
1394                 _CardDisableWithoutHWSM(hw);
1395 }
1396
1397 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1398 {
1399         struct rtl_priv *rtlpriv = rtl_priv(hw);
1400         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1401         u32 reg_rcr;
1402
1403         if (rtlpriv->psc.rfpwr_state != ERFON)
1404                 return;
1405
1406         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1407
1408         if (check_bssid) {
1409                 u8 tmp;
1410                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1411                         reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1412                         tmp = BIT(4);
1413                 } else {
1414                         reg_rcr |= RCR_CBSSID;
1415                         tmp = BIT(4) | BIT(5);
1416                 }
1417                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1418                                               (u8 *) (&reg_rcr));
1419                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp);
1420         } else {
1421                 u8 tmp;
1422                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1423                         reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1424                         tmp = BIT(4);
1425                 } else {
1426                         reg_rcr &= ~RCR_CBSSID;
1427                         tmp = BIT(4) | BIT(5);
1428                 }
1429                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1430                 rtlpriv->cfg->ops->set_hw_reg(hw,
1431                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1432                 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0);
1433         }
1434 }
1435
1436 /*========================================================================== */
1437
1438 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1439 {
1440         struct rtl_priv *rtlpriv = rtl_priv(hw);
1441
1442         if (_rtl92cu_set_media_status(hw, type))
1443                 return -EOPNOTSUPP;
1444
1445         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1446                 if (type != NL80211_IFTYPE_AP)
1447                         rtl92cu_set_check_bssid(hw, true);
1448         } else {
1449                 rtl92cu_set_check_bssid(hw, false);
1450         }
1451
1452         return 0;
1453 }
1454
1455 static void _InitBeaconParameters(struct ieee80211_hw *hw)
1456 {
1457         struct rtl_priv *rtlpriv = rtl_priv(hw);
1458         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1459
1460         rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1461
1462         /* TODO: Remove these magic number */
1463         rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1464         rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1465         rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1466         /* Change beacon AIFS to the largest number
1467          * beacause test chip does not contension before sending beacon. */
1468         if (IS_NORMAL_CHIP(rtlhal->version))
1469                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1470         else
1471                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1472 }
1473
1474 static void _beacon_function_enable(struct ieee80211_hw *hw)
1475 {
1476         struct rtl_priv *rtlpriv = rtl_priv(hw);
1477
1478         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1479         rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1480 }
1481
1482 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1483 {
1484
1485         struct rtl_priv *rtlpriv = rtl_priv(hw);
1486         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1487         u16 bcn_interval, atim_window;
1488         u32 value32;
1489
1490         bcn_interval = mac->beacon_interval;
1491         atim_window = 2;        /*FIX MERGE */
1492         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1493         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1494         _InitBeaconParameters(hw);
1495         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1496         /*
1497          * Force beacon frame transmission even after receiving beacon frame
1498          * from other ad hoc STA
1499          *
1500          *
1501          * Reset TSF Timer to zero, added by Roger. 2008.06.24
1502          */
1503         value32 = rtl_read_dword(rtlpriv, REG_TCR);
1504         value32 &= ~TSFRST;
1505         rtl_write_dword(rtlpriv, REG_TCR, value32);
1506         value32 |= TSFRST;
1507         rtl_write_dword(rtlpriv, REG_TCR, value32);
1508         RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1509                  "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1510                  value32);
1511         /* TODO: Modify later (Find the right parameters)
1512          * NOTE: Fix test chip's bug (about contention windows's randomness) */
1513         if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1514             (mac->opmode == NL80211_IFTYPE_MESH_POINT) ||
1515             (mac->opmode == NL80211_IFTYPE_AP)) {
1516                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1517                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1518         }
1519         _beacon_function_enable(hw);
1520 }
1521
1522 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1523 {
1524         struct rtl_priv *rtlpriv = rtl_priv(hw);
1525         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1526         u16 bcn_interval = mac->beacon_interval;
1527
1528         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1529                  bcn_interval);
1530         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1531 }
1532
1533 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1534                                    u32 add_msr, u32 rm_msr)
1535 {
1536 }
1537
1538 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1539 {
1540         struct rtl_priv *rtlpriv = rtl_priv(hw);
1541         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1542         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1543
1544         switch (variable) {
1545         case HW_VAR_RCR:
1546                 *((u32 *)(val)) = mac->rx_conf;
1547                 break;
1548         case HW_VAR_RF_STATE:
1549                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1550                 break;
1551         case HW_VAR_FWLPS_RF_ON:{
1552                         enum rf_pwrstate rfState;
1553                         u32 val_rcr;
1554
1555                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1556                                                       (u8 *)(&rfState));
1557                         if (rfState == ERFOFF) {
1558                                 *((bool *) (val)) = true;
1559                         } else {
1560                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1561                                 val_rcr &= 0x00070000;
1562                                 if (val_rcr)
1563                                         *((bool *) (val)) = false;
1564                                 else
1565                                         *((bool *) (val)) = true;
1566                         }
1567                         break;
1568                 }
1569         case HW_VAR_FW_PSMODE_STATUS:
1570                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1571                 break;
1572         case HW_VAR_CORRECT_TSF:{
1573                         u64 tsf;
1574                         u32 *ptsf_low = (u32 *)&tsf;
1575                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
1576
1577                         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1578                         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1579                         *((u64 *)(val)) = tsf;
1580                         break;
1581                 }
1582         case HW_VAR_MGT_FILTER:
1583                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1584                 break;
1585         case HW_VAR_CTRL_FILTER:
1586                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1587                 break;
1588         case HW_VAR_DATA_FILTER:
1589                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1590                 break;
1591         case HAL_DEF_WOWLAN:
1592                 break;
1593         default:
1594                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1595                          "switch case not processed\n");
1596                 break;
1597         }
1598 }
1599
1600 static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)
1601 {
1602   /* Currently nothing happens here.
1603    * Traffic stops after some seconds in WPA2 802.11n mode.
1604    * Maybe because rtl8192cu chip should be set from here?
1605    * If I understand correctly, the realtek vendor driver sends some urbs
1606    * if its "here".
1607    *
1608    * This is maybe necessary:
1609    * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb);
1610    */
1611         return true;
1612 }
1613
1614 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1615 {
1616         struct rtl_priv *rtlpriv = rtl_priv(hw);
1617         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1618         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1619         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1620         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1621         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1622         enum wireless_mode wirelessmode = mac->mode;
1623         u8 idx = 0;
1624
1625         switch (variable) {
1626         case HW_VAR_ETHER_ADDR:{
1627                         for (idx = 0; idx < ETH_ALEN; idx++) {
1628                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1629                                                val[idx]);
1630                         }
1631                         break;
1632                 }
1633         case HW_VAR_BASIC_RATE:{
1634                         u16 rate_cfg = ((u16 *) val)[0];
1635                         u8 rate_index = 0;
1636
1637                         rate_cfg &= 0x15f;
1638                         /* TODO */
1639                         /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1640                          *     && ((rate_cfg & 0x150) == 0)) {
1641                          *        rate_cfg |= 0x010;
1642                          * } */
1643                         rate_cfg |= 0x01;
1644                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1645                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
1646                                        (rate_cfg >> 8) & 0xff);
1647                         while (rate_cfg > 0x1) {
1648                                 rate_cfg >>= 1;
1649                                 rate_index++;
1650                         }
1651                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1652                                        rate_index);
1653                         break;
1654                 }
1655         case HW_VAR_BSSID:{
1656                         for (idx = 0; idx < ETH_ALEN; idx++) {
1657                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1658                                                val[idx]);
1659                         }
1660                         break;
1661                 }
1662         case HW_VAR_SIFS:{
1663                         rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1664                         rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1665                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1666                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1667                         rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1668                         rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1669                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
1670                         break;
1671                 }
1672         case HW_VAR_SLOT_TIME:{
1673                         u8 e_aci;
1674                         u8 QOS_MODE = 1;
1675
1676                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1677                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1678                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
1679                         if (QOS_MODE) {
1680                                 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1681                                         rtlpriv->cfg->ops->set_hw_reg(hw,
1682                                                                 HW_VAR_AC_PARAM,
1683                                                                 &e_aci);
1684                         } else {
1685                                 u8 sifstime = 0;
1686                                 u8      u1bAIFS;
1687
1688                                 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1689                                     IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1690                                     IS_WIRELESS_MODE_N_5G(wirelessmode))
1691                                         sifstime = 16;
1692                                 else
1693                                         sifstime = 10;
1694                                 u1bAIFS = sifstime + (2 *  val[0]);
1695                                 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1696                                                u1bAIFS);
1697                                 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1698                                                u1bAIFS);
1699                                 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1700                                                u1bAIFS);
1701                                 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1702                                                u1bAIFS);
1703                         }
1704                         break;
1705                 }
1706         case HW_VAR_ACK_PREAMBLE:{
1707                         u8 reg_tmp;
1708                         u8 short_preamble = (bool)*val;
1709                         reg_tmp = 0;
1710                         if (short_preamble)
1711                                 reg_tmp |= 0x80;
1712                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1713                         break;
1714                 }
1715         case HW_VAR_AMPDU_MIN_SPACE:{
1716                         u8 min_spacing_to_set;
1717                         u8 sec_min_space;
1718
1719                         min_spacing_to_set = *val;
1720                         if (min_spacing_to_set <= 7) {
1721                                 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1722                                 case NO_ENCRYPTION:
1723                                 case AESCCMP_ENCRYPTION:
1724                                         sec_min_space = 0;
1725                                         break;
1726                                 case WEP40_ENCRYPTION:
1727                                 case WEP104_ENCRYPTION:
1728                                 case TKIP_ENCRYPTION:
1729                                         sec_min_space = 6;
1730                                         break;
1731                                 default:
1732                                         sec_min_space = 7;
1733                                         break;
1734                                 }
1735                                 if (min_spacing_to_set < sec_min_space)
1736                                         min_spacing_to_set = sec_min_space;
1737                                 mac->min_space_cfg = ((mac->min_space_cfg &
1738                                                      0xf8) |
1739                                                      min_spacing_to_set);
1740                                 *val = min_spacing_to_set;
1741                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1742                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1743                                          mac->min_space_cfg);
1744                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1745                                                mac->min_space_cfg);
1746                         }
1747                         break;
1748                 }
1749         case HW_VAR_SHORTGI_DENSITY:{
1750                         u8 density_to_set;
1751
1752                         density_to_set = *val;
1753                         density_to_set &= 0x1f;
1754                         mac->min_space_cfg &= 0x07;
1755                         mac->min_space_cfg |= (density_to_set << 3);
1756                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1757                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1758                                  mac->min_space_cfg);
1759                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1760                                        mac->min_space_cfg);
1761                         break;
1762                 }
1763         case HW_VAR_AMPDU_FACTOR:{
1764                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1765                         u8 factor_toset;
1766                         u8 *p_regtoset = NULL;
1767                         u8 index = 0;
1768
1769                         p_regtoset = regtoset_normal;
1770                         factor_toset = *val;
1771                         if (factor_toset <= 3) {
1772                                 factor_toset = (1 << (factor_toset + 2));
1773                                 if (factor_toset > 0xf)
1774                                         factor_toset = 0xf;
1775                                 for (index = 0; index < 4; index++) {
1776                                         if ((p_regtoset[index] & 0xf0) >
1777                                             (factor_toset << 4))
1778                                                 p_regtoset[index] =
1779                                                      (p_regtoset[index] & 0x0f)
1780                                                      | (factor_toset << 4);
1781                                         if ((p_regtoset[index] & 0x0f) >
1782                                              factor_toset)
1783                                                 p_regtoset[index] =
1784                                                      (p_regtoset[index] & 0xf0)
1785                                                      | (factor_toset);
1786                                         rtl_write_byte(rtlpriv,
1787                                                        (REG_AGGLEN_LMT + index),
1788                                                        p_regtoset[index]);
1789                                 }
1790                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1791                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1792                                          factor_toset);
1793                         }
1794                         break;
1795                 }
1796         case HW_VAR_AC_PARAM:{
1797                         u8 e_aci = *val;
1798                         u32 u4b_ac_param;
1799                         u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1800                         u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1801                         u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1802
1803                         u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1804                         u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1805                                          AC_PARAM_ECW_MIN_OFFSET);
1806                         u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1807                                          AC_PARAM_ECW_MAX_OFFSET);
1808                         u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1809                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1810                                  "queue:%x, ac_param:%x\n",
1811                                  e_aci, u4b_ac_param);
1812                         switch (e_aci) {
1813                         case AC1_BK:
1814                                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1815                                                 u4b_ac_param);
1816                                 break;
1817                         case AC0_BE:
1818                                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1819                                                 u4b_ac_param);
1820                                 break;
1821                         case AC2_VI:
1822                                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1823                                                 u4b_ac_param);
1824                                 break;
1825                         case AC3_VO:
1826                                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1827                                                 u4b_ac_param);
1828                                 break;
1829                         default:
1830                                 RT_ASSERT(false,
1831                                           "SetHwReg8185(): invalid aci: %d !\n",
1832                                           e_aci);
1833                                 break;
1834                         }
1835                         if (rtlusb->acm_method != EACMWAY2_SW)
1836                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1837                                          HW_VAR_ACM_CTRL, &e_aci);
1838                         break;
1839                 }
1840         case HW_VAR_ACM_CTRL:{
1841                         u8 e_aci = *val;
1842                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
1843                                                         (&(mac->ac[0].aifs));
1844                         u8 acm = p_aci_aifsn->f.acm;
1845                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
1846
1847                         acm_ctrl =
1848                             acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
1849                         if (acm) {
1850                                 switch (e_aci) {
1851                                 case AC0_BE:
1852                                         acm_ctrl |= AcmHw_BeqEn;
1853                                         break;
1854                                 case AC2_VI:
1855                                         acm_ctrl |= AcmHw_ViqEn;
1856                                         break;
1857                                 case AC3_VO:
1858                                         acm_ctrl |= AcmHw_VoqEn;
1859                                         break;
1860                                 default:
1861                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1862                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
1863                                                  acm);
1864                                         break;
1865                                 }
1866                         } else {
1867                                 switch (e_aci) {
1868                                 case AC0_BE:
1869                                         acm_ctrl &= (~AcmHw_BeqEn);
1870                                         break;
1871                                 case AC2_VI:
1872                                         acm_ctrl &= (~AcmHw_ViqEn);
1873                                         break;
1874                                 case AC3_VO:
1875                                         acm_ctrl &= (~AcmHw_VoqEn);
1876                                         break;
1877                                 default:
1878                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1879                                                  "switch case not processed\n");
1880                                         break;
1881                                 }
1882                         }
1883                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
1884                                  "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
1885                                  acm_ctrl);
1886                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
1887                         break;
1888                 }
1889         case HW_VAR_RCR:{
1890                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
1891                         mac->rx_conf = ((u32 *) (val))[0];
1892                         RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
1893                                  "### Set RCR(0x%08x) ###\n", mac->rx_conf);
1894                         break;
1895                 }
1896         case HW_VAR_RETRY_LIMIT:{
1897                         u8 retry_limit = val[0];
1898
1899                         rtl_write_word(rtlpriv, REG_RL,
1900                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
1901                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
1902                         RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG,
1903                                  "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
1904                                  retry_limit);
1905                         break;
1906                 }
1907         case HW_VAR_DUAL_TSF_RST:
1908                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1909                 break;
1910         case HW_VAR_EFUSE_BYTES:
1911                 rtlefuse->efuse_usedbytes = *((u16 *) val);
1912                 break;
1913         case HW_VAR_EFUSE_USAGE:
1914                 rtlefuse->efuse_usedpercentage = *val;
1915                 break;
1916         case HW_VAR_IO_CMD:
1917                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
1918                 break;
1919         case HW_VAR_WPA_CONFIG:
1920                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
1921                 break;
1922         case HW_VAR_SET_RPWM:{
1923                         u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
1924
1925                         if (rpwm_val & BIT(7))
1926                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val);
1927                         else
1928                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
1929                                                *val | BIT(7));
1930                         break;
1931                 }
1932         case HW_VAR_H2C_FW_PWRMODE:{
1933                         u8 psmode = *val;
1934
1935                         if ((psmode != FW_PS_ACTIVE_MODE) &&
1936                            (!IS_92C_SERIAL(rtlhal->version)))
1937                                 rtl92c_dm_rf_saving(hw, true);
1938                         rtl92c_set_fw_pwrmode_cmd(hw, (*val));
1939                         break;
1940                 }
1941         case HW_VAR_FW_PSMODE_STATUS:
1942                 ppsc->fw_current_inpsmode = *((bool *) val);
1943                 break;
1944         case HW_VAR_H2C_FW_JOINBSSRPT:{
1945                         u8 mstatus = *val;
1946                         u8 tmp_reg422;
1947                         bool recover = false;
1948
1949                         if (mstatus == RT_MEDIA_CONNECT) {
1950                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1951                                                          HW_VAR_AID, NULL);
1952                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
1953                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1954                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1955                                 tmp_reg422 = rtl_read_byte(rtlpriv,
1956                                                         REG_FWHW_TXQ_CTRL + 2);
1957                                 if (tmp_reg422 & BIT(6))
1958                                         recover = true;
1959                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1960                                                tmp_reg422 & (~BIT(6)));
1961                                 rtl92c_set_fw_rsvdpagepkt(hw,
1962                                                           &usb_cmd_send_packet);
1963                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1964                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1965                                 if (recover)
1966                                         rtl_write_byte(rtlpriv,
1967                                                  REG_FWHW_TXQ_CTRL + 2,
1968                                                 tmp_reg422 | BIT(6));
1969                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1970                         }
1971                         rtl92c_set_fw_joinbss_report_cmd(hw, (*val));
1972                         break;
1973                 }
1974         case HW_VAR_AID:{
1975                         u16 u2btmp;
1976
1977                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
1978                         u2btmp &= 0xC000;
1979                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
1980                                        (u2btmp | mac->assoc_id));
1981                         break;
1982                 }
1983         case HW_VAR_CORRECT_TSF:{
1984                         u8 btype_ibss = val[0];
1985
1986                         if (btype_ibss)
1987                                 _rtl92cu_stop_tx_beacon(hw);
1988                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1989                         rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
1990                                         0xffffffff));
1991                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
1992                                         (u32)((mac->tsf >> 32) & 0xffffffff));
1993                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1994                         if (btype_ibss)
1995                                 _rtl92cu_resume_tx_beacon(hw);
1996                         break;
1997                 }
1998         case HW_VAR_MGT_FILTER:
1999                 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
2000                 break;
2001         case HW_VAR_CTRL_FILTER:
2002                 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
2003                 break;
2004         case HW_VAR_DATA_FILTER:
2005                 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
2006                 break;
2007         default:
2008                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2009                          "switch case not processed\n");
2010                 break;
2011         }
2012 }
2013
2014 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
2015                                           struct ieee80211_sta *sta)
2016 {
2017         struct rtl_priv *rtlpriv = rtl_priv(hw);
2018         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2019         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2020         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2021         u32 ratr_value;
2022         u8 ratr_index = 0;
2023         u8 nmode = mac->ht_enable;
2024         u8 mimo_ps = IEEE80211_SMPS_OFF;
2025         u16 shortgi_rate;
2026         u32 tmp_ratr_value;
2027         u8 curtxbw_40mhz = mac->bw_40;
2028         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2029                                1 : 0;
2030         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2031                                1 : 0;
2032         enum wireless_mode wirelessmode = mac->mode;
2033
2034         if (rtlhal->current_bandtype == BAND_ON_5G)
2035                 ratr_value = sta->supp_rates[1] << 4;
2036         else
2037                 ratr_value = sta->supp_rates[0];
2038         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2039                 ratr_value = 0xfff;
2040
2041         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2042                         sta->ht_cap.mcs.rx_mask[0] << 12);
2043         switch (wirelessmode) {
2044         case WIRELESS_MODE_B:
2045                 if (ratr_value & 0x0000000c)
2046                         ratr_value &= 0x0000000d;
2047                 else
2048                         ratr_value &= 0x0000000f;
2049                 break;
2050         case WIRELESS_MODE_G:
2051                 ratr_value &= 0x00000FF5;
2052                 break;
2053         case WIRELESS_MODE_N_24G:
2054         case WIRELESS_MODE_N_5G:
2055                 nmode = 1;
2056                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2057                         ratr_value &= 0x0007F005;
2058                 } else {
2059                         u32 ratr_mask;
2060
2061                         if (get_rf_type(rtlphy) == RF_1T2R ||
2062                             get_rf_type(rtlphy) == RF_1T1R)
2063                                 ratr_mask = 0x000ff005;
2064                         else
2065                                 ratr_mask = 0x0f0ff005;
2066
2067                         ratr_value &= ratr_mask;
2068                 }
2069                 break;
2070         default:
2071                 if (rtlphy->rf_type == RF_1T2R)
2072                         ratr_value &= 0x000ff0ff;
2073                 else
2074                         ratr_value &= 0x0f0ff0ff;
2075
2076                 break;
2077         }
2078
2079         ratr_value &= 0x0FFFFFFF;
2080
2081         if (nmode && ((curtxbw_40mhz &&
2082                          curshortgi_40mhz) || (!curtxbw_40mhz &&
2083                                                curshortgi_20mhz))) {
2084
2085                 ratr_value |= 0x10000000;
2086                 tmp_ratr_value = (ratr_value >> 12);
2087
2088                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2089                         if ((1 << shortgi_rate) & tmp_ratr_value)
2090                                 break;
2091                 }
2092
2093                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2094                     (shortgi_rate << 4) | (shortgi_rate);
2095         }
2096
2097         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2098
2099         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2100                  rtl_read_dword(rtlpriv, REG_ARFR0));
2101 }
2102
2103 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
2104                                          struct ieee80211_sta *sta,
2105                                          u8 rssi_level)
2106 {
2107         struct rtl_priv *rtlpriv = rtl_priv(hw);
2108         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2109         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2110         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2111         struct rtl_sta_info *sta_entry = NULL;
2112         u32 ratr_bitmap;
2113         u8 ratr_index;
2114         u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2115         u8 curshortgi_40mhz = curtxbw_40mhz &&
2116                               (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2117                                 1 : 0;
2118         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2119                                 1 : 0;
2120         enum wireless_mode wirelessmode = 0;
2121         bool shortgi = false;
2122         u8 rate_mask[5];
2123         u8 macid = 0;
2124         u8 mimo_ps = IEEE80211_SMPS_OFF;
2125
2126         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2127         wirelessmode = sta_entry->wireless_mode;
2128         if (mac->opmode == NL80211_IFTYPE_STATION ||
2129             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2130                 curtxbw_40mhz = mac->bw_40;
2131         else if (mac->opmode == NL80211_IFTYPE_AP ||
2132                 mac->opmode == NL80211_IFTYPE_ADHOC)
2133                 macid = sta->aid + 1;
2134
2135         if (rtlhal->current_bandtype == BAND_ON_5G)
2136                 ratr_bitmap = sta->supp_rates[1] << 4;
2137         else
2138                 ratr_bitmap = sta->supp_rates[0];
2139         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2140                 ratr_bitmap = 0xfff;
2141         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2142                         sta->ht_cap.mcs.rx_mask[0] << 12);
2143         switch (wirelessmode) {
2144         case WIRELESS_MODE_B:
2145                 ratr_index = RATR_INX_WIRELESS_B;
2146                 if (ratr_bitmap & 0x0000000c)
2147                         ratr_bitmap &= 0x0000000d;
2148                 else
2149                         ratr_bitmap &= 0x0000000f;
2150                 break;
2151         case WIRELESS_MODE_G:
2152                 ratr_index = RATR_INX_WIRELESS_GB;
2153
2154                 if (rssi_level == 1)
2155                         ratr_bitmap &= 0x00000f00;
2156                 else if (rssi_level == 2)
2157                         ratr_bitmap &= 0x00000ff0;
2158                 else
2159                         ratr_bitmap &= 0x00000ff5;
2160                 break;
2161         case WIRELESS_MODE_A:
2162                 ratr_index = RATR_INX_WIRELESS_A;
2163                 ratr_bitmap &= 0x00000ff0;
2164                 break;
2165         case WIRELESS_MODE_N_24G:
2166         case WIRELESS_MODE_N_5G:
2167                 ratr_index = RATR_INX_WIRELESS_NGB;
2168
2169                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2170                         if (rssi_level == 1)
2171                                 ratr_bitmap &= 0x00070000;
2172                         else if (rssi_level == 2)
2173                                 ratr_bitmap &= 0x0007f000;
2174                         else
2175                                 ratr_bitmap &= 0x0007f005;
2176                 } else {
2177                         if (rtlphy->rf_type == RF_1T2R ||
2178                             rtlphy->rf_type == RF_1T1R) {
2179                                 if (curtxbw_40mhz) {
2180                                         if (rssi_level == 1)
2181                                                 ratr_bitmap &= 0x000f0000;
2182                                         else if (rssi_level == 2)
2183                                                 ratr_bitmap &= 0x000ff000;
2184                                         else
2185                                                 ratr_bitmap &= 0x000ff015;
2186                                 } else {
2187                                         if (rssi_level == 1)
2188                                                 ratr_bitmap &= 0x000f0000;
2189                                         else if (rssi_level == 2)
2190                                                 ratr_bitmap &= 0x000ff000;
2191                                         else
2192                                                 ratr_bitmap &= 0x000ff005;
2193                                 }
2194                         } else {
2195                                 if (curtxbw_40mhz) {
2196                                         if (rssi_level == 1)
2197                                                 ratr_bitmap &= 0x0f0f0000;
2198                                         else if (rssi_level == 2)
2199                                                 ratr_bitmap &= 0x0f0ff000;
2200                                         else
2201                                                 ratr_bitmap &= 0x0f0ff015;
2202                                 } else {
2203                                         if (rssi_level == 1)
2204                                                 ratr_bitmap &= 0x0f0f0000;
2205                                         else if (rssi_level == 2)
2206                                                 ratr_bitmap &= 0x0f0ff000;
2207                                         else
2208                                                 ratr_bitmap &= 0x0f0ff005;
2209                                 }
2210                         }
2211                 }
2212
2213                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2214                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2215
2216                         if (macid == 0)
2217                                 shortgi = true;
2218                         else if (macid == 1)
2219                                 shortgi = false;
2220                 }
2221                 break;
2222         default:
2223                 ratr_index = RATR_INX_WIRELESS_NGB;
2224
2225                 if (rtlphy->rf_type == RF_1T2R)
2226                         ratr_bitmap &= 0x000ff0ff;
2227                 else
2228                         ratr_bitmap &= 0x0f0ff0ff;
2229                 break;
2230         }
2231         sta_entry->ratr_index = ratr_index;
2232
2233         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2234                  "ratr_bitmap :%x\n", ratr_bitmap);
2235         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2236                                      (ratr_index << 28);
2237         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2238         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2239                  "Rate_index:%x, ratr_val:%x, %5phC\n",
2240                  ratr_index, ratr_bitmap, rate_mask);
2241         memcpy(rtlpriv->rate_mask, rate_mask, 5);
2242         /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
2243          * "scheduled while atomic" if called directly */
2244         schedule_work(&rtlpriv->works.fill_h2c_cmd);
2245
2246         if (macid != 0)
2247                 sta_entry->ratr_index = ratr_index;
2248 }
2249
2250 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
2251                                  struct ieee80211_sta *sta,
2252                                  u8 rssi_level)
2253 {
2254         struct rtl_priv *rtlpriv = rtl_priv(hw);
2255
2256         if (rtlpriv->dm.useramask)
2257                 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
2258         else
2259                 rtl92cu_update_hal_rate_table(hw, sta);
2260 }
2261
2262 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2263 {
2264         struct rtl_priv *rtlpriv = rtl_priv(hw);
2265         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2266         u16 sifs_timer;
2267
2268         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2269                                       &mac->slot_time);
2270         if (!mac->ht_enable)
2271                 sifs_timer = 0x0a0a;
2272         else
2273                 sifs_timer = 0x0e0e;
2274         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2275 }
2276
2277 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2278 {
2279         struct rtl_priv *rtlpriv = rtl_priv(hw);
2280         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2281         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2282         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2283         u8 u1tmp = 0;
2284         bool actuallyset = false;
2285         unsigned long flag = 0;
2286         /* to do - usb autosuspend */
2287         u8 usb_autosuspend = 0;
2288
2289         if (ppsc->swrf_processing)
2290                 return false;
2291         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2292         if (ppsc->rfchange_inprogress) {
2293                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2294                 return false;
2295         } else {
2296                 ppsc->rfchange_inprogress = true;
2297                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2298         }
2299         cur_rfstate = ppsc->rfpwr_state;
2300         if (usb_autosuspend) {
2301                 /* to do................... */
2302         } else {
2303                 if (ppsc->pwrdown_mode) {
2304                         u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2305                         e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2306                                                ERFOFF : ERFON;
2307                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2308                                  "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
2309                 } else {
2310                         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2311                                        rtl_read_byte(rtlpriv,
2312                                        REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2313                         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2314                         e_rfpowerstate_toset  = (u1tmp & BIT(3)) ?
2315                                                  ERFON : ERFOFF;
2316                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2317                                  "GPIO_IN=%02x\n", u1tmp);
2318                 }
2319                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2320                          e_rfpowerstate_toset);
2321         }
2322         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2323                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2324                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2325                 ppsc->hwradiooff = false;
2326                 actuallyset = true;
2327         } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset  ==
2328                     ERFOFF)) {
2329                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2330                          "GPIOChangeRF  - HW Radio OFF\n");
2331                 ppsc->hwradiooff = true;
2332                 actuallyset = true;
2333         } else {
2334                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2335                          "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2336                          ppsc->hwradiooff, e_rfpowerstate_toset);
2337         }
2338         if (actuallyset) {
2339                 ppsc->hwradiooff = true;
2340                 if (e_rfpowerstate_toset == ERFON) {
2341                         if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM) &&
2342                              RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2343                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2344                         else if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2345                                  && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2346                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2347                 }
2348                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2349                 ppsc->rfchange_inprogress = false;
2350                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2351                 /* For power down module, we need to enable register block
2352                  * contrl reg at 0x1c. Then enable power down control bit
2353                  * of register 0x04 BIT4 and BIT15 as 1.
2354                  */
2355                 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2356                         /* Enable register area 0x0-0xc. */
2357                         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2358                         if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2359                                 /*
2360                                  * We should configure HW PDn source for WiFi
2361                                  * ONLY, and then our HW will be set in
2362                                  * power-down mode if PDn source from all
2363                                  * functions are configured.
2364                                  */
2365                                 u1tmp = rtl_read_byte(rtlpriv,
2366                                                       REG_MULTI_FUNC_CTRL);
2367                                 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2368                                                (u1tmp|WL_HWPDN_EN));
2369                         } else {
2370                                 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2371                         }
2372                 }
2373                 if (e_rfpowerstate_toset == ERFOFF) {
2374                         if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2375                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2376                         else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2377                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2378                 }
2379         } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2380                 /* Enter D3 or ASPM after GPIO had been done. */
2381                 if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2382                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2383                 else if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2384                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2385                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2386                 ppsc->rfchange_inprogress = false;
2387                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2388         } else {
2389                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2390                 ppsc->rfchange_inprogress = false;
2391                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2392         }
2393         *valid = 1;
2394         return !ppsc->hwradiooff;
2395 }