kernel/drivers/net/wireless/rtlwifi/rtl8188ee/dm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../base.h"
  28 #include "../pci.h"
  29 #include "../core.h"
  30 #include "reg.h"
  31 #include "def.h"
  32 #include "phy.h"
  33 #include "dm.h"
  34 #include "fw.h"
  35 #include "trx.h"
  36
  37 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  38         0x7f8001fe,             /* 0, +6.0dB */
  39         0x788001e2,             /* 1, +5.5dB */
  40         0x71c001c7,             /* 2, +5.0dB */
  41         0x6b8001ae,             /* 3, +4.5dB */
  42         0x65400195,             /* 4, +4.0dB */
  43         0x5fc0017f,             /* 5, +3.5dB */
  44         0x5a400169,             /* 6, +3.0dB */
  45         0x55400155,             /* 7, +2.5dB */
  46         0x50800142,             /* 8, +2.0dB */
  47         0x4c000130,             /* 9, +1.5dB */
  48         0x47c0011f,             /* 10, +1.0dB */
  49         0x43c0010f,             /* 11, +0.5dB */
  50         0x40000100,             /* 12, +0dB */
  51         0x3c8000f2,             /* 13, -0.5dB */
  52         0x390000e4,             /* 14, -1.0dB */
  53         0x35c000d7,             /* 15, -1.5dB */
  54         0x32c000cb,             /* 16, -2.0dB */
  55         0x300000c0,             /* 17, -2.5dB */
  56         0x2d4000b5,             /* 18, -3.0dB */
  57         0x2ac000ab,             /* 19, -3.5dB */
  58         0x288000a2,             /* 20, -4.0dB */
  59         0x26000098,             /* 21, -4.5dB */
  60         0x24000090,             /* 22, -5.0dB */
  61         0x22000088,             /* 23, -5.5dB */
  62         0x20000080,             /* 24, -6.0dB */
  63         0x1e400079,             /* 25, -6.5dB */
  64         0x1c800072,             /* 26, -7.0dB */
  65         0x1b00006c,             /* 27. -7.5dB */
  66         0x19800066,             /* 28, -8.0dB */
  67         0x18000060,             /* 29, -8.5dB */
  68         0x16c0005b,             /* 30, -9.0dB */
  69         0x15800056,             /* 31, -9.5dB */
  70         0x14400051,             /* 32, -10.0dB */
  71         0x1300004c,             /* 33, -10.5dB */
  72         0x12000048,             /* 34, -11.0dB */
  73         0x11000044,             /* 35, -11.5dB */
  74         0x10000040,             /* 36, -12.0dB */
  75         0x0f00003c,             /* 37, -12.5dB */
  76         0x0e400039,             /* 38, -13.0dB */
  77         0x0d800036,             /* 39, -13.5dB */
  78         0x0cc00033,             /* 40, -14.0dB */
  79         0x0c000030,             /* 41, -14.5dB */
  80         0x0b40002d,             /* 42, -15.0dB */
  81 };
  82
  83 static const u8 cck_tbl_ch1_13[CCK_TABLE_SIZE][8] = {
  84         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},       /* 0, +0dB */
  85         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},       /* 1, -0.5dB */
  86         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},       /* 2, -1.0dB */
  87         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},       /* 3, -1.5dB */
  88         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},       /* 4, -2.0dB */
  89         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},       /* 5, -2.5dB */
  90         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},       /* 6, -3.0dB */
  91         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},       /* 7, -3.5dB */
  92         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},       /* 8, -4.0dB */
  93         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},       /* 9, -4.5dB */
  94         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},       /* 10, -5.0dB */
  95         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},       /* 11, -5.5dB */
  96         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},       /* 12, -6.0dB */
  97         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},       /* 13, -6.5dB */
  98         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},       /* 14, -7.0dB */
  99         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},       /* 15, -7.5dB */
 100         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},       /* 16, -8.0dB */
 101         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},       /* 17, -8.5dB */
 102         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},       /* 18, -9.0dB */
 103         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       /* 19, -9.5dB */
 104         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       /* 20, -10.0dB*/
 105         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},       /* 21, -10.5dB*/
 106         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},       /* 22, -11.0dB*/
 107         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},       /* 23, -11.5dB*/
 108         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},       /* 24, -12.0dB*/
 109         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},       /* 25, -12.5dB*/
 110         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},       /* 26, -13.0dB*/
 111         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},       /* 27, -13.5dB*/
 112         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},       /* 28, -14.0dB*/
 113         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},       /* 29, -14.5dB*/
 114         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},       /* 30, -15.0dB*/
 115         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},       /* 31, -15.5dB*/
 116         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        /* 32, -16.0dB*/
 117 };
 118
 119 static const u8 cck_tbl_ch14[CCK_TABLE_SIZE][8] = {
 120         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},       /* 0, +0dB */
 121         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},       /* 1, -0.5dB */
 122         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},       /* 2, -1.0dB */
 123         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},       /* 3, -1.5dB */
 124         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},       /* 4, -2.0dB */
 125         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},       /* 5, -2.5dB */
 126         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},       /* 6, -3.0dB */
 127         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},       /* 7, -3.5dB */
 128         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},       /* 8, -4.0dB */
 129         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},       /* 9, -4.5dB */
 130         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},       /* 10, -5.0dB */
 131         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},       /* 11, -5.5dB */
 132         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},       /* 12, -6.0dB */
 133         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},       /* 13, -6.5dB */
 134         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},       /* 14, -7.0dB */
 135         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},       /* 15, -7.5dB */
 136         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},       /* 16, -8.0dB */
 137         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},       /* 17, -8.5dB */
 138         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},       /* 18, -9.0dB */
 139         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       /* 19, -9.5dB */
 140         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       /* 20, -10.0dB*/
 141         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},       /* 21, -10.5dB*/
 142         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},       /* 22, -11.0dB*/
 143         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       /* 23, -11.5dB*/
 144         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       /* 24, -12.0dB*/
 145         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},       /* 25, -12.5dB*/
 146         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       /* 26, -13.0dB*/
 147         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       /* 27, -13.5dB*/
 148         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       /* 28, -14.0dB*/
 149         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       /* 29, -14.5dB*/
 150         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       /* 30, -15.0dB*/
 151         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       /* 31, -15.5dB*/
 152         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}        /* 32, -16.0dB*/
 153 };
 154
 155 #define CAL_SWING_OFF(_off, _dir, _size, _del)                          \
 156         do {                                                            \
 157                 for (_off = 0; _off < _size; _off++) {                  \
 158                         if (_del < thermal_threshold[_dir][_off]) {     \
 159                                 if (_off != 0)                          \
 160                                         _off--;                         \
 161                                 break;                                  \
 162                         }                                               \
 163                 }                                                       \
 164                 if (_off >= _size)                                      \
 165                         _off = _size - 1;                               \
 166         } while (0)
 167
 168 static void rtl88e_set_iqk_matrix(struct ieee80211_hw *hw,
 169                                   u8 ofdm_index, u8 rfpath,
 170                                   long iqk_result_x, long iqk_result_y)
 171 {
 172         long ele_a = 0, ele_d, ele_c = 0, value32;
 173
 174         ele_d = (ofdmswing_table[ofdm_index] & 0xFFC00000)>>22;
 175
 176         if (iqk_result_x != 0) {
 177                 if ((iqk_result_x & 0x00000200) != 0)
 178                         iqk_result_x = iqk_result_x | 0xFFFFFC00;
 179                 ele_a = ((iqk_result_x * ele_d)>>8)&0x000003FF;
 180
 181                 if ((iqk_result_y & 0x00000200) != 0)
 182                         iqk_result_y = iqk_result_y | 0xFFFFFC00;
 183                 ele_c = ((iqk_result_y * ele_d)>>8)&0x000003FF;
 184
 185                 switch (rfpath) {
 186                 case RF90_PATH_A:
 187                         value32 = (ele_d << 22)|((ele_c & 0x3F)<<16) | ele_a;
 188                         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
 189                                       MASKDWORD, value32);
 190                         value32 = (ele_c & 0x000003C0) >> 6;
 191                         rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
 192                                       value32);
 193                         value32 = ((iqk_result_x * ele_d) >> 7) & 0x01;
 194                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
 195                                       value32);
 196                         break;
 197                 case RF90_PATH_B:
 198                         value32 = (ele_d << 22)|((ele_c & 0x3F)<<16) | ele_a;
 199                         rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
 200                                       value32);
 201                         value32 = (ele_c & 0x000003C0) >> 6;
 202                         rtl_set_bbreg(hw, ROFDM0_XDTXAFE, MASKH4BITS, value32);
 203                         value32 = ((iqk_result_x * ele_d) >> 7) & 0x01;
 204                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
 205                                       value32);
 206                         break;
 207                 default:
 208                         break;
 209                 }
 210         } else {
 211                 switch (rfpath) {
 212                 case RF90_PATH_A:
 213                         rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
 214                                       MASKDWORD, ofdmswing_table[ofdm_index]);
 215                         rtl_set_bbreg(hw, ROFDM0_XCTXAFE,
 216                                       MASKH4BITS, 0x00);
 217                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
 218                                       BIT(24), 0x00);
 219                         break;
 220                 case RF90_PATH_B:
 221                         rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
 222                                       MASKDWORD, ofdmswing_table[ofdm_index]);
 223                         rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
 224                                       MASKH4BITS, 0x00);
 225                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
 226                                       BIT(28), 0x00);
 227                         break;
 228                 default:
 229                         break;
 230                 }
 231         }
 232 }
 233
 234 void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw,
 235         u8 type, u8 *pdirection, u32 *poutwrite_val)
 236 {
 237         struct rtl_priv *rtlpriv = rtl_priv(hw);
 238         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
 239         u8 pwr_val = 0;
 240         u8 cck_base = rtldm->swing_idx_cck_base;
 241         u8 cck_val = rtldm->swing_idx_cck;
 242         u8 ofdm_base = rtldm->swing_idx_ofdm_base[0];
 243         u8 ofdm_val = rtlpriv->dm.swing_idx_ofdm[RF90_PATH_A];
 244
 245         if (type == 0) {
 246                 if (ofdm_val <= ofdm_base) {
 247                         *pdirection = 1;
 248                         pwr_val = ofdm_base - ofdm_val;
 249                 } else {
 250                         *pdirection = 2;
 251                         pwr_val = ofdm_base - ofdm_val;
 252                 }
 253         } else if (type == 1) {
 254                 if (cck_val <= cck_base) {
 255                         *pdirection = 1;
 256                         pwr_val = cck_base - cck_val;
 257                 } else {
 258                         *pdirection = 2;
 259                         pwr_val = cck_val - cck_base;
 260                 }
 261         }
 262
 263         if (pwr_val >= TXPWRTRACK_MAX_IDX && (*pdirection == 1))
 264                 pwr_val = TXPWRTRACK_MAX_IDX;
 265
 266         *poutwrite_val = pwr_val | (pwr_val << 8) | (pwr_val << 16) |
 267                          (pwr_val << 24);
 268 }
 269
 270 static void dm_tx_pwr_track_set_pwr(struct ieee80211_hw *hw,
 271                                     enum pwr_track_control_method method,
 272                                     u8 rfpath, u8 channel_mapped_index)
 273 {
 274         struct rtl_priv *rtlpriv = rtl_priv(hw);
 275         struct rtl_phy *rtlphy = &rtlpriv->phy;
 276         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
 277
 278         if (method == TXAGC) {
 279                 if (rtldm->swing_flag_ofdm ||
 280                     rtldm->swing_flag_cck) {
 281                         rtl88e_phy_set_txpower_level(hw,
 282                                                      rtlphy->current_channel);
 283                         rtldm->swing_flag_ofdm = false;
 284                         rtldm->swing_flag_cck = false;
 285                 }
 286         } else if (method == BBSWING) {
 287                 if (!rtldm->cck_inch14) {
 288                         rtl_write_byte(rtlpriv, 0xa22,
 289                                        cck_tbl_ch1_13[rtldm->swing_idx_cck][0]);
 290                         rtl_write_byte(rtlpriv, 0xa23,
 291                                        cck_tbl_ch1_13[rtldm->swing_idx_cck][1]);
 292                         rtl_write_byte(rtlpriv, 0xa24,
 293                                        cck_tbl_ch1_13[rtldm->swing_idx_cck][2]);
 294                         rtl_write_byte(rtlpriv, 0xa25,
 295                                        cck_tbl_ch1_13[rtldm->swing_idx_cck][3]);
 296                         rtl_write_byte(rtlpriv, 0xa26,
 297                                        cck_tbl_ch1_13[rtldm->swing_idx_cck][4]);
 298                         rtl_write_byte(rtlpriv, 0xa27,
 299                                        cck_tbl_ch1_13[rtldm->swing_idx_cck][5]);
 300                         rtl_write_byte(rtlpriv, 0xa28,
 301                                        cck_tbl_ch1_13[rtldm->swing_idx_cck][6]);
 302                         rtl_write_byte(rtlpriv, 0xa29,
 303                                        cck_tbl_ch1_13[rtldm->swing_idx_cck][7]);
 304                 } else {
 305                         rtl_write_byte(rtlpriv, 0xa22,
 306                                        cck_tbl_ch14[rtldm->swing_idx_cck][0]);
 307                         rtl_write_byte(rtlpriv, 0xa23,
 308                                        cck_tbl_ch14[rtldm->swing_idx_cck][1]);
 309                         rtl_write_byte(rtlpriv, 0xa24,
 310                                        cck_tbl_ch14[rtldm->swing_idx_cck][2]);
 311                         rtl_write_byte(rtlpriv, 0xa25,
 312                                        cck_tbl_ch14[rtldm->swing_idx_cck][3]);
 313                         rtl_write_byte(rtlpriv, 0xa26,
 314                                        cck_tbl_ch14[rtldm->swing_idx_cck][4]);
 315                         rtl_write_byte(rtlpriv, 0xa27,
 316                                        cck_tbl_ch14[rtldm->swing_idx_cck][5]);
 317                         rtl_write_byte(rtlpriv, 0xa28,
 318                                        cck_tbl_ch14[rtldm->swing_idx_cck][6]);
 319                         rtl_write_byte(rtlpriv, 0xa29,
 320                                        cck_tbl_ch14[rtldm->swing_idx_cck][7]);
 321                 }
 322
 323                 if (rfpath == RF90_PATH_A) {
 324                         rtl88e_set_iqk_matrix(hw, rtldm->swing_idx_ofdm[rfpath],
 325                                               rfpath, rtlphy->iqk_matrix
 326                                               [channel_mapped_index].
 327                                               value[0][0],
 328                                               rtlphy->iqk_matrix
 329                                               [channel_mapped_index].
 330                                               value[0][1]);
 331                 } else if (rfpath == RF90_PATH_B) {
 332                         rtl88e_set_iqk_matrix(hw, rtldm->swing_idx_ofdm[rfpath],
 333                                               rfpath, rtlphy->iqk_matrix
 334                                               [channel_mapped_index].
 335                                               value[0][4],
 336                                               rtlphy->iqk_matrix
 337                                               [channel_mapped_index].
 338                                               value[0][5]);
 339                 }
 340         } else {
 341                 return;
 342         }
 343 }
 344
 345 static u8 rtl88e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
 346 {
 347         struct rtl_priv *rtlpriv = rtl_priv(hw);
 348         struct dig_t *dm_dig = &rtlpriv->dm_digtable;
 349         long rssi_val_min = 0;
 350
 351         if ((dm_dig->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
 352             (dm_dig->cur_sta_cstate == DIG_STA_CONNECT)) {
 353                 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
 354                         rssi_val_min =
 355                             (rtlpriv->dm.entry_min_undec_sm_pwdb >
 356                              rtlpriv->dm.undec_sm_pwdb) ?
 357                             rtlpriv->dm.undec_sm_pwdb :
 358                             rtlpriv->dm.entry_min_undec_sm_pwdb;
 359                 else
 360                         rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
 361         } else if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT ||
 362                    dm_dig->cur_sta_cstate == DIG_STA_BEFORE_CONNECT) {
 363                 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
 364         } else if (dm_dig->curmultista_cstate ==
 365                 DIG_MULTISTA_CONNECT) {
 366                 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
 367         }
 368
 369         return (u8)rssi_val_min;
 370 }
 371
 372 static void rtl88e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
 373 {
 374         u32 ret_value;
 375         struct rtl_priv *rtlpriv = rtl_priv(hw);
 376         struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
 377
 378         rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1);
 379         rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1);
 380
 381         ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD);
 382         falsealm_cnt->cnt_fast_fsync_fail = (ret_value&0xffff);
 383         falsealm_cnt->cnt_sb_search_fail = ((ret_value&0xffff0000)>>16);
 384
 385         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
 386         falsealm_cnt->cnt_ofdm_cca = (ret_value&0xffff);
 387         falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
 388
 389         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
 390         falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
 391         falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
 392
 393         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
 394         falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
 395         falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
 396                 falsealm_cnt->cnt_rate_illegal +
 397                 falsealm_cnt->cnt_crc8_fail +
 398                 falsealm_cnt->cnt_mcs_fail +
 399                 falsealm_cnt->cnt_fast_fsync_fail +
 400                 falsealm_cnt->cnt_sb_search_fail;
 401
 402         ret_value = rtl_get_bbreg(hw, REG_SC_CNT, MASKDWORD);
 403         falsealm_cnt->cnt_bw_lsc = (ret_value & 0xffff);
 404         falsealm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16);
 405
 406         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(12), 1);
 407         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
 408
 409         ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
 410         falsealm_cnt->cnt_cck_fail = ret_value;
 411
 412         ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
 413         falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
 414
 415         ret_value = rtl_get_bbreg(hw, RCCK0_CCA_CNT, MASKDWORD);
 416         falsealm_cnt->cnt_cck_cca = ((ret_value & 0xff) << 8) |
 417                 ((ret_value&0xFF00)>>8);
 418
 419         falsealm_cnt->cnt_all = (falsealm_cnt->cnt_fast_fsync_fail +
 420                                 falsealm_cnt->cnt_sb_search_fail +
 421                                 falsealm_cnt->cnt_parity_fail +
 422                                 falsealm_cnt->cnt_rate_illegal +
 423                                 falsealm_cnt->cnt_crc8_fail +
 424                                 falsealm_cnt->cnt_mcs_fail +
 425                                 falsealm_cnt->cnt_cck_fail);
 426         falsealm_cnt->cnt_cca_all = falsealm_cnt->cnt_ofdm_cca +
 427                 falsealm_cnt->cnt_cck_cca;
 428
 429         rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 1);
 430         rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 0);
 431         rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 1);
 432         rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 0);
 433         rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0);
 434         rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0);
 435         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 0);
 436         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 2);
 437         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 0);
 438         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 2);
 439
 440         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 441                  "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
 442                  falsealm_cnt->cnt_parity_fail,
 443                  falsealm_cnt->cnt_rate_illegal,
 444                  falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
 445
 446         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 447                  "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
 448                  falsealm_cnt->cnt_ofdm_fail,
 449                  falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
 450 }
 451
 452 static void rtl88e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
 453 {
 454         struct rtl_priv *rtlpriv = rtl_priv(hw);
 455         struct dig_t *dm_dig = &rtlpriv->dm_digtable;
 456         u8 cur_cck_cca_thresh;
 457
 458         if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT) {
 459                 dm_dig->rssi_val_min = rtl88e_dm_initial_gain_min_pwdb(hw);
 460                 if (dm_dig->rssi_val_min > 25) {
 461                         cur_cck_cca_thresh = 0xcd;
 462                 } else if ((dm_dig->rssi_val_min <= 25) &&
 463                            (dm_dig->rssi_val_min > 10)) {
 464                         cur_cck_cca_thresh = 0x83;
 465                 } else {
 466                         if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
 467                                 cur_cck_cca_thresh = 0x83;
 468                         else
 469                                 cur_cck_cca_thresh = 0x40;
 470                 }
 471
 472         } else {
 473                 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
 474                         cur_cck_cca_thresh = 0x83;
 475                 else
 476                         cur_cck_cca_thresh = 0x40;
 477         }
 478
 479         if (dm_dig->cur_cck_cca_thres != cur_cck_cca_thresh)
 480                 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, cur_cck_cca_thresh);
 481
 482         dm_dig->cur_cck_cca_thres = cur_cck_cca_thresh;
 483         dm_dig->pre_cck_cca_thres = dm_dig->cur_cck_cca_thres;
 484         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 485                  "CCK cca thresh hold =%x\n", dm_dig->cur_cck_cca_thres);
 486 }
 487
 488 static void rtl88e_dm_dig(struct ieee80211_hw *hw)
 489 {
 490         struct rtl_priv *rtlpriv = rtl_priv(hw);
 491         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 492         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 493         struct dig_t *dm_dig = &rtlpriv->dm_digtable;
 494         u8 dig_dynamic_min, dig_maxofmin;
 495         bool bfirstconnect;
 496         u8 dm_dig_max, dm_dig_min;
 497         u8 current_igi = dm_dig->cur_igvalue;
 498
 499         if (rtlpriv->dm.dm_initialgain_enable == false)
 500                 return;
 501         if (dm_dig->dig_enable_flag == false)
 502                 return;
 503         if (mac->act_scanning == true)
 504                 return;
 505
 506         if (mac->link_state >= MAC80211_LINKED)
 507                 dm_dig->cur_sta_cstate = DIG_STA_CONNECT;
 508         else
 509                 dm_dig->cur_sta_cstate = DIG_STA_DISCONNECT;
 510         if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
 511             rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
 512                 dm_dig->cur_sta_cstate = DIG_STA_DISCONNECT;
 513
 514         dm_dig_max = DM_DIG_MAX;
 515         dm_dig_min = DM_DIG_MIN;
 516         dig_maxofmin = DM_DIG_MAX_AP;
 517         dig_dynamic_min = dm_dig->dig_min_0;
 518         bfirstconnect = ((mac->link_state >= MAC80211_LINKED) ? true : false) &&
 519                          !dm_dig->media_connect_0;
 520
 521         dm_dig->rssi_val_min =
 522                 rtl88e_dm_initial_gain_min_pwdb(hw);
 523
 524         if (mac->link_state >= MAC80211_LINKED) {
 525                 if ((dm_dig->rssi_val_min + 20) > dm_dig_max)
 526                         dm_dig->rx_gain_max = dm_dig_max;
 527                 else if ((dm_dig->rssi_val_min + 20) < dm_dig_min)
 528                         dm_dig->rx_gain_max = dm_dig_min;
 529                 else
 530                         dm_dig->rx_gain_max = dm_dig->rssi_val_min + 20;
 531
 532                 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
 533                         dig_dynamic_min  = dm_dig->antdiv_rssi_max;
 534                 } else {
 535                         if (dm_dig->rssi_val_min < dm_dig_min)
 536                                 dig_dynamic_min = dm_dig_min;
 537                         else if (dm_dig->rssi_val_min < dig_maxofmin)
 538                                 dig_dynamic_min = dig_maxofmin;
 539                         else
 540                                 dig_dynamic_min = dm_dig->rssi_val_min;
 541                 }
 542         } else {
 543                 dm_dig->rx_gain_max = dm_dig_max;
 544                 dig_dynamic_min = dm_dig_min;
 545                 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "no link\n");
 546         }
 547
 548         if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
 549                 dm_dig->large_fa_hit++;
 550                 if (dm_dig->forbidden_igi < current_igi) {
 551                         dm_dig->forbidden_igi = current_igi;
 552                         dm_dig->large_fa_hit = 1;
 553                 }
 554
 555                 if (dm_dig->large_fa_hit >= 3) {
 556                         if ((dm_dig->forbidden_igi + 1) >
 557                                 dm_dig->rx_gain_max)
 558                                 dm_dig->rx_gain_min =
 559                                         dm_dig->rx_gain_max;
 560                         else
 561                                 dm_dig->rx_gain_min =
 562                                         dm_dig->forbidden_igi + 1;
 563                         dm_dig->recover_cnt = 3600;
 564                 }
 565         } else {
 566                 if (dm_dig->recover_cnt != 0) {
 567                         dm_dig->recover_cnt--;
 568                 } else {
 569                         if (dm_dig->large_fa_hit == 0) {
 570                                 if ((dm_dig->forbidden_igi - 1) <
 571                                     dig_dynamic_min) {
 572                                         dm_dig->forbidden_igi = dig_dynamic_min;
 573                                         dm_dig->rx_gain_min = dig_dynamic_min;
 574                                 } else {
 575                                         dm_dig->forbidden_igi--;
 576                                         dm_dig->rx_gain_min =
 577                                                 dm_dig->forbidden_igi + 1;
 578                                 }
 579                         } else if (dm_dig->large_fa_hit == 3) {
 580                                 dm_dig->large_fa_hit = 0;
 581                         }
 582                 }
 583         }
 584
 585         if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT) {
 586                 if (bfirstconnect) {
 587                         current_igi = dm_dig->rssi_val_min;
 588                 } else {
 589                         if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
 590                                 current_igi += 2;
 591                         else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
 592                                 current_igi++;
 593                         else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
 594                                 current_igi--;
 595                 }
 596         } else {
 597                 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
 598                         current_igi += 2;
 599                 else if (rtlpriv->falsealm_cnt.cnt_all > 8000)
 600                         current_igi++;
 601                 else if (rtlpriv->falsealm_cnt.cnt_all < 500)
 602                         current_igi--;
 603         }
 604
 605         if (current_igi > DM_DIG_FA_UPPER)
 606                 current_igi = DM_DIG_FA_UPPER;
 607         else if (current_igi < DM_DIG_FA_LOWER)
 608                 current_igi = DM_DIG_FA_LOWER;
 609
 610         if (rtlpriv->falsealm_cnt.cnt_all > 10000)
 611                 current_igi = DM_DIG_FA_UPPER;
 612
 613         dm_dig->cur_igvalue = current_igi;
 614         rtl88e_dm_write_dig(hw);
 615         dm_dig->media_connect_0 =
 616                 ((mac->link_state >= MAC80211_LINKED) ? true : false);
 617         dm_dig->dig_min_0 = dig_dynamic_min;
 618
 619         rtl88e_dm_cck_packet_detection_thresh(hw);
 620 }
 621
 622 static void rtl88e_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
 623 {
 624         struct rtl_priv *rtlpriv = rtl_priv(hw);
 625
 626         rtlpriv->dm.dynamic_txpower_enable = false;
 627
 628         rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
 629         rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
 630 }
 631
 632 static void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
 633 {
 634         struct rtl_priv *rtlpriv = rtl_priv(hw);
 635         struct rtl_phy *rtlphy = &rtlpriv->phy;
 636         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 637         long undec_sm_pwdb;
 638
 639         if (!rtlpriv->dm.dynamic_txpower_enable)
 640                 return;
 641
 642         if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
 643                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
 644                 return;
 645         }
 646
 647         if ((mac->link_state < MAC80211_LINKED) &&
 648             (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
 649                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 650                          "Not connected to any\n");
 651
 652                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
 653
 654                 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
 655                 return;
 656         }
 657
 658         if (mac->link_state >= MAC80211_LINKED) {
 659                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
 660                         undec_sm_pwdb =
 661                             rtlpriv->dm.entry_min_undec_sm_pwdb;
 662                         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 663                                  "AP Client PWDB = 0x%lx\n",
 664                                   undec_sm_pwdb);
 665                 } else {
 666                         undec_sm_pwdb =
 667                             rtlpriv->dm.undec_sm_pwdb;
 668                         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 669                                  "STA Default Port PWDB = 0x%lx\n",
 670                                   undec_sm_pwdb);
 671                 }
 672         } else {
 673                 undec_sm_pwdb =
 674                     rtlpriv->dm.entry_min_undec_sm_pwdb;
 675
 676                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 677                          "AP Ext Port PWDB = 0x%lx\n",
 678                           undec_sm_pwdb);
 679         }
 680
 681         if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
 682                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
 683                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 684                          "TXHIGHPWRLEVEL_LEVEL1 (TxPwr = 0x0)\n");
 685         } else if ((undec_sm_pwdb <
 686                     (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
 687                    (undec_sm_pwdb >=
 688                     TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
 689                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
 690                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 691                          "TXHIGHPWRLEVEL_LEVEL1 (TxPwr = 0x10)\n");
 692         } else if (undec_sm_pwdb <
 693                    (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
 694                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
 695                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 696                          "TXHIGHPWRLEVEL_NORMAL\n");
 697         }
 698
 699         if ((rtlpriv->dm.dynamic_txhighpower_lvl !=
 700                 rtlpriv->dm.last_dtp_lvl)) {
 701                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 702                          "PHY_SetTxPowerLevel8192S() Channel = %d\n",
 703                           rtlphy->current_channel);
 704                 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel);
 705         }
 706
 707         rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
 708 }
 709
 710 void rtl88e_dm_write_dig(struct ieee80211_hw *hw)
 711 {
 712         struct rtl_priv *rtlpriv = rtl_priv(hw);
 713         struct dig_t *dm_dig = &rtlpriv->dm_digtable;
 714
 715         RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
 716                  "cur_igvalue = 0x%x, pre_igvalue = 0x%x, backoff_val = %d\n",
 717                  dm_dig->cur_igvalue, dm_dig->pre_igvalue,
 718                  dm_dig->back_val);
 719
 720         if (dm_dig->cur_igvalue > 0x3f)
 721                 dm_dig->cur_igvalue = 0x3f;
 722         if (dm_dig->pre_igvalue != dm_dig->cur_igvalue) {
 723                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
 724                               dm_dig->cur_igvalue);
 725
 726                 dm_dig->pre_igvalue = dm_dig->cur_igvalue;
 727         }
 728 }
 729
 730 static void rtl88e_dm_pwdb_monitor(struct ieee80211_hw *hw)
 731 {
 732         struct rtl_priv *rtlpriv = rtl_priv(hw);
 733         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 734         struct rtl_sta_info *drv_priv;
 735         static u64 last_record_txok_cnt;
 736         static u64 last_record_rxok_cnt;
 737         long tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff;
 738
 739         if (rtlhal->oem_id == RT_CID_819X_HP) {
 740                 u64 cur_txok_cnt = 0;
 741                 u64 cur_rxok_cnt = 0;
 742                 cur_txok_cnt = rtlpriv->stats.txbytesunicast -
 743                         last_record_txok_cnt;
 744                 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast -
 745                         last_record_rxok_cnt;
 746                 last_record_txok_cnt = cur_txok_cnt;
 747                 last_record_rxok_cnt = cur_rxok_cnt;
 748
 749                 if (cur_rxok_cnt > (cur_txok_cnt * 6))
 750                         rtl_write_dword(rtlpriv, REG_ARFR0, 0x8f015);
 751                 else
 752                         rtl_write_dword(rtlpriv, REG_ARFR0, 0xff015);
 753         }
 754
 755         /* AP & ADHOC & MESH */
 756         spin_lock_bh(&rtlpriv->locks.entry_list_lock);
 757         list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
 758                 if (drv_priv->rssi_stat.undec_sm_pwdb <
 759                         tmp_entry_min_pwdb)
 760                         tmp_entry_min_pwdb = drv_priv->rssi_stat.undec_sm_pwdb;
 761                 if (drv_priv->rssi_stat.undec_sm_pwdb >
 762                         tmp_entry_max_pwdb)
 763                         tmp_entry_max_pwdb = drv_priv->rssi_stat.undec_sm_pwdb;
 764         }
 765         spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
 766
 767         /* If associated entry is found */
 768         if (tmp_entry_max_pwdb != 0) {
 769                 rtlpriv->dm.entry_max_undec_sm_pwdb = tmp_entry_max_pwdb;
 770                 RTPRINT(rtlpriv, FDM, DM_PWDB, "EntryMaxPWDB = 0x%lx(%ld)\n",
 771                         tmp_entry_max_pwdb, tmp_entry_max_pwdb);
 772         } else {
 773                 rtlpriv->dm.entry_max_undec_sm_pwdb = 0;
 774         }
 775         /* If associated entry is found */
 776         if (tmp_entry_min_pwdb != 0xff) {
 777                 rtlpriv->dm.entry_min_undec_sm_pwdb = tmp_entry_min_pwdb;
 778                 RTPRINT(rtlpriv, FDM, DM_PWDB, "EntryMinPWDB = 0x%lx(%ld)\n",
 779                                         tmp_entry_min_pwdb, tmp_entry_min_pwdb);
 780         } else {
 781                 rtlpriv->dm.entry_min_undec_sm_pwdb = 0;
 782         }
 783         /* Indicate Rx signal strength to FW. */
 784         if (rtlpriv->dm.useramask) {
 785                 u8 h2c_parameter[3] = { 0 };
 786
 787                 h2c_parameter[2] = (u8)(rtlpriv->dm.undec_sm_pwdb & 0xFF);
 788                 h2c_parameter[0] = 0x20;
 789         } else {
 790                 rtl_write_byte(rtlpriv, 0x4fe, rtlpriv->dm.undec_sm_pwdb);
 791         }
 792 }
 793
 794 void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw)
 795 {
 796         struct rtl_priv *rtlpriv = rtl_priv(hw);
 797
 798         rtlpriv->dm.current_turbo_edca = false;
 799         rtlpriv->dm.is_any_nonbepkts = false;
 800         rtlpriv->dm.is_cur_rdlstate = false;
 801 }
 802
 803 static void rtl88e_dm_check_edca_turbo(struct ieee80211_hw *hw)
 804 {
 805         struct rtl_priv *rtlpriv = rtl_priv(hw);
 806         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 807         static u64 last_txok_cnt;
 808         static u64 last_rxok_cnt;
 809         static u32 last_bt_edca_ul;
 810         static u32 last_bt_edca_dl;
 811         u64 cur_txok_cnt = 0;
 812         u64 cur_rxok_cnt = 0;
 813         u32 edca_be_ul = 0x5ea42b;
 814         u32 edca_be_dl = 0x5ea42b;
 815         bool bt_change_edca = false;
 816
 817         if ((last_bt_edca_ul != rtlpriv->btcoexist.bt_edca_ul) ||
 818             (last_bt_edca_dl != rtlpriv->btcoexist.bt_edca_dl)) {
 819                 rtlpriv->dm.current_turbo_edca = false;
 820                 last_bt_edca_ul = rtlpriv->btcoexist.bt_edca_ul;
 821                 last_bt_edca_dl = rtlpriv->btcoexist.bt_edca_dl;
 822         }
 823
 824         if (rtlpriv->btcoexist.bt_edca_ul != 0) {
 825                 edca_be_ul = rtlpriv->btcoexist.bt_edca_ul;
 826                 bt_change_edca = true;
 827         }
 828
 829         if (rtlpriv->btcoexist.bt_edca_dl != 0) {
 830                 edca_be_ul = rtlpriv->btcoexist.bt_edca_dl;
 831                 bt_change_edca = true;
 832         }
 833
 834         if (mac->link_state != MAC80211_LINKED) {
 835                 rtlpriv->dm.current_turbo_edca = false;
 836                 return;
 837         }
 838         if ((bt_change_edca) ||
 839             ((!rtlpriv->dm.is_any_nonbepkts) &&
 840              (!rtlpriv->dm.disable_framebursting))) {
 841
 842                 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
 843                 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
 844
 845                 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
 846                         if (!rtlpriv->dm.is_cur_rdlstate ||
 847                             !rtlpriv->dm.current_turbo_edca) {
 848                                 rtl_write_dword(rtlpriv,
 849                                                 REG_EDCA_BE_PARAM,
 850                                                 edca_be_dl);
 851                                 rtlpriv->dm.is_cur_rdlstate = true;
 852                         }
 853                 } else {
 854                         if (rtlpriv->dm.is_cur_rdlstate ||
 855                             !rtlpriv->dm.current_turbo_edca) {
 856                                 rtl_write_dword(rtlpriv,
 857                                                 REG_EDCA_BE_PARAM,
 858                                                 edca_be_ul);
 859                                 rtlpriv->dm.is_cur_rdlstate = false;
 860                         }
 861                 }
 862                 rtlpriv->dm.current_turbo_edca = true;
 863         } else {
 864                 if (rtlpriv->dm.current_turbo_edca) {
 865                         u8 tmp = AC0_BE;
 866
 867                         rtlpriv->cfg->ops->set_hw_reg(hw,
 868                                                       HW_VAR_AC_PARAM,
 869                                                       &tmp);
 870                         rtlpriv->dm.current_turbo_edca = false;
 871                 }
 872         }
 873
 874         rtlpriv->dm.is_any_nonbepkts = false;
 875         last_txok_cnt = rtlpriv->stats.txbytesunicast;
 876         last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
 877 }
 878
 879 static void dm_txpower_track_cb_therm(struct ieee80211_hw *hw)
 880 {
 881         struct rtl_priv *rtlpriv = rtl_priv(hw);
 882         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 883         struct rtl_dm   *rtldm = rtl_dm(rtl_priv(hw));
 884         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 885         u8 thermalvalue = 0, delta, delta_lck, delta_iqk, offset;
 886         u8 thermalvalue_avg_count = 0;
 887         u32 thermalvalue_avg = 0;
 888         long  ele_d, temp_cck;
 889         char ofdm_index[2], cck_index = 0,
 890                 ofdm_index_old[2] = {0, 0}, cck_index_old = 0;
 891         int i = 0;
 892         /*bool is2t = false;*/
 893
 894         u8 ofdm_min_index = 6, rf = 1;
 895         /*u8 index_for_channel;*/
 896         enum _power_dec_inc {power_dec, power_inc};
 897
 898         /*0.1 the following TWO tables decide the
 899          *final index of OFDM/CCK swing table
 900          */
 901         char delta_swing_table_idx[2][15]  = {
 902                 {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11},
 903                 {0, 0, -1, -2, -3, -4, -4, -4, -4, -5, -7, -8, -9, -9, -10}
 904         };
 905         u8 thermal_threshold[2][15] = {
 906                 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27},
 907                 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25}
 908         };
 909
 910         /*Initilization (7 steps in total) */
 911         rtlpriv->dm.txpower_trackinginit = true;
 912         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 913                  "dm_txpower_track_cb_therm\n");
 914
 915         thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER,
 916                                          0xfc00);
 917         if (!thermalvalue)
 918                 return;
 919         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 920                  "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
 921                  thermalvalue, rtlpriv->dm.thermalvalue,
 922                  rtlefuse->eeprom_thermalmeter);
 923
 924         /*1. Query OFDM Default Setting: Path A*/
 925         ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) &
 926                               MASKOFDM_D;
 927         for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
 928                 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
 929                         ofdm_index_old[0] = (u8)i;
 930                         rtldm->swing_idx_ofdm_base[RF90_PATH_A] = (u8)i;
 931                         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 932                                  "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index = 0x%x\n",
 933                                  ROFDM0_XATXIQIMBALANCE,
 934                                  ele_d, ofdm_index_old[0]);
 935                         break;
 936                 }
 937         }
 938
 939         /*2.Query CCK default setting From 0xa24*/
 940         temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
 941         for (i = 0; i < CCK_TABLE_LENGTH; i++) {
 942                 if (rtlpriv->dm.cck_inch14) {
 943                         if (memcmp(&temp_cck, &cck_tbl_ch14[i][2], 4) == 0) {
 944                                 cck_index_old = (u8)i;
 945                                 rtldm->swing_idx_cck_base = (u8)i;
 946                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
 947                                          DBG_LOUD,
 948                                          "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch 14 %d\n",
 949                                          RCCK0_TXFILTER2, temp_cck,
 950                                          cck_index_old,
 951                                          rtlpriv->dm.cck_inch14);
 952                                 break;
 953                         }
 954                 } else {
 955                         if (memcmp(&temp_cck, &cck_tbl_ch1_13[i][2], 4) == 0) {
 956                                 cck_index_old = (u8)i;
 957                                 rtldm->swing_idx_cck_base = (u8)i;
 958                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
 959                                          DBG_LOUD,
 960                                          "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n",
 961                                          RCCK0_TXFILTER2, temp_cck,
 962                                          cck_index_old,
 963                                          rtlpriv->dm.cck_inch14);
 964                                 break;
 965                         }
 966                 }
 967         }
 968
 969         /*3 Initialize ThermalValues of RFCalibrateInfo*/
 970         if (!rtldm->thermalvalue) {
 971                 rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter;
 972                 rtlpriv->dm.thermalvalue_lck = thermalvalue;
 973                 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
 974                 for (i = 0; i < rf; i++)
 975                         rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
 976                 rtlpriv->dm.cck_index = cck_index_old;
 977         }
 978
 979         /*4 Calculate average thermal meter*/
 980         rtldm->thermalvalue_avg[rtldm->thermalvalue_avg_index] = thermalvalue;
 981         rtldm->thermalvalue_avg_index++;
 982         if (rtldm->thermalvalue_avg_index == AVG_THERMAL_NUM_88E)
 983                 rtldm->thermalvalue_avg_index = 0;
 984
 985         for (i = 0; i < AVG_THERMAL_NUM_88E; i++) {
 986                 if (rtldm->thermalvalue_avg[i]) {
 987                         thermalvalue_avg += rtldm->thermalvalue_avg[i];
 988                         thermalvalue_avg_count++;
 989                 }
 990         }
 991
 992         if (thermalvalue_avg_count)
 993                 thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count);
 994
 995         /* 5 Calculate delta, delta_LCK, delta_IQK.*/
 996         if (rtlhal->reloadtxpowerindex) {
 997                 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
 998                     (thermalvalue - rtlefuse->eeprom_thermalmeter) :
 999                     (rtlefuse->eeprom_thermalmeter - thermalvalue);
1000                 rtlhal->reloadtxpowerindex = false;
1001                 rtlpriv->dm.done_txpower = false;
1002         } else if (rtlpriv->dm.done_txpower) {
1003                 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
1004                     (thermalvalue - rtlpriv->dm.thermalvalue) :
1005                     (rtlpriv->dm.thermalvalue - thermalvalue);
1006         } else {
1007                 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
1008                     (thermalvalue - rtlefuse->eeprom_thermalmeter) :
1009                     (rtlefuse->eeprom_thermalmeter - thermalvalue);
1010         }
1011         delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
1012             (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
1013             (rtlpriv->dm.thermalvalue_lck - thermalvalue);
1014         delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
1015             (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
1016             (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
1017
1018         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1019                  "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
1020                  thermalvalue, rtlpriv->dm.thermalvalue,
1021                  rtlefuse->eeprom_thermalmeter, delta, delta_lck,
1022                  delta_iqk);
1023         /* 6 If necessary, do LCK.*/
1024         if (delta_lck >= 8) {
1025                 rtlpriv->dm.thermalvalue_lck = thermalvalue;
1026                 rtl88e_phy_lc_calibrate(hw);
1027         }
1028
1029         /* 7 If necessary, move the index of
1030          * swing table to adjust Tx power.
1031          */
1032         if (delta > 0 && rtlpriv->dm.txpower_track_control) {
1033                 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
1034                     (thermalvalue - rtlefuse->eeprom_thermalmeter) :
1035                     (rtlefuse->eeprom_thermalmeter - thermalvalue);
1036
1037                 /* 7.1 Get the final CCK_index and OFDM_index for each
1038                  * swing table.
1039                  */
1040                 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
1041                         CAL_SWING_OFF(offset, power_inc, INDEX_MAPPING_NUM,
1042                                       delta);
1043                         for (i = 0; i < rf; i++)
1044                                 ofdm_index[i] =
1045                                   rtldm->ofdm_index[i] +
1046                                   delta_swing_table_idx[power_inc][offset];
1047                         cck_index = rtldm->cck_index +
1048                                 delta_swing_table_idx[power_inc][offset];
1049                 } else {
1050                         CAL_SWING_OFF(offset, power_dec, INDEX_MAPPING_NUM,
1051                                       delta);
1052                         for (i = 0; i < rf; i++)
1053                                 ofdm_index[i] =
1054                                   rtldm->ofdm_index[i] +
1055                                   delta_swing_table_idx[power_dec][offset];
1056                         cck_index = rtldm->cck_index +
1057                                 delta_swing_table_idx[power_dec][offset];
1058                 }
1059
1060                 /* 7.2 Handle boundary conditions of index.*/
1061                 for (i = 0; i < rf; i++) {
1062                         if (ofdm_index[i] > OFDM_TABLE_SIZE-1)
1063                                 ofdm_index[i] = OFDM_TABLE_SIZE-1;
1064                         else if (rtldm->ofdm_index[i] < ofdm_min_index)
1065                                 ofdm_index[i] = ofdm_min_index;
1066                 }
1067
1068                 if (cck_index > CCK_TABLE_SIZE-1)
1069                         cck_index = CCK_TABLE_SIZE-1;
1070                 else if (cck_index < 0)
1071                         cck_index = 0;
1072
1073                 /*7.3Configure the Swing Table to adjust Tx Power.*/
1074                 if (rtlpriv->dm.txpower_track_control) {
1075                         rtldm->done_txpower = true;
1076                         rtldm->swing_idx_ofdm[RF90_PATH_A] =
1077                                 (u8)ofdm_index[RF90_PATH_A];
1078                         rtldm->swing_idx_cck = cck_index;
1079                         if (rtldm->swing_idx_ofdm_cur !=
1080                             rtldm->swing_idx_ofdm[0]) {
1081                                 rtldm->swing_idx_ofdm_cur =
1082                                          rtldm->swing_idx_ofdm[0];
1083                                 rtldm->swing_flag_ofdm = true;
1084                         }
1085
1086                         if (rtldm->swing_idx_cck_cur != rtldm->swing_idx_cck) {
1087                                 rtldm->swing_idx_cck_cur = rtldm->swing_idx_cck;
1088                                 rtldm->swing_flag_cck = true;
1089                         }
1090
1091                         dm_tx_pwr_track_set_pwr(hw, TXAGC, 0, 0);
1092                 }
1093         }
1094
1095         if (delta_iqk >= 8) {
1096                 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1097                 rtl88e_phy_iq_calibrate(hw, false);
1098         }
1099
1100         if (rtldm->txpower_track_control)
1101                 rtldm->thermalvalue = thermalvalue;
1102         rtldm->txpowercount = 0;
1103         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "end\n");
1104 }
1105
1106 static void rtl88e_dm_init_txpower_tracking(struct ieee80211_hw *hw)
1107 {
1108         struct rtl_priv *rtlpriv = rtl_priv(hw);
1109
1110         rtlpriv->dm.txpower_tracking = true;
1111         rtlpriv->dm.txpower_trackinginit = false;
1112         rtlpriv->dm.txpowercount = 0;
1113         rtlpriv->dm.txpower_track_control = true;
1114
1115         rtlpriv->dm.swing_idx_ofdm[RF90_PATH_A] = 12;
1116         rtlpriv->dm.swing_idx_ofdm_cur = 12;
1117         rtlpriv->dm.swing_flag_ofdm = false;
1118         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1119                  "rtlpriv->dm.txpower_tracking = %d\n",
1120                  rtlpriv->dm.txpower_tracking);
1121 }
1122
1123 void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1124 {
1125         struct rtl_priv *rtlpriv = rtl_priv(hw);
1126         static u8 tm_trigger;
1127
1128         if (!rtlpriv->dm.txpower_tracking)
1129                 return;
1130
1131         if (!tm_trigger) {
1132                 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17)|BIT(16),
1133                               0x03);
1134                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1135                          "Trigger 88E Thermal Meter!!\n");
1136                 tm_trigger = 1;
1137                 return;
1138         } else {
1139                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1140                          "Schedule TxPowerTracking !!\n");
1141                                 dm_txpower_track_cb_therm(hw);
1142                 tm_trigger = 0;
1143         }
1144 }
1145
1146 void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1147 {
1148         struct rtl_priv *rtlpriv = rtl_priv(hw);
1149         struct rate_adaptive *p_ra = &rtlpriv->ra;
1150
1151         p_ra->ratr_state = DM_RATR_STA_INIT;
1152         p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1153
1154         if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1155                 rtlpriv->dm.useramask = true;
1156         else
1157                 rtlpriv->dm.useramask = false;
1158 }
1159
1160 static void rtl88e_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1161 {
1162         struct rtl_priv *rtlpriv = rtl_priv(hw);
1163         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1164         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1165         struct rate_adaptive *p_ra = &rtlpriv->ra;
1166         u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
1167         struct ieee80211_sta *sta = NULL;
1168
1169         if (is_hal_stop(rtlhal)) {
1170                 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1171                          "driver is going to unload\n");
1172                 return;
1173         }
1174
1175         if (!rtlpriv->dm.useramask) {
1176                 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1177                          "driver does not control rate adaptive mask\n");
1178                 return;
1179         }
1180
1181         if (mac->link_state == MAC80211_LINKED &&
1182             mac->opmode == NL80211_IFTYPE_STATION) {
1183                 switch (p_ra->pre_ratr_state) {
1184                 case DM_RATR_STA_HIGH:
1185                         high_rssithresh_for_ra = 50;
1186                         low_rssithresh_for_ra = 20;
1187                         break;
1188                 case DM_RATR_STA_MIDDLE:
1189                         high_rssithresh_for_ra = 55;
1190                         low_rssithresh_for_ra = 20;
1191                         break;
1192                 case DM_RATR_STA_LOW:
1193                         high_rssithresh_for_ra = 50;
1194                         low_rssithresh_for_ra = 25;
1195                         break;
1196                 default:
1197                         high_rssithresh_for_ra = 50;
1198                         low_rssithresh_for_ra = 20;
1199                         break;
1200                 }
1201
1202                 if (rtlpriv->dm.undec_sm_pwdb >
1203                     (long)high_rssithresh_for_ra)
1204                         p_ra->ratr_state = DM_RATR_STA_HIGH;
1205                 else if (rtlpriv->dm.undec_sm_pwdb >
1206                          (long)low_rssithresh_for_ra)
1207                         p_ra->ratr_state = DM_RATR_STA_MIDDLE;
1208                 else
1209                         p_ra->ratr_state = DM_RATR_STA_LOW;
1210
1211                 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
1212                         RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1213                                  "RSSI = %ld\n",
1214                                   rtlpriv->dm.undec_sm_pwdb);
1215                         RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1216                                  "RSSI_LEVEL = %d\n", p_ra->ratr_state);
1217                         RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1218                                  "PreState = %d, CurState = %d\n",
1219                                   p_ra->pre_ratr_state, p_ra->ratr_state);
1220
1221                         rcu_read_lock();
1222                         sta = rtl_find_sta(hw, mac->bssid);
1223                         if (sta)
1224                                 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
1225                                                                    p_ra->ratr_state);
1226                         rcu_read_unlock();
1227
1228                         p_ra->pre_ratr_state = p_ra->ratr_state;
1229                 }
1230         }
1231 }
1232
1233 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1234 {
1235         struct rtl_priv *rtlpriv = rtl_priv(hw);
1236         struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1237
1238         dm_pstable->pre_ccastate = CCA_MAX;
1239         dm_pstable->cur_ccasate = CCA_MAX;
1240         dm_pstable->pre_rfstate = RF_MAX;
1241         dm_pstable->cur_rfstate = RF_MAX;
1242         dm_pstable->rssi_val_min = 0;
1243 }
1244
1245 static void rtl88e_dm_update_rx_idle_ant(struct ieee80211_hw *hw,
1246                                          u8 ant)
1247 {
1248         struct rtl_priv *rtlpriv = rtl_priv(hw);
1249         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1250         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1251         struct fast_ant_training *pfat_table = &rtldm->fat_table;
1252         u32 default_ant, optional_ant;
1253
1254         if (pfat_table->rx_idle_ant != ant) {
1255                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1256                          "need to update rx idle ant\n");
1257                 if (ant == MAIN_ANT) {
1258                         default_ant =
1259                           (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1260                           MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
1261                         optional_ant =
1262                           (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1263                           AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
1264                 } else {
1265                         default_ant =
1266                            (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1267                            AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
1268                         optional_ant =
1269                            (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ?
1270                            MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
1271                 }
1272
1273                 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
1274                         rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1275                                       BIT(5) | BIT(4) | BIT(3), default_ant);
1276                         rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1277                                       BIT(8) | BIT(7) | BIT(6), optional_ant);
1278                         rtl_set_bbreg(hw, DM_REG_ANTSEL_CTRL_11N,
1279                                       BIT(14) | BIT(13) | BIT(12),
1280                                       default_ant);
1281                         rtl_set_bbreg(hw, DM_REG_RESP_TX_11N,
1282                                       BIT(6) | BIT(7), default_ant);
1283                 } else if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) {
1284                         rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1285                                       BIT(5) | BIT(4) | BIT(3), default_ant);
1286                         rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1287                                       BIT(8) | BIT(7) | BIT(6), optional_ant);
1288                 }
1289         }
1290         pfat_table->rx_idle_ant = ant;
1291         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RxIdleAnt %s\n",
1292                  (ant == MAIN_ANT) ? ("MAIN_ANT") : ("AUX_ANT"));
1293 }
1294
1295 static void rtl88e_dm_update_tx_ant(struct ieee80211_hw *hw,
1296                                     u8 ant, u32 mac_id)
1297 {
1298         struct rtl_priv *rtlpriv = rtl_priv(hw);
1299         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1300         struct fast_ant_training *pfat_table = &rtldm->fat_table;
1301         u8 target_ant;
1302
1303         if (ant == MAIN_ANT)
1304                 target_ant = MAIN_ANT_CG_TRX;
1305         else
1306                 target_ant = AUX_ANT_CG_TRX;
1307
1308         pfat_table->antsel_a[mac_id] = target_ant & BIT(0);
1309         pfat_table->antsel_b[mac_id] = (target_ant & BIT(1)) >> 1;
1310         pfat_table->antsel_c[mac_id] = (target_ant & BIT(2)) >> 2;
1311         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "txfrominfo target ant %s\n",
1312                 (ant == MAIN_ANT) ? ("MAIN_ANT") : ("AUX_ANT"));
1313         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "antsel_tr_mux = 3'b%d%d%d\n",
1314                 pfat_table->antsel_c[mac_id],
1315                 pfat_table->antsel_b[mac_id],
1316                 pfat_table->antsel_a[mac_id]);
1317 }
1318
1319 static void rtl88e_dm_rx_hw_antena_div_init(struct ieee80211_hw *hw)
1320 {
1321         u32  value32;
1322
1323         /*MAC Setting*/
1324         value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1325         rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N,
1326                       MASKDWORD, value32 | (BIT(23) | BIT(25)));
1327         /*Pin Setting*/
1328         rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1329         rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1330         rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 1);
1331         rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1332         /*OFDM Setting*/
1333         rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1334         /*CCK Setting*/
1335         rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1336         rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1337         rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT);
1338         rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201);
1339 }
1340
1341 static void rtl88e_dm_trx_hw_antenna_div_init(struct ieee80211_hw *hw)
1342 {
1343         u32  value32;
1344
1345         /*MAC Setting*/
1346         value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1347         rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD,
1348                       value32 | (BIT(23) | BIT(25)));
1349         /*Pin Setting*/
1350         rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1351         rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1352         rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0);
1353         rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1354         /*OFDM Setting*/
1355         rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1356         /*CCK Setting*/
1357         rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
1358         rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
1359         /*TX Setting*/
1360         rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 0);
1361         rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT);
1362         rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201);
1363 }
1364
1365 static void rtl88e_dm_fast_training_init(struct ieee80211_hw *hw)
1366 {
1367         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1368         struct fast_ant_training *pfat_table = &rtldm->fat_table;
1369         u32 ant_combination = 2;
1370         u32 value32, i;
1371
1372         for (i = 0; i < 6; i++) {
1373                 pfat_table->bssid[i] = 0;
1374                 pfat_table->ant_sum[i] = 0;
1375                 pfat_table->ant_cnt[i] = 0;
1376                 pfat_table->ant_ave[i] = 0;
1377         }
1378         pfat_table->train_idx = 0;
1379         pfat_table->fat_state = FAT_NORMAL_STATE;
1380
1381         /*MAC Setting*/
1382         value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD);
1383         rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N,
1384                       MASKDWORD, value32 | (BIT(23) | BIT(25)));
1385         value32 = rtl_get_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, MASKDWORD);
1386         rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N,
1387                       MASKDWORD, value32 | (BIT(16) | BIT(17)));
1388         rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N,
1389                       MASKLWORD, 0);
1390         rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA1_11N,
1391                       MASKDWORD, 0);
1392
1393         /*Pin Setting*/
1394         rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
1395         rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
1396         rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0);
1397         rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1);
1398
1399         /*OFDM Setting*/
1400         rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
1401         /*antenna mapping table*/
1402         rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE0, 1);
1403         rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE1, 2);
1404
1405         /*TX Setting*/
1406         rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 1);
1407         rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1408                       BIT(5) | BIT(4) | BIT(3), 0);
1409         rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1410                       BIT(8) | BIT(7) | BIT(6), 1);
1411         rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N,
1412                       BIT(2) | BIT(1) | BIT(0), (ant_combination - 1));
1413
1414         rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1415 }
1416
1417 static void rtl88e_dm_antenna_div_init(struct ieee80211_hw *hw)
1418 {
1419         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1420
1421         if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1422                 rtl88e_dm_rx_hw_antena_div_init(hw);
1423         else if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1424                 rtl88e_dm_trx_hw_antenna_div_init(hw);
1425         else if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)
1426                 rtl88e_dm_fast_training_init(hw);
1427
1428 }
1429
1430 void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
1431                                      u8 *pdesc, u32 mac_id)
1432 {
1433         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1434         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1435         struct fast_ant_training *pfat_table = &rtldm->fat_table;
1436
1437         if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
1438             (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)) {
1439                 SET_TX_DESC_ANTSEL_A(pdesc, pfat_table->antsel_a[mac_id]);
1440                 SET_TX_DESC_ANTSEL_B(pdesc, pfat_table->antsel_b[mac_id]);
1441                 SET_TX_DESC_ANTSEL_C(pdesc, pfat_table->antsel_c[mac_id]);
1442         }
1443 }
1444
1445 void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw,
1446                                   u8 antsel_tr_mux, u32 mac_id,
1447                                   u32 rx_pwdb_all)
1448 {
1449         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1450         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1451         struct fast_ant_training *pfat_table = &rtldm->fat_table;
1452
1453         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) {
1454                 if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
1455                         pfat_table->main_ant_sum[mac_id] += rx_pwdb_all;
1456                         pfat_table->main_ant_cnt[mac_id]++;
1457                 } else {
1458                         pfat_table->aux_ant_sum[mac_id] += rx_pwdb_all;
1459                         pfat_table->aux_ant_cnt[mac_id]++;
1460                 }
1461         } else if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) {
1462                 if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
1463                         pfat_table->main_ant_sum[mac_id] += rx_pwdb_all;
1464                         pfat_table->main_ant_cnt[mac_id]++;
1465                 } else {
1466                         pfat_table->aux_ant_sum[mac_id] += rx_pwdb_all;
1467                         pfat_table->aux_ant_cnt[mac_id]++;
1468                 }
1469         }
1470 }
1471
1472 static void rtl88e_dm_hw_ant_div(struct ieee80211_hw *hw)
1473 {
1474         struct rtl_priv *rtlpriv = rtl_priv(hw);
1475         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1476         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1477         struct rtl_sta_info *drv_priv;
1478         struct fast_ant_training *pfat_table = &rtldm->fat_table;
1479         struct dig_t *dm_dig = &rtlpriv->dm_digtable;
1480         u32 i, min_rssi = 0xff, ant_div_max_rssi = 0;
1481         u32 max_rssi = 0, local_min_rssi, local_max_rssi;
1482         u32 main_rssi, aux_rssi;
1483         u8 rx_idle_ant = 0, target_ant = 7;
1484
1485         /*for sta its self*/
1486         i = 0;
1487         main_rssi = (pfat_table->main_ant_cnt[i] != 0) ?
1488                 (pfat_table->main_ant_sum[i] / pfat_table->main_ant_cnt[i]) : 0;
1489         aux_rssi = (pfat_table->aux_ant_cnt[i] != 0) ?
1490                 (pfat_table->aux_ant_sum[i] / pfat_table->aux_ant_cnt[i]) : 0;
1491         target_ant = (main_rssi == aux_rssi) ?
1492                 pfat_table->rx_idle_ant : ((main_rssi >= aux_rssi) ?
1493                 MAIN_ANT : AUX_ANT);
1494         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1495                 "main_ant_sum %d main_ant_cnt %d\n",
1496                 pfat_table->main_ant_sum[i],
1497                 pfat_table->main_ant_cnt[i]);
1498         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1499                  "aux_ant_sum %d aux_ant_cnt %d\n",
1500                  pfat_table->aux_ant_sum[i], pfat_table->aux_ant_cnt[i]);
1501         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "main_rssi %d aux_rssi%d\n",
1502                  main_rssi, aux_rssi);
1503         local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;
1504         if ((local_max_rssi > ant_div_max_rssi) && (local_max_rssi < 40))
1505                 ant_div_max_rssi = local_max_rssi;
1506         if (local_max_rssi > max_rssi)
1507                 max_rssi = local_max_rssi;
1508
1509         if ((pfat_table->rx_idle_ant == MAIN_ANT) && (main_rssi == 0))
1510                 main_rssi = aux_rssi;
1511         else if ((pfat_table->rx_idle_ant == AUX_ANT) && (aux_rssi == 0))
1512                 aux_rssi = main_rssi;
1513
1514         local_min_rssi = (main_rssi > aux_rssi) ? aux_rssi : main_rssi;
1515         if (local_min_rssi < min_rssi) {
1516                 min_rssi = local_min_rssi;
1517                 rx_idle_ant = target_ant;
1518         }
1519         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1520                 rtl88e_dm_update_tx_ant(hw, target_ant, i);
1521
1522         if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
1523             rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC) {
1524                 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1525                 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
1526                         i++;
1527                         main_rssi = (pfat_table->main_ant_cnt[i] != 0) ?
1528                                 (pfat_table->main_ant_sum[i] /
1529                                 pfat_table->main_ant_cnt[i]) : 0;
1530                         aux_rssi = (pfat_table->aux_ant_cnt[i] != 0) ?
1531                                 (pfat_table->aux_ant_sum[i] /
1532                                 pfat_table->aux_ant_cnt[i]) : 0;
1533                         target_ant = (main_rssi == aux_rssi) ?
1534                                 pfat_table->rx_idle_ant : ((main_rssi >=
1535                                 aux_rssi) ? MAIN_ANT : AUX_ANT);
1536
1537                         local_max_rssi = (main_rssi > aux_rssi) ?
1538                                          main_rssi : aux_rssi;
1539                         if ((local_max_rssi > ant_div_max_rssi) &&
1540                             (local_max_rssi < 40))
1541                                 ant_div_max_rssi = local_max_rssi;
1542                         if (local_max_rssi > max_rssi)
1543                                 max_rssi = local_max_rssi;
1544
1545                         if ((pfat_table->rx_idle_ant == MAIN_ANT) &&
1546                             (main_rssi == 0))
1547                                 main_rssi = aux_rssi;
1548                         else if ((pfat_table->rx_idle_ant == AUX_ANT) &&
1549                                  (aux_rssi == 0))
1550                                 aux_rssi = main_rssi;
1551
1552                         local_min_rssi = (main_rssi > aux_rssi) ?
1553                                 aux_rssi : main_rssi;
1554                         if (local_min_rssi < min_rssi) {
1555                                 min_rssi = local_min_rssi;
1556                                 rx_idle_ant = target_ant;
1557                         }
1558                         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1559                                 rtl88e_dm_update_tx_ant(hw, target_ant, i);
1560                 }
1561                 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1562         }
1563
1564         for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
1565                 pfat_table->main_ant_sum[i] = 0;
1566                 pfat_table->aux_ant_sum[i] = 0;
1567                 pfat_table->main_ant_cnt[i] = 0;
1568                 pfat_table->aux_ant_cnt[i] = 0;
1569         }
1570
1571         rtl88e_dm_update_rx_idle_ant(hw, rx_idle_ant);
1572
1573         dm_dig->antdiv_rssi_max = ant_div_max_rssi;
1574         dm_dig->rssi_max = max_rssi;
1575 }
1576
1577 static void rtl88e_set_next_mac_address_target(struct ieee80211_hw *hw)
1578 {
1579         struct rtl_priv *rtlpriv = rtl_priv(hw);
1580         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1581         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1582         struct rtl_sta_info *drv_priv;
1583         struct fast_ant_training *pfat_table = &rtldm->fat_table;
1584         u32 value32, i, j = 0;
1585
1586         if (mac->link_state >= MAC80211_LINKED) {
1587                 for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
1588                         if ((pfat_table->train_idx + 1) == ASSOCIATE_ENTRY_NUM)
1589                                 pfat_table->train_idx = 0;
1590                         else
1591                                 pfat_table->train_idx++;
1592
1593                         if (pfat_table->train_idx == 0) {
1594                                 value32 = (mac->mac_addr[5] << 8) |
1595                                           mac->mac_addr[4];
1596                                 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N,
1597                                               MASKLWORD, value32);
1598
1599                                 value32 = (mac->mac_addr[3] << 24) |
1600                                           (mac->mac_addr[2] << 16) |
1601                                           (mac->mac_addr[1] << 8) |
1602                                           mac->mac_addr[0];
1603                                 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA1_11N,
1604                                               MASKDWORD, value32);
1605                                 break;
1606                         }
1607
1608                         if (rtlpriv->mac80211.opmode !=
1609                             NL80211_IFTYPE_STATION) {
1610                                 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1611                                 list_for_each_entry(drv_priv,
1612                                                     &rtlpriv->entry_list, list) {
1613                                         j++;
1614                                         if (j != pfat_table->train_idx)
1615                                                 continue;
1616
1617                                         value32 = (drv_priv->mac_addr[5] << 8) |
1618                                                   drv_priv->mac_addr[4];
1619                                         rtl_set_bbreg(hw,
1620                                                       DM_REG_ANT_TRAIN_PARA2_11N,
1621                                                       MASKLWORD, value32);
1622
1623                                         value32 = (drv_priv->mac_addr[3] << 24) |
1624                                                   (drv_priv->mac_addr[2] << 16) |
1625                                                   (drv_priv->mac_addr[1] << 8) |
1626                                                   drv_priv->mac_addr[0];
1627                                         rtl_set_bbreg(hw,
1628                                                       DM_REG_ANT_TRAIN_PARA1_11N,
1629                                                       MASKDWORD, value32);
1630                                         break;
1631                                 }
1632                                 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1633                                 /*find entry, break*/
1634                                 if (j == pfat_table->train_idx)
1635                                         break;
1636                         }
1637                 }
1638         }
1639 }
1640
1641 static void rtl88e_dm_fast_ant_training(struct ieee80211_hw *hw)
1642 {
1643         struct rtl_priv *rtlpriv = rtl_priv(hw);
1644         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1645         struct fast_ant_training *pfat_table = &rtldm->fat_table;
1646         u32 i, max_rssi = 0;
1647         u8 target_ant = 2;
1648         bool bpkt_filter_match = false;
1649
1650         if (pfat_table->fat_state == FAT_TRAINING_STATE) {
1651                 for (i = 0; i < 7; i++) {
1652                         if (pfat_table->ant_cnt[i] == 0) {
1653                                 pfat_table->ant_ave[i] = 0;
1654                         } else {
1655                                 pfat_table->ant_ave[i] =
1656                                         pfat_table->ant_sum[i] /
1657                                         pfat_table->ant_cnt[i];
1658                                 bpkt_filter_match = true;
1659                         }
1660
1661                         if (pfat_table->ant_ave[i] > max_rssi) {
1662                                 max_rssi = pfat_table->ant_ave[i];
1663                                 target_ant = (u8) i;
1664                         }
1665                 }
1666
1667                 if (bpkt_filter_match == false) {
1668                         rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N,
1669                                       BIT(16), 0);
1670                         rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1671                 } else {
1672                         rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N,
1673                                       BIT(16), 0);
1674                         rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(8) |
1675                                       BIT(7) | BIT(6), target_ant);
1676                         rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N,
1677                                       BIT(21), 1);
1678
1679                         pfat_table->antsel_a[pfat_table->train_idx] =
1680                                 target_ant & BIT(0);
1681                         pfat_table->antsel_b[pfat_table->train_idx] =
1682                                 (target_ant & BIT(1)) >> 1;
1683                         pfat_table->antsel_c[pfat_table->train_idx] =
1684                                 (target_ant & BIT(2)) >> 2;
1685
1686                         if (target_ant == 0)
1687                                 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1688                 }
1689
1690                 for (i = 0; i < 7; i++) {
1691                         pfat_table->ant_sum[i] = 0;
1692                         pfat_table->ant_cnt[i] = 0;
1693                 }
1694
1695                 pfat_table->fat_state = FAT_NORMAL_STATE;
1696                 return;
1697         }
1698
1699         if (pfat_table->fat_state == FAT_NORMAL_STATE) {
1700                 rtl88e_set_next_mac_address_target(hw);
1701
1702                 pfat_table->fat_state = FAT_TRAINING_STATE;
1703                 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N, BIT(16), 1);
1704                 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1705
1706                 mod_timer(&rtlpriv->works.fast_antenna_training_timer,
1707                           jiffies + MSECS(RTL_WATCH_DOG_TIME));
1708         }
1709 }
1710
1711 void rtl88e_dm_fast_antenna_training_callback(unsigned long data)
1712 {
1713         struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
1714
1715         rtl88e_dm_fast_ant_training(hw);
1716 }
1717
1718 static void rtl88e_dm_antenna_diversity(struct ieee80211_hw *hw)
1719 {
1720         struct rtl_priv *rtlpriv = rtl_priv(hw);
1721         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1722         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1723         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1724         struct fast_ant_training *pfat_table = &rtldm->fat_table;
1725
1726         if (mac->link_state < MAC80211_LINKED) {
1727                 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "No Link\n");
1728                 if (pfat_table->becomelinked) {
1729                         RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1730                                  "need to turn off HW AntDiv\n");
1731                         rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0);
1732                         rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N,
1733                                       BIT(15), 0);
1734                         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1735                                 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N,
1736                                               BIT(21), 0);
1737                         pfat_table->becomelinked =
1738                                 (mac->link_state == MAC80211_LINKED) ?
1739                                 true : false;
1740                 }
1741                 return;
1742         } else {
1743                 if (!pfat_table->becomelinked) {
1744                         RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
1745                                  "Need to turn on HW AntDiv\n");
1746                         rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1);
1747                         rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N,
1748                                       BIT(15), 1);
1749                         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)
1750                                 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N,
1751                                               BIT(21), 1);
1752                         pfat_table->becomelinked =
1753                                 (mac->link_state >= MAC80211_LINKED) ?
1754                                 true : false;
1755                 }
1756         }
1757
1758         if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
1759             (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV))
1760                 rtl88e_dm_hw_ant_div(hw);
1761         else if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)
1762                 rtl88e_dm_fast_ant_training(hw);
1763 }
1764
1765 void rtl88e_dm_init(struct ieee80211_hw *hw)
1766 {
1767         struct rtl_priv *rtlpriv = rtl_priv(hw);
1768         u32 cur_igvalue = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f);
1769
1770         rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1771         rtl_dm_diginit(hw, cur_igvalue);
1772         rtl88e_dm_init_dynamic_txpower(hw);
1773         rtl88e_dm_init_edca_turbo(hw);
1774         rtl88e_dm_init_rate_adaptive_mask(hw);
1775         rtl88e_dm_init_txpower_tracking(hw);
1776         rtl92c_dm_init_dynamic_bb_powersaving(hw);
1777         rtl88e_dm_antenna_div_init(hw);
1778 }
1779
1780 void rtl88e_dm_watchdog(struct ieee80211_hw *hw)
1781 {
1782         struct rtl_priv *rtlpriv = rtl_priv(hw);
1783         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1784         bool fw_current_inpsmode = false;
1785         bool fw_ps_awake = true;
1786
1787         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1788                                       (u8 *)(&fw_current_inpsmode));
1789         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1790                                       (u8 *)(&fw_ps_awake));
1791         if (ppsc->p2p_ps_info.p2p_ps_mode)
1792                 fw_ps_awake = false;
1793
1794         if ((ppsc->rfpwr_state == ERFON) &&
1795             ((!fw_current_inpsmode) && fw_ps_awake) &&
1796             (!ppsc->rfchange_inprogress)) {
1797                 rtl88e_dm_pwdb_monitor(hw);
1798                 rtl88e_dm_dig(hw);
1799                 rtl88e_dm_false_alarm_counter_statistics(hw);
1800                 rtl92c_dm_dynamic_txpower(hw);
1801                 rtl88e_dm_check_txpower_tracking(hw);
1802                 rtl88e_dm_refresh_rate_adaptive_mask(hw);
1803                 rtl88e_dm_check_edca_turbo(hw);
1804                 rtl88e_dm_antenna_diversity(hw);
1805         }
1806 }